coreboot-gerrit June 2019

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Change in ...coreboot[master]: qualcomm/qcs405: enable SPI bus 4 for TPM
by Patrick Georgi (Code Review) 02 Jun '19

02 Jun '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30934 Change subject: qualcomm/qcs405: enable SPI bus 4 for TPM ...................................................................... qualcomm/qcs405: enable SPI bus 4 for TPM Change-Id: Ic282daf10dad42bc4513cc55f15ce80a4bd316a5 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/mainboard/google/mistral/Makefile.inc A src/mainboard/google/mistral/verstage.c M src/soc/qualcomm/qcs405/clock.c M src/soc/qualcomm/qcs405/include/soc/clock.h M src/soc/qualcomm/qcs405/include/soc/spi.h M src/soc/qualcomm/qcs405/spi.c 6 files changed, 93 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/30934/1 diff --git a/src/mainboard/google/mistral/Makefile.inc b/src/mainboard/google/mistral/Makefile.inc index 0e2f6bd..e9013af 100644 --- a/src/mainboard/google/mistral/Makefile.inc +++ b/src/mainboard/google/mistral/Makefile.inc @@ -5,6 +5,7 @@ verstage-y += memlayout.ld verstage-y += chromeos.c +verstage-y += verstage.c romstage-y += memlayout.ld romstage-y += chromeos.c diff --git a/src/mainboard/google/mistral/verstage.c b/src/mainboard/google/mistral/verstage.c new file mode 100644 index 0000000..1fad7f5 --- /dev/null +++ b/src/mainboard/google/mistral/verstage.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <console/console.h> +#include <security/vboot/vboot_common.h> +#include <spi-generic.h> + +void verstage_mainboard_init(void) +{ + struct spi_slave spi; + printk(BIOS_ERR, "Trying to initialize TPM SPI bus\n"); + if (spi_setup_slave(CONFIG_DRIVER_TPM_SPI_BUS, + CONFIG_DRIVER_TPM_SPI_CHIP, &spi)) { + printk(BIOS_ERR, "Failed to setup TPM SPI slave\n"); + } +} diff --git a/src/soc/qualcomm/qcs405/clock.c b/src/soc/qualcomm/qcs405/clock.c index 270dad3..015632f 100644 --- a/src/soc/qualcomm/qcs405/clock.c +++ b/src/soc/qualcomm/qcs405/clock.c @@ -87,6 +87,9 @@ static struct qcs405_clock *const blsp1_uart2_clk = (void *)GCC_BLSP1_UART2_BASE; +static struct qcs405_clock *const blsp1_qup0_spi_clk = + (void *)GCC_BLSP1_QUP0_SPI_BASE; + static struct qcs405_clock *const blsp2_qup0_spi_clk = (void *)GCC_BLSP2_QUP0_SPI_BASE; @@ -207,6 +210,13 @@ REG(GCC_APCS_CLOCK_BRANCH_ENA_VOTE), BLSP1_AHB_CLK_ENA); + clock_configure(blsp1_qup0_spi_clk, spi_cfg, 50000000, + ARRAY_SIZE(spi_cfg)); + clock_enable(REG(GCC_BLSP1_QUP0_SPI_APPS_CBCR)); + clock_enable_vote(REG(GCC_BLSP1_AHB_CBCR), + REG(GCC_APCS_CLOCK_BRANCH_ENA_VOTE), + BLSP1_AHB_CLK_ENA); + clock_configure(blsp2_qup0_spi_clk, spi_cfg, 50000000, ARRAY_SIZE(spi_cfg)); clock_enable(REG(GCC_BLSP2_QUP0_SPI_APPS_CBCR)); diff --git a/src/soc/qualcomm/qcs405/include/soc/clock.h b/src/soc/qualcomm/qcs405/include/soc/clock.h index 2736133..7e7af3f 100644 --- a/src/soc/qualcomm/qcs405/include/soc/clock.h +++ b/src/soc/qualcomm/qcs405/include/soc/clock.h @@ -45,6 +45,7 @@ #define GCC_BLSP1_UART3_APPS_CBCR 0x180400C #define GCC_BLSP2_UART0_APPS_CBCR 0x180C03C +#define GCC_BLSP1_QUP0_SPI_APPS_CBCR 0x1802004 #define GCC_BLSP2_QUP0_SPI_APPS_CBCR 0x180C004 #define GCC_BLSP1_AHB_CBCR 0x1801008 diff --git a/src/soc/qualcomm/qcs405/include/soc/spi.h b/src/soc/qualcomm/qcs405/include/soc/spi.h index 5da709f..10f259b 100644 --- a/src/soc/qualcomm/qcs405/include/soc/spi.h +++ b/src/soc/qualcomm/qcs405/include/soc/spi.h @@ -37,60 +37,80 @@ #include <spi-generic.h> #define BLSP0_QUP_REG_BASE ((void *)0x78b5000u) +#define BLSP4_QUP_REG_BASE ((void *)0x78b9000u) #define BLSP5_QUP_REG_BASE ((void *)0x7af5000u) #define BLSP0_SPI_CONFIG_REG (BLSP0_QUP_REG_BASE + 0x00000300) +#define BLSP4_SPI_CONFIG_REG (BLSP4_QUP_REG_BASE + 0x00000300) #define BLSP5_SPI_CONFIG_REG (BLSP5_QUP_REG_BASE + 0x00000300) #define BLSP0_SPI_IO_CONTROL_REG (BLSP0_QUP_REG_BASE + 0x00000304) +#define BLSP4_SPI_IO_CONTROL_REG (BLSP4_QUP_REG_BASE + 0x00000304) #define BLSP5_SPI_IO_CONTROL_REG (BLSP5_QUP_REG_BASE + 0x00000304) #define BLSP0_SPI_ERROR_FLAGS_REG (BLSP0_QUP_REG_BASE + 0x00000308) +#define BLSP4_SPI_ERROR_FLAGS_REG (BLSP4_QUP_REG_BASE + 0x00000308) #define BLSP5_SPI_ERROR_FLAGS_REG (BLSP5_QUP_REG_BASE + 0x00000308) #define BLSP0_SPI_DEASSERT_WAIT_REG (BLSP0_QUP_REG_BASE + 0x00000310) +#define BLSP4_SPI_DEASSERT_WAIT_REG (BLSP4_QUP_REG_BASE + 0x00000310) #define BLSP5_SPI_DEASSERT_WAIT_REG (BLSP5_QUP_REG_BASE + 0x00000310) #define BLSP0_SPI_ERROR_FLAGS_EN_REG (BLSP0_QUP_REG_BASE + 0x0000030c) +#define BLSP4_SPI_ERROR_FLAGS_EN_REG (BLSP4_QUP_REG_BASE + 0x0000030c) #define BLSP5_SPI_ERROR_FLAGS_EN_REG (BLSP5_QUP_REG_BASE + 0x0000030c) #define BLSP0_QUP_CONFIG_REG (BLSP0_QUP_REG_BASE + 0x00000000) +#define BLSP4_QUP_CONFIG_REG (BLSP4_QUP_REG_BASE + 0x00000000) #define BLSP5_QUP_CONFIG_REG (BLSP5_QUP_REG_BASE + 0x00000000) #define BLSP0_QUP_ERROR_FLAGS_REG (BLSP0_QUP_REG_BASE + 0x0000001c) +#define BLSP4_QUP_ERROR_FLAGS_REG (BLSP4_QUP_REG_BASE + 0x0000001c) #define BLSP5_QUP_ERROR_FLAGS_REG (BLSP5_QUP_REG_BASE + 0x0000001c) #define BLSP0_QUP_ERROR_FLAGS_EN_REG (BLSP0_QUP_REG_BASE + 0x00000020) +#define BLSP4_QUP_ERROR_FLAGS_EN_REG (BLSP4_QUP_REG_BASE + 0x00000020) #define BLSP5_QUP_ERROR_FLAGS_EN_REG (BLSP5_QUP_REG_BASE + 0x00000020) #define BLSP0_QUP_OPERATIONAL_MASK (BLSP0_QUP_REG_BASE + 0x00000028) +#define BLSP4_QUP_OPERATIONAL_MASK (BLSP4_QUP_REG_BASE + 0x00000028) #define BLSP5_QUP_OPERATIONAL_MASK (BLSP5_QUP_REG_BASE + 0x00000028) #define BLSP0_QUP_OPERATIONAL_REG (BLSP0_QUP_REG_BASE + 0x00000018) +#define BLSP4_QUP_OPERATIONAL_REG (BLSP4_QUP_REG_BASE + 0x00000018) #define BLSP5_QUP_OPERATIONAL_REG (BLSP5_QUP_REG_BASE + 0x00000018) #define BLSP0_QUP_IO_MODES_REG (BLSP0_QUP_REG_BASE + 0x00000008) +#define BLSP4_QUP_IO_MODES_REG (BLSP4_QUP_REG_BASE + 0x00000008) #define BLSP5_QUP_IO_MODES_REG (BLSP5_QUP_REG_BASE + 0x00000008) #define BLSP0_QUP_STATE_REG (BLSP0_QUP_REG_BASE + 0x00000004) +#define BLSP4_QUP_STATE_REG (BLSP4_QUP_REG_BASE + 0x00000004) #define BLSP5_QUP_STATE_REG (BLSP5_QUP_REG_BASE + 0x00000004) #define BLSP0_QUP_INPUT_FIFOc_REG(c) \ (BLSP0_QUP_REG_BASE + 0x00000218 + 4 * (c)) +#define BLSP4_QUP_INPUT_FIFOc_REG(c) \ + (BLSP4_QUP_REG_BASE + 0x00000218 + 4 * (c)) #define BLSP5_QUP_INPUT_FIFOc_REG(c) \ (BLSP5_QUP_REG_BASE + 0x00000218 + 4 * (c)) #define BLSP0_QUP_OUTPUT_FIFOc_REG(c) \ (BLSP0_QUP_REG_BASE + 0x00000110 + 4 * (c)) +#define BLSP4_QUP_OUTPUT_FIFOc_REG(c) \ + (BLSP4_QUP_REG_BASE + 0x00000110 + 4 * (c)) #define BLSP5_QUP_OUTPUT_FIFOc_REG(c) \ (BLSP5_QUP_REG_BASE + 0x00000110 + 4 * (c)) #define BLSP0_QUP_MX_INPUT_COUNT_REG (BLSP0_QUP_REG_BASE + 0x00000200) +#define BLSP4_QUP_MX_INPUT_COUNT_REG (BLSP4_QUP_REG_BASE + 0x00000200) #define BLSP5_QUP_MX_INPUT_COUNT_REG (BLSP5_QUP_REG_BASE + 0x00000200) #define BLSP0_QUP_MX_OUTPUT_COUNT_REG (BLSP0_QUP_REG_BASE + 0x00000100) +#define BLSP4_QUP_MX_OUTPUT_COUNT_REG (BLSP4_QUP_REG_BASE + 0x00000100) #define BLSP5_QUP_MX_OUTPUT_COUNT_REG (BLSP5_QUP_REG_BASE + 0x00000100) #define BLSP0_QUP_SW_RESET_REG (BLSP0_QUP_REG_BASE + 0x0000000c) +#define BLSP4_QUP_SW_RESET_REG (BLSP4_QUP_REG_BASE + 0x0000000c) #define BLSP5_QUP_SW_RESET_REG (BLSP5_QUP_REG_BASE + 0x0000000c) #define QUP_CONFIG_MINI_CORE_MSK (0x0F << 8) @@ -138,6 +158,7 @@ #define SPI_MODE2 2 #define SPI_MODE3 3 #define BLSP0_SPI 0 +#define BLSP4_SPI 4 #define BLSP5_SPI 5 struct blsp_spi { diff --git a/src/soc/qualcomm/qcs405/spi.c b/src/soc/qualcomm/qcs405/spi.c index 245569b..d4fb29e 100644 --- a/src/soc/qualcomm/qcs405/spi.c +++ b/src/soc/qualcomm/qcs405/spi.c @@ -60,7 +60,29 @@ BLSP0_QUP_OPERATIONAL_MASK, BLSP0_SPI_DEASSERT_WAIT_REG, }, - {0}, {0}, {0}, {0}, + {0}, {0}, {0}, + /* BLSP4 registers for SPI interface */ + { + BLSP4_SPI_CONFIG_REG, + BLSP4_SPI_IO_CONTROL_REG, + BLSP4_SPI_ERROR_FLAGS_REG, + BLSP4_SPI_ERROR_FLAGS_EN_REG, + BLSP4_QUP_CONFIG_REG, + BLSP4_QUP_ERROR_FLAGS_REG, + BLSP4_QUP_ERROR_FLAGS_EN_REG, + BLSP4_QUP_OPERATIONAL_REG, + BLSP4_QUP_IO_MODES_REG, + BLSP4_QUP_STATE_REG, + BLSP4_QUP_INPUT_FIFOc_REG(0), + BLSP4_QUP_OUTPUT_FIFOc_REG(0), + BLSP4_QUP_MX_INPUT_COUNT_REG, + BLSP4_QUP_MX_OUTPUT_COUNT_REG, + BLSP4_QUP_SW_RESET_REG, + 0, + 0, + BLSP4_QUP_OPERATIONAL_MASK, + BLSP4_SPI_DEASSERT_WAIT_REG, + }, /* BLSP5 registers for SPI interface */ { BLSP5_SPI_CONFIG_REG, @@ -202,7 +224,7 @@ check_qup_state_valid(ds); } -static struct ipq_spi_slave spi_slave_pool[2]; +static struct ipq_spi_slave spi_slave_pool[3]; static struct ipq_spi_slave *to_ipq_spi(const struct spi_slave *slave) { @@ -669,6 +691,7 @@ int i; unsigned int bus = slave->bus; unsigned int cs = slave->cs; + printk(BIOS_ERR, "trying to initialize SPI bus %d\n", bus); if ((bus < BLSP0_SPI) || (bus > BLSP5_SPI) || ((bus == BLSP0_SPI) && (cs > 2)) @@ -694,6 +717,7 @@ * to configure this */ ds->freq = 10000000; + ds->freq = 800000; ds->mode = SPI_MODE0; ds->allocated = 1; @@ -725,6 +749,11 @@ .bus_start = BLSP5_SPI, .bus_end = BLSP5_SPI, }, + { + .ctrlr = &spi_ctrlr, + .bus_start = BLSP4_SPI, + .bus_end = BLSP4_SPI, + }, }; const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); -- To view, visit https://review.coreboot.org/c/coreboot/+/30934 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic282daf10dad42bc4513cc55f15ce80a4bd316a5 Gerrit-Change-Number: 30934 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

8 31

Change in ...coreboot[master]: arch/riscv: Don't enable ARCH_RISCV_M on non-RISC-V architecture
by Martin Roth (Code Review) 02 Jun '19

02 Jun '19

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33163 Change subject: arch/riscv: Don't enable ARCH_RISCV_M on non-RISC-V architecture ...................................................................... arch/riscv: Don't enable ARCH_RISCV_M on non-RISC-V architecture I found that ARCH_RISCV_M was enabled on my x86 platform, which is confusing. Disable it unless the chip is RISC-V based. Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: Ie6ddda60d60b45608245939303982dc0952cb9c3 --- M src/arch/riscv/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/33163/1 diff --git a/src/arch/riscv/Kconfig b/src/arch/riscv/Kconfig index 9d325af..f5253bb 100644 --- a/src/arch/riscv/Kconfig +++ b/src/arch/riscv/Kconfig @@ -24,6 +24,7 @@ # one implementation that will not have it due # to security concerns. bool + depends on ARCH_RISCV default n if ARCH_RISCV_M_DISABLED default y -- To view, visit https://review.coreboot.org/c/coreboot/+/33163 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie6ddda60d60b45608245939303982dc0952cb9c3 Gerrit-Change-Number: 33163 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

1 1

Change in ...coreboot[master]: Makefile.inc: Remove unnecessary CONFIG_ARCH_RAMSTAGE_X86_32 dependency
by Subrata Banik (Code Review) 02 Jun '19

02 Jun '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33113 Change subject: Makefile.inc: Remove unnecessary CONFIG_ARCH_RAMSTAGE_X86_32 dependency ...................................................................... Makefile.inc: Remove unnecessary CONFIG_ARCH_RAMSTAGE_X86_32 dependency Change-Id: Ic9d1a95e80178775dd78e756f97f6da13a24dc95 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/arch/x86/Makefile.inc M src/lib/Makefile.inc 2 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/33113/1 diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 6e4ee76..7e518d8 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -193,7 +193,7 @@ verstage-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c verstage-$(CONFIG_IDT_IN_EVERY_STAGE) += idt.S -verstage-$(CONFIG_ARCH_RAMSTAGE_X86_32) += cpu_common.c +verstage-y += cpu_common.c verstage-y += memset.c verstage-y += memcpy.c verstage-y += memmove.c @@ -230,7 +230,7 @@ romstage-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += gdt_init.S romstage-y += cbmem.c romstage-y += cbfs_and_run.c -romstage-$(CONFIG_ARCH_RAMSTAGE_X86_32) += cpu_common.c +romstage-y += cpu_common.c romstage-$(CONFIG_EARLY_EBDA_INIT) += ebda.c romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += idt.S diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 1350152..b28be84 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -104,7 +104,7 @@ verstage-$(CONFIG_ARCH_VERSTAGE_X86_32) += gcc.c romstage-$(CONFIG_ARCH_ROMSTAGE_X86_32) += gcc.c ramstage-$(CONFIG_ARCH_RAMSTAGE_X86_32) += gcc.c -smm-$(CONFIG_ARCH_RAMSTAGE_X86_32) += gcc.c +smm-y += gcc.c endif romstage-$(CONFIG_GENERIC_UDELAY) += timer.c @@ -272,7 +272,7 @@ ifeq ($(CONFIG_RELOCATABLE_MODULES),y) ramstage-y += rmodule.c -romstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += rmodule.c +romstage-y += rmodule.c RMODULE_LDFLAGS := -z defs -Bsymbolic -- To view, visit https://review.coreboot.org/c/coreboot/+/33113 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9d1a95e80178775dd78e756f97f6da13a24dc95 Gerrit-Change-Number: 33113 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

3 6

Change in ...coreboot[master]: cpu/intel/sandybridge: Add `hyper_threading` option
by Evgeny Zinoviev (Code Review) 02 Jun '19

02 Jun '19

Evgeny Zinoviev has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29669 ) Change subject: cpu/intel/sandybridge: Add `hyper_threading` option ...................................................................... Patch Set 4: Using the latest patch set on X220 for 4 days already, seems stable. -- To view, visit https://review.coreboot.org/c/coreboot/+/29669 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b73e32ff5af8ea64a47e8aa706e27648aaf0993 Gerrit-Change-Number: 29669 Gerrit-PatchSet: 4 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-CC: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Comment-Date: Sun, 02 Jun 2019 01:29:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/up/squared: Remove unnecessary code
by Felix Singer (Code Review) 01 Jun '19

01 Jun '19

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33136 ) Change subject: mb/up/squared: Remove unnecessary code ...................................................................... Patch Set 5: (1 comment) This change is ready for review. https://review.coreboot.org/#/c/33136/4/src/mainboard/up/squared/ramstage.c File src/mainboard/up/squared/ramstage.c: https://review.coreboot.org/#/c/33136/4/src/mainboard/up/squared/ramstage.c… PS4, Line 57: silconfig->WriteProtectionEnable[0] = 0x1; // 0x0 > I think we don't need WriteProtectionEnable/ReadProtectionEnable here and can do it in coreboot Done -- To view, visit https://review.coreboot.org/c/coreboot/+/33136 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7dae4f24a9fcb01d2d47063dd3a0f4ce6c120d2 Gerrit-Change-Number: 33136 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sat, 01 Jun 2019 16:51:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: doc/mb/upsquared: Add documentation
by Felix Singer (Code Review) 01 Jun '19

01 Jun '19

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32935 ) Change subject: doc/mb/upsquared: Add documentation ...................................................................... Patch Set 8: (2 comments) This change is ready for review. https://review.coreboot.org/#/c/32935/7/Documentation/soc/intel/apollolake/… File Documentation/soc/intel/apollolake/index.md: https://review.coreboot.org/#/c/32935/7/Documentation/soc/intel/apollolake/… PS7, Line 3: ![][apl_flash_layout] > missing topic: […] Done https://review.coreboot.org/#/c/32935/7/Documentation/soc/intel/apollolake/… PS7, Line 7: Usually on x86 platforms the bootblock is stored at the end of the bios region and the Intel ME / TXE has its own IFD region. On Apollolake both have been moved into the IFWI region, which is a subregion of "BIOS", since it allows to store multiple firmware components. > 80 char limit per line Done -- To view, visit https://review.coreboot.org/c/coreboot/+/32935 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic708ddbd2616eee4e5ec2740b3eac18b408bde38 Gerrit-Change-Number: 32935 Gerrit-PatchSet: 8 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 01 Jun 2019 16:47:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: nb/intel/i945: Set CxDRT1 tRPALL bit if populated with 8-bank
by HAOUAS Elyes (Code Review) 01 Jun '19

01 Jun '19

HAOUAS Elyes has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/28648 ) Change subject: nb/intel/i945: Set CxDRT1 tRPALL bit if populated with 8-bank ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/28648 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id6c7dccd295e187acfe00a08294010af53b4d0ee Gerrit-Change-Number: 28648 Gerrit-PatchSet: 10 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

1 0

Change in ...coreboot[master]: qcs405: Add bl31 stage and elf
by build bot (Jenkins) (Code Review) 01 Jun '19

01 Jun '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29981 ) Change subject: qcs405: Add bl31 stage and elf ...................................................................... Patch Set 26: (1 comment) https://review.coreboot.org/#/c/29981/26/src/soc/qualcomm/qcs405/soc.c File src/soc/qualcomm/qcs405/soc.c: https://review.coreboot.org/#/c/29981/26/src/soc/qualcomm/qcs405/soc.c@26 PS26, Line 26: bootmem_add_range((uintptr_t)_dram_reserved, _dram_reserved_size, BM_MEM_BL31); line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/29981 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I967c0b78a3561574609bf8332a22838c85e43429 Gerrit-Change-Number: 29981 Gerrit-PatchSet: 26 Gerrit-Owner: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 01 Jun 2019 09:30:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: qcs405: Combine BB with QC-Sec for ROM boot
by Nitheesh Sekar (Code Review) 01 Jun '19

01 Jun '19

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29958 to look at the new patch set (#26). Change subject: qcs405: Combine BB with QC-Sec for ROM boot ...................................................................... qcs405: Combine BB with QC-Sec for ROM boot TEST=build & run Change-Id: I2428fd067c0216d9cf6a63e218d1792788317db0 Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- M src/soc/qualcomm/qcs405/Makefile.inc 1 file changed, 25 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/29958/26 -- To view, visit https://review.coreboot.org/c/coreboot/+/29958 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2428fd067c0216d9cf6a63e218d1792788317db0 Gerrit-Change-Number: 29958 Gerrit-PatchSet: 26 Gerrit-Owner: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: QCS405: Added RPM support
by Nitheesh Sekar (Code Review) 01 Jun '19

01 Jun '19

Hello Julius Werner, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29970 to look at the new patch set (#27). Change subject: QCS405: Added RPM support ...................................................................... QCS405: Added RPM support This patch adds support to read RPM image from 3rdparty/blobs and load it. It takes RPM out of reset. Note that, clock_reset_rpm function to touch the GCC registers actually should reside in clock.c, but for now keeping it here till clock patches are posted. Change-Id: I17f491f0a4bd0dce7522b7e80e1bac97ec18b945 Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> --- M src/soc/qualcomm/qcs405/Makefile.inc M src/soc/qualcomm/qcs405/include/soc/memlayout.ld A src/soc/qualcomm/qcs405/include/soc/rpm.h M src/soc/qualcomm/qcs405/include/soc/symbols.h M src/soc/qualcomm/qcs405/mmu.c A src/soc/qualcomm/qcs405/rpm_load_reset.c M src/soc/qualcomm/qcs405/soc.c 7 files changed, 106 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/29970/27 -- To view, visit https://review.coreboot.org/c/coreboot/+/29970 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I17f491f0a4bd0dce7522b7e80e1bac97ec18b945 Gerrit-Change-Number: 29970 Gerrit-PatchSet: 27 Gerrit-Owner: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Sricharan Ramabadhran <srichara(a)qualcomm.corp-partner.google.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit June 2019