May 2025 - coreboot-gerrit - mail.coreboot.org

Change in coreboot[master]: mb/google/dedede/var/magolor: Configure I2C high and low time
by Ren Kuo (Code Review) Sept. 16, 2025

Sept. 16, 2025

Ren Kuo has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46613 ) Change subject: mb/google/dedede/var/magolor: Configure I2C high and low time ...................................................................... mb/google/dedede/var/magolor: Configure I2C high and low time Configure the I2C bus high and low time for all enabled I2C buses. BUG=b:168783630 TEST=Measured the I2C bus frequency reduce to 387 KHz. Signed-off-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Change-Id: I9f5b81815f86db7bdcea95a95b9c9b235b4a34b1 --- M src/mainboard/google/dedede/variants/magolor/overridetree.cb 1 file changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/46613/1 diff --git a/src/mainboard/google/dedede/variants/magolor/overridetree.cb b/src/mainboard/google/dedede/variants/magolor/overridetree.cb index f41e9fa..625546e 100644 --- a/src/mainboard/google/dedede/variants/magolor/overridetree.cb +++ b/src/mainboard/google/dedede/variants/magolor/overridetree.cb @@ -25,18 +25,42 @@ }, .i2c[0] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } }, .i2c[1] = { .speed = I2C_SPEED_FAST, }, .i2c[2] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } }, .i2c[3] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } }, .i2c[4] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } }, }" -- To view, visit https://review.coreboot.org/c/coreboot/+/46613 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f5b81815f86db7bdcea95a95b9c9b235b4a34b1 Gerrit-Change-Number: 46613 Gerrit-PatchSet: 1 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

4 8

Change in ...coreboot[master]: SeaBIOS - unofficial patches: advanced_bootmenu and multiple_floppies
by mikeb mikeb (Code Review) June 12, 2025

June 12, 2025

Hello Mike Banon, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/32351 to review the following change. Change subject: SeaBIOS - unofficial patches: advanced_bootmenu and multiple_floppies ...................................................................... SeaBIOS - unofficial patches: advanced_bootmenu and multiple_floppies If you'd like to add the useful floppies to your coreboot (read about them at http://dangerousprototypes.com/docs/Lenovo_G505S_hacking#Useful_floppies ), or to use your USB numpad for choosing a SeaBIOS boot entry, then this change is for you! It contains two valuable patches together with a Makefile mod needed to automatically apply these patches to a cloned SeaBIOS before its' compilation. advanced_bootmenu: up to 35 entries (2 pages if >18), numpad support (console) https://mail.coreboot.org/hyperkitty/list/seabios@seabios.org/thread/CKWLNT… [PATCH v2] ramdisk: search for all available floppy images instead of one https://mail.coreboot.org/pipermail/seabios/2018-December/012670.html Patch descriptions are available at these links, and just in case here's a copy: advanced_bootmenu: up to 35 entries (2 pages if >18), numpad support (console) Add support for up to 35 boot menu entries (2 pages if >18). To solve the ">10" problem currently experienced by SeaBIOS users (there are no 11, 12, etc. keys on a keyboard - so impossible to choose the last menu entries if you got >10 entries because of multiple hard drives / secondary payloads / floppies) - the boot menu has been extended to the letter keys. NOTE: TPM menu has been moved from T to M letter: it is at the end of keyboard's 3rd row of letters and "Trusted" is adjective while "Module" is a noun; alternatively could press '-'. Also, add support for a numpad. Small USB numpad could be really convenient for choosing the boot entries at coreboot boards used as (maybe headless) servers. '/' char on numpad could be used to open the boot menu or to exit it. If there are >10 boot menu entries - the numpad console interface will be enabled: press one or two digit keys and then ENTER to confirm your choice, or remove a digit by pressing the '.Del' key. Also you could call TPM with '-' key at any moment, or boot with a single key press of your fullsize keyboard. [PATCH v2] ramdisk: search for all available floppy images instead of one All the floppy images available at CBFS will be found and listed in a boot menu, instead of the first found. Could be highly valuable if you are participating in a hobby OS development - would like to test multiple versions of your floppy at the same coreboot image, to reduce the amount of re-flashes and accelerate the development at bare metal - or simply you would like to access multiple floppies as a coreboot user. For example: KolibriOS (nice assembly OS with GUI and apps), FreeDOS, MichalOS, Snowdrop and memtest (coreboot's memtest version is buggy, e.g. external USB keyboard isn't working at some laptops; floppy is much better) Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: Idf4efba31091a8678b51c2f6541d440c5cc6d37d --- M payloads/external/SeaBIOS/Makefile A payloads/external/SeaBIOS/advanced_bootmenu.patch A payloads/external/SeaBIOS/multiple_floppies.patch 3 files changed, 551 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/32351/1 diff --git a/payloads/external/SeaBIOS/Makefile b/payloads/external/SeaBIOS/Makefile index e505c8c..ae58c8c 100644 --- a/payloads/external/SeaBIOS/Makefile +++ b/payloads/external/SeaBIOS/Makefile @@ -76,7 +76,18 @@ # echo "# CONFIG_SMBIOS is not set" >> seabios/.config $(MAKE) -C seabios olddefconfig OUT=out/ -build: config +patch: + if [ -d seabios ]; then \ + cd seabios; \ + if [ ! -f .patched ]; then \ + echo " PATCH SeaBIOS $(TAG-y)"; \ + patch -p1 < ./../advanced_bootmenu.patch; \ + patch -p1 < ./../multiple_floppies.patch; \ + touch .patched; \ + fi; \ + fi + +build: config patch echo " MAKE SeaBIOS $(TAG-y)" $(MAKE) -C seabios OUT=out/ diff --git a/payloads/external/SeaBIOS/advanced_bootmenu.patch b/payloads/external/SeaBIOS/advanced_bootmenu.patch new file mode 100644 index 0000000..c914588 --- /dev/null +++ b/payloads/external/SeaBIOS/advanced_bootmenu.patch @@ -0,0 +1,332 @@ +diff --git a/src/boot.c b/src/boot.c +index 9f82f3c..f94dd27 100644 +--- a/src/boot.c ++++ b/src/boot.c +@@ -463,6 +463,7 @@ get_keystroke(int msec) + * Boot menu and BCV execution + ****************************************************************/ + ++#define BOOTMENU_PAGE_SIZE 18 + #define DEFAULT_BOOTMENU_WAIT 2500 + + // Show IPL option menu. +@@ -478,59 +479,282 @@ interactive_bootmenu(void) + ; + + char *bootmsg = romfile_loadfile("etc/boot-menu-message", NULL); +- int menukey = romfile_loadint("etc/boot-menu-key", 1); +- printf("%s", bootmsg ?: "\nPress ESC for boot menu.\n\n"); ++ int menukey = romfile_loadint("etc/boot-menu-key", 1); // custom menukey ++ printf("%s", bootmsg ?: "\nPress ESC or \\ / slash for boot menu.\n\n"); + free(bootmsg); + + u32 menutime = romfile_loadint("etc/boot-menu-wait", DEFAULT_BOOTMENU_WAIT); + enable_bootsplash(); + int scan_code = get_keystroke(menutime); + disable_bootsplash(); +- if (scan_code != menukey) ++ if (scan_code != menukey && // custom menukey ++ scan_code != 1 && // ESC ++ scan_code != 43 && // '\' char on keyboard ++ scan_code != 53 && // '/' char on keyboard ++ scan_code != 98) { // '/' char on numpad ++ if (scan_code == -1) ++ printf("No key pressed.\n"); ++ else ++ printf("Not a menukey pressed.\n"); + return; ++ } + + while (get_keystroke(0) >= 0) + ; + +- printf("Select boot device:\n\n"); + wait_threads(); + +- // Show menu items ++ char keyboard_keys[35] = {'1','2','3','4','5','6','7','8','9','0', ++ 'q','w','e','r','t','y','u','i','o','p', ++ 'a','s','d','f','g','h','j','k','l', ++ 'z','x','c','v','b','n'}; /* m = TPM */ ++ int numpad_scancodes[10] = { 82, 79, 80, 81, 75, 76, 77, 71, 72, 73 }; ++ int numpi = 0; // Key index: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9. ++ int digits = 0; // Numerical length of a current choice number. ++ int decode = 0; // Decode the current choice number into a letter? ++ int entry_id = 0; ++ char desc[77]; ++ ++ printf("Select boot device"); ++ ++ // Show menu items after counting them and determining a number of pages. ++ // Only 35 boot menu items (36 if to count a TPM) are supported currently. ++ + int maxmenu = 0; + struct bootentry_s *pos; +- hlist_for_each_entry(pos, &BootList, node) { +- char desc[77]; ++ hlist_for_each_entry(pos, &BootList, node) + maxmenu++; +- printf("%d. %s\n", maxmenu ++ ++ if (maxmenu > 10) { ++ if (maxmenu > 35) ++ maxmenu = 35; ++ if (maxmenu > BOOTMENU_PAGE_SIZE) ++ printf(" - page 1 :"); ++ else ++ printf(": "); ++ printf(" // press ENTER after your numpad input"); ++ if (maxmenu > BOOTMENU_PAGE_SIZE) ++ printf(" - if any -\n " ++ " // - or to switch between the pages...\n"); ++ else ++ printf(" (if any)\n\n"); ++ } else { ++ printf(":\n\n"); ++ } ++ ++ hlist_for_each_entry(pos, &BootList, node) { ++ if (entry_id == BOOTMENU_PAGE_SIZE) // Show only the first page. ++ break; ++ printf("%c. %s\n", keyboard_keys[entry_id] + , strtcpy(desc, pos->description, ARRAY_SIZE(desc))); ++ entry_id++; + } ++ int tpm_cshm = 0; + if (tpm_can_show_menu()) { +- printf("\nt. TPM Configuration\n"); ++ tpm_cshm = 1; ++ printf("\nm-. TPM Configuration"); + } +- +- // Get key press. If the menu key is ESC, do not restart boot unless +- // 1.5 seconds have passed. Otherwise users (trained by years of +- // repeatedly hitting keys to enter the BIOS) will end up hitting ESC +- // multiple times and immediately booting the primary boot device. +- int esc_accepted_time = irqtimer_calc(menukey == 1 ? 1500 : 0); ++ printf("\n> "); ++ ++ // Do not restart boot on menukey press, unless DEFAULT_BOOTMENU_WAIT msecs ++ // have passed. Otherwise users (trained by years of repeatedly hitting keys ++ // to enter the BIOS) will end up hitting menukey multiple times and ++ // immediately booting the primary boot device. ++ int esc_accepted_time = irqtimer_calc(DEFAULT_BOOTMENU_WAIT); ++ int choice = 0, kb_choice = 0; ++ int page_num = 1; ++ int enter = 0; ++ int backspace = 0; ++ int tpm_show_menu = 0; + for (;;) { + scan_code = get_keystroke(1000); +- if (scan_code == 1 && !irqtimer_check(esc_accepted_time)) +- continue; +- if (tpm_can_show_menu() && scan_code == 20 /* t */) { ++ if (scan_code == menukey || // custom menukey ++ scan_code == 1 || // ESC ++ scan_code == 43 || // '\' char on keyboard ++ scan_code == 53 || // '/' char on keyboard ++ scan_code == 98) { // '/' char on numpad ++ if (!irqtimer_check(esc_accepted_time)) ++ continue; ++ if (digits == 2) // Remove the decoded "(*)" ++ printf(" \b\b\b"); ++ /* Remove the existing input before printing a message. */ ++ for (; digits > 0; digits--) ++ printf("\b \b"); ++ printf("Menukey pressed.\n"); ++ return; ++ } ++ kb_choice = 0; ++ /* 4 rows of keyboard_keys: 1 row with numbers, 3 rows with letters. ++ Use any of them to select a boot device (except the TPM 'm-' keys) */ ++ // 1st range: 1-9 and 0 (10) keys <==> 2-11 scan codes <==> 1-10 choice ++ if (scan_code >= 2 && scan_code <= 11) kb_choice = scan_code - 1; ++ // 2nd range: Q-P row of letters <==> 16-25 scan codes <==> 11-20 choice ++ if (scan_code >= 16 && scan_code <= 25) kb_choice = scan_code - 5; ++ // 3rd range: A-L row of letters <==> 30-38 scan codes <==> 21-29 choice ++ if (scan_code >= 30 && scan_code <= 38) kb_choice = scan_code - 9; ++ // 4th range: Z-N row of letters <==> 44-49 scan codes <==> 30-35 choice ++ if (scan_code >= 44 && scan_code <= 49) kb_choice = scan_code - 14; ++ // ENTER: (28) on keyboard, (96) on numpad. ++ if (scan_code == 28 || scan_code == 96) ++ enter = 1; ++ // BCKSPC: '<-'(14) and 'Delete'(111) on keyboard, '.Del'(83) on numpad. ++ if (scan_code == 14 || scan_code == 111 || scan_code == 83) ++ backspace = 1; ++ // TPM keys: 'm'(50) and '-'(12) chars on keyboard, '-'(74) on numpad. ++ if ((scan_code == 50 || scan_code == 12 || scan_code == 74) && tpm_cshm) ++ tpm_show_menu = 1; ++ ++ if (kb_choice != 0 || tpm_show_menu) { ++ if (kb_choice > maxmenu) { ++ if (!tpm_show_menu) ++ continue; ++ } else { ++ choice = kb_choice; ++ } ++ if (digits == 2) // Remove the decoded "(*)" ++ printf(" \b\b\b"); ++ /* Remove the existing input before printing a choice. */ ++ for (; digits > 0; digits--) ++ printf("\b \b"); ++ if (!tpm_show_menu) { ++ // Choice is any of the detected boot devices ==> lets boot! ++ break; ++ } ++ } else { ++ // Internal/USB Numpad console interface. ++ if (digits < 9) { ++ for (numpi = 0; numpi < 10; numpi++) { ++ if (scan_code == numpad_scancodes[numpi]) { ++ if (maxmenu <= 10) { // Console interface is not needed. ++ if ((numpi != 0 && numpi <= maxmenu) || ++ (numpi == 0 && 10 <= maxmenu)) { // 10(0) ++ choice = numpi; ++ enter = 1; // Fake ENTER to boot this entry now. ++ } else { // If no such an entry, don't try to boot. ++ break; ++ } ++ } else { ++ if (digits == 2) { ++ printf(" \b\b\b"); // Remove the decoded "(*)" ++ if (choice == 0) { ++ printf("\b\b \b\b"); // Remove "10". ++ digits = 0; ++ } ++ } ++ choice = 10 * choice + numpi; ++ } ++ if (choice > 0) { ++ printf("%d", numpi); // Print the entered digit. ++ digits++; ++ } else { ++ if (10 <= maxmenu) ++ printf("10(0)\b\b\b"); ++ else ++ printf("10(?)\b\b\b"); ++ digits = 2; ++ } ++ if (choice > 9 && digits == 2) // Decode into a letter. ++ decode = 1; ++ break; ++ } ++ } ++ } ++ if (backspace && digits > 0) { ++ backspace = 0; ++ choice = choice / 10; ++ if (digits == 2) { ++ printf(" \b\b\b"); // Remove the decoded "(*)" ++ // 0 turned into 10: one more Backspace is needed to remove. ++ if (choice == 0) { ++ printf("\b \b"); ++ digits--; ++ } ++ } ++ printf("\b \b"); // Remove the last entered digit. ++ digits--; ++ if (choice > 9 && digits == 2) // Decode into a letter. ++ decode = 1; ++ } ++ if (decode) { // Decode the current choice number into a letter. ++ decode = 0; ++ if (choice <= maxmenu) { ++ printf("(%c)", keyboard_keys[choice-1]); ++ } else { ++ if (tpm_cshm && choice == 36) ++ printf("(m)"); // For TPM. ++ else ++ printf("(?)"); // No matching letter found. ++ } ++ printf("\b\b\b"); // Move a cursor before the "(*)" ++ } ++ } ++ ++ if (enter) { ++ enter = 0; ++ if (choice == 0) { ++ if (digits == 2) { // for 0 that turned into 10 ++ if (10 <= maxmenu) ++ break; ++ else ++ continue; ++ } ++ // If there are two pages - switch between them. ++ if (maxmenu > BOOTMENU_PAGE_SIZE) { ++ entry_id = 0; ++ page_num = 3 - page_num; // 3 - 1 = 2; 3 - 2 = 1. ++ printf("\n\nSelect boot device - page %d :" ++ " // press ENTER after your numpad input" ++ " - if any -\n " ++ " // - or to switch between the pages...\n", ++ page_num); ++ hlist_for_each_entry(pos, &BootList, node) { ++ if ((page_num == 1 && entry_id == BOOTMENU_PAGE_SIZE) || ++ (page_num == 2 && entry_id == 35)) ++ break; ++ if (page_num == 1 || entry_id >= BOOTMENU_PAGE_SIZE) ++ printf("%c. %s\n", keyboard_keys[entry_id], ++ strtcpy(desc, pos->description, ARRAY_SIZE(desc))); ++ entry_id++; ++ } ++ if (tpm_cshm) ++ printf("\nm-. TPM Configuration"); ++ printf("\n> "); ++ } ++ } else { ++ if (choice > maxmenu) { ++ if (tpm_cshm && choice == 36) ++ tpm_show_menu = 1; ++ } else { ++ // Choice is any of the detected boot devices ==> lets boot! ++ break; ++ } ++ } ++ } ++ ++ if (tpm_show_menu) { ++ tpm_show_menu = 0; ++ choice = 0; ++ if (digits == 0) ++ printf("TPM key pressed."); ++ else ++ digits = 0; + printf("\n"); + tpm_menu(); ++ printf("> "); + } +- if (scan_code >= 1 && scan_code <= maxmenu+1) +- break; ++ } ++ ++ if (choice == 0) // 10(0) ++ choice = 10; ++ ++ if (digits == 0 && choice < 36) { ++ printf("%c", keyboard_keys[choice-1]); ++ if (choice > 9) // Decode into a number. ++ printf("(%d)", choice); + } + printf("\n"); +- if (scan_code == 0x01) +- // ESC +- return; + + // Find entry and make top priority. +- int choice = scan_code - 1; + hlist_for_each_entry(pos, &BootList, node) { + if (! --choice) + break; +diff --git a/src/config.h b/src/config.h +index 93c8dbc..f85cc14 100644 +--- a/src/config.h ++++ b/src/config.h +@@ -19,7 +19,7 @@ + // Space to reserve in high-memory for tables + #define BUILD_MAX_HIGHTABLE (256*1024) + // Largest supported externaly facing drive id +-#define BUILD_MAX_EXTDRIVE 16 ++#define BUILD_MAX_EXTDRIVE 36 + // Number of bytes the smbios may be and still live in the f-segment + #define BUILD_MAX_SMBIOS_FSEG 600 + // Maximum number of bytes the mptable may be and still be copied to f-segment diff --git a/payloads/external/SeaBIOS/multiple_floppies.patch b/payloads/external/SeaBIOS/multiple_floppies.patch new file mode 100644 index 0000000..5249394 --- /dev/null +++ b/payloads/external/SeaBIOS/multiple_floppies.patch @@ -0,0 +1,207 @@ +diff --git a/src/block.h b/src/block.h +index f64e880..aaa236f 100644 +--- a/src/block.h ++++ b/src/block.h +@@ -2,7 +2,7 @@ + #define __BLOCK_H + + #include "types.h" // u32 +- ++#include "romfile.h" // struct romfile_s + + /**************************************************************** + * Disk command request +@@ -48,6 +48,7 @@ struct drive_s { + struct drive_s { + u8 type; // Driver type (DTYPE_*) + u8 floppy_type; // Type of floppy (only for floppy drives). ++ struct romfile_s *floppy_file; // Floppy file (only for virtual floppies). + struct chs_s lchs; // Logical CHS + u64 sectors; // Total sectors count + u32 cntl_id; // Unique id for a given driver type. +diff --git a/src/boot.c b/src/boot.c +index 9f82f3c..79f1e7d 100644 +--- a/src/boot.c ++++ b/src/boot.c +@@ -584,7 +584,7 @@ bcv_prepboot(void) + break; + case IPL_TYPE_FLOPPY: + map_floppy_drive(pos->drive); +- add_bev(IPL_TYPE_FLOPPY, 0); ++ add_bev(IPL_TYPE_FLOPPY, (u32)pos->drive); + break; + case IPL_TYPE_HARDDISK: + map_hd_drive(pos->drive); +@@ -733,6 +733,12 @@ do_boot(int seq_nr) + static void + do_boot(int seq_nr) + { ++ ++ int ret; ++ void *pos; ++ struct romfile_s *file; ++ struct drive_s *drive; ++ + if (! CONFIG_BOOT) + panic("Boot support not compiled in.\n"); + +@@ -744,6 +750,16 @@ do_boot(int seq_nr) + switch (ie->type) { + case IPL_TYPE_FLOPPY: + printf("Booting from Floppy...\n"); ++ drive = (struct drive_s *)ie->vector; ++ file = drive->floppy_file; ++ // File is NULL if a floppy is physical. ++ if (file) { ++ // Copy virtual floppy image into ram. ++ pos = (void *)drive->cntl_id; ++ ret = file->copy(file, pos, file->size); ++ if (ret < 0) ++ break; ++ } + boot_disk(0x00, CheckFloppySig); + break; + case IPL_TYPE_HARDDISK: +diff --git a/src/hw/floppy.c b/src/hw/floppy.c +index 9e6647d..5b37c6c 100644 +--- a/src/hw/floppy.c ++++ b/src/hw/floppy.c +@@ -107,7 +107,7 @@ struct floppyinfo_s FloppyInfo[] VARFSEG = { + }; + + struct drive_s * +-init_floppy(int floppyid, int ftype) ++init_floppy(int floppyid, int ftype, struct romfile_s *ffile) + { + if (ftype <= 0 || ftype >= ARRAY_SIZE(FloppyInfo)) { + dprintf(1, "Bad floppy type %d\n", ftype); +@@ -124,6 +124,7 @@ init_floppy(int floppyid, int ftype) + drive->type = DTYPE_FLOPPY; + drive->blksize = DISK_SECTOR_SIZE; + drive->floppy_type = ftype; ++ drive->floppy_file = ffile; + drive->sectors = (u64)-1; + + memcpy(&drive->lchs, &FloppyInfo[ftype].chs +@@ -134,7 +135,7 @@ addFloppy(int floppyid, int ftype) + static void + addFloppy(int floppyid, int ftype) + { +- struct drive_s *drive = init_floppy(floppyid, ftype); ++ struct drive_s *drive = init_floppy(floppyid, ftype, 0); + if (!drive) + return; + char *desc = znprintf(MAXDESCSIZE, "Floppy [drive %c]", 'A' + floppyid); +diff --git a/src/hw/ramdisk.c b/src/hw/ramdisk.c +index b9e9baa..a679385 100644 +--- a/src/hw/ramdisk.c ++++ b/src/hw/ramdisk.c +@@ -23,40 +23,69 @@ ramdisk_setup(void) + if (!CONFIG_FLASH_FLOPPY) + return; + +- // Find image. +- struct romfile_s *file = romfile_findprefix("floppyimg/", NULL); +- if (!file) +- return; +- const char *filename = file->name; +- u32 size = file->size; +- dprintf(3, "Found floppy file %s of size %d\n", filename, size); +- int ftype = find_floppy_type(size); +- if (ftype < 0) { +- dprintf(3, "No floppy type found for ramdisk size\n"); ++ struct romfile_s *file = NULL; ++ char *filename, *desc; ++ u32 size, max_size = 0; ++ int ftype; ++ void *pos; ++ struct drive_s *drive; ++ ++ // Find the max floppy size ++ for (;;) { ++ // Find the next image. ++ file = romfile_findprefix("floppyimg/", file); ++ if (!file) ++ break; ++ filename = file->name; ++ size = file->size; ++ dprintf(3, "Found floppy file %s of size %d\n", filename, size); ++ // Check if this size is valid. ++ ftype = find_floppy_type(size); ++ if (ftype < 0) { ++ dprintf(3, "No floppy type found for ramdisk size\n"); ++ } else { ++ if (size > max_size) ++ max_size = size; ++ } ++ } ++ if (max_size == 0) { ++ dprintf(3, "No floppies found\n"); + return; + } + + // Allocate ram for image. +- void *pos = memalign_tmphigh(PAGE_SIZE, size); ++ pos = memalign_tmphigh(PAGE_SIZE, max_size); + if (!pos) { + warn_noalloc(); + return; + } +- e820_add((u32)pos, size, E820_RESERVED); ++ e820_add((u32)pos, max_size, E820_RESERVED); ++ dprintf(3, "Allocate %u bytes for a floppy\n", max_size); + +- // Copy image into ram. +- int ret = file->copy(file, pos, size); +- if (ret < 0) +- return; +- +- // Setup driver. +- struct drive_s *drive = init_floppy((u32)pos, ftype); +- if (!drive) +- return; +- drive->type = DTYPE_RAMDISK; +- dprintf(1, "Mapping floppy %s to addr %p\n", filename, pos); +- char *desc = znprintf(MAXDESCSIZE, "Ramdisk [%s]", &filename[10]); +- boot_add_floppy(drive, desc, bootprio_find_named_rom(filename, 0)); ++ // Setup the floppy drivers. ++ file = NULL; ++ for (;;) { ++ // Find the next image. ++ file = romfile_findprefix("floppyimg/", file); ++ if (!file) ++ return; ++ filename = file->name; ++ size = file->size; ++ dprintf(3, "Found floppy file %s of size %d\n", filename, size); ++ ftype = find_floppy_type(size); ++ if (ftype < 0) { ++ dprintf(3, "No floppy type found for ramdisk size\n"); ++ } else { ++ // Setup driver. ++ drive = init_floppy((u32)pos, ftype, file); ++ if (!drive) ++ return; ++ drive->type = DTYPE_RAMDISK; ++ dprintf(1, "Mapping floppy %s to addr %p\n", filename, pos); ++ desc = znprintf(MAXDESCSIZE, "Ramdisk [%s]", &filename[10]); ++ boot_add_floppy(drive, desc, bootprio_find_named_rom(filename, 0)); ++ } ++ } + } + + static int +diff --git a/src/util.h b/src/util.h +index 9c06850..ce3a26d 100644 +--- a/src/util.h ++++ b/src/util.h +@@ -147,7 +147,8 @@ void dma_setup(void); + // hw/floppy.c + extern struct floppy_ext_dbt_s diskette_param_table2; + void floppy_setup(void); +-struct drive_s *init_floppy(int floppyid, int ftype); ++extern struct romfile_s *ffile; ++struct drive_s *init_floppy(int floppyid, int ftype, struct romfile_s *ffile); + int find_floppy_type(u32 size); + int floppy_process_op(struct disk_op_s *op); + void floppy_tick(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/32351 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf4efba31091a8678b51c2f6541d440c5cc6d37d Gerrit-Change-Number: 32351 Gerrit-PatchSet: 1 Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

5 32

[L] Change in coreboot[main]: ec/google: Add support for Realtek EC in ChromeOS EC
by Chao Jhan Bo (Code Review) May 31, 2025

May 31, 2025

Attention is currently required from: Boris Mittelberg, Caveh Jalali, Jon Murphy, Karthik Ramasubramanian, Keith Short, Paul Menzel, Subrata Banik. Chao Jhan Bo has posted comments on this change by Chao Jhan Bo. ( https://review.coreboot.org/c/coreboot/+/87544?usp=email ) Change subject: ec/google: Add support for Realtek EC in ChromeOS EC ...................................................................... Patch Set 23: (5 comments) File src/ec/google/chromeec/rtk.c: https://review.coreboot.org/c/coreboot/+/87544/comment/2f63b998_1562cdde?us… : PS21, Line 70: initial > initiated? Done https://review.coreboot.org/c/coreboot/+/87544/comment/354fed07_291db8c6?us… : PS21, Line 71: emi > EMI Done https://review.coreboot.org/c/coreboot/+/87544/comment/a8ff0b03_c3506da1?us… : PS21, Line 71: acpi > ACPI Done https://review.coreboot.org/c/coreboot/+/87544/comment/f2f342da_a4596ab7?us… : PS21, Line 71: need > need*s* Done https://review.coreboot.org/c/coreboot/+/87544/comment/bdcac89d_b1ecd465?us… : PS21, Line 74: printk(BIOS_INFO, "RTS5915 EMI initial.\n"); > Add it to the end, or do two: […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/87544?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I44118c7b61a7efcee81acdd04be90b5022007a41 Gerrit-Change-Number: 87544 Gerrit-PatchSet: 23 Gerrit-Owner: Chao Jhan Bo <jhan_bo_chao(a)realtek.corp-partner.google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Keith Short <keithshort(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jon Murphy <jpmurphy(a)google.com> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Keith Short <keithshort(a)chromium.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Sat, 31 May 2025 16:59:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

1 0

[L] Change in coreboot[main]: ec/google: Add support for Realtek EC in ChromeOS EC
by Chao Jhan Bo (Code Review) May 31, 2025

May 31, 2025

Attention is currently required from: Boris Mittelberg, Caveh Jalali, Chao Jhan Bo, Jon Murphy, Karthik Ramasubramanian, Keith Short, Subrata Banik. Hello Boris Mittelberg, Caveh Jalali, Keith Short, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/87544?usp=email to look at the new patch set (#23). Change subject: ec/google: Add support for Realtek EC in ChromeOS EC ...................................................................... ec/google: Add support for Realtek EC in ChromeOS EC This commit adds the necessary infrastructure to support Realtek EC controllers RTS5912/RTS5915 within the ChromeOS EC framework. TEST=With this commit and 87702, flash to brox board with realtek rts5915 Boot normally and got those message from ap console: [DEBUG] Google Chrome EC uptime: 698.137 seconds [DEBUG] Google Chrome AP resets since EC boot: 6 [DEBUG] Google Chrome most recent AP reset causes: [DEBUG] 635.380: 8 reset: during EC initialization [DEBUG] 645.374: 32775 shutdown: entering G3 [DEBUG] 680.284: 8 reset: during EC initialization [DEBUG] 684.586: 8 reset: during EC initialization [DEBUG] Google Chrome EC reset flags at last EC boot: soft [DEBUG] PNP: 0c09.0 init finished in 284 msecs Change-Id: I44118c7b61a7efcee81acdd04be90b5022007a41 Signed-off-by: Jhan Bo Chao <jhan_bo_chao(a)realtek.com> --- M src/ec/google/chromeec/Kconfig M src/ec/google/chromeec/Makefile.mk M src/ec/google/chromeec/ec.h M src/ec/google/chromeec/ec_lpc.c A src/ec/google/chromeec/mec.c A src/ec/google/chromeec/rtk.c M src/ec/google/common/Kconfig 7 files changed, 247 insertions(+), 107 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/87544/23 -- To view, visit https://review.coreboot.org/c/coreboot/+/87544?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I44118c7b61a7efcee81acdd04be90b5022007a41 Gerrit-Change-Number: 87544 Gerrit-PatchSet: 23 Gerrit-Owner: Chao Jhan Bo <jhan_bo_chao(a)realtek.corp-partner.google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Keith Short <keithshort(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jon Murphy <jpmurphy(a)google.com> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Keith Short <keithshort(a)chromium.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Chao Jhan Bo <jhan_bo_chao(a)realtek.corp-partner.google.com> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com>

1 0

[L] Change in coreboot[main]: ec/google: Add support for Realtek EC in ChromeOS EC
by Chao Jhan Bo (Code Review) May 31, 2025

May 31, 2025

Attention is currently required from: Boris Mittelberg, Caveh Jalali, Chao Jhan Bo, Jon Murphy, Karthik Ramasubramanian, Keith Short, Subrata Banik. Hello Boris Mittelberg, Caveh Jalali, Keith Short, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/87544?usp=email to look at the new patch set (#22). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: ec/google: Add support for Realtek EC in ChromeOS EC ...................................................................... ec/google: Add support for Realtek EC in ChromeOS EC This commit adds the necessary infrastructure to support Realtek EC controllers RTS5912/RTS5915 within the ChromeOS EC framework. TEST=With this commit and 87702, flash to brox board with realtek rts5915 Boot normally and got those message from ap console: [DEBUG] Google Chrome EC uptime: 698.137 seconds [DEBUG] Google Chrome AP resets since EC boot: 6 [DEBUG] Google Chrome most recent AP reset causes: [DEBUG] 635.380: 8 reset: during EC initialization [DEBUG] 645.374: 32775 shutdown: entering G3 [DEBUG] 680.284: 8 reset: during EC initialization [DEBUG] 684.586: 8 reset: during EC initialization [DEBUG] Google Chrome EC reset flags at last EC boot: soft [DEBUG] PNP: 0c09.0 init finished in 284 msecs Change-Id: I44118c7b61a7efcee81acdd04be90b5022007a41 Signed-off-by: Jhan Bo Chao <jhan_bo_chao(a)realtek.com> --- M src/ec/google/chromeec/Kconfig M src/ec/google/chromeec/Makefile.mk M src/ec/google/chromeec/ec.h M src/ec/google/chromeec/ec_lpc.c A src/ec/google/chromeec/mec.c A src/ec/google/chromeec/rtk.c M src/ec/google/common/Kconfig 7 files changed, 247 insertions(+), 107 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/87544/22 -- To view, visit https://review.coreboot.org/c/coreboot/+/87544?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I44118c7b61a7efcee81acdd04be90b5022007a41 Gerrit-Change-Number: 87544 Gerrit-PatchSet: 22 Gerrit-Owner: Chao Jhan Bo <jhan_bo_chao(a)realtek.corp-partner.google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Keith Short <keithshort(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jon Murphy <jpmurphy(a)google.com> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Keith Short <keithshort(a)chromium.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Chao Jhan Bo <jhan_bo_chao(a)realtek.corp-partner.google.com> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com>

1 0

[S] Change in coreboot[main]: mb/google/skywalker: Add RT1019 support for beep sound
by Yidi Lin (Code Review) May 31, 2025

May 31, 2025

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87887?usp=email ) Change subject: mb/google/skywalker: Add RT1019 support for beep sound ...................................................................... mb/google/skywalker: Add RT1019 support for beep sound Derive the audio amplifier from FW_CONFIG, and set up I2C and I2S for RT1019.RT1019 and RT9123 use the same GPIOs on the Skywalker reference design, so the same function is used to improve code reusability. Also pass the corresponding GPIO to the payload. BUG=b:417083722 BRANCH=none TEST=Build pass and test with Depthcharge change: https://chromium-review.googlesource.com/c/chromiumos/platform/depthcharge/… Check audio cmd in depthcharge with: firmware-shell: AUDIO CMD=audio 500 100 1 Change-Id: I512cd5c8635d08c6b6c54f04d11bf87c64d1b843 Signed-off-by: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87887 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yidi Lin <yidilin(a)google.com> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/mainboard/google/skywalker/chromeos.c M src/mainboard/google/skywalker/devicetree.cb M src/mainboard/google/skywalker/mainboard.c 3 files changed, 10 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Yidi Lin: Looks good to me, approved Yu-Ping Wu: Looks good to me, approved diff --git a/src/mainboard/google/skywalker/chromeos.c b/src/mainboard/google/skywalker/chromeos.c index 36be542..700d815 100644 --- a/src/mainboard/google/skywalker/chromeos.c +++ b/src/mainboard/google/skywalker/chromeos.c @@ -56,6 +56,11 @@ {GPIO_EN_SPKR.id, ACTIVE_HIGH, -1, "rt9123_spk_en"}, }; lb_add_gpios(gpios, rt9123_gpios, ARRAY_SIZE(rt9123_gpios)); + } else if (fw_config_probe(FW_CONFIG(AUDIO_AMP, AMP_RT1019))) { + struct lb_gpio rt1019_gpios[] = { + {GPIO_EN_SPKR.id, ACTIVE_HIGH, -1, "rt1019_spk_en"}, + }; + lb_add_gpios(gpios, rt1019_gpios, ARRAY_SIZE(rt1019_gpios)); } else if (fw_config_probe(FW_CONFIG(AUDIO_AMP, AMP_ALC5645))) { struct lb_gpio alc5645_gpios[] = { {GPIO_EN_SPKR.id, ACTIVE_HIGH, -1, "alc5645_spk_en"}, diff --git a/src/mainboard/google/skywalker/devicetree.cb b/src/mainboard/google/skywalker/devicetree.cb index bb54417..92f9c5d 100644 --- a/src/mainboard/google/skywalker/devicetree.cb +++ b/src/mainboard/google/skywalker/devicetree.cb @@ -7,6 +7,7 @@ fw_config field AUDIO_AMP 25 27 option AMP_RT9123 0 + option AMP_RT1019 1 option AMP_ALC5645 3 end end diff --git a/src/mainboard/google/skywalker/mainboard.c b/src/mainboard/google/skywalker/mainboard.c index bd18299..652d812 100644 --- a/src/mainboard/google/skywalker/mainboard.c +++ b/src/mainboard/google/skywalker/mainboard.c @@ -17,7 +17,7 @@ #define AFE_SE_SECURE_CON1 (AUDIO_BASE + 0x5634) -static void configure_rt9123(void) +static void configure_rt9123_rt1019(void) { /* SoC I2S */ gpio_set_mode(GPIO_I2SOUT1_BCK, GPIO_FUNC(DMIC0_DAT0, I2SOUT1_BCK)); @@ -49,8 +49,9 @@ /* Switch to normal mode */ write32p(AFE_SE_SECURE_CON1, 0x0); - if (fw_config_probe(FW_CONFIG(AUDIO_AMP, AMP_RT9123))) - configure_rt9123(); + if (fw_config_probe(FW_CONFIG(AUDIO_AMP, AMP_RT9123)) || + fw_config_probe(FW_CONFIG(AUDIO_AMP, AMP_RT1019))) + configure_rt9123_rt1019(); else if (fw_config_probe(FW_CONFIG(AUDIO_AMP, AMP_ALC5645))) configure_alc5645(); else -- To view, visit https://review.coreboot.org/c/coreboot/+/87887?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I512cd5c8635d08c6b6c54f04d11bf87c64d1b843 Gerrit-Change-Number: 87887 Gerrit-PatchSet: 6 Gerrit-Owner: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

1 0

[S] Change in coreboot[main]: mb/google/skywalker: Add ALC5645 support for beep sound
by Yidi Lin (Code Review) May 31, 2025

May 31, 2025

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87886?usp=email ) Change subject: mb/google/skywalker: Add ALC5645 support for beep sound ...................................................................... mb/google/skywalker: Add ALC5645 support for beep sound Derive the audio amplifier from FW_CONFIG, and set up I2C and I2S for ALC5645. Also pass the corresponding GPIO to the payload. BUG=b:359705470 BRANCH=none TEST=build ok and test audio cmd ok AUDIO CMD=audio 500 100 1 Signed-off-by: Cyril Chao <cyril.chao(a)mediatek.corp-partner.google.com> Change-Id: Ib53175f559eecb3d8b5104b12dabfd4793f65d08 Reviewed-on: https://review.coreboot.org/c/coreboot/+/87886 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yidi Lin <yidilin(a)google.com> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/mainboard/google/skywalker/chromeos.c M src/mainboard/google/skywalker/devicetree.cb M src/mainboard/google/skywalker/gpio.h M src/mainboard/google/skywalker/mainboard.c 4 files changed, 27 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Yidi Lin: Looks good to me, approved diff --git a/src/mainboard/google/skywalker/chromeos.c b/src/mainboard/google/skywalker/chromeos.c index 9b5a9c0..36be542 100644 --- a/src/mainboard/google/skywalker/chromeos.c +++ b/src/mainboard/google/skywalker/chromeos.c @@ -56,6 +56,11 @@ {GPIO_EN_SPKR.id, ACTIVE_HIGH, -1, "rt9123_spk_en"}, }; lb_add_gpios(gpios, rt9123_gpios, ARRAY_SIZE(rt9123_gpios)); + } else if (fw_config_probe(FW_CONFIG(AUDIO_AMP, AMP_ALC5645))) { + struct lb_gpio alc5645_gpios[] = { + {GPIO_EN_SPKR.id, ACTIVE_HIGH, -1, "alc5645_spk_en"}, + }; + lb_add_gpios(gpios, alc5645_gpios, ARRAY_SIZE(alc5645_gpios)); } } diff --git a/src/mainboard/google/skywalker/devicetree.cb b/src/mainboard/google/skywalker/devicetree.cb index 6ec4e25..bb54417 100644 --- a/src/mainboard/google/skywalker/devicetree.cb +++ b/src/mainboard/google/skywalker/devicetree.cb @@ -7,5 +7,6 @@ fw_config field AUDIO_AMP 25 27 option AMP_RT9123 0 + option AMP_ALC5645 3 end end diff --git a/src/mainboard/google/skywalker/gpio.h b/src/mainboard/google/skywalker/gpio.h index 208a3d9..4398a6c 100644 --- a/src/mainboard/google/skywalker/gpio.h +++ b/src/mainboard/google/skywalker/gpio.h @@ -31,6 +31,10 @@ #define GPIO_I2SOUT1_BCK GPIO(DMIC0_DAT0) #define GPIO_I2SOUT1_LRCK GPIO(DMIC1_CLK) #define GPIO_I2SOUT1_DOUT GPIO(DMIC1_DAT0) +#define GPIO_I2SOUT0_MCK GPIO(I2SOUT0_MCK) +#define GPIO_I2SOUT0_BCK GPIO(I2SOUT0_BCK) +#define GPIO_I2SOUT0_LRCK GPIO(I2SOUT0_LRCK) +#define GPIO_I2SOUT0_DOUT GPIO(I2SOUT0_DO) void setup_chromeos_gpios(void); diff --git a/src/mainboard/google/skywalker/mainboard.c b/src/mainboard/google/skywalker/mainboard.c index f6dc5ca..bd18299 100644 --- a/src/mainboard/google/skywalker/mainboard.c +++ b/src/mainboard/google/skywalker/mainboard.c @@ -6,6 +6,7 @@ #include <gpio.h> #include <soc/bl31.h> #include <soc/dpm_v2.h> +#include <soc/i2c.h> #include <soc/msdc.h> #include <soc/mt6359p.h> #include <soc/mtcmos.h> @@ -26,6 +27,20 @@ printk(BIOS_INFO, "%s: AMP configuration done\n", __func__); } +static void configure_alc5645(void) +{ + /* SoC I2S */ + gpio_set_mode(GPIO_I2SOUT0_MCK, GPIO_FUNC(I2SOUT0_MCK, I2SOUT0_MCK)); + gpio_set_mode(GPIO_I2SOUT0_BCK, GPIO_FUNC(I2SOUT0_BCK, I2SOUT0_BCK)); + gpio_set_mode(GPIO_I2SOUT0_LRCK, GPIO_FUNC(I2SOUT0_LRCK, I2SOUT0_LRCK)); + gpio_set_mode(GPIO_I2SOUT0_DOUT, GPIO_FUNC(I2SOUT0_DO, I2SOUT0_DO)); + + /* Init I2C bus timing register for audio codecs */ + mtk_i2c_bus_init(I2C2, I2C_SPEED_STANDARD); + + printk(BIOS_INFO, "%s: AMP configuration done\n", __func__); +} + static void configure_audio(void) { mtcmos_audio_power_on(); @@ -36,6 +51,8 @@ if (fw_config_probe(FW_CONFIG(AUDIO_AMP, AMP_RT9123))) configure_rt9123(); + else if (fw_config_probe(FW_CONFIG(AUDIO_AMP, AMP_ALC5645))) + configure_alc5645(); else printk(BIOS_WARNING, "Unknown amp\n"); } -- To view, visit https://review.coreboot.org/c/coreboot/+/87886?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib53175f559eecb3d8b5104b12dabfd4793f65d08 Gerrit-Change-Number: 87886 Gerrit-PatchSet: 6 Gerrit-Owner: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

1 0

[S] Change in coreboot[main]: mb/google/skywalker: Add RT9123 support for beep sound
by Yidi Lin (Code Review) May 31, 2025

May 31, 2025

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87885?usp=email ) Change subject: mb/google/skywalker: Add RT9123 support for beep sound ...................................................................... mb/google/skywalker: Add RT9123 support for beep sound Derive the audio amplifier from FW_CONFIG, and set up I2S for RT9123. Also pass the corresponding GPIO to the payload. BUG=b:359705470 BRANCH=none TEST=Build pass and test with Depthcahrge change: https://chromium-review.googlesource.com/c/chromiumos/platform/depthcharge/… https://chromium-review.googlesource.com/c/chromiumos/platform/depthcharge/… Check audio cmd in depthcharge with: firmware-shell: AUDIO CMD=audio 500 100 1 Signed-off-by: Cyril Chao <cyril.chao(a)mediatek.corp-partner.google.com> Change-Id: I3b9b347ad8b754cbc02d942da9a7b0886c4c3cc4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/87885 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yidi Lin <yidilin(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> --- M src/mainboard/google/skywalker/chromeos.c M src/mainboard/google/skywalker/devicetree.cb M src/mainboard/google/skywalker/gpio.h M src/mainboard/google/skywalker/mainboard.c 4 files changed, 49 insertions(+), 0 deletions(-) Approvals: Yu-Ping Wu: Looks good to me, approved Yidi Lin: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve build bot (Jenkins): Verified diff --git a/src/mainboard/google/skywalker/chromeos.c b/src/mainboard/google/skywalker/chromeos.c index 26f0644..9b5a9c0 100644 --- a/src/mainboard/google/skywalker/chromeos.c +++ b/src/mainboard/google/skywalker/chromeos.c @@ -3,6 +3,7 @@ #include <boot/coreboot_tables.h> #include <drivers/tpm/cr50.h> #include <ec/google/chromeec/ec.h> +#include <fw_config.h> #include <gpio.h> #include "gpio.h" @@ -31,6 +32,7 @@ gpio_output(GPIO_AP_FP_FW_UP_STRAP, 0); gpio_output(GPIO_EN_PWR_FP, 0); gpio_output(GPIO_FP_RST_1V8_S3_L, 0); + gpio_output(GPIO_EN_SPKR, 0); } void fill_lb_gpios(struct lb_gpios *gpios) @@ -48,6 +50,13 @@ }; lb_add_gpios(gpios, sd_card_gpios, ARRAY_SIZE(sd_card_gpios)); } + + if (fw_config_probe(FW_CONFIG(AUDIO_AMP, AMP_RT9123))) { + struct lb_gpio rt9123_gpios[] = { + {GPIO_EN_SPKR.id, ACTIVE_HIGH, -1, "rt9123_spk_en"}, + }; + lb_add_gpios(gpios, rt9123_gpios, ARRAY_SIZE(rt9123_gpios)); + } } int cr50_plat_irq_status(void) diff --git a/src/mainboard/google/skywalker/devicetree.cb b/src/mainboard/google/skywalker/devicetree.cb index c76b4e6..6ec4e25 100644 --- a/src/mainboard/google/skywalker/devicetree.cb +++ b/src/mainboard/google/skywalker/devicetree.cb @@ -3,3 +3,9 @@ chip soc/mediatek/mt8189 device cpu_cluster 0 on end end + +fw_config + field AUDIO_AMP 25 27 + option AMP_RT9123 0 + end +end diff --git a/src/mainboard/google/skywalker/gpio.h b/src/mainboard/google/skywalker/gpio.h index 8a1925a..208a3d9 100644 --- a/src/mainboard/google/skywalker/gpio.h +++ b/src/mainboard/google/skywalker/gpio.h @@ -27,6 +27,10 @@ #define GPIO_SD_CD_ODL GPIO(GBE_INTR) #define GPIO_HDMI_HPD_1V8_ODL GPIO(CONN_TOP_CLK) #define GPIO_AP_HDMI_RST_ODL GPIO(GBE_TXC) +#define GPIO_EN_SPKR GPIO(GPIO05) +#define GPIO_I2SOUT1_BCK GPIO(DMIC0_DAT0) +#define GPIO_I2SOUT1_LRCK GPIO(DMIC1_CLK) +#define GPIO_I2SOUT1_DOUT GPIO(DMIC1_DAT0) void setup_chromeos_gpios(void); diff --git a/src/mainboard/google/skywalker/mainboard.c b/src/mainboard/google/skywalker/mainboard.c index 74c3ea7..f6dc5ca 100644 --- a/src/mainboard/google/skywalker/mainboard.c +++ b/src/mainboard/google/skywalker/mainboard.c @@ -1,16 +1,45 @@ /* SPDX-License-Identifier: GPL-2.0-only OR MIT */ #include <device/device.h> +#include <device/mmio.h> +#include <fw_config.h> #include <gpio.h> #include <soc/bl31.h> #include <soc/dpm_v2.h> #include <soc/msdc.h> #include <soc/mt6359p.h> +#include <soc/mtcmos.h> #include <soc/spm_common.h> #include <soc/usb.h> #include "gpio.h" +#define AFE_SE_SECURE_CON1 (AUDIO_BASE + 0x5634) + +static void configure_rt9123(void) +{ + /* SoC I2S */ + gpio_set_mode(GPIO_I2SOUT1_BCK, GPIO_FUNC(DMIC0_DAT0, I2SOUT1_BCK)); + gpio_set_mode(GPIO_I2SOUT1_LRCK, GPIO_FUNC(DMIC1_CLK, I2SOUT1_LRCK)); + gpio_set_mode(GPIO_I2SOUT1_DOUT, GPIO_FUNC(DMIC1_DAT0, I2SOUT1_DO)); + + printk(BIOS_INFO, "%s: AMP configuration done\n", __func__); +} + +static void configure_audio(void) +{ + mtcmos_audio_power_on(); + mtcmos_protect_audio_bus(); + + /* Switch to normal mode */ + write32p(AFE_SE_SECURE_CON1, 0x0); + + if (fw_config_probe(FW_CONFIG(AUDIO_AMP, AMP_RT9123))) + configure_rt9123(); + else + printk(BIOS_WARNING, "Unknown amp\n"); +} + static void power_on_fpmcu(void) { /* Power on the fingerprint MCU */ @@ -24,6 +53,7 @@ setup_usb_host(); spm_init(); power_on_fpmcu(); + configure_audio(); if (CONFIG(SKYWALKER_SDCARD_INIT)) mtk_msdc_configure_sdcard(); -- To view, visit https://review.coreboot.org/c/coreboot/+/87885?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3b9b347ad8b754cbc02d942da9a7b0886c4c3cc4 Gerrit-Change-Number: 87885 Gerrit-PatchSet: 5 Gerrit-Owner: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jarried Lin <jarried.lin(a)mediatek.com>

1 0

[S] Change in coreboot[main]: mb/google/skywalker: Add SD card configurations
by Yidi Lin (Code Review) May 31, 2025

May 31, 2025

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87884?usp=email ) Change subject: mb/google/skywalker: Add SD card configurations ...................................................................... mb/google/skywalker: Add SD card configurations Pass SD card detect GPIO to payloads for SD card detection and configure SD card in ramstage. Currently, only Skywalker supports the SD card. BUG=b:379008996 BRANCH=none TEST=Build pass. Check storage in depthcharge. firmware-shell: storage init * 0: UFS LUN 0 1: removable mtk_mmc Signed-off-by: Mengqi Zhang <mengqi.zhang(a)mediatek.corp-partner.google.com> Change-Id: I3b198d5e237006c299581ab4a5da8577dbcca7a6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/87884 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Yidi Lin <yidilin(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/skywalker/Kconfig M src/mainboard/google/skywalker/chromeos.c M src/mainboard/google/skywalker/mainboard.c 3 files changed, 17 insertions(+), 0 deletions(-) Approvals: Yidi Lin: Looks good to me, approved Yu-Ping Wu: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/skywalker/Kconfig b/src/mainboard/google/skywalker/Kconfig index b5134a529..49b3d21 100644 --- a/src/mainboard/google/skywalker/Kconfig +++ b/src/mainboard/google/skywalker/Kconfig @@ -9,6 +9,9 @@ if BOARD_GOOGLE_SKYWALKER_COMMON +config SKYWALKER_SDCARD_INIT + def_bool BOARD_GOOGLE_SKYWALKER + config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES select VBOOT_VBNV_FLASH @@ -31,6 +34,8 @@ select FW_CONFIG select FW_CONFIG_SOURCE_CHROMEEC_CBI select RTC + select COMMONLIB_STORAGE + select COMMONLIB_STORAGE_MMC config MAINBOARD_DIR string diff --git a/src/mainboard/google/skywalker/chromeos.c b/src/mainboard/google/skywalker/chromeos.c index c5b9f8e..26f0644 100644 --- a/src/mainboard/google/skywalker/chromeos.c +++ b/src/mainboard/google/skywalker/chromeos.c @@ -41,6 +41,13 @@ {GPIO_GSC_AP_INT_ODL.id, ACTIVE_HIGH, -1, "TPM interrupt"}, }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); + + if (CONFIG(SKYWALKER_SDCARD_INIT)) { + struct lb_gpio sd_card_gpios[] = { + { GPIO_SD_CD_ODL.id, ACTIVE_LOW, -1, "SD card detect" }, + }; + lb_add_gpios(gpios, sd_card_gpios, ARRAY_SIZE(sd_card_gpios)); + } } int cr50_plat_irq_status(void) diff --git a/src/mainboard/google/skywalker/mainboard.c b/src/mainboard/google/skywalker/mainboard.c index af27c82..74c3ea7 100644 --- a/src/mainboard/google/skywalker/mainboard.c +++ b/src/mainboard/google/skywalker/mainboard.c @@ -4,6 +4,8 @@ #include <gpio.h> #include <soc/bl31.h> #include <soc/dpm_v2.h> +#include <soc/msdc.h> +#include <soc/mt6359p.h> #include <soc/spm_common.h> #include <soc/usb.h> @@ -23,6 +25,9 @@ spm_init(); power_on_fpmcu(); + if (CONFIG(SKYWALKER_SDCARD_INIT)) + mtk_msdc_configure_sdcard(); + if (CONFIG(ARM64_USE_ARM_TRUSTED_FIRMWARE)) register_reset_to_bl31(GPIO_AP_EC_WARM_RST_REQ.id, true); } -- To view, visit https://review.coreboot.org/c/coreboot/+/87884?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3b198d5e237006c299581ab4a5da8577dbcca7a6 Gerrit-Change-Number: 87884 Gerrit-PatchSet: 5 Gerrit-Owner: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-CC: Mengqi Zhang <mengqi.zhang(a)mediatek.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

1 0

[XS] Change in coreboot[main]: payloads/libpayload/Makefile.mk: Replace nm with $(NM)
by NyeonWoo Kim (Code Review) May 31, 2025

May 31, 2025

NyeonWoo Kim has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/87906?usp=email ) Change subject: payloads/libpayload/Makefile.mk: Replace nm with $(NM) ...................................................................... payloads/libpayload/Makefile.mk: Replace nm with $(NM) I got 'nm' usage error when i built coreinfo payload. nm: unrecognized option '--no-weak' it seems that this is occurred by using nm for host, not for coreboot. So, I replace nm with $(NM) Change-Id: I0a0a04b351c9131b1238e8cc7e63e396820494d9 Signed-off-by: NyeonWoo Kim <knw0507(a)naver.com> --- M payloads/libpayload/Makefile.mk 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/87906/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87906?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0a0a04b351c9131b1238e8cc7e63e396820494d9 Gerrit-Change-Number: 87906 Gerrit-PatchSet: 2 Gerrit-Owner: NyeonWoo Kim Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0