February 2020 - coreboot-gerrit

Change in coreboot[master]: Doc/mb/asus: Add H110M-E/M.2 Documentation

by Pavel Sayekat (Code Review)

Pavel Sayekat has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35011 ) Change subject: Doc/mb/asus: Add H110M-E/M.2 Documentation ...................................................................... Doc/mb/asus: Add H110M-E/M.2 Documentation Followed and adapted from the ASRock H110M-DVS Documentation Signed-off-by: Pavel Sayekat <pavelsayekat(a)gmail.com> Change-Id: I6c5aad50b513935eab70b502df1d95fb3413fa6b --- A Documentation/mainboard/asus/h110m-e_m2.md 1 file changed, 136 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/35011/1 diff --git a/Documentation/mainboard/asus/h110m-e_m2.md b/Documentation/mainboard/asus/h110m-e_m2.md new file mode 100644 index 0000000..134dca8 --- /dev/null +++ b/Documentation/mainboard/asus/h110m-e_m2.md @@ -0,0 +1,136 @@ +# ASUS H110M-E/M.2 + +This page describes how to run coreboot on the [ASUS H110M-E/M.2]. + +## Required proprietary blobs + +Mainboard is based on Intel Skylake/Kaby Lake processor and H110 Chipset. +Intel company provides [Firmware Support Package (2.0)](../../soc/intel/fsp/index.md) +(intel FSP 2.0) to initialize this generation silicon. Please see this +[document](../../soc/intel/code_development_model/code_development_model.md). + +FSP Information: + +```eval_rst ++-----------------------------+-------------------+-------------------+ +| FSP Project Name | Directory | Specification | ++-----------------------------+-------------------+-------------------+ +| 7th Generation Intel® Core™ | KabylakeFspBinPkg | 2.0 | +| processors and chipsets | | | +| (formerly Kaby Lake) | | | ++-----------------------------+-------------------+-------------------+ +``` + +## Building coreboot + +The following steps set the default parameters for this board to build a +fully working image: + +```bash +make distclean +touch .config +./util/scripts/config --enable VENDOR_ASUS +./util/scripts/config --enable BOARD_ASUS_H110M_E_M2 +./util/scripts/config --enable CONFIG_ADD_FSP_BINARIES +./util/scripts/config --enable CONFIG_FSP_USE_REPO +./util/scripts/config --set-str REALTEK_8168_MACADDRESS "xx:xx:xx:xx:xx:xx" +make olddefconfig +``` + +However, it is strongly advised to use `make menuconfig` afterwards +(or instead), so that you can see all of the settings. + +Use the following command to disable the serial console if debugging +output is not required: + +```bash +./util/scripts/config --disable CONSOLE_SERIAL +``` + +However, a more flexible method is to change the console log level from +within an OS using `util/nvramtool`, or with the `nvramcui` payload. + +Now, run `make` to build the coreboot image. + +## Flashing coreboot + +### Internal programming + +The main SPI flash can be accessed using [flashrom]. By default, only +the BIOS region of the flash is writable. If you wish to change any +other region, such as the Management Engine or firmware descriptor, then +an external programmer is required (unless you find a clever way around +the flash protection). More information about this [here](../../flash_tutorial/index.md). + +### External programming + +The flash chip is a 16 MiB socketed DIP-8 chip. Specifically, it's a +GIgaDevice GD25B128CPIG, whose datasheet can be found [here][GD25B128CPIG]. +The chip is located to the bottom right-hand side of the board. For +a precise location, refer to section 1.3 (Motherboard Layout) of the +[H110M-E/M.2 manual], where the chip is labelled "128Mb BIOS". Take note of +the chip's orientation, remove it from its socket, and flash it with +an external programmer. For reference, the notch in the chip should be +facing towards the bottom of the board. + +## Known issues + +- The VGA port doesn't work. Discrete graphic card is used as primary + device for display output (if CONFIG_ONBOARD_VGA_IS_PRIMARY is not + set). Dynamic switching between iGPU and PEG is not yet supported. + +- SuperIO GPIO pin is used to reset Realtek chip. However, since the + Logical Device 7 (GPIO7, GPIO8) is not initialized, the network + chip is in a reset state all the time. + +## Untested + +- parallel port +- PS/2 keyboard +- PS/2 mouse +- EHCI debug +- TPM +- infrared module +- chassis intrusion header +- chassis speaker header + +## Working + +- integrated graphics init with libgfxinit (see [Known issues](#known-issues)) +- PCIe x1 +- PEG x16 Gen3 +- SATA +- USB +- serial port +- onboard audio +- using `me_cleaner` +- using `flashrom` + +## TODO + +- NCT5539D GPIOs +- onboard network (see [Known issues](#known-issues)) +- S3 suspend/resume +- Wake-on-LAN +- hardware monitor + +## Technology + +```eval_rst ++------------------+--------------------------------------------------+ +| CPU | Intel Skylake/Kaby Lake (LGA1151) | ++------------------+--------------------------------------------------+ +| PCH | Intel Sunrise Point H110 | ++------------------+--------------------------------------------------+ +| Super I/O | Nuvoton NCT5539D | ++------------------+--------------------------------------------------+ +| EC | None | ++------------------+--------------------------------------------------+ +| Coprocessor | Intel Management Engine | ++------------------+--------------------------------------------------+ +``` + +[ASUS H110M-E/M.2]: https://www.asus.com/Motherboards/H110M-E-M-2/overview/ +[GD25B128CPIG]: https://www.gigadevice.com/datasheet/gd25b127d/ [The closest match found] +[flashrom]: https://flashrom.org/Flashrom +[ASUS H110M-E/M.2 manual]: https://dlcdnets.asus.com/pub/ASUS/mb/LGA1151/H110M-E_M2/E11622_H110M-E_M2_… -- To view, visit https://review.coreboot.org/c/coreboot/+/35011 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6c5aad50b513935eab70b502df1d95fb3413fa6b Gerrit-Change-Number: 35011 Gerrit-PatchSet: 1 Gerrit-Owner: Pavel Sayekat Gerrit-MessageType: newchange

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Change in coreboot[master]: src/mainboard/asus: Add h110m-e_m2 mainboard support

by Pavel Sayekat (Code Review)

Pavel Sayekat has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34603 ) Change subject: src/mainboard/asus: Add h110m-e_m2 mainboard support ...................................................................... src/mainboard/asus: Add h110m-e_m2 mainboard support Signed-off-by: Pavel Sayekat <pavelsayekat(a)gmail.com> Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c --- A src/mainboard/asus/h110m-e_m2/6776.txt A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/acpi_tables.c A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/gpio.txt A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 23 files changed, 1,875 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/1 diff --git a/src/mainboard/asus/h110m-e_m2/6776.txt b/src/mainboard/asus/h110m-e_m2/6776.txt new file mode 100644 index 0000000..9969ca7 --- /dev/null +++ b/src/mainboard/asus/h110m-e_m2/6776.txt @@ -0,0 +1,10 @@ +acpi/superio.asl:#define NCT6776_SHOW_PP +acpi/superio.asl:#define NCT6776_SHOW_SP1 +acpi/superio.asl:#define NCT6776_SHOW_KBC +acpi/superio.asl:#define NCT6776_SHOW_HWM +acpi/superio.asl:#undef NCT6776_SHOW_GPIO +acpi/superio.asl:#include <superio/nuvoton/nct6776/acpi/superio.asl> +gpio.txt:acpi/superio.asl:#undef NCT6776_SHOW_GPIO +gpio.txt:acpi/superio.asl:#undef NCT6776_SHOW_GPIO +gpio.txt:gpio.txt:acpi/superio.asl:#undef NCT6776_SHOW_GPIO +gpio.txt:gpio.txt:acpi/superio.asl:#undef NCT6776_SHOW_GPIO diff --git a/src/mainboard/asus/h110m-e_m2/Kconfig b/src/mainboard/asus/h110m-e_m2/Kconfig new file mode 100644 index 0000000..55a21cf --- /dev/null +++ b/src/mainboard/asus/h110m-e_m2/Kconfig @@ -0,0 +1,53 @@ +if BOARD_ASUS-H110M_E-M2 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select INTEL_GMA_HAVE_VBT + select INTEL_INT15 + select SOC_INTEL_KABYLAKE + select SKYLAKE_SOC_PCH_H + select GENERIC_SPD_BIN + select SUPERIO_NUVOTON_NCT5539D + select SUPERIO_NUVOTON_NCT5539D_COM_A + select REALTEK_8168_RESET + select RT8168_SET_LED_MODE + +config IRQ_SLOT_COUNT + int + default 18 + +config MAINBOARD_DIR + string + default "asus/h110m" + +config MAINBOARD_PART_NUMBER + string + default "H110M" + +config MAX_CPUS + int + default 8 + +config DEVICETREE + string + default "devicetree.cb" + +config PRERAM_CBMEM_CONSOLE_SIZE + hex + default 0xd00 + +config DIMM_SPD_SIZE + int + default 512 #DDR4 + +# This is overridden if CMOS is used for configuration values. +config MAINBOARD_POWER_ON_AFTER_POWER_FAIL + bool + default n + +endif diff --git a/src/mainboard/asus/h110m-e_m2/Kconfig.name b/src/mainboard/asus/h110m-e_m2/Kconfig.name new file mode 100644 index 0000000..788594c --- /dev/null +++ b/src/mainboard/asus/h110m-e_m2/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ASUS_H110M_E-M.2 + bool "H110M_E-M.2" diff --git a/src/mainboard/asus/h110m-e_m2/Makefile.inc b/src/mainboard/asus/h110m-e_m2/Makefile.inc new file mode 100644 index 0000000..ce6cf80 --- /dev/null +++ b/src/mainboard/asus/h110m-e_m2/Makefile.inc @@ -0,0 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## Copyright (C) 2016 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +subdirs-y += spd +bootblock-y += bootblock.c + +ramstage-y += mainboard.c +ramstage-y += ramstage.c +ramstage-y += hda_verb.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asus/h110m-e_m2/acpi/dptf.asl b/src/mainboard/asus/h110m-e_m2/acpi/dptf.asl new file mode 100644 index 0000000..4453f3b --- /dev/null +++ b/src/mainboard/asus/h110m-e_m2/acpi/dptf.asl @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * Copyright (C) 2019 Maxim Polyakov <max.senia.poliak(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 98 +#define DPTF_CPU_CRITICAL 125 +#define DPTF_CPU_ACTIVE_AC0 91 +#define DPTF_CPU_ACTIVE_AC1 85 +#define DPTF_CPU_ACTIVE_AC2 83 +#define DPTF_CPU_ACTIVE_AC3 80 +#define DPTF_CPU_ACTIVE_AC4 75 + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 }, + +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 10000, /* PowerLimitMinimum */ + 31000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 28000, /* TimeWindowMaximum */ + 100 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 15000, /* PowerLimitMinimum */ + 65000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 28000, /* TimeWindowMaximum */ + 100 /* StepSize */ + } +}) + +/* Include DPTF */ +#include <soc/intel/skylake/acpi/dptf/dptf.asl> diff --git a/src/mainboard/asus/h110m-e_m2/acpi/ec.asl b/src/mainboard/asus/h110m-e_m2/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/asus/h110m-e_m2/acpi/ec.asl diff --git a/src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl b/src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl diff --git a/src/mainboard/asus/h110m-e_m2/acpi/superio.asl b/src/mainboard/asus/h110m-e_m2/acpi/superio.asl new file mode 100644 index 0000000..b671e3c --- /dev/null +++ b/src/mainboard/asus/h110m-e_m2/acpi/superio.asl @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Tristan Corrick <tristan(a)corrick.kiwi> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define SUPERIO_DEV SIO0 +#define SUPERIO_PNP_BASE 0x2e +#define NCT6776_SHOW_PP +#define NCT6776_SHOW_SP1 +#define NCT6776_SHOW_KBC +#define NCT6776_SHOW_HWM + +#undef NCT6776_SHOW_GPIO + +#include <superio/nuvoton/nct6776/acpi/superio.asl> diff --git a/src/mainboard/asus/h110m-e_m2/acpi_tables.c b/src/mainboard/asus/h110m-e_m2/acpi_tables.c new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/asus/h110m-e_m2/acpi_tables.c diff --git a/src/mainboard/asus/h110m-e_m2/board_info.txt b/src/mainboard/asus/h110m-e_m2/board_info.txt new file mode 100644 index 0000000..23fd8e6 --- /dev/null +++ b/src/mainboard/asus/h110m-e_m2/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asus.com/Motherboards/H110M-E-M-2/ +ROM package: DIP-8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: y +Release year: 2017 diff --git a/src/mainboard/asus/h110m-e_m2/bootblock.c b/src/mainboard/asus/h110m-e_m2/bootblock.c new file mode 100644 index 0000000..eb019c2 --- /dev/null +++ b/src/mainboard/asus/h110m-e_m2/bootblock.c @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * Copyright (C) 2019 Pavel Sayekat <pavelsayekat(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <soc/gpio.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct5539d/nct5539d.h> +#include "include/gpio.h" + +static void early_config_superio(void) +{ + const pnp_devfn_t serial_dev = PNP_DEV(0x2e, NCT5539D_SP1); + nuvoton_enable_serial(serial_dev, CONFIG_TTYS0_BASE); +} + +static void early_config_gpio(void) +{ + /* This is a hack for FSP because it does things in MemoryInit() + * which it shouldn't do. We have to prepare certain gpios here + * because of the brokenness in FSP. */ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} + +void bootblock_mainboard_init(void) +{ + early_config_gpio(); +} + +void bootblock_mainboard_early_init(void) +{ + early_config_superio(); +} diff --git a/src/mainboard/asus/h110m-e_m2/cmos.default b/src/mainboard/asus/h110m-e_m2/cmos.default new file mode 100644 index 0000000..3296093 --- /dev/null +++ b/src/mainboard/asus/h110m-e_m2/cmos.default @@ -0,0 +1,4 @@ +boot_option=Fallback +debug_level=Debug +power_on_after_fail=Disable +nmi=Enable diff --git a/src/mainboard/asus/h110m-e_m2/cmos.layout b/src/mainboard/asus/h110m-e_m2/cmos.layout new file mode 100644 index 0000000..916db62 --- /dev/null +++ b/src/mainboard/asus/h110m-e_m2/cmos.layout @@ -0,0 +1,125 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2016 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +#392 3 r 0 unused +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +#411 5 r 0 unused + +# coreboot config options: bootloader +#Used by ChromeOS: +416 128 r 0 vbnv +#544 440 r 0 unused + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/asus/h110m-e_m2/data.vbt b/src/mainboard/asus/h110m-e_m2/data.vbt new file mode 100644 index 0000000..fb03cca --- /dev/null +++ b/src/mainboard/asus/h110m-e_m2/data.vbt Binary files differ diff --git a/src/mainboard/asus/h110m-e_m2/devicetree.cb b/src/mainboard/asus/h110m-e_m2/devicetree.cb new file mode 100644 index 0000000..cdc6c2d --- /dev/null +++ b/src/mainboard/asus/h110m-e_m2/devicetree.cb @@ -0,0 +1,388 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2017 Intel Corporation. +## Copyright (C) 2019 Pavel Sayekat <pavelsayekat(a)gmail.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip soc/intel/skylake + + # Enable deep Sx states + register "deep_s3_enable_ac" = "0" + register "deep_s3_enable_dc" = "0" + register "deep_s5_enable_ac" = "0" + register "deep_s5_enable_dc" = "0" + register "deep_sx_config" = "DSX_EN_WAKE_PIN" + + register "eist_enable" = "1" + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_B" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # Enable DPTF + register "dptf_enable" = "1" + + # FSP Configuration + register "SmbusEnable" = "1" + register "ScsEmmcEnabled" = "0" + register "ScsEmmcHs400Enabled" = "0" + register "ScsSdCardEnabled" = "0" + register "HeciEnabled" = "0" + register "SkipExtGfxScan" = "0" + register "PrimaryDisplay" = "Display_PEG" + register "Device4Enable" = "1" + register "SaGv" = "SaGv_Enabled" + register "PmTimerDisabled" = "0" + register "EnableAzalia" = "1" + register "DspEnable" = "0" + + register "pirqa_routing" = "PCH_IRQ11" + register "pirqb_routing" = "PCH_IRQ10" + register "pirqc_routing" = "PCH_IRQ11" + register "pirqd_routing" = "PCH_IRQ11" + register "pirqe_routing" = "PCH_IRQ11" + register "pirqf_routing" = "PCH_IRQ11" + register "pirqg_routing" = "PCH_IRQ11" + register "pirqh_routing" = "PCH_IRQ11" + + # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch + # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s + register "PmConfigSlpS3MinAssert" = "0x02" + + # SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s + register "PmConfigSlpS4MinAssert" = "0x04" + + # SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s + register "PmConfigSlpSusMinAssert" = "0x03" + + # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s + register "PmConfigSlpAMinAssert" = "0x03" + + # VR Settings Configuration for 5 Domains + #+----------------+-------+-------+-------------+-------------+-------+ + #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT | + #+----------------+-------+-------+-------------+-------------+-------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | 0 | + #| IccMax | 7A | 34A | 34A | 35A | 35A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V | + #+----------------+-------+-------+-------------+-------------+-------+ + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x10, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x0, \ + .voltage_limit = 0x0 \ + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x14, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x0, \ + .voltage_limit = 0x0 \ + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x14, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x0 ,\ + .voltage_limit = 0x0 \ + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x14, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x0, \ + .voltage_limit = 0x0 \ + }" + + register "EnableLan" = "0" + register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V + + register "PmTimerDisabled" = "0" + + # USB + register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[2]" = "USB2_PORT_MID(OC4)" + register "usb2_ports[3]" = "USB2_PORT_MID(OC4)" + register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" + register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" + register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[8]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[9]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[10]" = "USB2_PORT_MID(OC1)" + register "usb2_ports[11]" = "USB2_PORT_MID(OC1)" + register "usb2_ports[12]" = "USB2_PORT_MID(OC_SKIP)" + register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)" + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)" + register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC_SKIP)" + + # SATA + register "EnableSata" = "1" + register "SataSalpSupport" = "1" + register "SataPortsEnable" = "{ \ + [0] = 1, \ + [1] = 1, \ + [2] = 1, \ + [3] = 1, \ + [4] = 1, \ + [5] = 1, \ + [6] = 1, \ + [7] = 1, \ + }" + + # PCH UART, SPI, I2C + register "SerialIoDevMode" = "{ \ + [PchSerialIoIndexI2C0] = PchSerialIoPci, \ + [PchSerialIoIndexI2C1] = PchSerialIoPci, \ + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \ + [PchSerialIoIndexSpi0] = PchSerialIoPci, \ + [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart0] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart2] = PchSerialIoDisabled, \ + }" + + # Set params for PEG 0:1:0 + register "Peg0MaxLinkWidth" = "Peg0_x16" + # Configure PCIe clockgen in PCH + # PEG0 uses SRCCLKREQ0 and CLKSRC0 + register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqNumber[0]" = "0" + register "PcieRpClkSrcNumber[0]" = "0" + + # Enable Root port 6(x1) for LAN. + register "PcieRpEnable[5]" = "1" + # Enable CLKREQ# + register "PcieRpClkReqSupport[5]" = "1" + # Use SRCCLKREQ1# + register "PcieRpClkReqNumber[5]" = "1" + # Enable Advanced Error Reporting + register "PcieRpAdvancedErrorReporting[5]" = "1" + # Enable Latency Tolerance Reporting Mechanism + register "PcieRpLtrEnable[5]" = "1" + # Use CLK SRC 1 + register "PcieRpClkSrcNumber[5]" = "1" + + # Enable Root port 5 (x1) for PCIE slot. + register "PcieRpEnable[4]" = "1" + # Enable CLKREQ# + register "PcieRpClkReqSupport[4]" = "1" + # Use SRCCLKREQ2# + register "PcieRpClkReqNumber[4]" = "2" + # Enable Advanced Error Reporting + register "PcieRpAdvancedErrorReporting[4]" = "1" + # Enable Latency Tolerance Reporting Mechanism + register "PcieRpLtrEnable[4]" = "1" + # Use CLK SRC 2 + register "PcieRpClkSrcNumber[4]" = "2" + # Use Hot Plug subsystem + register "PcieRpHotPlug[4]" = "1" + + # Enable Root port 7(x1) for PCIE slot. + register "PcieRpEnable[6]" = "1" + # Enable CLKREQ# + register "PcieRpClkReqSupport[6]" = "1" + # Use SRCCLKREQ3# + register "PcieRpClkReqNumber[6]" = "3" + # Enable Advanced Error Reporting + register "PcieRpAdvancedErrorReporting[6]" = "1" + # Enable Latency Tolerance Reporting Mechanism + register "PcieRpLtrEnable[6]" = "1" + # Use CLK SRC 3 + register "PcieRpClkSrcNumber[6]" = "3" + # Use Hot Plug subsystem + register "PcieRpHotPlug[6]" = "1" + + # PL2 override 91W + register "tdp_pl2_override" = "91" + + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on # Host Bridge + subsystemid 0x1849 0x191f + end + device pci 01.0 on # PEG + subsystemid 0x1849 0x1901 + end + device pci 02.0 on # Integrated Graphics Device + subsystemid 0x1849 0x1912 + end + device pci 14.0 on # USB xHCI + subsystemid 0x1849 0xa131 + end + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 on # Thermal Subsystem + subsystemid 0x1849 0xa131 + end + device pci 15.0 off end # I2C #0 + device pci 15.1 off end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x1849 0xa131 + end + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 17.0 on # SATA + subsystemid 0x1849 0xa102 + end + device pci 19.0 off end # UART #2 + device pci 19.1 off end # I2C #5 + device pci 19.2 off end # I2C #4 + device pci 1c.0 on end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 on end # PCI Express Port 5 + device pci 1c.5 on end # PCI Express Port 6 + device pci 1c.6 on end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 off end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1e.0 off end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1e.4 off end # eMMC + device pci 1e.5 off end # SDIO + device pci 1e.6 off end # SDCard + device pci 1f.0 on # LPC bridge + subsystemid 0x1849 0x1a43 + chip superio/nuvoton/nct5539d + device pnp 2e.0 off end # Floppy + device pnp 2e.1 on # Parallel + # global + irq 0x1c = 0x10 + irq 0x27 = 0x10 + irq 0x2a = 0x64 + # parallel port + io 0x60 = 0x0378 + irq 0x70 = 7 + drq 0x74 = 4 # No DMA + irq 0xf0 = 0x3c # Printer mode + end + device pnp 2e.2 on # UART A + io 0x60 = 0x03f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # IR + io 0x60 = 0x02f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # PS/2 KBC + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 # Keyboard + irq 0x72 = 12 # Mouse + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO6 + device pnp 2e.107 off end # GPIO7 + device pnp 2e.207 off end # GPIO8 + device pnp 2e.8 off end # WDT + device pnp 2e.108 off end # GPIO0 + device pnp 2e.308 off end # GPIO base + device pnp 2e.408 off end # WDTMEM + device pnp 2e.708 off end # GPIO1 + device pnp 2e.9 off end # GPIO2 + device pnp 2e.109 off end # GPIO3 + device pnp 2e.209 off end # GPIO4 + device pnp 2e.309 off end # GPIO5 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HWM, LED + io 0x60 = 0x0290 + io 0x62 = 0 + irq 0x70 = 0 + end + device pnp 2e.d off end # BCLK, WDT2, WDT_MEM + device pnp 2e.e off end # CIR wake-up + device pnp 2e.f off end # GPIO PP/OD + device pnp 2e.14 off end # SVID, Port 80 UART + device pnp 2e.16 off end # DS5 + device pnp 2e.116 off end # DS3 + device pnp 2e.316 off end # PCHDSW + device pnp 2e.416 off end # DSWWOPT + device pnp 2e.516 off end # DS3OPT + device pnp 2e.616 off end # DSDSS + device pnp 2e.716 off end # DSPU + end # superio/nuvoton/nct5539d + chip drivers/pc80/tpm + device pnp 4e.0 on end # TPM module + end + end # LPC Interface + device pci 1f.1 on end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/asus/h110m-e_m2/dsdt.asl b/src/mainboard/asus/h110m-e_m2/dsdt.asl new file mode 100644 index 0000000..f3e216d --- /dev/null +++ b/src/mainboard/asus/h110m-e_m2/dsdt.asl @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2016 Intel Corporation + * Copyright (C) 2019 Maxim Polyakov <max.senia.poliak(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + #include <soc/intel/skylake/acpi/platform.asl> + + // global NVS and variables + #include <soc/intel/skylake/acpi/globalnvs.asl> + + // CPU + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + /* Image processing unit */ + #include <soc/intel/skylake/acpi/ipu.asl> + #include <soc/intel/skylake/acpi/systemagent.asl> + #include <soc/intel/skylake/acpi/pch.asl> + } + + // Dynamic Platform Thermal Framework + #include "acpi/dptf.asl" + } + + // Chipset specific sleep states + #include <soc/intel/skylake/acpi/sleepstates.asl> + + // Mainboard specific + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/asus/h110m-e_m2/gma-mainboard.ads b/src/mainboard/asus/h110m-e_m2/gma-mainboard.ads new file mode 100644 index 0000000..86a3a62 --- /dev/null +++ b/src/mainboard/asus/h110m-e_m2/gma-mainboard.ads @@ -0,0 +1,32 @@ +-- +-- This file is part of the coreboot project. +-- +-- Copyright (C) 2018 Tristan Corrick <tristan(a)corrick.kiwi> +-- Copyright (C) 2019 Maxim Polyakov <max.senia.poliak(a)gmail.com> +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, -- mainboard DVI port + HDMI3, -- mainboard HDMI port + Analog, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asus/h110m-e_m2/gpio.txt b/src/mainboard/asus/h110m-e_m2/gpio.txt new file mode 100644 index 0000000..3416eee --- /dev/null +++ b/src/mainboard/asus/h110m-e_m2/gpio.txt @@ -0,0 +1,580 @@ +acpi/superio.asl:#undef NCT6776_SHOW_GPIO +include/gpio.h:#ifndef _GPIO_DVS_H +include/gpio.h:#define _GPIO_DVS_H +include/gpio.h: /* GPIO Group GPP_A */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A7, 0x84000102, 0x0000001f), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A11, 0x84000102, 0x00000023), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A12, 0x84000102, 0x00000024), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A16, 0x84000102, 0x00000028), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A17, 0x84000102, 0x00000029), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A18, 0x84000102, 0x0000002a), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A19, 0x84000102, 0x0000002b), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A20, 0x84000100, 0x0000002c), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A21, 0x84000102, 0x0000002d), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A22, 0x84000102, 0x0000002e), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A23, 0x84000102, 0x0000002f), /* GPIO */ +include/gpio.h: /* GPIO Group GPP_B */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B0, 0x84000100, 0x00000030), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B1, 0x84000100, 0x00000031), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B2, 0x84000102, 0x00000032), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B3, 0x44000201, 0x00000033), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B5, 0x84000102, 0x00000035), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B6, 0x84000102, 0x00000036), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B7, 0x44000300, 0x00000037), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B8, 0x84000102, 0x00002838), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B9, 0x84000100, 0x00000039), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B10, 0x84000102, 0x0000003a), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B11, 0x04000000, 0x0000003b), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B15, 0x84000102, 0x0000003f), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B16, 0x84000102, 0x00000040), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B17, 0x44000201, 0x00000041), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B18, 0x84000100, 0x00000042), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B19, 0x84000102, 0x00000043), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B20, 0x84000102, 0x00000044), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B21, 0x84000102, 0x00000045), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B22, 0x84000100, 0x00000046), /* GPIO */ +include/gpio.h: /* GPIO Group GPP_C */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C2, 0x44000201, 0x0000004a), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C5, 0x84000100, 0x0000004d), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C12, 0x84000102, 0x00000054), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C13, 0x84000102, 0x00000055), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C14, 0x84000102, 0x00000056), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C15, 0x84000102, 0x00000057), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C16, 0x84000102, 0x00000058), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C17, 0x84000102, 0x00000059), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C18, 0x84000102, 0x0000005a), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C19, 0x84000102, 0x0000005b), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C23, 0x40880102, 0x0000005f), /* GPIO */ +include/gpio.h: /* GPIO Group GPP_D */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D0, 0x84000102, 0x00000060), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D1, 0x84000102, 0x00000061), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D2, 0x84000102, 0x00000062), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D3, 0x84000102, 0x00000063), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D4, 0x84000102, 0x00000064), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D9, 0x84000102, 0x00000069), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D10, 0x84000102, 0x0000006a), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D11, 0x84000102, 0x0000006b), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D12, 0x84000102, 0x0000006c), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D13, 0x84000102, 0x0000006d), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D14, 0x84000100, 0x0000006e), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D15, 0x84000100, 0x0000006f), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D16, 0x84000102, 0x00000070), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D17, 0x84000102, 0x00000071), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D18, 0x84000102, 0x00000072), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D21, 0x84000102, 0x00000075), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D22, 0x84000102, 0x00000076), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D23, 0x84000102, 0x00000077), /* GPIO */ +include/gpio.h: /* GPIO Group GPP_E */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_E7, 0x84000102, 0x0000001f), /* GPIO */ +include/gpio.h: /* GPIO Group GPP_F */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F0, 0x84000102, 0x00000025), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F2, 0x44000300, 0x00000027), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F3, 0x84000102, 0x00000028), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F4, 0x84000102, 0x00000029), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F5, 0x84000102, 0x0000002a), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F6, 0x84000102, 0x0000002b), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F7, 0x84000102, 0x0000002c), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F8, 0x84000102, 0x0000002d), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F9, 0x84000102, 0x0000002e), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F10, 0x80100102, 0x0000002f), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F11, 0x84000102, 0x00000030), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F12, 0x80900102, 0x00000031), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F13, 0x80100102, 0x00000032), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F14, 0x40900102, 0x00000033), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F18, 0x84000201, 0x00000037), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F19, 0x84000100, 0x00000038), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F20, 0x84000102, 0x00000039), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F21, 0x84000102, 0x0000003a), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F22, 0x84000102, 0x0000003b), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F23, 0x84000102, 0x0000003c), /* GPIO */ +include/gpio.h: /* GPIO Group GPP_G */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G0, 0xc4000102, 0x0000003d), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G1, 0xc4000102, 0x0000003e), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G2, 0xc4000100, 0x0000003f), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G3, 0xc4000100, 0x00000040), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G4, 0x44000200, 0x00000041), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G5, 0xc4000102, 0x00000042), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G6, 0xc0800102, 0x00000043), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G7, 0xc4000102, 0x00000044), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G8, 0x84000100, 0x00000045), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G9, 0x84000100, 0x00000046), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G10, 0x84000102, 0x00000047), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G11, 0x84000100, 0x00000048), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G12, 0x80800102, 0x00000049), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G13, 0x84000201, 0x0000004a), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G14, 0x80800102, 0x0000004b), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G15, 0x84000200, 0x0000004c), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G16, 0x84000201, 0x0000104d), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G17, 0x84000102, 0x0000004e), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G18, 0x80100102, 0x0000004f), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G20, 0x84000102, 0x00000051), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G21, 0x84000102, 0x00000052), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G22, 0x84000102, 0x00000053), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G23, 0x84000102, 0x00000054), /* GPIO */ +include/gpio.h: /* GPIO Group GPP_H */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H0, 0x84000102, 0x00000055), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H1, 0x44000300, 0x00000056), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H2, 0x84000102, 0x00000057), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H3, 0x84000102, 0x00000058), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H4, 0x84000102, 0x00000059), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H5, 0x84000102, 0x0000005a), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H6, 0x84000102, 0x0000005b), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H7, 0x84000102, 0x0000005c), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H8, 0x84000100, 0x0000005d), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H9, 0x84000102, 0x0000005e), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H10, 0x84000102, 0x0000005f), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H11, 0x84000102, 0x00000060), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H12, 0x84000100, 0x00000061), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H13, 0x80100102, 0x00000062), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H14, 0x80100102, 0x00000063), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H15, 0x80100100, 0x00000064), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H16, 0x80000102, 0x00000065), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H17, 0x84000201, 0x00000066), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H18, 0x84000102, 0x00000067), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H19, 0x84000102, 0x00000068), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H20, 0x84000102, 0x00000069), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H21, 0x84000102, 0x0000006a), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H22, 0x84000102, 0x0000006b), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H23, 0x04000100, 0x0000006c), /* GPIO */ +include/gpio.h: /* GPIO Group GPD */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPD0, 0x84000102, 0x00000018), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPD1, 0x04000200, 0x00000019), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPD6, 0x84000102, 0x0000001e), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPD7, 0x84000103, 0x0000001f), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPD11, 0x04000200, 0x00000023), /* GPIO */ +include/gpio.h: /* GPIO Group GPP_I */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_I4, 0x84000100, 0x00000071), /* GPIO */ +include/gpio.h: /* GPIO Group GPP_A */ +devicetree.cb: device pnp 2e.7 off end # GPIO6 +devicetree.cb: device pnp 2e.107 off end # GPIO7 +devicetree.cb: device pnp 2e.207 off end # GPIO8 +devicetree.cb: device pnp 2e.108 off end # GPIO0 +devicetree.cb: device pnp 2e.308 off end # GPIO base +devicetree.cb: device pnp 2e.708 off end # GPIO1 +devicetree.cb: device pnp 2e.9 off end # GPIO2 +devicetree.cb: device pnp 2e.109 off end # GPIO3 +devicetree.cb: device pnp 2e.209 off end # GPIO4 +devicetree.cb: device pnp 2e.309 off end # GPIO5 +devicetree.cb: device pnp 2e.f off end # GPIO PP/OD +acpi/superio.asl:#undef NCT6776_SHOW_GPIO +include/gpio.h:#ifndef _GPIO_DVS_H +include/gpio.h:#define _GPIO_DVS_H +include/gpio.h: /* GPIO Group GPP_A */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A7, 0x84000102, 0x0000001f), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A11, 0x84000102, 0x00000023), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A12, 0x84000102, 0x00000024), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A16, 0x84000102, 0x00000028), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A17, 0x84000102, 0x00000029), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A18, 0x84000102, 0x0000002a), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A19, 0x84000102, 0x0000002b), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A20, 0x84000100, 0x0000002c), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A21, 0x84000102, 0x0000002d), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A22, 0x84000102, 0x0000002e), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A23, 0x84000102, 0x0000002f), /* GPIO */ +include/gpio.h: /* GPIO Group GPP_B */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B0, 0x84000100, 0x00000030), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B1, 0x84000100, 0x00000031), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B2, 0x84000102, 0x00000032), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B3, 0x44000201, 0x00000033), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B5, 0x84000102, 0x00000035), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B6, 0x84000102, 0x00000036), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B7, 0x44000300, 0x00000037), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B8, 0x84000102, 0x00002838), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B9, 0x84000100, 0x00000039), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B10, 0x84000102, 0x0000003a), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B11, 0x04000000, 0x0000003b), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B15, 0x84000102, 0x0000003f), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B16, 0x84000102, 0x00000040), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B17, 0x44000201, 0x00000041), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B18, 0x84000100, 0x00000042), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B19, 0x84000102, 0x00000043), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B20, 0x84000102, 0x00000044), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B21, 0x84000102, 0x00000045), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B22, 0x84000100, 0x00000046), /* GPIO */ +include/gpio.h: /* GPIO Group GPP_C */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C2, 0x44000201, 0x0000004a), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C5, 0x84000100, 0x0000004d), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C12, 0x84000102, 0x00000054), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C13, 0x84000102, 0x00000055), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C14, 0x84000102, 0x00000056), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C15, 0x84000102, 0x00000057), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C16, 0x84000102, 0x00000058), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C17, 0x84000102, 0x00000059), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C18, 0x84000102, 0x0000005a), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C19, 0x84000102, 0x0000005b), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C23, 0x40880102, 0x0000005f), /* GPIO */ +include/gpio.h: /* GPIO Group GPP_D */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D0, 0x84000102, 0x00000060), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D1, 0x84000102, 0x00000061), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D2, 0x84000102, 0x00000062), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D3, 0x84000102, 0x00000063), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D4, 0x84000102, 0x00000064), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D9, 0x84000102, 0x00000069), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D10, 0x84000102, 0x0000006a), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D11, 0x84000102, 0x0000006b), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D12, 0x84000102, 0x0000006c), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D13, 0x84000102, 0x0000006d), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D14, 0x84000100, 0x0000006e), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D15, 0x84000100, 0x0000006f), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D16, 0x84000102, 0x00000070), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D17, 0x84000102, 0x00000071), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D18, 0x84000102, 0x00000072), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D21, 0x84000102, 0x00000075), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D22, 0x84000102, 0x00000076), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D23, 0x84000102, 0x00000077), /* GPIO */ +include/gpio.h: /* GPIO Group GPP_E */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_E7, 0x84000102, 0x0000001f), /* GPIO */ +include/gpio.h: /* GPIO Group GPP_F */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F0, 0x84000102, 0x00000025), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F2, 0x44000300, 0x00000027), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F3, 0x84000102, 0x00000028), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F4, 0x84000102, 0x00000029), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F5, 0x84000102, 0x0000002a), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F6, 0x84000102, 0x0000002b), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F7, 0x84000102, 0x0000002c), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F8, 0x84000102, 0x0000002d), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F9, 0x84000102, 0x0000002e), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F10, 0x80100102, 0x0000002f), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F11, 0x84000102, 0x00000030), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F12, 0x80900102, 0x00000031), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F13, 0x80100102, 0x00000032), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F14, 0x40900102, 0x00000033), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F18, 0x84000201, 0x00000037), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F19, 0x84000100, 0x00000038), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F20, 0x84000102, 0x00000039), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F21, 0x84000102, 0x0000003a), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F22, 0x84000102, 0x0000003b), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F23, 0x84000102, 0x0000003c), /* GPIO */ +include/gpio.h: /* GPIO Group GPP_G */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G0, 0xc4000102, 0x0000003d), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G1, 0xc4000102, 0x0000003e), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G2, 0xc4000100, 0x0000003f), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G3, 0xc4000100, 0x00000040), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G4, 0x44000200, 0x00000041), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G5, 0xc4000102, 0x00000042), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G6, 0xc0800102, 0x00000043), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G7, 0xc4000102, 0x00000044), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G8, 0x84000100, 0x00000045), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G9, 0x84000100, 0x00000046), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G10, 0x84000102, 0x00000047), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G11, 0x84000100, 0x00000048), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G12, 0x80800102, 0x00000049), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G13, 0x84000201, 0x0000004a), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G14, 0x80800102, 0x0000004b), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G15, 0x84000200, 0x0000004c), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G16, 0x84000201, 0x0000104d), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G17, 0x84000102, 0x0000004e), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G18, 0x80100102, 0x0000004f), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G20, 0x84000102, 0x00000051), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G21, 0x84000102, 0x00000052), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G22, 0x84000102, 0x00000053), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G23, 0x84000102, 0x00000054), /* GPIO */ +include/gpio.h: /* GPIO Group GPP_H */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H0, 0x84000102, 0x00000055), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H1, 0x44000300, 0x00000056), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H2, 0x84000102, 0x00000057), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H3, 0x84000102, 0x00000058), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H4, 0x84000102, 0x00000059), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H5, 0x84000102, 0x0000005a), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H6, 0x84000102, 0x0000005b), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H7, 0x84000102, 0x0000005c), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H8, 0x84000100, 0x0000005d), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H9, 0x84000102, 0x0000005e), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H10, 0x84000102, 0x0000005f), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H11, 0x84000102, 0x00000060), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H12, 0x84000100, 0x00000061), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H13, 0x80100102, 0x00000062), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H14, 0x80100102, 0x00000063), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H15, 0x80100100, 0x00000064), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H16, 0x80000102, 0x00000065), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H17, 0x84000201, 0x00000066), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H18, 0x84000102, 0x00000067), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H19, 0x84000102, 0x00000068), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H20, 0x84000102, 0x00000069), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H21, 0x84000102, 0x0000006a), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H22, 0x84000102, 0x0000006b), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H23, 0x04000100, 0x0000006c), /* GPIO */ +include/gpio.h: /* GPIO Group GPD */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPD0, 0x84000102, 0x00000018), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPD1, 0x04000200, 0x00000019), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPD6, 0x84000102, 0x0000001e), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPD7, 0x84000103, 0x0000001f), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPD11, 0x04000200, 0x00000023), /* GPIO */ +include/gpio.h: /* GPIO Group GPP_I */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_I4, 0x84000100, 0x00000071), /* GPIO */ +include/gpio.h: /* GPIO Group GPP_A */ +devicetree.cb: device pnp 2e.7 off end # GPIO6 +devicetree.cb: device pnp 2e.107 off end # GPIO7 +devicetree.cb: device pnp 2e.207 off end # GPIO8 +devicetree.cb: device pnp 2e.108 off end # GPIO0 +devicetree.cb: device pnp 2e.308 off end # GPIO base +devicetree.cb: device pnp 2e.708 off end # GPIO1 +devicetree.cb: device pnp 2e.9 off end # GPIO2 +devicetree.cb: device pnp 2e.109 off end # GPIO3 +devicetree.cb: device pnp 2e.209 off end # GPIO4 +devicetree.cb: device pnp 2e.309 off end # GPIO5 +devicetree.cb: device pnp 2e.f off end # GPIO PP/OD +gpio.txt:acpi/superio.asl:#undef NCT6776_SHOW_GPIO +gpio.txt:include/gpio.h:#ifndef _GPIO_DVS_H +gpio.txt:include/gpio.h:#define _GPIO_DVS_H +gpio.txt:include/gpio.h: /* GPIO Group GPP_A */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A7, 0x84000102, 0x0000001f), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A11, 0x84000102, 0x00000023), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A12, 0x84000102, 0x00000024), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A16, 0x84000102, 0x00000028), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A17, 0x84000102, 0x00000029), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A18, 0x84000102, 0x0000002a), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A19, 0x84000102, 0x0000002b), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A20, 0x84000100, 0x0000002c), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A21, 0x84000102, 0x0000002d), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A22, 0x84000102, 0x0000002e), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A23, 0x84000102, 0x0000002f), /* GPIO */ +gpio.txt:include/gpio.h: /* GPIO Group GPP_B */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B0, 0x84000100, 0x00000030), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B1, 0x84000100, 0x00000031), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B2, 0x84000102, 0x00000032), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B3, 0x44000201, 0x00000033), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B5, 0x84000102, 0x00000035), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B6, 0x84000102, 0x00000036), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B7, 0x44000300, 0x00000037), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B8, 0x84000102, 0x00002838), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B9, 0x84000100, 0x00000039), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B10, 0x84000102, 0x0000003a), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B11, 0x04000000, 0x0000003b), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B15, 0x84000102, 0x0000003f), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B16, 0x84000102, 0x00000040), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B17, 0x44000201, 0x00000041), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B18, 0x84000100, 0x00000042), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B19, 0x84000102, 0x00000043), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B20, 0x84000102, 0x00000044), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B21, 0x84000102, 0x00000045), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B22, 0x84000100, 0x00000046), /* GPIO */ +gpio.txt:include/gpio.h: /* GPIO Group GPP_C */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C2, 0x44000201, 0x0000004a), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C5, 0x84000100, 0x0000004d), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C12, 0x84000102, 0x00000054), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C13, 0x84000102, 0x00000055), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C14, 0x84000102, 0x00000056), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C15, 0x84000102, 0x00000057), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C16, 0x84000102, 0x00000058), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C17, 0x84000102, 0x00000059), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C18, 0x84000102, 0x0000005a), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C19, 0x84000102, 0x0000005b), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C23, 0x40880102, 0x0000005f), /* GPIO */ +gpio.txt:include/gpio.h: /* GPIO Group GPP_D */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D0, 0x84000102, 0x00000060), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D1, 0x84000102, 0x00000061), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D2, 0x84000102, 0x00000062), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D3, 0x84000102, 0x00000063), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D4, 0x84000102, 0x00000064), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D9, 0x84000102, 0x00000069), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D10, 0x84000102, 0x0000006a), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D11, 0x84000102, 0x0000006b), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D12, 0x84000102, 0x0000006c), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D13, 0x84000102, 0x0000006d), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D14, 0x84000100, 0x0000006e), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D15, 0x84000100, 0x0000006f), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D16, 0x84000102, 0x00000070), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D17, 0x84000102, 0x00000071), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D18, 0x84000102, 0x00000072), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D21, 0x84000102, 0x00000075), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D22, 0x84000102, 0x00000076), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D23, 0x84000102, 0x00000077), /* GPIO */ +gpio.txt:include/gpio.h: /* GPIO Group GPP_E */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_E7, 0x84000102, 0x0000001f), /* GPIO */ +gpio.txt:include/gpio.h: /* GPIO Group GPP_F */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F0, 0x84000102, 0x00000025), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F2, 0x44000300, 0x00000027), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F3, 0x84000102, 0x00000028), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F4, 0x84000102, 0x00000029), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F5, 0x84000102, 0x0000002a), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F6, 0x84000102, 0x0000002b), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F7, 0x84000102, 0x0000002c), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F8, 0x84000102, 0x0000002d), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F9, 0x84000102, 0x0000002e), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F10, 0x80100102, 0x0000002f), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F11, 0x84000102, 0x00000030), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F12, 0x80900102, 0x00000031), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F13, 0x80100102, 0x00000032), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F14, 0x40900102, 0x00000033), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F18, 0x84000201, 0x00000037), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F19, 0x84000100, 0x00000038), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F20, 0x84000102, 0x00000039), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F21, 0x84000102, 0x0000003a), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F22, 0x84000102, 0x0000003b), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F23, 0x84000102, 0x0000003c), /* GPIO */ +gpio.txt:include/gpio.h: /* GPIO Group GPP_G */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G0, 0xc4000102, 0x0000003d), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G1, 0xc4000102, 0x0000003e), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G2, 0xc4000100, 0x0000003f), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G3, 0xc4000100, 0x00000040), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G4, 0x44000200, 0x00000041), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G5, 0xc4000102, 0x00000042), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G6, 0xc0800102, 0x00000043), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G7, 0xc4000102, 0x00000044), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G8, 0x84000100, 0x00000045), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G9, 0x84000100, 0x00000046), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G10, 0x84000102, 0x00000047), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G11, 0x84000100, 0x00000048), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G12, 0x80800102, 0x00000049), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G13, 0x84000201, 0x0000004a), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G14, 0x80800102, 0x0000004b), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G15, 0x84000200, 0x0000004c), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G16, 0x84000201, 0x0000104d), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G17, 0x84000102, 0x0000004e), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G18, 0x80100102, 0x0000004f), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G20, 0x84000102, 0x00000051), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G21, 0x84000102, 0x00000052), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G22, 0x84000102, 0x00000053), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G23, 0x84000102, 0x00000054), /* GPIO */ +gpio.txt:include/gpio.h: /* GPIO Group GPP_H */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H0, 0x84000102, 0x00000055), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H1, 0x44000300, 0x00000056), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H2, 0x84000102, 0x00000057), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H3, 0x84000102, 0x00000058), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H4, 0x84000102, 0x00000059), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H5, 0x84000102, 0x0000005a), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H6, 0x84000102, 0x0000005b), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H7, 0x84000102, 0x0000005c), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H8, 0x84000100, 0x0000005d), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H9, 0x84000102, 0x0000005e), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H10, 0x84000102, 0x0000005f), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H11, 0x84000102, 0x00000060), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H12, 0x84000100, 0x00000061), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H13, 0x80100102, 0x00000062), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H14, 0x80100102, 0x00000063), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H15, 0x80100100, 0x00000064), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H16, 0x80000102, 0x00000065), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H17, 0x84000201, 0x00000066), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H18, 0x84000102, 0x00000067), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H19, 0x84000102, 0x00000068), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H20, 0x84000102, 0x00000069), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H21, 0x84000102, 0x0000006a), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H22, 0x84000102, 0x0000006b), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H23, 0x04000100, 0x0000006c), /* GPIO */ +gpio.txt:include/gpio.h: /* GPIO Group GPD */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPD0, 0x84000102, 0x00000018), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPD1, 0x04000200, 0x00000019), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPD6, 0x84000102, 0x0000001e), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPD7, 0x84000103, 0x0000001f), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPD11, 0x04000200, 0x00000023), /* GPIO */ +gpio.txt:include/gpio.h: /* GPIO Group GPP_I */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_I4, 0x84000100, 0x00000071), /* GPIO */ +gpio.txt:include/gpio.h: /* GPIO Group GPP_A */ +gpio.txt:devicetree.cb: device pnp 2e.7 off end # GPIO6 +gpio.txt:devicetree.cb: device pnp 2e.107 off end # GPIO7 +gpio.txt:devicetree.cb: device pnp 2e.207 off end # GPIO8 +gpio.txt:devicetree.cb: device pnp 2e.108 off end # GPIO0 +gpio.txt:devicetree.cb: device pnp 2e.308 off end # GPIO base +gpio.txt:devicetree.cb: device pnp 2e.708 off end # GPIO1 +gpio.txt:devicetree.cb: device pnp 2e.9 off end # GPIO2 +gpio.txt:devicetree.cb: device pnp 2e.109 off end # GPIO3 +gpio.txt:devicetree.cb: device pnp 2e.209 off end # GPIO4 +gpio.txt:devicetree.cb: device pnp 2e.309 off end # GPIO5 +gpio.txt:devicetree.cb: device pnp 2e.f off end # GPIO PP/OD +gpio.txt:acpi/superio.asl:#undef NCT6776_SHOW_GPIO +gpio.txt:include/gpio.h:#ifndef _GPIO_DVS_H +gpio.txt:include/gpio.h:#define _GPIO_DVS_H +gpio.txt:include/gpio.h: /* GPIO Group GPP_A */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A7, 0x84000102, 0x0000001f), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A11, 0x84000102, 0x00000023), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A12, 0x84000102, 0x00000024), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A16, 0x84000102, 0x00000028), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A17, 0x84000102, 0x00000029), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A18, 0x84000102, 0x0000002a), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A19, 0x84000102, 0x0000002b), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A20, 0x84000100, 0x0000002c), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A21, 0x84000102, 0x0000002d), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A22, 0x84000102, 0x0000002e), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A23, 0x84000102, 0x0000002f), /* GPIO */ +gpio.txt:include/gpio.h: /* GPIO Group GPP_B */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B0, 0x84000100, 0x00000030), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B1, 0x84000100, 0x00000031), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B2, 0x84000102, 0x00000032), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B3, 0x44000201, 0x00000033), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B5, 0x84000102, 0x00000035), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B6, 0x84000102, 0x00000036), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B7, 0x44000300, 0x00000037), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B8, 0x84000102, 0x00002838), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B9, 0x84000100, 0x00000039), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B10, 0x84000102, 0x0000003a), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B11, 0x04000000, 0x0000003b), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B15, 0x84000102, 0x0000003f), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B16, 0x84000102, 0x00000040), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B17, 0x44000201, 0x00000041), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B18, 0x84000100, 0x00000042), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B19, 0x84000102, 0x00000043), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B20, 0x84000102, 0x00000044), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B21, 0x84000102, 0x00000045), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B22, 0x84000100, 0x00000046), /* GPIO */ +gpio.txt:include/gpio.h: /* GPIO Group GPP_C */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C2, 0x44000201, 0x0000004a), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C5, 0x84000100, 0x0000004d), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C12, 0x84000102, 0x00000054), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C13, 0x84000102, 0x00000055), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C14, 0x84000102, 0x00000056), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C15, 0x84000102, 0x00000057), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C16, 0x84000102, 0x00000058), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C17, 0x84000102, 0x00000059), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C18, 0x84000102, 0x0000005a), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C19, 0x84000102, 0x0000005b), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C23, 0x40880102, 0x0000005f), /* GPIO */ +gpio.txt:include/gpio.h: /* GPIO Group GPP_D */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D0, 0x84000102, 0x00000060), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D1, 0x84000102, 0x00000061), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D2, 0x84000102, 0x00000062), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D3, 0x84000102, 0x00000063), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D4, 0x84000102, 0x00000064), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D9, 0x84000102, 0x00000069), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D10, 0x84000102, 0x0000006a), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D11, 0x84000102, 0x0000006b), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D12, 0x84000102, 0x0000006c), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D13, 0x84000102, 0x0000006d), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D14, 0x84000100, 0x0000006e), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D15, 0x84000100, 0x0000006f), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D16, 0x84000102, 0x00000070), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D17, 0x84000102, 0x00000071), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D18, 0x84000102, 0x00000072), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D21, 0x84000102, 0x00000075), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D22, 0x84000102, 0x00000076), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D23, 0x84000102, 0x00000077), /* GPIO */ +gpio.txt:include/gpio.h: /* GPIO Group GPP_E */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_E7, 0x84000102, 0x0000001f), /* GPIO */ +gpio.txt:include/gpio.h: /* GPIO Group GPP_F */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F0, 0x84000102, 0x00000025), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F2, 0x44000300, 0x00000027), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F3, 0x84000102, 0x00000028), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F4, 0x84000102, 0x00000029), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F5, 0x84000102, 0x0000002a), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F6, 0x84000102, 0x0000002b), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F7, 0x84000102, 0x0000002c), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F8, 0x84000102, 0x0000002d), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F9, 0x84000102, 0x0000002e), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F10, 0x80100102, 0x0000002f), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F11, 0x84000102, 0x00000030), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F12, 0x80900102, 0x00000031), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F13, 0x80100102, 0x00000032), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F14, 0x40900102, 0x00000033), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F18, 0x84000201, 0x00000037), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F19, 0x84000100, 0x00000038), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F20, 0x84000102, 0x00000039), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F21, 0x84000102, 0x0000003a), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F22, 0x84000102, 0x0000003b), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F23, 0x84000102, 0x0000003c), /* GPIO */ +gpio.txt:include/gpio.h: /* GPIO Group GPP_G */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G0, 0xc4000102, 0x0000003d), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G1, 0xc4000102, 0x0000003e), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G2, 0xc4000100, 0x0000003f), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G3, 0xc4000100, 0x00000040), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G4, 0x44000200, 0x00000041), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G5, 0xc4000102, 0x00000042), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G6, 0xc0800102, 0x00000043), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G7, 0xc4000102, 0x00000044), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G8, 0x84000100, 0x00000045), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G9, 0x84000100, 0x00000046), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G10, 0x84000102, 0x00000047), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G11, 0x84000100, 0x00000048), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G12, 0x80800102, 0x00000049), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G13, 0x84000201, 0x0000004a), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G14, 0x80800102, 0x0000004b), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G15, 0x84000200, 0x0000004c), /* GPIO */ diff --git a/src/mainboard/asus/h110m-e_m2/hda_verb.c b/src/mainboard/asus/h110m-e_m2/hda_verb.c new file mode 100644 index 0000000..1d1627b --- /dev/null +++ b/src/mainboard/asus/h110m-e_m2/hda_verb.c @@ -0,0 +1,60 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation + * (Written by Naresh G Solanki <naresh.solanki(a)intel.com> for Intel Corp.) + * Copyright (C) 2019 Pavel Sayekat <pavelsayekat(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header ALC887 */ + 0x10ec0887, /* Codec Vendor / Device ID: Realtek */ + 0x10438445, /* Subsystem ID */ + 15, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0x0, 0x10438445), + AZALIA_PIN_CFG(0x0, 0x11, 0x40000000), + AZALIA_PIN_CFG(0x0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x14, 0x01014020), + AZALIA_PIN_CFG(0x0, 0x15, 0x90170110), + AZALIA_PIN_CFG(0x0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x18, 0x01a19040), + AZALIA_PIN_CFG(0x0, 0x19, 0x02a19050), + AZALIA_PIN_CFG(0x0, 0x1a, 0x0181304f), + AZALIA_PIN_CFG(0x0, 0x1b, 0x02214030), + AZALIA_PIN_CFG(0x0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x1d, 0x4026c629), + AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x1f, 0x411111f0), + + /* coreboot specific header */ + 0x80862809, /* Codec Vendor / Device ID: Intel Skylake HDMI */ + 0x80860101, + 0x00000004, + /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */ + AZALIA_SUBVENDOR(0x2, 0x80860101), + + /* Pin Complex (NID 0x05) Digital Out at Int HDMI */ + AZALIA_PIN_CFG(0x2, 0x05, 0x18560010), + + /* Pin Complex (NID 0x06) Digital Out at Int HDMI */ + AZALIA_PIN_CFG(0x2, 0x06, 0x18560020), + + /* Pin Complex (NID 0x07) Digital Out at Int HDMI */ + AZALIA_PIN_CFG(0x2, 0x07, 0x18560030) +}; + +const u32 pc_beep_verbs[] = { +}; +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asus/h110m-e_m2/include/gpio.h b/src/mainboard/asus/h110m-e_m2/include/gpio.h new file mode 100644 index 0000000..a8a4d19 --- /dev/null +++ b/src/mainboard/asus/h110m-e_m2/include/gpio.h @@ -0,0 +1,266 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Pavel Sayekat <pavelsayekat(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef _GPIO_DVS_H +#define _GPIO_DVS_H + +#include <soc/gpe.h> +#include <soc/gpio.h> + +#define H110_PAD_DW0_DW1_CFG(val, config0, config1) \ + _PAD_CFG_STRUCT(val, config0, config1) + +/* Pad configuration in ramstage. */ +static const struct pad_config gpio_table[] = { + /* GPIO Group GPP_A */ + H110_PAD_DW0_DW1_CFG(GPP_A0, 0x84000502, 0x00000018), /* RCIN# */ + H110_PAD_DW0_DW1_CFG(GPP_A1, 0x84000402, 0x00000019), /* LAD0 */ + H110_PAD_DW0_DW1_CFG(GPP_A2, 0x84000402, 0x0000001a), /* LAD1 */ + H110_PAD_DW0_DW1_CFG(GPP_A3, 0x84000402, 0x0000001b), /* LAD2 */ + H110_PAD_DW0_DW1_CFG(GPP_A4, 0x84000402, 0x0000001c), /* LAD3 */ + H110_PAD_DW0_DW1_CFG(GPP_A5, 0x84000600, 0x0000001d), /* LFRAME# */ + H110_PAD_DW0_DW1_CFG(GPP_A6, 0x84000402, 0x0000001e), /* SERIRQ */ + H110_PAD_DW0_DW1_CFG(GPP_A7, 0x84000102, 0x0000001f), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_A8, 0x84000500, 0x00000020), /* CLKRUN# */ + H110_PAD_DW0_DW1_CFG(GPP_A9, 0x84000600, 0x00001021), /* CLKOUT_LPC0 */ + H110_PAD_DW0_DW1_CFG(GPP_A10, 0x84000600, 0x00001022), /* CLKOUT_LPC1 */ + H110_PAD_DW0_DW1_CFG(GPP_A11, 0x44000502, 0x00003023), /* PME# */ + H110_PAD_DW0_DW1_CFG(GPP_A12, 0x84000102, 0x00000024), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_A13, 0x44000600, 0x00000025), /* SUSWARN#/SUSPWRDNACK */ + H110_PAD_DW0_DW1_CFG(GPP_A14, 0x84000100, 0x00001026), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_A15, 0x44000500, 0x00000027), /* SUS_ACK# */ + H110_PAD_DW0_DW1_CFG(GPP_A16, 0x04000100, 0x00001028), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_A17, 0x04000100, 0x00001029), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_A18, 0x04000100, 0x0000102a), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_A19, 0x04000100, 0x0000102b), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_A20, 0x04000100, 0x0000102c), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_A21, 0x04000100, 0x0000102d), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_A22, 0x04000100, 0x0000102e), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_A23, 0x04000100, 0x0000102f), /* GPIO */ + /* GPIO Group GPP_B */ + H110_PAD_DW0_DW1_CFG(GPP_B0, 0x84000100, 0x00000030), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B1, 0x04000100, 0x00001031), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B2, 0x84000102, 0x00000032), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B3, 0x04000100, 0x00001033), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B4, 0x04000100, 0x00001034), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B5, 0x44000702, 0x00000035), /* SRCCLKREQ0# */ + H110_PAD_DW0_DW1_CFG(GPP_B6, 0x04000100, 0x00001036), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B7, 0x04000500, 0x00001037), /* SRCCLKREQ2# */ + H110_PAD_DW0_DW1_CFG(GPP_B8, 0x04000100, 0x00001038), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B9, 0x04000500, 0x00001039), /* SRCCLKREQ4# */ + H110_PAD_DW0_DW1_CFG(GPP_B10, 0x04000500, 0x0000103a), /* SRCCLKREQ5# */ + H110_PAD_DW0_DW1_CFG(GPP_B11, 0x84000100, 0x0000003b), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B12, 0x84000100, 0x0000103c), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B13, 0x84000600, 0x0000003d), /* PLTRST# */ + H110_PAD_DW0_DW1_CFG(GPP_B14, 0x84000600, 0x0000003e), /* SPKR */ + H110_PAD_DW0_DW1_CFG(GPP_B15, 0x84000102, 0x0000003f), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B16, 0x84000200, 0x00000040), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B17, 0x04000100, 0x00001041), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B18, 0x84000100, 0x00000042), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B19, 0x84000102, 0x00000043), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B20, 0x84000102, 0x00000044), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B21, 0x84000100, 0x00000045), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B22, 0x84000100, 0x00000046), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B23, 0x84000100, 0x00001047), /* GPIO */ + /* GPIO Group GPP_C */ + H110_PAD_DW0_DW1_CFG(GPP_C0, 0x84000502, 0x00000048), /* SMBCLK */ + H110_PAD_DW0_DW1_CFG(GPP_C1, 0x84000502, 0x00000049), /* SMBDATA */ + H110_PAD_DW0_DW1_CFG(GPP_C2, 0x84000100, 0x0000004a), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C3, 0x84000502, 0x0000004b), /* SML0CLK */ + H110_PAD_DW0_DW1_CFG(GPP_C4, 0x84000502, 0x0000004c), /* SML0DATA */ + H110_PAD_DW0_DW1_CFG(GPP_C5, 0x84000100, 0x0000004d), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C6, 0x04000102, 0x0000104e), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C7, 0x04000102, 0x0000104f), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C8, 0x04000100, 0x00001050), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C9, 0x04000100, 0x00001051), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C10, 0x04000100, 0x00001052), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C11, 0x04000100, 0x00001053), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C12, 0x04000100, 0x00000054), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C13, 0x04000100, 0x00001055), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C14, 0x84000102, 0x00000056), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C15, 0x04000100, 0x00001057), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C16, 0x04000100, 0x00001058), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C17, 0x04000100, 0x00001059), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C18, 0x04000100, 0x0000105a), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C19, 0x04000100, 0x0000105b), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C20, 0x84000100, 0x0000005c), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C21, 0x84000100, 0x0000005d), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C22, 0x84000100, 0x0000005e), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C23, 0x84000100, 0x0000005f), /* GPIO */ + /* GPIO Group GPP_D */ + H110_PAD_DW0_DW1_CFG(GPP_D0, 0x04000100, 0x00001060), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D1, 0x04000100, 0x00001061), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D2, 0x84000102, 0x00000062), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D3, 0x04000100, 0x00001063), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D4, 0x84000100, 0x00000064), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D5, 0x04000100, 0x00001065), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D6, 0x04000100, 0x00001066), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D7, 0x04000100, 0x00001067), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D8, 0x04000100, 0x00001068), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D9, 0x84000100, 0x00000069), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D10, 0x84000100, 0x0000006a), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D11, 0x04000100, 0x0000106b), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D12, 0x04000102, 0x0000106c), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D13, 0x84000100, 0x0000006d), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D14, 0x84000102, 0x0000006e), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D15, 0x84000100, 0x0000006f), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D16, 0x04000100, 0x00001070), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D17, 0x04000100, 0x00001071), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D18, 0x04000100, 0x00001072), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D19, 0x04000100, 0x00001073), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D20, 0x04000100, 0x00001074), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D21, 0x84000102, 0x00000075), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D22, 0x84000102, 0x00000076), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D23, 0x04000100, 0x00001077), /* GPIO */ + /* GPIO Group GPP_E */ + H110_PAD_DW0_DW1_CFG(GPP_E0, 0x84000102, 0x00000018), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_E1, 0x84000102, 0x00000019), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_E2, 0x84000100, 0x0000001a), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_E3, 0x04000100, 0x0000101b), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_E4, 0x44000100, 0x0000001c), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_E5, 0x04000100, 0x0000101d), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_E6, 0x04000100, 0x0000101e), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_E7, 0x04000100, 0x0000101f), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_E8, 0x84000600, 0x00000020), /* SATA_LED# */ + H110_PAD_DW0_DW1_CFG(GPP_E9, 0x84000502, 0x00000021), /* USB_OC0# */ + H110_PAD_DW0_DW1_CFG(GPP_E10, 0x84000502, 0x00000022), /* USB_OC1# */ + H110_PAD_DW0_DW1_CFG(GPP_E11, 0x84000502, 0x00000023), /* USB_OC2# */ + H110_PAD_DW0_DW1_CFG(GPP_E12, 0x84000502, 0x00000024), /* USB_OC3# */ + /* GPIO Group GPP_F */ + H110_PAD_DW0_DW1_CFG(GPP_F0, 0x84000100, 0x00000025), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F1, 0x04000100, 0x00001026), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F2, 0x04000100, 0x00001027), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F3, 0x04000100, 0x00001028), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F4, 0x84000100, 0x00000029), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F5, 0x84000100, 0x0000002a), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F6, 0x84000100, 0x0000002b), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F7, 0x84000100, 0x0000002c), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F8, 0x84000100, 0x0000002d), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F9, 0x84000100, 0x0000002e), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F10, 0x84000100, 0x0000002f), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F11, 0x04000100, 0x00001030), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F12, 0x04000100, 0x00001031), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F13, 0x04000100, 0x00001032), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F14, 0x04000100, 0x00001033), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F15, 0x84000502, 0x00000034), /* USB_OC4# */ + H110_PAD_DW0_DW1_CFG(GPP_F16, 0x84000102, 0x00000035), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F17, 0x84000102, 0x00000036), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F18, 0x84000102, 0x00000037), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F19, 0x04000100, 0x00001038), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F20, 0x04000100, 0x00001039), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F21, 0x04000100, 0x0000103a), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F22, 0x04000100, 0x0000103b), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F23, 0x04000100, 0x0000103c), /* GPIO */ + /* GPIO Group GPP_G */ + H110_PAD_DW0_DW1_CFG(GPP_G0, 0x04000100, 0x0000103d), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G1, 0x04000100, 0x0000103e), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G2, 0x04000100, 0x0000103f), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G3, 0x04000100, 0x00001040), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G4, 0x04000100, 0x00001041), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G5, 0x84000100, 0x00000042), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G6, 0x84000100, 0x00000043), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G7, 0x84000100, 0x00000044), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G8, 0x04000100, 0x00001045), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G9, 0x04000100, 0x00001046), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G10, 0x04000100, 0x00001047), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G11, 0x04000100, 0x00001048), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G12, 0x04000100, 0x00001049), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G13, 0x04000100, 0x0000104a), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G14, 0x84000100, 0x0000004b), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G15, 0x84000100, 0x0000004c), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G16, 0x04000100, 0x0000104d), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G17, 0x04000100, 0x0000104e), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G18, 0x84000100, 0x0000104f), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G19, 0x84000100, 0x00001050), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G20, 0x04000100, 0x00001051), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G21, 0x04000100, 0x00001052), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G22, 0x04000100, 0x00001053), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G23, 0x04000100, 0x00001054), /* GPIO */ + /* GPIO Group GPP_H */ + H110_PAD_DW0_DW1_CFG(GPP_H0, 0x84000100, 0x00000055), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H1, 0x44000702, 0x00000056), /* SRCCLKREQ7# */ + H110_PAD_DW0_DW1_CFG(GPP_H2, 0x84000100, 0x00000057), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H3, 0x84000100, 0x00000058), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H4, 0x04000100, 0x00001059), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H5, 0x84000100, 0x0000005a), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H6, 0x04000100, 0x0000105b), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H7, 0x04000100, 0x0000105c), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H8, 0x44000702, 0x0000005d), /* SRCCLKREQ14# */ + H110_PAD_DW0_DW1_CFG(GPP_H9, 0x04000100, 0x0000105e), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H10, 0x04000100, 0x0000105f), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H11, 0x04000100, 0x00001060), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H12, 0x84000100, 0x00000061), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H13, 0x44000100, 0x00000062), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H14, 0x84000100, 0x00000063), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H15, 0x04000100, 0x00001064), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H16, 0x84000100, 0x00000065), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H17, 0x04000100, 0x00001066), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H18, 0x84000100, 0x00000067), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H19, 0x84000100, 0x00000068), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H20, 0x84000102, 0x00000069), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H21, 0x84000102, 0x0000006a), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H22, 0x84000100, 0x0000006b), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H23, 0x84000102, 0x0000006c), /* GPIO */ + /* GPIO Group GPD */ + H110_PAD_DW0_DW1_CFG(GPD0, 0x84000102, 0x00000018), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPD1, 0x84000102, 0x00000019), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPD2, 0x84000502, 0x0000001a), /* LAN_WAKE# */ + H110_PAD_DW0_DW1_CFG(GPD3, 0x84000502, 0x0000001b), /* PWRBTN# */ + H110_PAD_DW0_DW1_CFG(GPD4, 0x84000600, 0x0000001c), /* SLP_S3# */ + H110_PAD_DW0_DW1_CFG(GPD5, 0x84000600, 0x0000001d), /* SLP_S4# */ + H110_PAD_DW0_DW1_CFG(GPD6, 0x84000100, 0x0000001e), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPD7, 0x84000103, 0x0000001f), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPD8, 0x84000500, 0x00000020), /* SUSCLK */ + H110_PAD_DW0_DW1_CFG(GPD9, 0x04000100, 0x00000021), /* SLP_WLAN# */ + H110_PAD_DW0_DW1_CFG(GPD10, 0x84000100, 0x00000022), /* SLP_S5# */ + H110_PAD_DW0_DW1_CFG(GPD11, 0x04000102, 0x00000023), /* GPIO */ + /* GPIO Group GPP_I */ + H110_PAD_DW0_DW1_CFG(GPP_I0, 0x84000500, 0x0000006d), /* DDPB_HPD0 */ + H110_PAD_DW0_DW1_CFG(GPP_I1, 0x84000500, 0x0000006e), /* DDPC_HPD1 */ + H110_PAD_DW0_DW1_CFG(GPP_I2, 0x84000100, 0x0000006f), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_I3, 0x84000502, 0x00000070), /* DDPE_HPD3 */ + H110_PAD_DW0_DW1_CFG(GPP_I4, 0x04000100, 0x00001071), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_I5, 0x84000500, 0x00000072), /* DDPB_CTRLCLK */ + H110_PAD_DW0_DW1_CFG(GPP_I6, 0x84000500, 0x00000073), + /* DDPB_CTRLDATA */ + H110_PAD_DW0_DW1_CFG(GPP_I7, 0x84000502, 0x00000074), + /* DDPC_CTRLCLK */ + H110_PAD_DW0_DW1_CFG(GPP_I8, 0x84000502, 0x00000075), + /* DDPC_CTRLDATA */ + H110_PAD_DW0_DW1_CFG(GPP_I9, 0x84000102, 0x00000076), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_I10, 0x84000100, 0x00000077), /* GPIO */ +}; + +/* Early pad configuration in romstage. */ +static const struct pad_config early_gpio_table[] = { + /* GPIO Group GPP_A */ + H110_PAD_DW0_DW1_CFG(GPP_A0, 0x84000502, 0x00000018), /* RCIN# */ + H110_PAD_DW0_DW1_CFG(GPP_A1, 0x84000402, 0x00000019), /* LAD0 */ + H110_PAD_DW0_DW1_CFG(GPP_A2, 0x84000402, 0x0000001a), /* LAD1 */ + H110_PAD_DW0_DW1_CFG(GPP_A3, 0x84000402, 0x0000001b), /* LAD2 */ + H110_PAD_DW0_DW1_CFG(GPP_A4, 0x84000402, 0x0000001c), /* LAD3 */ + H110_PAD_DW0_DW1_CFG(GPP_A5, 0x84000600, 0x0000001d), /* LFRAME# */ + H110_PAD_DW0_DW1_CFG(GPP_A6, 0x84000402, 0x0000001e), /* SERIRQ */ + H110_PAD_DW0_DW1_CFG(GPP_A8, 0x84000500, 0x00000020), /* CLKRUN# */ + H110_PAD_DW0_DW1_CFG(GPP_A9, 0x84000600, 0x00001021), /* CLKOUT_LPC0 */ + H110_PAD_DW0_DW1_CFG(GPP_A10, 0x84000600, 0x00001022), /* CLKOUT_LPC1 */ + /* ---- */ + /* SUSWARN#/SUSPWRDNACK */ + H110_PAD_DW0_DW1_CFG(GPP_A13, 0x44000600, 0x00000025), /* SUSWARN#/SUSPWRDNACK */ + H110_PAD_DW0_DW1_CFG(GPP_A14, 0x84000100, 0x00001026), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_A15, 0x44000500, 0x00000027), /* SUS_ACK# */ +}; + +#endif diff --git a/src/mainboard/asus/h110m-e_m2/mainboard.c b/src/mainboard/asus/h110m-e_m2/mainboard.c new file mode 100644 index 0000000..4c1c6cd --- /dev/null +++ b/src/mainboard/asus/h110m-e_m2/mainboard.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Tristan Corrick <tristan(a)corrick.kiwi> + * Copyright (C) 2019 Maxim Polyakov <max.senia.poliak(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> + +static void mainboard_enable(struct device *dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/asus/h110m-e_m2/ramstage.c b/src/mainboard/asus/h110m-e_m2/ramstage.c new file mode 100644 index 0000000..c93e84c --- /dev/null +++ b/src/mainboard/asus/h110m-e_m2/ramstage.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation + * Copyright (C) 2019 Maxim Polyakov <max.senia.poliak(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/ramstage.h> +#include "include/gpio.h" + +void mainboard_silicon_init_params(FSP_SIL_UPD *params) +{ + /* Configure pads prior to SiliconInit() in case there's any + * dependencies during hardware initialization. */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + + params->CdClock = 3; + /* Enable Virtual Channel 1 */ + params->PchHdaVcType = 0x1; +} diff --git a/src/mainboard/asus/h110m-e_m2/romstage.c b/src/mainboard/asus/h110m-e_m2/romstage.c new file mode 100644 index 0000000..ae5e297 --- /dev/null +++ b/src/mainboard/asus/h110m-e_m2/romstage.c @@ -0,0 +1,86 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * Copyright (C) 2019 Pavel Sayekat <pavelsayekat(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/romstage.h> +#include <string.h> +#include <spd_bin.h> + +#define RCOMP_TARGET_PARAMS 0x5 + +static void mainboard_fill_dq_map_data(void *dq_map_ptr) +{ + /* DQ byte map */ + const u8 dq_map[2][12] = { + { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, + { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, + 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; + memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); +} + +static void mainboard_fill_dqs_map_data(void *dqs_map_ptr) +{ + /* DQS CPU<>DRAM map */ + const u8 dqs_map[2][8] = { + { 0, 1, 3, 2, 4, 5, 6, 7 }, + { 1, 0, 4, 5, 2, 3, 6, 7 } }; + memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map)); +} + +static void mainboard_fill_rcomp_res_data(void *rcomp_ptr) +{ + /* Rcomp resistor */ + const u16 RcompResistor[3] = { 200, 81, 162 }; + memcpy(rcomp_ptr, RcompResistor, + sizeof(RcompResistor)); +} + +static void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) +{ + /* Rcomp target */ + static const u16 RcompTarget[RCOMP_TARGET_PARAMS] = { + 100, 40, 40, 23, 40 }; + memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); +} + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *mem_cfg; + struct spd_block blk = { + .addr_map = { 0x50, 0x51, 0x52, 0x53, }, + }; + + mem_cfg = &mupd->FspmConfig; + mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0); + mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0); + mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); + mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); + + mem_cfg->DqPinsInterleaved = 1; + get_spd_smbus(&blk); + mem_cfg->MemorySpdDataLen = blk.len; + mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; + mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[2]; + mem_cfg->MemorySpdPtr01 = (uintptr_t)blk.spd_array[1]; + mem_cfg->MemorySpdPtr11 = (uintptr_t)blk.spd_array[3]; + dump_spd_info(&blk); + + /* use virtual channel 1 for the dmi interface of the PCH */ + mupd->FspmTestConfig.DmiVc1 = 1; + + /* desktop type */ + mem_cfg->UserBd = BOARD_TYPE_DESKTOP; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/34603 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Gerrit-Change-Number: 34603 Gerrit-PatchSet: 1 Gerrit-Owner: Pavel Sayekat Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP]crossgcc: Upgrade Python to version 3.8.2

by HAOUAS Elyes (Code Review)

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39148 ) Change subject: [WIP]crossgcc: Upgrade Python to version 3.8.2 ...................................................................... [WIP]crossgcc: Upgrade Python to version 3.8.2 Change-Id: I660994ece28f04d97de2fe3a074ebcf93fb4d2f4 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc D util/crossgcc/sum/Python-3.8.1.tar.xz.cksum A util/crossgcc/sum/Python-3.8.2.tar.xz.cksum 3 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/39148/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index fef4b82..eb2e4e9 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -55,7 +55,7 @@ BINUTILS_VERSION=2.34 GDB_VERSION=8.3.1 IASL_VERSION=20200214 -PYTHON_VERSION=3.8.1 +PYTHON_VERSION=3.8.2 EXPAT_VERSION=2.2.9 # CLANG version number CLANG_VERSION=9.0.0 diff --git a/util/crossgcc/sum/Python-3.8.1.tar.xz.cksum b/util/crossgcc/sum/Python-3.8.1.tar.xz.cksum deleted file mode 100644 index e899a45..0000000 --- a/util/crossgcc/sum/Python-3.8.1.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -a48fd28a037c0bcd7b7fc4d914c023f584e910ed tarballs/Python-3.8.1.tar.xz diff --git a/util/crossgcc/sum/Python-3.8.2.tar.xz.cksum b/util/crossgcc/sum/Python-3.8.2.tar.xz.cksum new file mode 100644 index 0000000..1a0c784 --- /dev/null +++ b/util/crossgcc/sum/Python-3.8.2.tar.xz.cksum @@ -0,0 +1 @@ +5ae54baf26628a7ed74206650a31192e6d5c6f93 tarballs/Python-3.8.2.tar.xz -- To view, visit https://review.coreboot.org/c/coreboot/+/39148 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I660994ece28f04d97de2fe3a074ebcf93fb4d2f4 Gerrit-Change-Number: 39148 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: crossgcc: Upgrade GMP to v6.2.0

by HAOUAS Elyes (Code Review)

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38465 ) Change subject: crossgcc: Upgrade GMP to v6.2.0 ...................................................................... crossgcc: Upgrade GMP to v6.2.0 gmp_freebsd-configure.patch is integrated in upstream so we don't need them anymore. Change-Id: I8404872f1b65e9173c1fcbd24d7da7bdd7937503 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc D util/crossgcc/patches/gmp-6.1.2_freebsd-configure.patch D util/crossgcc/sum/gmp-6.1.2.tar.xz.cksum A util/crossgcc/sum/gmp-6.2.0.tar.xz.cksum 4 files changed, 2 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/38465/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index ab2ea89..c9609e0 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -47,7 +47,7 @@ THREADS=1 # GCC toolchain version numbers -GMP_VERSION=6.1.2 +GMP_VERSION=6.2.0 MPFR_VERSION=4.0.2 MPC_VERSION=1.1.0 GCC_VERSION=8.3.0 diff --git a/util/crossgcc/patches/gmp-6.1.2_freebsd-configure.patch b/util/crossgcc/patches/gmp-6.1.2_freebsd-configure.patch deleted file mode 100644 index 5770af6..0000000 --- a/util/crossgcc/patches/gmp-6.1.2_freebsd-configure.patch +++ /dev/null @@ -1,20 +0,0 @@ ---- gmp-6.1.2.orig/configure 2016-12-16 16:45:32.000000000 +0100 -+++ gmp-6.1.2/configure 2017-03-08 14:26:11.194245000 +0100 -@@ -6776,7 +6776,7 @@ - long i; - for (i = 0; i < 88 + 1; i++) - a[i] = ~0L; -- r = malloc (10000 * sizeof (unsigned long)); -+ r = calloc (10000, sizeof (unsigned long)); - r2 = r; - for (i = 0; i < 528; i += 23) - { -@@ -8394,7 +8394,7 @@ - long i; - for (i = 0; i < 88 + 1; i++) - a[i] = ~0L; -- r = malloc (10000 * sizeof (unsigned long)); -+ r = calloc (10000, sizeof (unsigned long)); - r2 = r; - for (i = 0; i < 528; i += 23) - { diff --git a/util/crossgcc/sum/gmp-6.1.2.tar.xz.cksum b/util/crossgcc/sum/gmp-6.1.2.tar.xz.cksum deleted file mode 100644 index 774658c..0000000 --- a/util/crossgcc/sum/gmp-6.1.2.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -9dc6981197a7d92f339192eea974f5eca48fcffe tarballs/gmp-6.1.2.tar.xz diff --git a/util/crossgcc/sum/gmp-6.2.0.tar.xz.cksum b/util/crossgcc/sum/gmp-6.2.0.tar.xz.cksum new file mode 100644 index 0000000..b00b669 --- /dev/null +++ b/util/crossgcc/sum/gmp-6.2.0.tar.xz.cksum @@ -0,0 +1 @@ +052a5411dc74054240eec58132d2cf41211d0ff6 tarballs/gmp-6.2.0.tar.xz -- To view, visit https://review.coreboot.org/c/coreboot/+/38465 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8404872f1b65e9173c1fcbd24d7da7bdd7937503 Gerrit-Change-Number: 38465 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/lenovo/t530: Switch to overridetree

by Peter Lemenkov (Code Review)

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37602 ) Change subject: mb/lenovo/t530: Switch to overridetree ...................................................................... mb/lenovo/t530: Switch to overridetree Change-Id: I3dfa303b6aae2446fa3a1d67a6e31448277cacdb Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/lenovo/t530/Kconfig R src/mainboard/lenovo/t530/devicetree.cb A src/mainboard/lenovo/t530/variants/t530/overridetree.cb D src/mainboard/lenovo/t530/variants/w530/devicetree.cb A src/mainboard/lenovo/t530/variants/w530/overridetree.cb 5 files changed, 43 insertions(+), 198 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/37602/1 diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig index d1ba6a8..4b3303b 100644 --- a/src/mainboard/lenovo/t530/Kconfig +++ b/src/mainboard/lenovo/t530/Kconfig @@ -37,9 +37,9 @@ string default "lenovo/t530" -config DEVICETREE +config OVERRIDE_DEVICETREE string - default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/lenovo/t530/variants/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb similarity index 97% rename from src/mainboard/lenovo/t530/variants/t530/devicetree.cb rename to src/mainboard/lenovo/t530/devicetree.cb index c2a9259..62b622f 100644 --- a/src/mainboard/lenovo/t530/variants/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/devicetree.cb @@ -142,10 +142,6 @@ register "has_bdc_detection" = "1" register "bdc_gpio_num" = "54" register "bdc_gpio_lvl" = "0" - - register "has_wwan_detection" = "1" - register "wwan_gpio_num" = "70" - register "wwan_gpio_lvl" = "0" end chip drivers/lenovo/hybrid_graphics device pnp ff.f on end # dummy diff --git a/src/mainboard/lenovo/t530/variants/t530/overridetree.cb b/src/mainboard/lenovo/t530/variants/t530/overridetree.cb new file mode 100644 index 0000000..e106aa6 --- /dev/null +++ b/src/mainboard/lenovo/t530/variants/t530/overridetree.cb @@ -0,0 +1,13 @@ +chip northbridge/intel/sandybridge + device domain 0 on + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + device pci 1f.0 on # PCI-LPC bridge + chip ec/lenovo/h8 + register "has_wwan_detection" = "1" + register "wwan_gpio_num" = "70" + register "wwan_gpio_lvl" = "0" + end + end + end + end +end diff --git a/src/mainboard/lenovo/t530/variants/w530/devicetree.cb b/src/mainboard/lenovo/t530/variants/w530/devicetree.cb deleted file mode 100644 index f814c3f..0000000 --- a/src/mainboard/lenovo/t530/variants/w530/devicetree.cb +++ /dev/null @@ -1,192 +0,0 @@ -chip northbridge/intel/sandybridge - # IGD Displays - register "gfx.ndid" = "3" - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" - - # Enable DisplayPort Hotplug with 6ms pulse - register "gpu_dp_d_hotplug" = "0x06" - - register "gpu_dp_b_hotplug" = "0" - register "gpu_dp_c_hotplug" = "0" - - # Enable Panel as LVDS and configure power delays - register "gpu_panel_port_select" = "0" # LVDS - register "gpu_panel_power_cycle_delay" = "6" # T7: 500ms - register "gpu_panel_power_up_delay" = "100" # T1+T2: 10ms - register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms - register "gpu_panel_power_backlight_on_delay" = "2000" # T3: 200ms - register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms - register "gfx.use_spread_spectrum_clock" = "1" - register "gfx.link_frequency_270_mhz" = "1" - register "gpu_cpu_backlight" = "0x1155" - register "gpu_pch_backlight" = "0x11551155" - - device cpu_cluster 0 on - chip cpu/intel/model_206ax - # Magic APIC ID to locate this chip - device lapic 0x0 on end - device lapic 0xacac off end - - register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) - - register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7) - end - end - - register "pci_mmio_size" = "2048" - - device domain 0 on - subsystemid 0x17aa 0x21f6 inherit - - device pci 00.0 on end # Host bridge - device pci 01.0 on end # PCIe bridge for discrete graphics - device pci 02.0 on # Internal graphics VGA controller - subsystemid 0x17aa 0x21f5 - end - - chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - # GPI routing - # 0 No effect (default) - # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) - # 2 SCI (if corresponding GPIO_EN bit is also set) - register "alt_gp_smi_en" = "0x0000" - register "gpi1_routing" = "2" - register "gpi13_routing" = "2" - - # Enable SATA ports 0 (HDD bay) & 1 (ODD bay) & 2 (mSATA) & 3 (eSATA) & 4 (dock) - register "sata_port_map" = "0x3f" - # Set max SATA speed to 6.0 Gb/s - register "sata_interface_speed_support" = "0x3" - - register "gen1_dec" = "0x7c1601" - register "gen2_dec" = "0x0c15e1" - register "gen4_dec" = "0x0c06a1" - - # Enable zero-based linear PCIe root port functions - register "pcie_port_coalesce" = "1" - register "c2_latency" = "101" # c2 not supported - - register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" - - register "xhci_switchable_ports" = "0xf" - register "superspeed_capable_ports" = "0xf" - register "xhci_overcurrent_mapping" = "0x4000201" - - register "docking_supported" = "1" - - register "spi_uvscc" = "0x2005" - register "spi_lvscc" = "0x2005" - - device pci 14.0 on end # USB 3.0 Controller - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 on end # Management Engine KT - device pci 19.0 on # Intel Gigabit Ethernet - subsystemid 0x17aa 0x21f3 - end - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on # PCIe Port #1 - chip drivers/ricoh/rce822 # Ricoh cardreader - register "disable_mask" = "0x83" - register "sdwppol" = "1" - device pci 00.0 on end # Ricoh SD card reader - end - end - device pci 1c.1 on end # PCIe Port #2 - device pci 1c.2 on # PCIe Port #3 - smbios_slot_desc "7" "3" "ExpressCard Slot" "8" - end - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 off end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 off end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on # PCI-LPC bridge - chip ec/lenovo/pmh7 - device pnp ff.1 on end # dummy - register "backlight_enable" = "0x01" - register "dock_event_enable" = "0x01" - end - - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - - chip ec/lenovo/h8 - device pnp ff.2 on # dummy - io 0x60 = 0x62 - io 0x62 = 0x66 - io 0x64 = 0x1600 - io 0x66 = 0x1604 - end - - register "config0" = "0xa7" - register "config1" = "0x01" - register "config2" = "0xa0" - register "config3" = "0xe2" - - register "has_keyboard_backlight" = "1" - - register "beepmask0" = "0x00" - register "beepmask1" = "0x86" - register "has_power_management_beeps" = "0" - register "event2_enable" = "0xff" - register "event3_enable" = "0xff" - register "event4_enable" = "0xd0" - register "event5_enable" = "0xfc" - register "event6_enable" = "0x00" - register "event7_enable" = "0x01" - register "event8_enable" = "0x7b" - register "event9_enable" = "0xff" - register "eventa_enable" = "0x01" - register "eventb_enable" = "0x00" - register "eventc_enable" = "0xff" - register "eventd_enable" = "0xff" - register "evente_enable" = "0x0d" - - register "has_bdc_detection" = "1" - register "bdc_gpio_num" = "54" - register "bdc_gpio_lvl" = "0" - end - chip drivers/lenovo/hybrid_graphics - device pnp ff.f on end # dummy - - register "detect_gpio" = "21" - - register "has_panel_hybrid_gpio" = "1" - register "panel_hybrid_gpio" = "52" - register "panel_integrated_lvl" = "1" - - register "has_backlight_gpio" = "0" - register "has_dgpu_power_gpio" = "0" - - register "has_thinker1" = "1" - end - end - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on # SMBus - # eeprom, 8 virtual devices, same chip - chip drivers/i2c/at24rf08c - device i2c 54 on end - device i2c 55 on end - device i2c 56 on end - device i2c 57 on end - device i2c 5c on end - device i2c 5d on end - device i2c 5e on end - device i2c 5f on end - end - end - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 off end # Thermal - end - end -end diff --git a/src/mainboard/lenovo/t530/variants/w530/overridetree.cb b/src/mainboard/lenovo/t530/variants/w530/overridetree.cb new file mode 100644 index 0000000..31de364 --- /dev/null +++ b/src/mainboard/lenovo/t530/variants/w530/overridetree.cb @@ -0,0 +1,28 @@ +chip northbridge/intel/sandybridge + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" + register "gpu_dp_b_hotplug" = "0" + register "gpu_dp_c_hotplug" = "0" + device domain 0 on + device pci 02.0 on # Internal graphics VGA controller + subsystemid 0x17aa 0x21f5 + end + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "docking_supported" = "1" + device pci 16.3 on end # Management Engine KT + device pci 1c.0 on # PCIe Port #1 + chip drivers/ricoh/rce822 # Ricoh cardreader + register "disable_mask" = "0x83" + register "sdwppol" = "1" + device pci 00.0 on end # Ricoh SD card reader + end + end + device pci 1f.0 on # PCI-LPC bridge + chip ec/lenovo/h8 + register "config1" = "0x01" + register "config3" = "0xe2" + end + end + device pci 1f.6 off end # Thermal + end + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/37602 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3dfa303b6aae2446fa3a1d67a6e31448277cacdb Gerrit-Change-Number: 37602 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

12 hours, 26 minutes

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Change in coreboot[master]: asus/p2b,asus/p2b-ls: Declare \_SB.PCI0.MBRS in DSDT

by Keith Hui (Code Review)

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38601 ) Change subject: asus/p2b,asus/p2b-ls: Declare \_SB.PCI0.MBRS in DSDT ...................................................................... asus/p2b,asus/p2b-ls: Declare \_SB.PCI0.MBRS in DSDT sb/intel/i82371eb/isa.c has code that fills this path with CPU info, which was triggering errors in Linux because it was not declared in the DSDT. Change-Id: Ib85dd02504b068bb7ea71be2f22e425f3831595a Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/mainboard/asus/p2b-ls/dsdt.asl M src/mainboard/asus/p2b/dsdt.asl 2 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/38601/1 diff --git a/src/mainboard/asus/p2b-ls/dsdt.asl b/src/mainboard/asus/p2b-ls/dsdt.asl index 83e1df6..b350bc9 100644 --- a/src/mainboard/asus/p2b-ls/dsdt.asl +++ b/src/mainboard/asus/p2b-ls/dsdt.asl @@ -175,6 +175,7 @@ }) #include <northbridge/intel/i440bx/acpi/sb_pci0_crs.asl> + #include <southbridge/intel/i82371eb/acpi/isabridge.asl> /* Begin southbridge block */ Device (PX40) @@ -193,6 +194,7 @@ Device (SYSR) { Name (_HID, EisaId ("PNP0C02")) + Name (_UID, 0x02) Method (_CRS, 0, NotSerialized) { Name (BUF1, ResourceTemplate () diff --git a/src/mainboard/asus/p2b/dsdt.asl b/src/mainboard/asus/p2b/dsdt.asl index 279f772..3fc531a 100644 --- a/src/mainboard/asus/p2b/dsdt.asl +++ b/src/mainboard/asus/p2b/dsdt.asl @@ -161,6 +161,7 @@ }) #include <northbridge/intel/i440bx/acpi/sb_pci0_crs.asl> + #include <southbridge/intel/i82371eb/acpi/isabridge.asl> /* Begin southbridge block */ Device (PX40) @@ -179,6 +180,7 @@ Device (SYSR) { Name (_HID, EisaId ("PNP0C02")) + Name (_UID, 0x02) Method (_CRS, 0, NotSerialized) { Name (BUF1, ResourceTemplate () -- To view, visit https://review.coreboot.org/c/coreboot/+/38601 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib85dd02504b068bb7ea71be2f22e425f3831595a Gerrit-Change-Number: 38601 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-MessageType: newchange

12 hours, 29 minutes

3
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Change in coreboot[master]: i82371eb: Drop KB/Mouse/FDC declarations

by Keith Hui (Code Review)

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38600 ) Change subject: i82371eb: Drop KB/Mouse/FDC declarations ...................................................................... i82371eb: Drop KB/Mouse/FDC declarations These are declared by superio. Change-Id: I1db4aca7d682ec298b8f53cfab6ffe661e8ff6e0 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/southbridge/intel/i82371eb/acpi/isabridge.asl 1 file changed, 0 insertions(+), 68 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/38600/1 diff --git a/src/southbridge/intel/i82371eb/acpi/isabridge.asl b/src/southbridge/intel/i82371eb/acpi/isabridge.asl index 2f842d6..6a0cd45 100644 --- a/src/southbridge/intel/i82371eb/acpi/isabridge.asl +++ b/src/southbridge/intel/i82371eb/acpi/isabridge.asl @@ -14,74 +14,6 @@ * GNU General Public License for more details. */ -/* - * ISA portions taken from QEMU acpi-dsdt.dsl. - */ - -// Intel LPC Bus Device - 0:4.0 -Device (LPCB) -{ - Name(_ADR, 0x00040000) - - OperationRegion(PCIC, PCI_Config, 0x00, 0x100) - - /* PS/2 keyboard (seems to be important for WinXP install) */ - Device (KBD) - { - Name (_HID, EisaId ("PNP0303")) - Method (_STA, 0, NotSerialized) - { - Return (0x0f) - } - Method (_CRS, 0, NotSerialized) - { - Name (TMP, ResourceTemplate () { - IO (Decode16, 0x0060, 0x0060, 0x01, 0x01) - IO (Decode16, 0x0064, 0x0064, 0x01, 0x01) - IRQNoFlags () {1} - }) - Return (TMP) - } - } - - /* PS/2 mouse */ - Device (MOU) - { - Name (_HID, EisaId ("PNP0F13")) - Method (_STA, 0, NotSerialized) - { - Return (0x0f) - } - Method (_CRS, 0, NotSerialized) - { - Name (TMP, ResourceTemplate () { - IRQNoFlags () {12} - }) - Return (TMP) - } - } - - /* PS/2 floppy controller */ - Device (FDC0) - { - Name (_HID, EisaId ("PNP0700")) - Method (_STA, 0, NotSerialized) - { - Return (0x0f) - } - Method (_CRS, 0, NotSerialized) - { - Name (BUF0, ResourceTemplate () { - IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04) - IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01) - IRQNoFlags () {6} - DMA (Compatibility, NotBusMaster, Transfer8) {2} - }) - Return (BUF0) - } - } -} - Device(MBRS) { Name (_HID, EisaId ("PNP0C02")) Name (_UID, 0x01) -- To view, visit https://review.coreboot.org/c/coreboot/+/38600 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1db4aca7d682ec298b8f53cfab6ffe661e8ff6e0 Gerrit-Change-Number: 38600 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

12 hours, 29 minutes

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Change in coreboot[master]: asus/p2b-*: Move serial init to mainboard bootblock

by Keith Hui (Code Review)

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38670 ) Change subject: asus/p2b-*: Move serial init to mainboard bootblock ...................................................................... asus/p2b-*: Move serial init to mainboard bootblock Change-Id: I6f3ee68e7c76a8c6db6d75956e6a7fb75ef83850 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/mainboard/asus/p2b/Makefile.inc R src/mainboard/asus/p2b/early_init.c M src/northbridge/intel/i440bx/romstage.c 3 files changed, 3 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/38670/1 diff --git a/src/mainboard/asus/p2b/Makefile.inc b/src/mainboard/asus/p2b/Makefile.inc index 620b000..68cd7e7 100644 --- a/src/mainboard/asus/p2b/Makefile.inc +++ b/src/mainboard/asus/p2b/Makefile.inc @@ -1,4 +1,4 @@ -romstage-y += romstage.c +bootblock-y += early_init.c # If not building for the "main variant" of p2b, remove p2b's irq_tables.c from list # of files to compile, and replace with irq_tables.c for the variant only if diff --git a/src/mainboard/asus/p2b/romstage.c b/src/mainboard/asus/p2b/early_init.c similarity index 90% rename from src/mainboard/asus/p2b/romstage.c rename to src/mainboard/asus/p2b/early_init.c index fbd7124..725e614 100644 --- a/src/mainboard/asus/p2b/romstage.c +++ b/src/mainboard/asus/p2b/early_init.c @@ -14,13 +14,13 @@ * GNU General Public License for more details. */ -#include <northbridge/intel/i440bx/raminit.h> +#include <bootblock_common.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83977tf/w83977tf.h> #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) -void mainboard_enable_serial(void) +void bootblock_mainboard_early_init(void) { winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/northbridge/intel/i440bx/romstage.c b/src/northbridge/intel/i440bx/romstage.c index 1dee03a..8109c37 100644 --- a/src/northbridge/intel/i440bx/romstage.c +++ b/src/northbridge/intel/i440bx/romstage.c @@ -20,9 +20,6 @@ void mainboard_romstage_entry(void) { - mainboard_enable_serial(); - console_init(); - i82371eb_early_init(); sdram_initialize(); -- To view, visit https://review.coreboot.org/c/coreboot/+/38670 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f3ee68e7c76a8c6db6d75956e6a7fb75ef83850 Gerrit-Change-Number: 38670 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-MessageType: newchange

12 hours, 30 minutes

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Change in coreboot[master]: asus/p2b-*: Fold into p2b as variants thereof

by Keith Hui (Code Review)

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38621 ) Change subject: asus/p2b-*: Fold into p2b as variants thereof ...................................................................... asus/p2b-*: Fold into p2b as variants thereof Their DSDTs are unified in the process. As a result: p2b-ls gets the S1 entry from p2b All other p2b-* boards gain a DSDT paving the way for ACPI support. TEST=abuild Change-Id: Ibc9bfa4fc5b582bf658215bda298523e8ee7b36b Signed-off-by: Keith Hui <buurin(a)gmail.com> --- D src/mainboard/asus/p2b-d/Kconfig D src/mainboard/asus/p2b-d/Kconfig.name D src/mainboard/asus/p2b-d/board_info.txt D src/mainboard/asus/p2b-d/romstage.c D src/mainboard/asus/p2b-ds/Kconfig D src/mainboard/asus/p2b-ds/Kconfig.name D src/mainboard/asus/p2b-ds/board_info.txt D src/mainboard/asus/p2b-ds/mptable.c D src/mainboard/asus/p2b-ds/romstage.c D src/mainboard/asus/p2b-f/Kconfig D src/mainboard/asus/p2b-f/Kconfig.name D src/mainboard/asus/p2b-f/board_info.txt D src/mainboard/asus/p2b-f/romstage.c D src/mainboard/asus/p2b-ls/Kconfig D src/mainboard/asus/p2b-ls/Kconfig.name D src/mainboard/asus/p2b-ls/acpi_tables.c D src/mainboard/asus/p2b-ls/board_info.txt D src/mainboard/asus/p2b-ls/dsdt.asl D src/mainboard/asus/p2b-ls/romstage.c M src/mainboard/asus/p2b/Kconfig M src/mainboard/asus/p2b/Kconfig.name M src/mainboard/asus/p2b/dsdt.asl R src/mainboard/asus/p2b/mptable.c R src/mainboard/asus/p2b/variants/p2b-d/devicetree.cb R src/mainboard/asus/p2b/variants/p2b-d/irq_tables.c R src/mainboard/asus/p2b/variants/p2b-ds/devicetree.cb R src/mainboard/asus/p2b/variants/p2b-ds/irq_tables.c R src/mainboard/asus/p2b/variants/p2b-f/devicetree.cb R src/mainboard/asus/p2b/variants/p2b-f/irq_tables.c R src/mainboard/asus/p2b/variants/p2b-ls/devicetree.cb R src/mainboard/asus/p2b/variants/p2b-ls/irq_tables.c 31 files changed, 145 insertions(+), 665 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/38621/1 diff --git a/src/mainboard/asus/p2b-d/Kconfig b/src/mainboard/asus/p2b-d/Kconfig deleted file mode 100644 index 8db9b7a..0000000 --- a/src/mainboard/asus/p2b-d/Kconfig +++ /dev/null @@ -1,46 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -if BOARD_ASUS_P2B_D - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select CPU_INTEL_SLOT_1 - select NORTHBRIDGE_INTEL_I440BX - select SOUTHBRIDGE_INTEL_I82371EB - select SUPERIO_WINBOND_W83977TF - select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE - select SMP - select IOAPIC - select BOARD_ROMSIZE_KB_256 - select SDRAMPWR_4DIMM - -config MAINBOARD_DIR - string - default "asus/p2b-d" - -config MAINBOARD_PART_NUMBER - string - default "P2B-D" - -config IRQ_SLOT_COUNT - int - default 6 - -config MAX_CPUS - int - default 2 - -endif # BOARD_ASUS_P2B_D diff --git a/src/mainboard/asus/p2b-d/Kconfig.name b/src/mainboard/asus/p2b-d/Kconfig.name deleted file mode 100644 index 23e7808..0000000 --- a/src/mainboard/asus/p2b-d/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_ASUS_P2B_D - bool "P2B-D" diff --git a/src/mainboard/asus/p2b-d/board_info.txt b/src/mainboard/asus/p2b-d/board_info.txt deleted file mode 100644 index fdee74e..0000000 --- a/src/mainboard/asus/p2b-d/board_info.txt +++ /dev/null @@ -1,7 +0,0 @@ -Category: desktop -Board URL: ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440bx/p2b-d/ -ROM package: DIP32 -ROM protocol: Parallel -ROM socketed: y -Flashrom support: y -Release year: 1998 diff --git a/src/mainboard/asus/p2b-d/romstage.c b/src/mainboard/asus/p2b-d/romstage.c deleted file mode 100644 index 7fad06b..0000000 --- a/src/mainboard/asus/p2b-d/romstage.c +++ /dev/null @@ -1,18 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Shares romstage with P2B-DS */ -#include "../p2b-ds/romstage.c" diff --git a/src/mainboard/asus/p2b-ds/Kconfig b/src/mainboard/asus/p2b-ds/Kconfig deleted file mode 100644 index 8b55174..0000000 --- a/src/mainboard/asus/p2b-ds/Kconfig +++ /dev/null @@ -1,46 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -if BOARD_ASUS_P2B_DS - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select CPU_INTEL_SLOT_1 - select NORTHBRIDGE_INTEL_I440BX - select SOUTHBRIDGE_INTEL_I82371EB - select SUPERIO_WINBOND_W83977TF - select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE - select SMP - select IOAPIC - select BOARD_ROMSIZE_KB_256 - select SDRAMPWR_4DIMM - -config MAINBOARD_DIR - string - default "asus/p2b-ds" - -config MAINBOARD_PART_NUMBER - string - default "P2B-DS" - -config IRQ_SLOT_COUNT - int - default 7 - -config MAX_CPUS - int - default 2 - -endif # BOARD_ASUS_P2B_DS diff --git a/src/mainboard/asus/p2b-ds/Kconfig.name b/src/mainboard/asus/p2b-ds/Kconfig.name deleted file mode 100644 index 0335139..0000000 --- a/src/mainboard/asus/p2b-ds/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_ASUS_P2B_DS - bool "P2B-DS" diff --git a/src/mainboard/asus/p2b-ds/board_info.txt b/src/mainboard/asus/p2b-ds/board_info.txt deleted file mode 100644 index 29a7266..0000000 --- a/src/mainboard/asus/p2b-ds/board_info.txt +++ /dev/null @@ -1,7 +0,0 @@ -Category: desktop -Board URL: ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440bx/p2b-ds/ -ROM package: DIP32 -ROM protocol: Parallel -ROM socketed: y -Flashrom support: y -Release year: 1998 diff --git a/src/mainboard/asus/p2b-ds/mptable.c b/src/mainboard/asus/p2b-ds/mptable.c deleted file mode 100644 index b492511..0000000 --- a/src/mainboard/asus/p2b-ds/mptable.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Uwe Hermann <uwe(a)hermann-uwe.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <stdint.h> - -static void *smp_write_config_table(void *v) -{ - int ioapic_id, ioapic_ver, isa_bus; - struct mp_config_table *mc; - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - smp_write_processors(mc); - - mptable_write_buses(mc, NULL, &isa_bus); - - ioapic_id = 2; - ioapic_ver = 0x11; /* External Intel 82093AA IOAPIC. */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - /* Legacy Interrupts */ - mptable_add_isa_interrupts(mc, isa_bus, ioapic_id, 0); - - /* I/O Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x13, ioapic_id, 0x13); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x18, ioapic_id, 0x13); - - /* Local Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */ - mptable_lintsrc(mc, 0x1); - - /* Compute the checksums. */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/asus/p2b-ds/romstage.c b/src/mainboard/asus/p2b-ds/romstage.c deleted file mode 100644 index d0456e5..0000000 --- a/src/mainboard/asus/p2b-ds/romstage.c +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Uwe Hermann <uwe(a)hermann-uwe.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <northbridge/intel/i440bx/raminit.h> -#include <superio/winbond/common/winbond.h> -#include <superio/winbond/w83977tf/w83977tf.h> - -#define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) - -void mainboard_enable_serial(void) -{ - winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); -} diff --git a/src/mainboard/asus/p2b-f/Kconfig b/src/mainboard/asus/p2b-f/Kconfig deleted file mode 100644 index efe625c..0000000 --- a/src/mainboard/asus/p2b-f/Kconfig +++ /dev/null @@ -1,38 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -if BOARD_ASUS_P2B_F - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select CPU_INTEL_SLOT_1 - select NORTHBRIDGE_INTEL_I440BX - select SOUTHBRIDGE_INTEL_I82371EB - select SUPERIO_WINBOND_W83977TF - select HAVE_PIRQ_TABLE - select BOARD_ROMSIZE_KB_256 - -config MAINBOARD_DIR - string - default "asus/p2b-f" - -config MAINBOARD_PART_NUMBER - string - default "P2B-F" - -config IRQ_SLOT_COUNT - int - default 7 - -endif # BOARD_ASUS_P2B_F diff --git a/src/mainboard/asus/p2b-f/Kconfig.name b/src/mainboard/asus/p2b-f/Kconfig.name deleted file mode 100644 index a433376..0000000 --- a/src/mainboard/asus/p2b-f/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_ASUS_P2B_F - bool "P2B-F" diff --git a/src/mainboard/asus/p2b-f/board_info.txt b/src/mainboard/asus/p2b-f/board_info.txt deleted file mode 100644 index 79b8d91..0000000 --- a/src/mainboard/asus/p2b-f/board_info.txt +++ /dev/null @@ -1,7 +0,0 @@ -Category: desktop -Board URL: ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440bx/p2b-f/ -ROM package: DIP32 -ROM protocol: Parallel -ROM socketed: y -Flashrom support: y -Release year: 1998 diff --git a/src/mainboard/asus/p2b-f/romstage.c b/src/mainboard/asus/p2b-f/romstage.c deleted file mode 100644 index 31a100c..0000000 --- a/src/mainboard/asus/p2b-f/romstage.c +++ /dev/null @@ -1,18 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Shares romstage with the better supported P2B-LS sibling. */ -#include "../p2b-ls/romstage.c" diff --git a/src/mainboard/asus/p2b-ls/Kconfig b/src/mainboard/asus/p2b-ls/Kconfig deleted file mode 100644 index 60124fe..0000000 --- a/src/mainboard/asus/p2b-ls/Kconfig +++ /dev/null @@ -1,40 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2010 Keith Hui <buurin(a)gmail.com> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -if BOARD_ASUS_P2B_LS - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select CPU_INTEL_SLOT_1 - select NORTHBRIDGE_INTEL_I440BX - select SOUTHBRIDGE_INTEL_I82371EB - select SUPERIO_WINBOND_W83977TF - select HAVE_PIRQ_TABLE - select BOARD_ROMSIZE_KB_256 - select SDRAMPWR_4DIMM - select HAVE_ACPI_TABLES - -config MAINBOARD_DIR - string - default "asus/p2b-ls" - -config MAINBOARD_PART_NUMBER - string - default "P2B-LS" - -config IRQ_SLOT_COUNT - int - default 8 - -endif # BOARD_ASUS_P2B_LS diff --git a/src/mainboard/asus/p2b-ls/Kconfig.name b/src/mainboard/asus/p2b-ls/Kconfig.name deleted file mode 100644 index 0ad0f47..0000000 --- a/src/mainboard/asus/p2b-ls/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_ASUS_P2B_LS - bool "P2B-LS" diff --git a/src/mainboard/asus/p2b-ls/acpi_tables.c b/src/mainboard/asus/p2b-ls/acpi_tables.c deleted file mode 100644 index d740ee1..0000000 --- a/src/mainboard/asus/p2b-ls/acpi_tables.c +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/acpi.h> - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* mainboard has no ioapic */ - return current; -} diff --git a/src/mainboard/asus/p2b-ls/board_info.txt b/src/mainboard/asus/p2b-ls/board_info.txt deleted file mode 100644 index 21bf26e..0000000 --- a/src/mainboard/asus/p2b-ls/board_info.txt +++ /dev/null @@ -1,7 +0,0 @@ -Category: desktop -Board URL: ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440bx/p2b-ls/ -ROM package: DIP32 -ROM protocol: Parallel -ROM socketed: y -Flashrom support: y -Release year: 1998 diff --git a/src/mainboard/asus/p2b-ls/dsdt.asl b/src/mainboard/asus/p2b-ls/dsdt.asl deleted file mode 100644 index b350bc9..0000000 --- a/src/mainboard/asus/p2b-ls/dsdt.asl +++ /dev/null @@ -1,272 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2017 Keith Hui <buurin(a)gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <southbridge/intel/i82371eb/i82371eb.h> - -#define SUPERIO_PNP_BASE 0x3F0 -#define SUPERIO_SHOW_UARTA -#define SUPERIO_SHOW_UARTB -#define SUPERIO_SHOW_FDC -#define SUPERIO_SHOW_LPT - -#include <arch/acpi.h> -DefinitionBlock ("DSDT.aml", "DSDT", 2, OEM_ID, ACPI_TABLE_CREATOR, 1) -{ - /* \_PR scope defining the main processor is generated in SSDT. */ - - OperationRegion(X80, SystemIO, 0x80, 1) - Field(X80, ByteAcc, NoLock, Preserve) - { - P80, 8 - } - - /* - * For now only define 2 power states: - * - S0 which is fully on - * - S5 which is soft off - * Any others would involve declaring the wake up methods. - */ - - /* - * Intel 82371EB (PIIX4E) datasheet, section 7.2.3, page 142 - * - * 0: soft off/suspend to disk S5 - * 1: suspend to ram S3 - * 2: powered on suspend, context lost S2 - * Note: 'context lost' means the CPU restarts at the reset - * vector - * 3: powered on suspend, CPU context lost S1 - * Note: Looks like 'CPU context lost' does _not_ mean the - * CPU restarts at the reset vector. Most likely only - * caches are lost, so both 0x3 and 0x4 map to ACPI S1 - * 4: powered on suspend, context maintained S1 - * 5: working (clock control) S0 - * 6: reserved - * 7: reserved - */ - Name (\_S0, Package () { 0x05, 0x05, 0x00, 0x00 }) - /* - * Kept as a memo of the value needed, but blocked out until - * suspend/resume support is implemented. - */ - /*Name (\_S1, Package () { 0x04, 0x07, 0x00, 0x00 })*/ - /*Name (\_S4, Package () { 0x01, 0x06, 0x00, 0x00 })*/ - Name (\_S5, Package () { 0x00, 0x06, 0x00, 0x00 }) - - OperationRegion (GPOB, SystemIO, DEFAULT_PMBASE+DEVCTL, 0x10) - Field (GPOB, ByteAcc, NoLock, Preserve) - { - Offset (0x03), - TO12, 1, /* Device trap 12 */ - Offset (0x08), - FANM, 1, /* GPO0, meant for fan */ - Offset (0x09), - PLED, 1, /* GPO8, meant for power LED. Per PIIX4 datasheet */ - , 3, /* this goes low when power is cut from its core. */ - , 2, - , 16, - MSG0, 1 /* GPO30, message LED */ - } - - /* Prepare To Sleep, Arg0 is target S-state */ - Method (\_PTS, 1, NotSerialized) - { - /* Disable fan, blink power LED, if not turning off */ - If (LNotEqual (Arg0, 0x05)) - { - Store (Zero, FANM) - Store (Zero, PLED) - } - - /* Arms SMI for device 12 */ - Store (One, TO12) - /* Put out a POST code */ - Or (Arg0, 0xF0, P80) - } - - Method (\_WAK, 1, NotSerialized) - { - /* Re-enable fan, stop power led blinking */ - Store (One, FANM) - Store (One, PLED) - /* wake OK */ - Return(Package(0x02){0x00, 0x00}) - } - - /* Root of the bus hierarchy */ - Scope (\_SB) - { - Device (PWRB) - { - /* Power Button Device */ - Name (_HID, EisaId ("PNP0C0C")) - Method (_STA, 0, NotSerialized) - { - Return (0x0B) - } - } - #include <southbridge/intel/i82371eb/acpi/intx.asl> - - PCI_INTX_DEV(LNKA, \_SB.PCI0.PX40.PIRA, 1) - PCI_INTX_DEV(LNKB, \_SB.PCI0.PX40.PIRB, 2) - PCI_INTX_DEV(LNKC, \_SB.PCI0.PX40.PIRC, 3) - PCI_INTX_DEV(LNKD, \_SB.PCI0.PX40.PIRD, 4) - - /* Top PCI device */ - Device (PCI0) - { - Name (_HID, EisaId ("PNP0A03")) - Name (_UID, 0x00) - Name (_BBN, 0x00) - - /* PCI Routing Table */ - Name (_PRT, Package () { - Package (0x04) { 0x0001FFFF, 0, LNKA, 0 }, - Package (0x04) { 0x0001FFFF, 1, LNKB, 0 }, - Package (0x04) { 0x0001FFFF, 2, LNKC, 0 }, - Package (0x04) { 0x0001FFFF, 3, LNKD, 0 }, - - Package (0x04) { 0x0004FFFF, 0, LNKA, 0 }, - Package (0x04) { 0x0004FFFF, 1, LNKB, 0 }, - Package (0x04) { 0x0004FFFF, 2, LNKC, 0 }, - Package (0x04) { 0x0004FFFF, 3, LNKD, 0 }, - - Package (0x04) { 0x0006FFFF, 0, LNKD, 0 }, - Package (0x04) { 0x0006FFFF, 1, LNKA, 0 }, - Package (0x04) { 0x0006FFFF, 2, LNKB, 0 }, - Package (0x04) { 0x0006FFFF, 3, LNKC, 0 }, - - Package (0x04) { 0x0009FFFF, 0, LNKD, 0 }, - Package (0x04) { 0x0009FFFF, 1, LNKA, 0 }, - Package (0x04) { 0x0009FFFF, 2, LNKB, 0 }, - Package (0x04) { 0x0009FFFF, 3, LNKC, 0 }, - - Package (0x04) { 0x000AFFFF, 0, LNKC, 0 }, - Package (0x04) { 0x000AFFFF, 1, LNKD, 0 }, - Package (0x04) { 0x000AFFFF, 2, LNKA, 0 }, - Package (0x04) { 0x000AFFFF, 3, LNKB, 0 }, - - Package (0x04) { 0x0007FFFF, 0, LNKC, 0 }, - Package (0x04) { 0x0007FFFF, 1, LNKD, 0 }, - Package (0x04) { 0x0007FFFF, 2, LNKA, 0 }, - Package (0x04) { 0x0007FFFF, 3, LNKB, 0 }, - - Package (0x04) { 0x000BFFFF, 0, LNKB, 0 }, - Package (0x04) { 0x000BFFFF, 1, LNKC, 0 }, - Package (0x04) { 0x000BFFFF, 2, LNKD, 0 }, - Package (0x04) { 0x000BFFFF, 3, LNKA, 0 }, - - Package (0x04) { 0x000CFFFF, 0, LNKA, 0 }, - Package (0x04) { 0x000CFFFF, 1, LNKB, 0 }, - Package (0x04) { 0x000CFFFF, 2, LNKC, 0 }, - Package (0x04) { 0x000CFFFF, 3, LNKD, 0 }, - - }) - #include <northbridge/intel/i440bx/acpi/sb_pci0_crs.asl> - #include <southbridge/intel/i82371eb/acpi/isabridge.asl> - - /* Begin southbridge block */ - Device (PX40) - { - Name(_ADR, 0x00040000) - OperationRegion (PIRQ, PCI_Config, 0x60, 0x04) - Field (PIRQ, ByteAcc, NoLock, Preserve) - { - PIRA, 8, - PIRB, 8, - PIRC, 8, - PIRD, 8 - } - - /* PNP Motherboard Resources */ - Device (SYSR) - { - Name (_HID, EisaId ("PNP0C02")) - Name (_UID, 0x02) - Method (_CRS, 0, NotSerialized) - { - Name (BUF1, ResourceTemplate () - { - /* PM register ports */ - IO (Decode16, 0x0000, 0x0000, 0x01, 0x40, _Y06) - /* SMBus register ports */ - IO (Decode16, 0x0000, 0x0000, 0x01, 0x10, _Y07) - /* PIIX4E ports */ - /* Aliased DMA ports */ - IO (Decode16, 0x0010, 0x0010, 0x01, 0x10, ) - /* Aliased PIC ports */ - IO (Decode16, 0x0022, 0x0022, 0x01, 0x1E, ) - /* Aliased timer ports */ - IO (Decode16, 0x0050, 0x0050, 0x01, 0x04, ) - IO (Decode16, 0x0062, 0x0062, 0x01, 0x02, ) - IO (Decode16, 0x0065, 0x0065, 0x01, 0x0B, ) - IO (Decode16, 0x0074, 0x0074, 0x01, 0x0C, ) - IO (Decode16, 0x0091, 0x0091, 0x01, 0x03, ) - IO (Decode16, 0x00A2, 0x00A2, 0x01, 0x1E, ) - IO (Decode16, 0x00E0, 0x00E0, 0x01, 0x10, ) - IO (Decode16, 0x0294, 0x0294, 0x01, 0x04, ) - IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x02, ) - IO (Decode16, 0x04D0, 0x04D0, 0x01, 0x02, ) - }) - CreateWordField (BUF1, _Y06._MIN, PMLO) - CreateWordField (BUF1, _Y06._MAX, PMRL) - CreateWordField (BUF1, _Y07._MIN, SBLO) - CreateWordField (BUF1, _Y07._MAX, SBRL) - - And (\_SB.PCI0.PX43.PM00, 0xFFFE, PMLO) - And (\_SB.PCI0.PX43.SB00, 0xFFFE, SBLO) - Store (PMLO, PMRL) - Store (SBLO, SBRL) - Return (BUF1) - } - } - #include <southbridge/intel/i82371eb/acpi/i82371eb.asl> - } - Device (PX43) - { - Name (_ADR, 0x00040003) // _ADR: Address - OperationRegion (IPMU, PCI_Config, PMBA, 0x02) - Field (IPMU, ByteAcc, NoLock, Preserve) - { - PM00, 16 - } - - OperationRegion (ISMB, PCI_Config, SMBBA, 0x02) - Field (ISMB, ByteAcc, NoLock, Preserve) - { - SB00, 16 - } - } - - #include <superio/winbond/w83977tf/acpi/superio.asl> - } - } - - /* ACPI Message */ - Scope (\_SI) - { - Method (_MSG, 1, NotSerialized) - { - If (LEqual (Arg0, Zero)) - { - Store (One, MSG0) - } - Else - { - Store (Zero, MSG0) - } - } - } -} diff --git a/src/mainboard/asus/p2b-ls/romstage.c b/src/mainboard/asus/p2b-ls/romstage.c deleted file mode 100644 index b79ac82..0000000 --- a/src/mainboard/asus/p2b-ls/romstage.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <northbridge/intel/i440bx/raminit.h> -#include <superio/winbond/common/winbond.h> -/* FIXME: The ASUS P2B-LS has a Winbond W83977EF, actually. */ -#include <superio/winbond/w83977tf/w83977tf.h> - -#define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) - -void mainboard_enable_serial(void) -{ - winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); -} diff --git a/src/mainboard/asus/p2b/Kconfig b/src/mainboard/asus/p2b/Kconfig index 65e7681..3d18bf8 100644 --- a/src/mainboard/asus/p2b/Kconfig +++ b/src/mainboard/asus/p2b/Kconfig @@ -12,7 +12,15 @@ ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. ## -if BOARD_ASUS_P2B + +if BOARD_ASUS_P2B || BOARD_ASUS_P2B_D || BOARD_ASUS_P2B_DS || BOARD_ASUS_P2B_F || BOARD_ASUS_P2B_LS + +config BASE_ASUS_P2B_D + def_bool n + select SDRAMPWR_4DIMM + select HAVE_MP_TABLE + select IOAPIC + select SMP config BOARD_SPECIFIC_OPTIONS def_bool y @@ -22,18 +30,42 @@ select SUPERIO_WINBOND_W83977TF select HAVE_PIRQ_TABLE select BOARD_ROMSIZE_KB_256 - select HAVE_ACPI_TABLES + select HAVE_ACPI_TABLES if BOARD_ASUS_P2B || BOARD_ASUS_P2B_LS + select SDRAMPWR_4DIMM if BOARD_ASUS_P2B_F || BOARD_ASUS_P2B_LS + select BASE_ASUS_P2B_D if BOARD_ASUS_P2B_D || BOARD_ASUS_P2B_DS + +config MAX_CPUS + int + default 2 if BASE_ASUS_P2B_D + default 1 config MAINBOARD_DIR string default "asus/p2b" -config MAINBOARD_PART_NUMBER +config VARIANT_DIR string - default "P2B" + default "p2b-d" if BOARD_ASUS_P2B_D + default "p2b-ds" if BOARD_ASUS_P2B_DS + default "p2b-f" if BOARD_ASUS_P2B_F + default "p2b-ls" if BOARD_ASUS_P2B_LS + +config OVERRIDE_DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" if ! BOARD_ASUS_P2B config IRQ_SLOT_COUNT int - default 6 + default 8 if BOARD_ASUS_P2B_LS + default 6 if BOARD_ASUS_P2B || BOARD_ASUS_P2B_D + default 7 -endif # BOARD_ASUS_P2B +config MAINBOARD_PART_NUMBER + string + default "P2B" if BOARD_ASUS_P2B + default "P2B-D" if BOARD_ASUS_P2B_D + default "P2B-DS" if BOARD_ASUS_P2B_DS + default "P2B-F" if BOARD_ASUS_P2B_F + default "P2B-LS" if BOARD_ASUS_P2B_LS + +endif diff --git a/src/mainboard/asus/p2b/Kconfig.name b/src/mainboard/asus/p2b/Kconfig.name index 60d6028..a6cd510 100644 --- a/src/mainboard/asus/p2b/Kconfig.name +++ b/src/mainboard/asus/p2b/Kconfig.name @@ -1,2 +1,15 @@ config BOARD_ASUS_P2B bool "P2B" + +config BOARD_ASUS_P2B_D + bool "P2B-D" + +config BOARD_ASUS_P2B_DS + bool "P2B-DS" + +config BOARD_ASUS_P2B_F + bool "P2B-F" + +config BOARD_ASUS_P2B_LS + bool "P2B-LS" + diff --git a/src/mainboard/asus/p2b/dsdt.asl b/src/mainboard/asus/p2b/dsdt.asl index 3fc531a..08fb3a5b 100644 --- a/src/mainboard/asus/p2b/dsdt.asl +++ b/src/mainboard/asus/p2b/dsdt.asl @@ -46,12 +46,12 @@ * 0: soft off/suspend to disk S5 * 1: suspend to ram S3 * 2: powered on suspend, context lost S2 - * Note: 'context lost' means the CPU restarts at the reset - * vector + * Note: 'context lost' means the CPU restarts at the reset + * vector * 3: powered on suspend, CPU context lost S1 - * Note: Looks like 'CPU context lost' does _not_ mean the - * CPU restarts at the reset vector. Most likely only - * caches are lost, so both 0x3 and 0x4 map to ACPI S1 + * Note: Looks like 'CPU context lost' does _not_ mean the + * CPU restarts at the reset vector. Most likely only + * caches are lost, so both 0x3 and 0x4 map to ACPI S1 * 4: powered on suspend, context maintained S1 * 5: working (clock control) S0 * 6: reserved @@ -70,23 +70,32 @@ FANM, 1, /* GPO0, meant for fan */ Offset (0x09), PLED, 1, /* GPO8, meant for power LED. Per PIIX4 datasheet */ - , 3, /* this goes low when power is cut from its core. */ - , 2, - , 16, + , 3, /* this goes low when power is cut from its core. */ + , 2, + , 16, MSG0, 1 /* GPO30, message LED */ } +#if CONFIG(BOARD_ASUS_P2B_D) || CONFIG(BOARD_ASUS_P2B_DS) + Name (\PICF, 0x00) + Method (_PIC, 1, NotSerialized) // _PIC: Interrupt Model (ACPI spec 2.0c, 5.8.1) + { + \PICF = Arg0 + } +#endif + /* Prepare To Sleep, Arg0 is target S-state */ Method (\_PTS, 1, NotSerialized) { /* Disable fan, blink power LED, if not turning off */ If (LNotEqual (Arg0, 0x05)) { - Store (Zero, FANM) - Store (Zero, PLED) + Store (Zero, FANM) + Store (Zero, PLED) } /* Arms SMI for device 12 */ + /* TODO: Factory BIOS only does this for S1 */ Store (One, TO12) /* Put out a POST code */ Or (Arg0, 0xF0, P80) @@ -128,7 +137,11 @@ Name (_BBN, 0x00) /* PCI Routing Table */ +#if CONFIG(BOARD_ASUS_P2B_D) || CONFIG(BOARD_ASUS_P2B_DS) + Name (PICM, Package () { +#else Name (_PRT, Package () { +#endif Package (0x04) { 0x0001FFFF, 0, LNKA, 0 }, Package (0x04) { 0x0001FFFF, 1, LNKB, 0 }, Package (0x04) { 0x0001FFFF, 2, LNKC, 0 }, @@ -138,7 +151,18 @@ Package (0x04) { 0x0004FFFF, 1, LNKB, 0 }, Package (0x04) { 0x0004FFFF, 2, LNKC, 0 }, Package (0x04) { 0x0004FFFF, 3, LNKD, 0 }, - +#if CONFIG(BOARD_ASUS_P2B_LS) || CONFIG(BOARD_ASUS_P2B_DS) + Package (0x04) { 0x0006FFFF, 0, LNKD, 0 }, + Package (0x04) { 0x0006FFFF, 1, LNKA, 0 }, + Package (0x04) { 0x0006FFFF, 2, LNKB, 0 }, + Package (0x04) { 0x0006FFFF, 3, LNKC, 0 }, +#endif +#if CONFIG(BOARD_ASUS_P2B_LS) + Package (0x04) { 0x0007FFFF, 0, LNKC, 0 }, + Package (0x04) { 0x0007FFFF, 1, LNKD, 0 }, + Package (0x04) { 0x0007FFFF, 2, LNKA, 0 }, + Package (0x04) { 0x0007FFFF, 3, LNKB, 0 }, +#endif Package (0x04) { 0x0009FFFF, 0, LNKD, 0 }, Package (0x04) { 0x0009FFFF, 1, LNKA, 0 }, Package (0x04) { 0x0009FFFF, 2, LNKB, 0 }, @@ -158,8 +182,63 @@ Package (0x04) { 0x000CFFFF, 1, LNKB, 0 }, Package (0x04) { 0x000CFFFF, 2, LNKC, 0 }, Package (0x04) { 0x000CFFFF, 3, LNKD, 0 }, +#if CONFIG(BOARD_ASUS_P2B_F) + Package (0x04) { 0x000DFFFF, 0, LNKD, 0 }, + Package (0x04) { 0x000DFFFF, 1, LNKA, 0 }, + Package (0x04) { 0x000DFFFF, 2, LNKB, 0 }, + Package (0x04) { 0x000DFFFF, 3, LNKC, 0 }, +#endif }) +#if CONFIG(BOARD_ASUS_P2B_D) || CONFIG(BOARD_ASUS_P2B_DS) + Name (APIC, Package () { + Package (0x04) { 0x000CFFFF, 0, 0, 0x10 }, + Package (0x04) { 0x000CFFFF, 1, 0, 0x11 }, + Package (0x04) { 0x000CFFFF, 2, 0, 0x12 }, + Package (0x04) { 0x000CFFFF, 3, 0, 0x13 }, + + Package (0x04) { 0x000BFFFF, 0, 0, 0x11 }, + Package (0x04) { 0x000BFFFF, 1, 0, 0x12 }, + Package (0x04) { 0x000BFFFF, 2, 0, 0x13 }, + Package (0x04) { 0x000BFFFF, 3, 0, 0x10 }, + + Package (0x04) { 0x000AFFFF, 0, 0, 0x12 }, + Package (0x04) { 0x000AFFFF, 1, 0, 0x13 }, + Package (0x04) { 0x000AFFFF, 2, 0, 0x10 }, + Package (0x04) { 0x000AFFFF, 3, 0, 0x11 }, + + Package (0x04) { 0x0009FFFF, 0, 0, 0x13 }, + Package (0x04) { 0x0009FFFF, 1, 0, 0x10 }, + Package (0x04) { 0x0009FFFF, 2, 0, 0x11 }, + Package (0x04) { 0x0009FFFF, 3, 0, 0x12 }, +#if CONFIG(BOARD_ASUS_P2B_DS) + Package (0x04) { 0x0006FFFF, 0, 0, 0x13 }, + Package (0x04) { 0x0006FFFF, 1, 0, 0x10 }, + Package (0x04) { 0x0006FFFF, 2, 0, 0x11 }, + Package (0x04) { 0x0006FFFF, 3, 0, 0x12 }, +#endif + Package (0x04) { 0x0004FFFF, 0, 0, 0x10 }, + Package (0x04) { 0x0004FFFF, 1, 0, 0x11 }, + Package (0x04) { 0x0004FFFF, 2, 0, 0x12 }, + Package (0x04) { 0x0004FFFF, 3, 0, 0x13 }, + + Package (0x04) { 0x0001FFFF, 0, 0, 0x10 }, + Package (0x04) { 0x0001FFFF, 1, 0, 0x11 }, + Package (0x04) { 0x0001FFFF, 2, 0, 0x12 }, + Package (0x04) { 0x0001FFFF, 3, 0, 0x13 } + }) + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + If (!\PICF) + { + Return (PICM) + } + Else + { + Return (APIC) + } + } +#endif #include <northbridge/intel/i440bx/acpi/sb_pci0_crs.asl> #include <southbridge/intel/i82371eb/acpi/isabridge.asl> @@ -226,13 +305,13 @@ OperationRegion (IPMU, PCI_Config, PMBA, 0x02) Field (IPMU, ByteAcc, NoLock, Preserve) { - PM00, 16 + PM00, 16 } OperationRegion (ISMB, PCI_Config, SMBBA, 0x02) Field (ISMB, ByteAcc, NoLock, Preserve) { - SB00, 16 + SB00, 16 } } diff --git a/src/mainboard/asus/p2b-d/mptable.c b/src/mainboard/asus/p2b/mptable.c similarity index 92% rename from src/mainboard/asus/p2b-d/mptable.c rename to src/mainboard/asus/p2b/mptable.c index 8f643d1..fddb218 100644 --- a/src/mainboard/asus/p2b-d/mptable.c +++ b/src/mainboard/asus/p2b/mptable.c @@ -40,6 +40,8 @@ /* I/O Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x13, ioapic_id, 0x13); /* UHCI */ + if (CONFIG(BOARD_ASUS_P2B_DS)) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x18, ioapic_id, 0x13); /* Local Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */ mptable_lintsrc(mc, isa_bus); diff --git a/src/mainboard/asus/p2b-d/devicetree.cb b/src/mainboard/asus/p2b/variants/p2b-d/devicetree.cb similarity index 100% rename from src/mainboard/asus/p2b-d/devicetree.cb rename to src/mainboard/asus/p2b/variants/p2b-d/devicetree.cb diff --git a/src/mainboard/asus/p2b-d/irq_tables.c b/src/mainboard/asus/p2b/variants/p2b-d/irq_tables.c similarity index 100% rename from src/mainboard/asus/p2b-d/irq_tables.c rename to src/mainboard/asus/p2b/variants/p2b-d/irq_tables.c diff --git a/src/mainboard/asus/p2b-ds/devicetree.cb b/src/mainboard/asus/p2b/variants/p2b-ds/devicetree.cb similarity index 100% rename from src/mainboard/asus/p2b-ds/devicetree.cb rename to src/mainboard/asus/p2b/variants/p2b-ds/devicetree.cb diff --git a/src/mainboard/asus/p2b-ds/irq_tables.c b/src/mainboard/asus/p2b/variants/p2b-ds/irq_tables.c similarity index 100% rename from src/mainboard/asus/p2b-ds/irq_tables.c rename to src/mainboard/asus/p2b/variants/p2b-ds/irq_tables.c diff --git a/src/mainboard/asus/p2b-f/devicetree.cb b/src/mainboard/asus/p2b/variants/p2b-f/devicetree.cb similarity index 100% rename from src/mainboard/asus/p2b-f/devicetree.cb rename to src/mainboard/asus/p2b/variants/p2b-f/devicetree.cb diff --git a/src/mainboard/asus/p2b-f/irq_tables.c b/src/mainboard/asus/p2b/variants/p2b-f/irq_tables.c similarity index 100% rename from src/mainboard/asus/p2b-f/irq_tables.c rename to src/mainboard/asus/p2b/variants/p2b-f/irq_tables.c diff --git a/src/mainboard/asus/p2b-ls/devicetree.cb b/src/mainboard/asus/p2b/variants/p2b-ls/devicetree.cb similarity index 100% rename from src/mainboard/asus/p2b-ls/devicetree.cb rename to src/mainboard/asus/p2b/variants/p2b-ls/devicetree.cb diff --git a/src/mainboard/asus/p2b-ls/irq_tables.c b/src/mainboard/asus/p2b/variants/p2b-ls/irq_tables.c similarity index 100% rename from src/mainboard/asus/p2b-ls/irq_tables.c rename to src/mainboard/asus/p2b/variants/p2b-ls/irq_tables.c -- To view, visit https://review.coreboot.org/c/coreboot/+/38621 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibc9bfa4fc5b582bf658215bda298523e8ee7b36b Gerrit-Change-Number: 38621 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-MessageType: newchange

12 hours, 36 minutes

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Change in coreboot[master]: cpu/x86/Makefile.inc: Fix external toolchain build

by Arthur Heymans (Code Review)

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37193 ) Change subject: cpu/x86/Makefile.inc: Fix external toolchain build ...................................................................... cpu/x86/Makefile.inc: Fix external toolchain build The sipi_vector.S just needs to be linked as relocatable so there is no need to invoke the compiler. TEST: BUILD_TIMELESS=1 has the same hashes Change-Id: I0370f1590a70cffb48c7930f6ae85956b506b09c Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/37193/1 diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc index 9c18d44..194a76c 100644 --- a/src/cpu/x86/Makefile.inc +++ b/src/cpu/x86/Makefile.inc @@ -27,7 +27,7 @@ rmodules_$(ARCH-$(TARGET_STAGE)-y)-$(CONFIG_PARALLEL_MP) += sipi_vector.S $(SIPI_DOTO): $(call src-to-obj,rmodules_$(ARCH-$(TARGET_STAGE)-y),src/cpu/x86/sipi_vector.S) - $(CC_rmodules_$(ARCH-$(TARGET_STAGE)-y)) $(CFLAGS_rmodules_$(ARCH-$(TARGET_STAGE)-y)) -nostdlib -r -o $@ $^ + $(LD_rmodules_$(ARCH-$(TARGET_STAGE)-y)) -nostdlib -r -o $@ $^ $(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_DOTO), 0,$(ARCH-$(TARGET_STAGE)-y))) -- To view, visit https://review.coreboot.org/c/coreboot/+/37193 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0370f1590a70cffb48c7930f6ae85956b506b09c Gerrit-Change-Number: 37193 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

13 hours, 8 minutes

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