James has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31363
Change subject: mb/gigabyte: add GA-P67A-UD3R ......................................................................
mb/gigabyte: add GA-P67A-UD3R
This is a Intel P67 chipset motherboard for Sandy Bridge processors. The P67 chipset has no graphics support. This board has redundant 4MB SOIC-8 flash chips, and flashrom is usable with the vendor BIOS.
This is an original P67 chipset, and is affected by a SATA 2 hardware bug. There is a variant P67A-UD3R-B3 that is unaffected.
The function of PCIe ports PCIEX4 and PCIEX1_* are configured in PCHSTRP9. By default, PCIEX4 is configured for 4 lanes and PCIEX1_* are disabled. This can be switched to 1 lane for all ports.
Tested and working: - Intel Core i7 2600 - 4 DIMMs (4x4GB DDR3) - Booting Linux (SeaBIOS) - Native RAM init - PCIe graphics - Onboard Ethernet - Sensors (SuperIO) - S3 sleep - S4 hibernate - SATA 3 - USB 2.0 - USB 3.0 - Onboard audio (speakers, headphones) - CMOS - EHCI debug port - Serial port
Not tested: - SATA 2 - PS/2 keyboard/mouse - Digital audio
Change-Id: I4fbf50376be3184bf01a3bc8aae09bce54676707 Signed-off-by: James Ye jye836@gmail.com --- A src/mainboard/gigabyte/ga-p67a-ud3r/Kconfig A src/mainboard/gigabyte/ga-p67a-ud3r/Kconfig.name A src/mainboard/gigabyte/ga-p67a-ud3r/Makefile.inc A src/mainboard/gigabyte/ga-p67a-ud3r/acpi/ec.asl A src/mainboard/gigabyte/ga-p67a-ud3r/acpi/mainboard.asl A src/mainboard/gigabyte/ga-p67a-ud3r/acpi/platform.asl A src/mainboard/gigabyte/ga-p67a-ud3r/acpi/superio.asl A src/mainboard/gigabyte/ga-p67a-ud3r/acpi_tables.c A src/mainboard/gigabyte/ga-p67a-ud3r/board_info.txt A src/mainboard/gigabyte/ga-p67a-ud3r/cmos.default A src/mainboard/gigabyte/ga-p67a-ud3r/cmos.layout A src/mainboard/gigabyte/ga-p67a-ud3r/devicetree.cb A src/mainboard/gigabyte/ga-p67a-ud3r/dsdt.asl A src/mainboard/gigabyte/ga-p67a-ud3r/gpio.c A src/mainboard/gigabyte/ga-p67a-ud3r/hda_verb.c A src/mainboard/gigabyte/ga-p67a-ud3r/romstage.c 16 files changed, 781 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/31363/1
diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/Kconfig b/src/mainboard/gigabyte/ga-p67a-ud3r/Kconfig new file mode 100644 index 0000000..c1efe12 --- /dev/null +++ b/src/mainboard/gigabyte/ga-p67a-ud3r/Kconfig @@ -0,0 +1,40 @@ +if BOARD_GIGABYTE_GA_P67A_UD3R + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_4096 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_BD82X6X + select USE_NATIVE_RAMINIT + select SUPERIO_ITE_IT8728F + +config MAINBOARD_DIR + string + default "gigabyte/ga-p67a-ud3r" + +config MAINBOARD_PART_NUMBER + string + default "GA-P67A-UD3R" + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x5001 + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x1458 + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX + int + default 2 + +endif # BOARD_GIGABYTE_GA_P67A_UD3R diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/Kconfig.name b/src/mainboard/gigabyte/ga-p67a-ud3r/Kconfig.name new file mode 100644 index 0000000..15f0655 --- /dev/null +++ b/src/mainboard/gigabyte/ga-p67a-ud3r/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_GIGABYTE_GA_P67A_UD3R + bool "GA-P67A-UD3R" diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/Makefile.inc b/src/mainboard/gigabyte/ga-p67a-ud3r/Makefile.inc new file mode 100644 index 0000000..3dae61e --- /dev/null +++ b/src/mainboard/gigabyte/ga-p67a-ud3r/Makefile.inc @@ -0,0 +1 @@ +romstage-y += gpio.c diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/acpi/ec.asl b/src/mainboard/gigabyte/ga-p67a-ud3r/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/gigabyte/ga-p67a-ud3r/acpi/ec.asl diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/acpi/mainboard.asl b/src/mainboard/gigabyte/ga-p67a-ud3r/acpi/mainboard.asl new file mode 100644 index 0000000..34de86f --- /dev/null +++ b/src/mainboard/gigabyte/ga-p67a-ud3r/acpi/mainboard.asl @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (_SB) +{ + Device (PWRB) + { + Name (_HID, EisaId("PNP0C0C")) + } +} diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/acpi/platform.asl b/src/mainboard/gigabyte/ga-p67a-ud3r/acpi/platform.asl new file mode 100644 index 0000000..d8d3320 --- /dev/null +++ b/src/mainboard/gigabyte/ga-p67a-ud3r/acpi/platform.asl @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + Return(Package(){0,0}) +} diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/acpi/superio.asl b/src/mainboard/gigabyte/ga-p67a-ud3r/acpi/superio.asl new file mode 100644 index 0000000..2b20c77 --- /dev/null +++ b/src/mainboard/gigabyte/ga-p67a-ud3r/acpi/superio.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 James Ye jye836@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/acpi_tables.c b/src/mainboard/gigabyte/ga-p67a-ud3r/acpi_tables.c new file mode 100644 index 0000000..a2f383b --- /dev/null +++ b/src/mainboard/gigabyte/ga-p67a-ud3r/acpi_tables.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/bd82x6x/nvs.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; +} diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/board_info.txt b/src/mainboard/gigabyte/ga-p67a-ud3r/board_info.txt new file mode 100644 index 0000000..c6f16ae --- /dev/null +++ b/src/mainboard/gigabyte/ga-p67a-ud3r/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.gigabyte.com/Motherboard/GA-P67A-UD3R-rev-10 +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2011 diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/cmos.default b/src/mainboard/gigabyte/ga-p67a-ud3r/cmos.default new file mode 100644 index 0000000..60de212 --- /dev/null +++ b/src/mainboard/gigabyte/ga-p67a-ud3r/cmos.default @@ -0,0 +1,5 @@ +boot_option=Fallback +debug_level=Debug +nmi=Enable +power_on_after_fail=Disable +sata_mode=AHCI diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/cmos.layout b/src/mainboard/gigabyte/ga-p67a-ud3r/cmos.layout new file mode 100644 index 0000000..4e5c0a8 --- /dev/null +++ b/src/mainboard/gigabyte/ga-p67a-ud3r/cmos.layout @@ -0,0 +1,107 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2014 Vladimir Serbinenko +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +# Status Register A +# ----------------------------------------------------------------- +# Status Register B +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 3 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +#392 3 r 0 unused +395 4 e 4 debug_level +#399 1 r 0 unused + +#400 8 r 0 reserved for century byte + +# coreboot config options: southbridge +#400 1 e 0 unused +408 1 e 1 nmi +409 2 e 5 power_on_after_fail +411 1 e 6 sata_mode + +# coreboot config options: northbridge +#432 3 r 0 unused + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable + +2 0 Enable +2 1 Disable + +3 0 Fallback +3 1 Normal + +4 0 Emergency +4 1 Alert +4 2 Critical +4 3 Error +4 4 Warning +4 5 Notice +4 6 Info +4 7 Debug +4 8 Spew + +5 0 Disable +5 1 Enable +5 2 Keep + +6 0 AHCI +6 1 Compatible + +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/devicetree.cb b/src/mainboard/gigabyte/ga-p67a-ud3r/devicetree.cb new file mode 100644 index 0000000..4ed458d --- /dev/null +++ b/src/mainboard/gigabyte/ga-p67a-ud3r/devicetree.cb @@ -0,0 +1,124 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 James Ye jye836@gmail.com +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +# +chip northbridge/intel/sandybridge + device cpu_cluster 0x0 on + chip cpu/intel/model_206ax + device lapic 0x0 on end + + # Magic APIC ID to locate this chip + device lapic 0xacac off end + + register "c1_acpower" = "1" + register "c2_acpower" = "3" + register "c3_acpower" = "5" + + register "c1_battery" = "1" + register "c2_battery" = "3" + register "c3_battery" = "5" + end + end + + device domain 0x0 on + subsystemid 0x1458 0x5001 inherit + + device pci 00.0 on end # Host bridge + device pci 01.0 on # PCIe bridge (PCIEX16) + subsystemid 0x1458 0x5000 + end + device pci 02.0 off end # Internal graphics + + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "sata_port_map" = "0x3f" + register "sata_interface_speed_support" = "0x3" + + register "gen1_dec" = "0x000c0801" + register "gen2_dec" = "0x000c0291" + + register "pcie_port_coalesce" = "0" + register "c2_latency" = "0x0065" + register "p_cnt_throttling_supported" = "1" + + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + + device pci 16.0 off end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 off end # Intel Gigabit Ethernet + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x1458 0x5006 + end + device pci 1b.0 on # High Definition Audio controller + subsystemid 0x1458 0xa102 + end + device pci 1c.0 on end # Unrouted, to disable coalescing + device pci 1c.1 on # PCIe Port #2 + device pci 00.0 on # USB 3.0 controller + subsystemid 0x1458 0x5007 + end + end + device pci 1c.2 on # PCIe Port #3 + device pci 00.0 on # Ethernet controller + subsystemid 0x1458 0xe000 + end + end + device pci 1c.3 on # PCIe Port #4 + device pci 00.0 on # PCI bridge + subsystemid 0x1458 0x5000 + end + end + device pci 1c.4 on end # PCIe Port #5 (PCIEX4) + device pci 1c.5 off end # PCIe Port #6 (PCIEX1_1) + device pci 1c.6 off end # PCIe Port #7 (PCIEX1_2) + device pci 1c.7 off end # PCIe Port #8 (PCIEX1_3) + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x1458 0x5006 + end + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on # LPC bridge + chip superio/ite/it8728f + device pnp 2e.0 off end # Floppy, not routed + device pnp 2e.1 on # COM1 + io 0x60 = 0x03f8 + irq 0x70 = 4 + end + device pnp 2e.2 off end # COM2, not routed + device pnp 2e.3 off end # Parallel port, not rounted + device pnp 2e.4 on # Environment Controller + io 0x60 = 0x0290 + io 0x62 = 0x0 + irq 0x70 = 0 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.6 off end # Mouse + device pnp 2e.7 off end # GPIO + device pnp 2e.a off end # CIR, not routed + end + end + device pci 1f.2 on # SATA Controller 1 + subsystemid 0x1458 0xb005 + end + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/dsdt.asl b/src/mainboard/gigabyte/ga-p67a-ud3r/dsdt.asl new file mode 100644 index 0000000..365a0fa --- /dev/null +++ b/src/mainboard/gigabyte/ga-p67a-ud3r/dsdt.asl @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 James Ye jye836@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +DefinitionBlock ( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI 2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 // OEM revision +) +{ + // Some generic macros + #include "acpi/mainboard.asl" + #include "acpi/platform.asl" + #include "acpi/superio.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + + // Global NVS and variables + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + + // Chipset specific sleep states + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + + Device (_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } +} diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/gpio.c b/src/mainboard/gigabyte/ga-p67a-ud3r/gpio.c new file mode 100644 index 0000000..c65f432 --- /dev/null +++ b/src/mainboard/gigabyte/ga-p67a-ud3r/gpio.c @@ -0,0 +1,204 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2019 James Ye jye836@gmail.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio11 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_GPIO, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio47 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_LOW, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/hda_verb.c b/src/mainboard/gigabyte/ga-p67a-ud3r/hda_verb.c new file mode 100644 index 0000000..a843a2b --- /dev/null +++ b/src/mainboard/gigabyte/ga-p67a-ud3r/hda_verb.c @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2019 James Ye jye836@gmail.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0892, /* Codec Vendor / Device ID: Realtek */ + 0x1458a022, /* Subsystem ID */ + + 15, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x2, 0x1458a022), + + /* NID 0x11. */ + AZALIA_PIN_CFG(0x2, 0x11, 0x99430140), + + /* NID 0x12. */ + AZALIA_PIN_CFG(0x2, 0x12, 0x411111f0), + + /* NID 0x14. */ + AZALIA_PIN_CFG(0x2, 0x14, 0x01014410), + + /* NID 0x15. */ + AZALIA_PIN_CFG(0x2, 0x15, 0x01011412), + + /* NID 0x16. */ + AZALIA_PIN_CFG(0x2, 0x16, 0x01016411), + + /* NID 0x17. */ + AZALIA_PIN_CFG(0x2, 0x17, 0x01012414), + + /* NID 0x18. */ + AZALIA_PIN_CFG(0x2, 0x18, 0x01a19c50), + + /* NID 0x19. */ + AZALIA_PIN_CFG(0x2, 0x19, 0x02a19c60), + + /* NID 0x1a. */ + AZALIA_PIN_CFG(0x2, 0x1a, 0x0181345f), + + /* NID 0x1b. */ + AZALIA_PIN_CFG(0x2, 0x1b, 0x02214c20), + + /* NID 0x1c. */ + AZALIA_PIN_CFG(0x2, 0x1c, 0x593301f0), + + /* NID 0x1d. */ + AZALIA_PIN_CFG(0x2, 0x1d, 0x4005e601), + + /* NID 0x1e. */ + AZALIA_PIN_CFG(0x2, 0x1e, 0x014b6130), + + /* NID 0x1f. */ + AZALIA_PIN_CFG(0x2, 0x1f, 0x411111f0), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/romstage.c b/src/mainboard/gigabyte/ga-p67a-ud3r/romstage.c new file mode 100644 index 0000000..3037b73 --- /dev/null +++ b/src/mainboard/gigabyte/ga-p67a-ud3r/romstage.c @@ -0,0 +1,75 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2019 James Ye jye836@gmail.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <superio/ite/common/ite.h> +#include <superio/ite/it8728f/it8728f.h> + +#define SUPERIO_BASE 0x2e +#define SUPERIO_GPIO PNP_DEV(SUPERIO_BASE, IT8728F_GPIO) +#define SERIAL_DEV PNP_DEV(SUPERIO_BASE, 0x01) + +void pch_enable_lpc(void) +{ + pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | CNF1_LPC_EN | + CNF2_LPC_EN | COMA_LPC_EN); +} + +void mainboard_rcba_config(void) +{ +} + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 1, 0 }, + { 1, 1, 0 }, + { 1, 1, 1 }, + { 1, 1, 1 }, + { 1, 6, 2 }, + { 1, 6, 2 }, + { 1, 6, 3 }, + { 1, 5, 3 }, + { 1, 5, 4 }, + { 1, 5, 4 }, + { 1, 5, 5 }, + { 1, 5, 5 }, + { 1, 5, 6 }, + { 1, 5, 6 }, +}; + +void mainboard_early_init(int s3resume) +{ +} + +void mainboard_config_superio(void) +{ + /* Enable serial port */ + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + + /* Disable SIO WDT which kicks in DualBIOS */ + ite_reg_write(SUPERIO_GPIO, 0xEF, 0x7E); +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x51, id_only); + read_spd(&spd[2], 0x52, id_only); + read_spd(&spd[3], 0x53, id_only); +}
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31363 )
Change subject: mb/gigabyte: add GA-P67A-UD3R ......................................................................
Patch Set 1: Code-Review+1
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31363 )
Change subject: mb/gigabyte: add GA-P67A-UD3R ......................................................................
Patch Set 1:
(3 comments)
Could you please add a page for the documentation directory?
https://review.coreboot.org/#/c/31363/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/31363/1//COMMIT_MSG@11 PS1, Line 11: flashrom flashrom’s internal programmmer
https://review.coreboot.org/#/c/31363/1//COMMIT_MSG@20 PS1, Line 20: How did you create the port? autoport?
https://review.coreboot.org/#/c/31363/1//COMMIT_MSG@38 PS1, Line 38: What payload and Linux kernel version did you use?
James has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31363 )
Change subject: mb/gigabyte: add GA-P67A-UD3R ......................................................................
Patch Set 1:
(3 comments)
Could you please add a page for the documentation directory?
Should it go in this commit, or another?
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31363 )
Change subject: mb/gigabyte: add GA-P67A-UD3R ......................................................................
Patch Set 1:
(4 comments)
https://review.coreboot.org/#/c/31363/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/31363/1//COMMIT_MSG@40 PS1, Line 40: - SATA 2 Are these untested because they broke due to the hardware bug?
https://review.coreboot.org/#/c/31363/1/src/mainboard/gigabyte/ga-p67a-ud3r/... File src/mainboard/gigabyte/ga-p67a-ud3r/dsdt.asl:
https://review.coreboot.org/#/c/31363/1/src/mainboard/gigabyte/ga-p67a-ud3r/... PS1, Line 16: #include <arch/acpi.h> Please add a blank line after this line
https://review.coreboot.org/#/c/31363/1/src/mainboard/gigabyte/ga-p67a-ud3r/... PS1, Line 26: // Some generic macros Please remove
https://review.coreboot.org/#/c/31363/1/src/mainboard/gigabyte/ga-p67a-ud3r/... File src/mainboard/gigabyte/ga-p67a-ud3r/romstage.c:
https://review.coreboot.org/#/c/31363/1/src/mainboard/gigabyte/ga-p67a-ud3r/... PS1, Line 65: /* Disable SIO WDT which kicks in DualBIOS */ This line looks familiar.
James has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31363 )
Change subject: mb/gigabyte: add GA-P67A-UD3R ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/#/c/31363/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/31363/1//COMMIT_MSG@40 PS1, Line 40: - SATA 2
Are these untested because they broke due to the hardware bug?
They don't work in vendor BIOS, I assume this is the case.
https://review.coreboot.org/#/c/31363/1/src/mainboard/gigabyte/ga-p67a-ud3r/... File src/mainboard/gigabyte/ga-p67a-ud3r/romstage.c:
https://review.coreboot.org/#/c/31363/1/src/mainboard/gigabyte/ga-p67a-ud3r/... PS1, Line 65: /* Disable SIO WDT which kicks in DualBIOS */
This line looks familiar.
I'll add you to the copyright.
Hello Patrick Rudolph, Angel Pons, Arthur Heymans, Paul Menzel, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31363
to look at the new patch set (#2).
Change subject: mb/gigabyte: add GA-P67A-UD3R ......................................................................
mb/gigabyte: add GA-P67A-UD3R
This is a Intel P67 chipset motherboard for Sandy Bridge processors. The P67 chipset has no graphics support. This board has redundant 4MB SOIC-8 flash chips, and the flashrom internal programmer is usable with the vendor BIOS.
This is an original P67 chipset, and is affected by a SATA 2 hardware bug. There is a variant P67A-UD3R-B3 that is unaffected.
The function of PCIe ports PCIEX4 and PCIEX1_* are configured in PCHSTRP9. By default, PCIEX4 is configured for 4 lanes and PCIEX1_* are disabled. This can be switched to 1 lane for all ports.
This port was created with the help of autoport and other GIGABYTE ports.
Tested and working: - Intel Core i7 2600 - 4 DIMMs (4x4GB DDR3) with native RAM init - Booting Linux 4.9 from SeaBIOS (SATA and USB) - PCIe graphics - Onboard Ethernet - Sensors (SuperIO) - S3 sleep - S4 hibernate - SATA 3 - USB 2.0 - USB 3.0 - Onboard audio (speakers, headphones) - CMOS - EHCI debug port - Serial port
Not tested: - SATA 2 (hardware bug) - PS/2 keyboard/mouse - Digital audio
Change-Id: I4fbf50376be3184bf01a3bc8aae09bce54676707 Signed-off-by: James Ye jye836@gmail.com --- A src/mainboard/gigabyte/ga-p67a-ud3r/Kconfig A src/mainboard/gigabyte/ga-p67a-ud3r/Kconfig.name A src/mainboard/gigabyte/ga-p67a-ud3r/Makefile.inc A src/mainboard/gigabyte/ga-p67a-ud3r/acpi/ec.asl A src/mainboard/gigabyte/ga-p67a-ud3r/acpi/mainboard.asl A src/mainboard/gigabyte/ga-p67a-ud3r/acpi/platform.asl A src/mainboard/gigabyte/ga-p67a-ud3r/acpi/superio.asl A src/mainboard/gigabyte/ga-p67a-ud3r/acpi_tables.c A src/mainboard/gigabyte/ga-p67a-ud3r/board_info.txt A src/mainboard/gigabyte/ga-p67a-ud3r/cmos.default A src/mainboard/gigabyte/ga-p67a-ud3r/cmos.layout A src/mainboard/gigabyte/ga-p67a-ud3r/devicetree.cb A src/mainboard/gigabyte/ga-p67a-ud3r/dsdt.asl A src/mainboard/gigabyte/ga-p67a-ud3r/gpio.c A src/mainboard/gigabyte/ga-p67a-ud3r/hda_verb.c A src/mainboard/gigabyte/ga-p67a-ud3r/romstage.c 16 files changed, 782 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/31363/2
James has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31363 )
Change subject: mb/gigabyte: add GA-P67A-UD3R ......................................................................
Patch Set 2:
(6 comments)
Still need to add documentation.
https://review.coreboot.org/#/c/31363/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/31363/1//COMMIT_MSG@11 PS1, Line 11: flashrom
flashrom’s internal programmmer
Done
https://review.coreboot.org/#/c/31363/1//COMMIT_MSG@20 PS1, Line 20:
How did you create the port? autoport?
Done
https://review.coreboot.org/#/c/31363/1//COMMIT_MSG@38 PS1, Line 38:
What payload and Linux kernel version did you use?
Done
https://review.coreboot.org/#/c/31363/1//COMMIT_MSG@40 PS1, Line 40: - SATA 2
They don't work in vendor BIOS, I assume this is the case.
Done
https://review.coreboot.org/#/c/31363/1/src/mainboard/gigabyte/ga-p67a-ud3r/... File src/mainboard/gigabyte/ga-p67a-ud3r/dsdt.asl:
https://review.coreboot.org/#/c/31363/1/src/mainboard/gigabyte/ga-p67a-ud3r/... PS1, Line 16: #include <arch/acpi.h>
Please add a blank line after this line
Done
https://review.coreboot.org/#/c/31363/1/src/mainboard/gigabyte/ga-p67a-ud3r/... PS1, Line 26: // Some generic macros
Please remove
Done
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31363 )
Change subject: mb/gigabyte: add GA-P67A-UD3R ......................................................................
Patch Set 2: Code-Review+1
(5 comments)
https://review.coreboot.org/#/c/31363/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/31363/2//COMMIT_MSG@42 PS2, Line 42: - PS/2 keyboard/mouse As a side note: this is likely to be broken on IT8728 code, recently tested those ports on GA-H61M-S2PV and it doesn't work. It could also be mainboard-specific code is missing, but I haven't debugged any further.
(nothing to change on the commit message)
https://review.coreboot.org/#/c/31363/2/src/mainboard/gigabyte/ga-p67a-ud3r/... File src/mainboard/gigabyte/ga-p67a-ud3r/cmos.layout:
https://review.coreboot.org/#/c/31363/2/src/mainboard/gigabyte/ga-p67a-ud3r/... PS2, Line 62: # coreboot config options: northbridge : #432 3 r 0 unused This can be removed
https://review.coreboot.org/#/c/31363/2/src/mainboard/gigabyte/ga-p67a-ud3r/... PS2, Line 65: # SandyBridge MRC Scrambler Seed values : 896 32 r 0 mrc_scrambler_seed : 928 32 r 0 mrc_scrambler_seed_s3 : 960 16 r 0 mrc_scrambler_seed_chk These shouldn't be needed for native raminit.
https://review.coreboot.org/#/c/31363/2/src/mainboard/gigabyte/ga-p67a-ud3r/... File src/mainboard/gigabyte/ga-p67a-ud3r/devicetree.cb:
https://review.coreboot.org/#/c/31363/2/src/mainboard/gigabyte/ga-p67a-ud3r/... PS2, Line 80: device pci 00.0 on # PCI bridge : subsystemid 0x1458 0x5000 : end Were the PCI ports tested?
https://review.coreboot.org/#/c/31363/2/src/mainboard/gigabyte/ga-p67a-ud3r/... File src/mainboard/gigabyte/ga-p67a-ud3r/romstage.c:
https://review.coreboot.org/#/c/31363/2/src/mainboard/gigabyte/ga-p67a-ud3r/... PS2, Line 33: CNF2_LPC_EN This is for decoding I/O locations 4Eh and 4Fh to the LPC interface. The SuperIO is on 2Eh / 2Fh, so it doesn't seem to be needed, unless there is some other chip on the board.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31363 )
Change subject: mb/gigabyte: add GA-P67A-UD3R ......................................................................
Patch Set 2:
Patch Set 1:
(3 comments)
Could you please add a page for the documentation directory?
Should it go in this commit, or another?
I’d say the same commit, but it’s up to you.
James has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31363 )
Change subject: mb/gigabyte: add GA-P67A-UD3R ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/#/c/31363/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/31363/2//COMMIT_MSG@42 PS2, Line 42: - PS/2 keyboard/mouse
As a side note: this is likely to be broken on IT8728 code, recently tested those ports on GA-H61M-S […]
Interesting. I tested a PS/2 keyboard and it worked. Not sure if a mouse works, since it shares the same physical port.
https://review.coreboot.org/#/c/31363/2/src/mainboard/gigabyte/ga-p67a-ud3r/... File src/mainboard/gigabyte/ga-p67a-ud3r/devicetree.cb:
https://review.coreboot.org/#/c/31363/2/src/mainboard/gigabyte/ga-p67a-ud3r/... PS2, Line 80: device pci 00.0 on # PCI bridge : subsystemid 0x1458 0x5000 : end
Were the PCI ports tested?
I did a brief test, and at least one port works reliably. Not sure about the other port, there might be an issue with the PCI card I used, or the board itself.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31363 )
Change subject: mb/gigabyte: add GA-P67A-UD3R ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/#/c/31363/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/31363/2//COMMIT_MSG@42 PS2, Line 42: - PS/2 keyboard/mouse
Interesting. I tested a PS/2 keyboard and it worked. […]
Just a hunch: as the code calls set_kbc_ps2_mode(), maybe it is only needed for specific boards and not always for this chip?
https://review.coreboot.org/#/c/31363/2/src/mainboard/gigabyte/ga-p67a-ud3r/... File src/mainboard/gigabyte/ga-p67a-ud3r/devicetree.cb:
https://review.coreboot.org/#/c/31363/2/src/mainboard/gigabyte/ga-p67a-ud3r/... PS2, Line 80: device pci 00.0 on # PCI bridge : subsystemid 0x1458 0x5000 : end
I did a brief test, and at least one port works reliably. […]
Can't find a _PRT ACPI method for this in your code. Maybe it's worth to check if the original firmware had (a non-standard) one.
Hello Patrick Rudolph, Angel Pons, Arthur Heymans, Paul Menzel, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31363
to look at the new patch set (#3).
Change subject: mb/gigabyte: add GA-P67A-UD3R ......................................................................
mb/gigabyte: add GA-P67A-UD3R
This is a Intel P67 chipset motherboard for Sandy Bridge processors. The P67 chipset has no graphics support. This board has redundant 4MB SOIC-8 flash chips, and the flashrom internal programmer is usable with the vendor BIOS.
This is an original P67 chipset, and is affected by a SATA 2 hardware bug. There is a variant P67A-UD3R-B3 that is unaffected.
The function of PCI Express ports PCIEX4 and PCIEX1_* are configured in PCHSTRP9. By default, PCIEX4 is configured for 4 lanes and PCIEX1_* are disabled. This can be switched to 1 lane for all ports.
This port was created with the help of autoport and other GIGABYTE ports.
Tested and working: - Intel Core i7 2600 - 4 DIMMs (4x4GB DDR3) with native RAM init - Booting Linux 4.19 from SeaBIOS (SATA and USB) - PCI Express graphics - Onboard Ethernet - Sensors (SuperIO) - S3 sleep - S4 hibernate - SATA 3 - USB 2.0 - USB 3.0 - Onboard audio (speakers, headphones) - CMOS - EHCI debug port - Serial port - Conventional PCI - PS/2 keyboard
Not tested: - SATA 2 (hardware bug) - PS/2 mouse - Digital audio
Change-Id: I4fbf50376be3184bf01a3bc8aae09bce54676707 Signed-off-by: James Ye jye836@gmail.com --- A src/mainboard/gigabyte/ga-p67a-ud3r/Kconfig A src/mainboard/gigabyte/ga-p67a-ud3r/Kconfig.name A src/mainboard/gigabyte/ga-p67a-ud3r/Makefile.inc A src/mainboard/gigabyte/ga-p67a-ud3r/acpi/ec.asl A src/mainboard/gigabyte/ga-p67a-ud3r/acpi/mainboard.asl A src/mainboard/gigabyte/ga-p67a-ud3r/acpi/platform.asl A src/mainboard/gigabyte/ga-p67a-ud3r/acpi/superio.asl A src/mainboard/gigabyte/ga-p67a-ud3r/acpi_tables.c A src/mainboard/gigabyte/ga-p67a-ud3r/board_info.txt A src/mainboard/gigabyte/ga-p67a-ud3r/cmos.default A src/mainboard/gigabyte/ga-p67a-ud3r/cmos.layout A src/mainboard/gigabyte/ga-p67a-ud3r/devicetree.cb A src/mainboard/gigabyte/ga-p67a-ud3r/dsdt.asl A src/mainboard/gigabyte/ga-p67a-ud3r/early_init.c A src/mainboard/gigabyte/ga-p67a-ud3r/gpio.c A src/mainboard/gigabyte/ga-p67a-ud3r/hda_verb.c 16 files changed, 751 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/31363/3
James has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31363 )
Change subject: mb/gigabyte: add GA-P67A-UD3R ......................................................................
Patch Set 3:
(1 comment)
Still WIP. Question: do GENx_DEC values with a mask of 0 do anything?
https://review.coreboot.org/c/coreboot/+/31363/2/src/mainboard/gigabyte/ga-p... File src/mainboard/gigabyte/ga-p67a-ud3r/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/31363/2/src/mainboard/gigabyte/ga-p... PS2, Line 80: device pci 00.0 on # PCI bridge : subsystemid 0x1458 0x5000 : end
Can't find a _PRT ACPI method for this in your code. Maybe it's worth to […]
The original firmware has a completely broken _PRT, and in my testing with a RT2561 11g wifi card, the ports work fine without the _PRT method.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31363 )
Change subject: mb/gigabyte: add GA-P67A-UD3R ......................................................................
Patch Set 3: Code-Review+1
(2 comments)
https://review.coreboot.org/c/coreboot/+/31363/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/31363/3//COMMIT_MSG@10 PS3, Line 10: The P67 chipset has no graphics support. Please add a blank line below.
https://review.coreboot.org/c/coreboot/+/31363/3//COMMIT_MSG@14 PS3, Line 14: This is an original P67 chipset, and is affected by a SATA 2 hardware bug. Any reference/URL to the bug?
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31363 )
Change subject: mb/gigabyte: add GA-P67A-UD3R ......................................................................
Patch Set 3:
(14 comments)
https://review.coreboot.org/c/coreboot/+/31363/3/src/mainboard/gigabyte/ga-p... File src/mainboard/gigabyte/ga-p67a-ud3r/acpi/mainboard.asl:
PS3: Is this file needed?
https://review.coreboot.org/c/coreboot/+/31363/3/src/mainboard/gigabyte/ga-p... File src/mainboard/gigabyte/ga-p67a-ud3r/acpi_tables.c:
https://review.coreboot.org/c/coreboot/+/31363/3/src/mainboard/gigabyte/ga-p... PS3, Line 21: : /* Disable USB ports in S3 by default */ : gnvs->s3u0 = 0; : gnvs->s3u1 = 0; : : /* Disable USB ports in S5 by default */ : gnvs->s5u0 = 0; : gnvs->s5u1 = 0; Please remove, their value is already zero.
https://review.coreboot.org/c/coreboot/+/31363/2/src/mainboard/gigabyte/ga-p... File src/mainboard/gigabyte/ga-p67a-ud3r/cmos.layout:
https://review.coreboot.org/c/coreboot/+/31363/2/src/mainboard/gigabyte/ga-p... PS2, Line 62: # coreboot config options: northbridge : #432 3 r 0 unused
This can be removed
Ack
https://review.coreboot.org/c/coreboot/+/31363/2/src/mainboard/gigabyte/ga-p... PS2, Line 65: # SandyBridge MRC Scrambler Seed values : 896 32 r 0 mrc_scrambler_seed : 928 32 r 0 mrc_scrambler_seed_s3 : 960 16 r 0 mrc_scrambler_seed_chk
These shouldn't be needed for native raminit.
Ack
https://review.coreboot.org/c/coreboot/+/31363/3/src/mainboard/gigabyte/ga-p... File src/mainboard/gigabyte/ga-p67a-ud3r/cmos.layout:
https://review.coreboot.org/c/coreboot/+/31363/3/src/mainboard/gigabyte/ga-p... PS3, Line 81: 2 0 Enable : 2 1 Disable This isn't used
https://review.coreboot.org/c/coreboot/+/31363/3/src/mainboard/gigabyte/ga-p... File src/mainboard/gigabyte/ga-p67a-ud3r/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/31363/3/src/mainboard/gigabyte/ga-p... PS3, Line 17: 0x0 just 0
https://review.coreboot.org/c/coreboot/+/31363/3/src/mainboard/gigabyte/ga-p... PS3, Line 19: 0x0 just 0
https://review.coreboot.org/c/coreboot/+/31363/3/src/mainboard/gigabyte/ga-p... PS3, Line 34: 0x0 just 0
https://review.coreboot.org/c/coreboot/+/31363/3/src/mainboard/gigabyte/ga-p... PS3, Line 50: register "pcie_port_coalesce" = "0" This is zero by default already, so it can be removed.
https://review.coreboot.org/c/coreboot/+/31363/3/src/mainboard/gigabyte/ga-p... PS3, Line 56: off Shouldn't this be on?
https://review.coreboot.org/c/coreboot/+/31363/3/src/mainboard/gigabyte/ga-p... PS3, Line 84: (PCIEX1_1) huh? How are the PCIe ports distributed?
https://review.coreboot.org/c/coreboot/+/31363/3/src/mainboard/gigabyte/ga-p... PS3, Line 99: rounted routed
https://review.coreboot.org/c/coreboot/+/31363/1/src/mainboard/gigabyte/ga-p... File src/mainboard/gigabyte/ga-p67a-ud3r/romstage.c:
https://review.coreboot.org/c/coreboot/+/31363/1/src/mainboard/gigabyte/ga-p... PS1, Line 65: /* Disable SIO WDT which kicks in DualBIOS */
I'll add you to the copyright.
Ack
https://review.coreboot.org/c/coreboot/+/31363/2/src/mainboard/gigabyte/ga-p... File src/mainboard/gigabyte/ga-p67a-ud3r/romstage.c:
https://review.coreboot.org/c/coreboot/+/31363/2/src/mainboard/gigabyte/ga-p... PS2, Line 33: CNF2_LPC_EN
This is for decoding I/O locations 4Eh and 4Fh to the LPC interface. […]
Ack
James has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31363 )
Change subject: mb/gigabyte: add GA-P67A-UD3R ......................................................................
Patch Set 3:
(13 comments)
https://review.coreboot.org/c/coreboot/+/31363/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/31363/3//COMMIT_MSG@10 PS3, Line 10: The P67 chipset has no graphics support.
Please add a blank line below.
Done
https://review.coreboot.org/c/coreboot/+/31363/3//COMMIT_MSG@14 PS3, Line 14: This is an original P67 chipset, and is affected by a SATA 2 hardware bug.
Any reference/URL to the bug?
http://web.archive.org/web/20110623010109/http://www.intel.com/support/chips... https://www.anandtech.com/show/4142/intel-discovers-bug-in-6series-chipset-b...
Are you asking for reading material, or to include a reference on the commit message?
https://review.coreboot.org/c/coreboot/+/31363/3/src/mainboard/gigabyte/ga-p... File src/mainboard/gigabyte/ga-p67a-ud3r/acpi/mainboard.asl:
PS3:
Is this file needed?
I guess not? Linux picks up a PWRF power button, the ACPI spec says PNP0C0C is "only needed if the power button is not supported using the fixed register space" so I'm guessing that's what PWRF is?
https://review.coreboot.org/c/coreboot/+/31363/3/src/mainboard/gigabyte/ga-p... File src/mainboard/gigabyte/ga-p67a-ud3r/acpi_tables.c:
https://review.coreboot.org/c/coreboot/+/31363/3/src/mainboard/gigabyte/ga-p... PS3, Line 21: : /* Disable USB ports in S3 by default */ : gnvs->s3u0 = 0; : gnvs->s3u1 = 0; : : /* Disable USB ports in S5 by default */ : gnvs->s5u0 = 0; : gnvs->s5u1 = 0;
Please remove, their value is already zero.
Done
https://review.coreboot.org/c/coreboot/+/31363/3/src/mainboard/gigabyte/ga-p... File src/mainboard/gigabyte/ga-p67a-ud3r/cmos.layout:
https://review.coreboot.org/c/coreboot/+/31363/3/src/mainboard/gigabyte/ga-p... PS3, Line 81: 2 0 Enable : 2 1 Disable
This isn't used
Is there a standardised enum layout? Otherwise I should just renumber the following enums?
https://review.coreboot.org/c/coreboot/+/31363/3/src/mainboard/gigabyte/ga-p... File src/mainboard/gigabyte/ga-p67a-ud3r/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/31363/3/src/mainboard/gigabyte/ga-p... PS3, Line 17: 0x0
just 0
Done
https://review.coreboot.org/c/coreboot/+/31363/3/src/mainboard/gigabyte/ga-p... PS3, Line 19: 0x0
just 0
Done
https://review.coreboot.org/c/coreboot/+/31363/3/src/mainboard/gigabyte/ga-p... PS3, Line 34: 0x0
just 0
Done
https://review.coreboot.org/c/coreboot/+/31363/3/src/mainboard/gigabyte/ga-p... PS3, Line 50: register "pcie_port_coalesce" = "0"
This is zero by default already, so it can be removed.
Done
https://review.coreboot.org/c/coreboot/+/31363/3/src/mainboard/gigabyte/ga-p... PS3, Line 56: off
Shouldn't this be on?
Possibly? It looks like coreboot hides the ME device anyway, what difference does it make?
Having it enabled here results in error messages from mei_me if using me_cleaner, though I suppose coreboot should hide the device if it detects me_cleaner being used.
https://review.coreboot.org/c/coreboot/+/31363/3/src/mainboard/gigabyte/ga-p... PS3, Line 84: (PCIEX1_1)
huh? How are the PCIe ports distributed?
There are 4 lanes, allocated to either the x4 slot, or 4 x1 slots (one of which is the x4 slot). This is configured in PCHSTRAP9. Vendor BIOS is able to configure this and hide/show the relevant root ports, I don't know if that's doable in coreboot as it stands, or if that's even considered in scope.
I'll write this up in the documentation for this port I've yet to write.
https://review.coreboot.org/c/coreboot/+/31363/3/src/mainboard/gigabyte/ga-p... PS3, Line 99: rounted
routed
Done
https://review.coreboot.org/c/coreboot/+/31363/2/src/mainboard/gigabyte/ga-p... File src/mainboard/gigabyte/ga-p67a-ud3r/romstage.c:
https://review.coreboot.org/c/coreboot/+/31363/2/src/mainboard/gigabyte/ga-p... PS2, Line 33: CNF2_LPC_EN
Ack
This code is gone.
Hello Patrick Rudolph, Angel Pons, Arthur Heymans, Paul Menzel, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31363
to look at the new patch set (#4).
Change subject: mb/gigabyte: add GA-P67A-UD3R ......................................................................
mb/gigabyte: add GA-P67A-UD3R
This is a Intel P67 chipset motherboard for Sandy Bridge processors. The P67 chipset has no graphics support.
This board has redundant 4MB SOIC-8 flash chips, and the flashrom internal programmer is usable with the vendor BIOS.
This is an original P67 chipset, and is affected by a SATA 2 hardware bug. There is a variant P67A-UD3R-B3 that is unaffected.
The function of PCI Express ports PCIEX4 and PCIEX1_* are configured in PCHSTRP9. By default, PCIEX4 is configured for 4 lanes and PCIEX1_* are disabled. This can be switched to 1 lane for all ports.
This port was created with the help of autoport and other GIGABYTE ports.
Tested and working: - Intel Core i7 2600 - 4 DIMMs (4x4GB DDR3) with native RAM init - Booting Linux 4.19 from SeaBIOS (SATA and USB) - PCI Express graphics - Onboard Ethernet - Sensors (SuperIO) - S3 sleep - S4 hibernate - SATA 3 - USB 2.0 - USB 3.0 - Onboard audio (speakers, headphones) - CMOS - EHCI debug port - Serial port - Conventional PCI (only with one card) - PS/2 keyboard
Not tested: - SATA 2 (hardware bug) - PS/2 mouse - Digital audio
Change-Id: I4fbf50376be3184bf01a3bc8aae09bce54676707 Signed-off-by: James Ye jye836@gmail.com --- A src/mainboard/gigabyte/ga-p67a-ud3r/Kconfig A src/mainboard/gigabyte/ga-p67a-ud3r/Kconfig.name A src/mainboard/gigabyte/ga-p67a-ud3r/Makefile.inc A src/mainboard/gigabyte/ga-p67a-ud3r/acpi/ec.asl A src/mainboard/gigabyte/ga-p67a-ud3r/acpi/platform.asl A src/mainboard/gigabyte/ga-p67a-ud3r/acpi/superio.asl A src/mainboard/gigabyte/ga-p67a-ud3r/acpi_tables.c A src/mainboard/gigabyte/ga-p67a-ud3r/board_info.txt A src/mainboard/gigabyte/ga-p67a-ud3r/cmos.default A src/mainboard/gigabyte/ga-p67a-ud3r/cmos.layout A src/mainboard/gigabyte/ga-p67a-ud3r/devicetree.cb A src/mainboard/gigabyte/ga-p67a-ud3r/dsdt.asl A src/mainboard/gigabyte/ga-p67a-ud3r/early_init.c A src/mainboard/gigabyte/ga-p67a-ud3r/gpio.c A src/mainboard/gigabyte/ga-p67a-ud3r/hda_verb.c 15 files changed, 710 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/31363/4
James has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31363 )
Change subject: mb/gigabyte: add GA-P67A-UD3R ......................................................................
Patch Set 4:
Addressed most comments from previous patch set, still needs documentation page though.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31363 )
Change subject: mb/gigabyte: add GA-P67A-UD3R ......................................................................
Patch Set 4:
James, no idea why the last build failed, but can you get this verified by Jenkins, so it can be submitted? (And documentation can be added in a follow-up commit.)
Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, Paul Menzel, Angel Pons, Arthur Heymans, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31363
to look at the new patch set (#5).
Change subject: mb/gigabyte: add GA-P67A-UD3R ......................................................................
mb/gigabyte: add GA-P67A-UD3R
This is a Intel P67 chipset motherboard for Sandy Bridge processors. The P67 chipset has no graphics support.
This board has redundant 4MB SOIC-8 flash chips, and the flashrom internal programmer is usable with the vendor BIOS.
This is an original P67 chipset, and is affected by a SATA 2 hardware bug. There is a variant P67A-UD3R-B3, that is the same board with a B3 stepping chipset that fixes this bug.
The function of PCI Express ports PCIEX4 and PCIEX1_* are configured in PCHSTRP9. By default, PCIEX4 is configured for 4 lanes and PCIEX1_* are disabled. This can be switched to 1 lane for all ports.
This port was created with the help of autoport and other GIGABYTE ports.
Tested and working: - Intel Core i5-2500/i7-2600 - 4 DIMMs (4x4GB DDR3-1333) with native RAM init - Booting Linux 4.19 from SeaBIOS (SATA and USB) - PCI Express graphics - Onboard Ethernet - Sensors (SuperIO) - S3 sleep - SATA 3 - USB 2.0 - USB 3.0 (NEC xHCI) - Onboard audio (speakers, headphones) - CMOS - EHCI debug port - Serial port - Conventional PCI (only with one card) - PS/2 keyboard
Not tested: - SATA 2 (hardware bug) - PS/2 mouse - Digital audio
Change-Id: I4fbf50376be3184bf01a3bc8aae09bce54676707 Signed-off-by: James Ye jye836@gmail.com --- A src/mainboard/gigabyte/ga-p67a-ud3r/Kconfig A src/mainboard/gigabyte/ga-p67a-ud3r/Kconfig.name A src/mainboard/gigabyte/ga-p67a-ud3r/Makefile.inc A src/mainboard/gigabyte/ga-p67a-ud3r/acpi/ec.asl A src/mainboard/gigabyte/ga-p67a-ud3r/acpi/platform.asl A src/mainboard/gigabyte/ga-p67a-ud3r/acpi/superio.asl A src/mainboard/gigabyte/ga-p67a-ud3r/acpi_tables.c A src/mainboard/gigabyte/ga-p67a-ud3r/board_info.txt A src/mainboard/gigabyte/ga-p67a-ud3r/cmos.default A src/mainboard/gigabyte/ga-p67a-ud3r/cmos.layout A src/mainboard/gigabyte/ga-p67a-ud3r/devicetree.cb A src/mainboard/gigabyte/ga-p67a-ud3r/dsdt.asl A src/mainboard/gigabyte/ga-p67a-ud3r/early_init.c A src/mainboard/gigabyte/ga-p67a-ud3r/gpio.c A src/mainboard/gigabyte/ga-p67a-ud3r/hda_verb.c 15 files changed, 576 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/31363/5
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31363 )
Change subject: mb/gigabyte: add GA-P67A-UD3R ......................................................................
Patch Set 5: Code-Review+1
Nice.
Martin L Roth has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/31363?usp=email )
Change subject: mb/gigabyte: add GA-P67A-UD3R ......................................................................
Abandoned
This patch has not been touched in over 12 months. Anyone who wants to take over work on this patch, please feel free to restore it and do any work needed to get it merged. If you create a new patch based on this work, please credit the original author.
-
Angel Pons (Code Review) -
James (Code Review)
-
Martin L Roth (Code Review)
-
Nico Huber (Code Review)
-
Paul Menzel (Code Review)