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13 comments:

• Commit Message:

  • Patch Set #3, Line 10: The P67 chipset has no graphics support.

    Please add a blank line below.

    Done

  • Patch Set #3, Line 14: This is an original P67 chipset, and is affected by a SATA 2 hardware bug.

    Any reference/URL to the bug?

    http://web.archive.org/web/20110623010109/http://www.intel.com/support/chipsets/6/sb/CS-032521.htm
    https://www.anandtech.com/show/4142/intel-discovers-bug-in-6series-chipset-begins-recall

    Are you asking for reading material, or to include a reference on the commit message?

• File src/mainboard/gigabyte/ga-p67a-ud3r/acpi/mainboard.asl:

  • Patch Set #3:

    Is this file needed?

    I guess not? Linux picks up a PWRF power button, the ACPI spec says PNP0C0C is "only needed if the power button is not supported using the fixed register space" so I'm guessing that's what PWRF is?

• File src/mainboard/gigabyte/ga-p67a-ud3r/acpi_tables.c:

  • Patch Set #3, Line 21:

    
    	/* Disable USB ports in S3 by default */
    	gnvs->s3u0 = 0;
    	gnvs->s3u1 = 0;
    
    	/* Disable USB ports in S5 by default */
    	gnvs->s5u0 = 0;
    	gnvs->s5u1 = 0;
    

    Please remove, their value is already zero.

    Done

• File src/mainboard/gigabyte/ga-p67a-ud3r/cmos.layout:

  • Patch Set #3, Line 81:

    2     0     Enable
    2     1     Disable
    

    This isn't used

    Is there a standardised enum layout? Otherwise I should just renumber the following enums?

• File src/mainboard/gigabyte/ga-p67a-ud3r/devicetree.cb:

  • Patch Set #3, Line 17: 0x0

    just 0

    Done

  • Patch Set #3, Line 19: 0x0

    just 0

    Done

  • Patch Set #3, Line 34: 0x0

    just 0

    Done

  • Patch Set #3, Line 50: register "pcie_port_coalesce" = "0"

    This is zero by default already, so it can be removed.

    Done

  • Patch Set #3, Line 56: off

    Shouldn't this be on?

    Possibly? It looks like coreboot hides the ME device anyway, what difference does it make?

    Having it enabled here results in error messages from mei_me if using me_cleaner, though I suppose coreboot should hide the device if it detects me_cleaner being used.

  • Patch Set #3, Line 84: (PCIEX1_1)

    huh? How are the PCIe ports distributed?

    There are 4 lanes, allocated to either the x4 slot, or 4 x1 slots (one of which is the x4 slot). This is configured in PCHSTRAP9. Vendor BIOS is able to configure this and hide/show the relevant root ports, I don't know if that's doable in coreboot as it stands, or if that's even considered in scope.

    I'll write this up in the documentation for this port I've yet to write.

  • Patch Set #3, Line 99: rounted

    routed

    Done

• File src/mainboard/gigabyte/ga-p67a-ud3r/romstage.c:

  • Patch Set #2, Line 33: CNF2_LPC_EN

    Ack

    This code is gone.

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