14 comments:
File src/mainboard/gigabyte/ga-p67a-ud3r/acpi/mainboard.asl:
Is this file needed?
File src/mainboard/gigabyte/ga-p67a-ud3r/acpi_tables.c:
/* Disable USB ports in S3 by default */
gnvs->s3u0 = 0;
gnvs->s3u1 = 0;
/* Disable USB ports in S5 by default */
gnvs->s5u0 = 0;
gnvs->s5u1 = 0;
Please remove, their value is already zero.
File src/mainboard/gigabyte/ga-p67a-ud3r/cmos.layout:
# coreboot config options: northbridge
#432 3 r 0 unused
This can be removed
Ack
# SandyBridge MRC Scrambler Seed values
896 32 r 0 mrc_scrambler_seed
928 32 r 0 mrc_scrambler_seed_s3
960 16 r 0 mrc_scrambler_seed_chk
These shouldn't be needed for native raminit.
Ack
File src/mainboard/gigabyte/ga-p67a-ud3r/cmos.layout:
2 0 Enable
2 1 Disable
This isn't used
File src/mainboard/gigabyte/ga-p67a-ud3r/devicetree.cb:
just 0
just 0
just 0
Patch Set #3, Line 50: register "pcie_port_coalesce" = "0"
This is zero by default already, so it can be removed.
Shouldn't this be on?
Patch Set #3, Line 84: (PCIEX1_1)
huh? How are the PCIe ports distributed?
Patch Set #3, Line 99: rounted
routed
File src/mainboard/gigabyte/ga-p67a-ud3r/romstage.c:
Patch Set #1, Line 65: /* Disable SIO WDT which kicks in DualBIOS */
I'll add you to the copyright.
Ack
File src/mainboard/gigabyte/ga-p67a-ud3r/romstage.c:
Patch Set #2, Line 33: CNF2_LPC_EN
This is for decoding I/O locations 4Eh and 4Fh to the LPC interface. […]
Ack
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