- coreboot-gerrit - mail.coreboot.org

Change in coreboot[master]: Documentation/vendorcode/eltan/security.md: Fix bugs in the guide

by Michał Żygowski (Code Review)

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43483 ) Change subject: Documentation/vendorcode/eltan/security.md: Fix bugs in the guide ...................................................................... Documentation/vendorcode/eltan/security.md: Fix bugs in the guide ELTAN verified boot seems to be using vboot 2.1 key format not vboot 1.0. Generating vboot 1.0 keys results in public key of incorrect size (according to the verified boot implementation in vendorcode) which results in errors during booting. Fix the cbfstool extraction command to take account for stage file which may have certain sections removed. Add note about endianess of digest generated by openssl. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I27cf8e3f8e22876f671092fe4d3265a98564d996 --- M Documentation/vendorcode/eltan/security.md 1 file changed, 8 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/43483/1 diff --git a/Documentation/vendorcode/eltan/security.md b/Documentation/vendorcode/eltan/security.md index 9dd47c0..1c05cd5 100644 --- a/Documentation/vendorcode/eltan/security.md +++ b/Documentation/vendorcode/eltan/security.md @@ -42,7 +42,7 @@ Create private key in RSA2048 format: `openssl genrsa -F4 -out <private_key_file> 2048` Create public key using private key: -`futility --vb1 create <private_key_file> <public_key_file_without_extension>` +`futility --vb21 create <private_key_file> <public_key_file_without_extension>` The public key will be included into coreboot and used for verified boot only. @@ -79,9 +79,15 @@ The total number of items must match `VENDORCODE_ELTAN_OEM_MANIFEST_ITEMS`. For every part the SHA (SHA-256) must be calculated. First extract the binary from the coreboot -image using: `cbfstool <coreboot_file_name> extract -n <cbfs_name> -f <item_binary_file_name>` +image using: `cbfstool <coreboot_file_name> extract -n <cbfs_name> -f <item_binary_file_name> -m x86 -U` +Note the `-m x86 -U` flags are required for correct extraction of stages. Certain stages are +put in CBFS without certain program sections so extraction process must also remove these sections. + followed by: `openssl dgst -sha256 -binary -out <hash_file_name> <item_binary_file_name>` +The SHA256 digest will be in big endian so it must be converted to little endian with: +`< <hash_file_name> xxd -p -c1 | tac | xxd -p -r > <hash_file_name_le>` + Replace -sha256 with -sha512 when `VENDORCODE_ELTAN_VBOOT_USE_SHA512` is enabled. All the hashes must be combined to a hash binary. The hashes need to be placed in the same order as -- To view, visit https://review.coreboot.org/c/coreboot/+/43483 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27cf8e3f8e22876f671092fe4d3265a98564d996 Gerrit-Change-Number: 43483 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

14 minutes

1
0
0 0

Change in coreboot[master]: util/board-status: Reject logs with unknown timestamps

by Paul Menzel (Code Review)

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41857 ) Change subject: util/board-status: Reject logs with unknown timestamps ...................................................................... util/board-status: Reject logs with unknown timestamps Check the output of `cbmem -t` for unknown timestamps. If present, ask the user to rebuild `cbmem`. Change-Id: Ief7aa1a698f10d9721964ad1bee057fcd9f4aa40 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M util/board_status/board_status.sh 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/41857/1 diff --git a/util/board_status/board_status.sh b/util/board_status/board_status.sh index 2e93fe2..e772238 100755 --- a/util/board_status/board_status.sh +++ b/util/board_status/board_status.sh @@ -431,6 +431,11 @@ echo "Getting timestamp data" cmd_nonfatal $LOCAL "$cbmem_cmd -t" "${tmpdir}/${results}/coreboot_timestamps.txt" + if [ $(grep -- unknown "${tmpdir}/${results}/coreboot_timestamps.txt") ]; then + echo "Unknown timestamps found in 'coreboot_timestamps.txt'." \ + "Please rebuild the utility 'cbmem'." + exit $EXIT_FAILURE + fi if [ "$cmos_enabled" -eq 1 ]; then echo "Verifying that nvramtool is available" -- To view, visit https://review.coreboot.org/c/coreboot/+/41857 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief7aa1a698f10d9721964ad1bee057fcd9f4aa40 Gerrit-Change-Number: 41857 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

15 minutes

3
10
0 0

Change in coreboot[master]: mb/google/puff: update USB3 gen2 parameters

by Tim Chen (Code Review)

Hello Tim Chen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/43482 to review the following change. Change subject: mb/google/puff: update USB3 gen2 parameters ...................................................................... mb/google/puff: update USB3 gen2 parameters Based on USB3 gen2 SI report to fine tune the parameters for USB3 gen2. BRANCH=none BUG=b:150515720 TEST=build and check the USB3 gen2 register on DUT is correct. Change-Id: I6ec109871d682a1ae2fa4c22fdd6b87ad8a39e9e Signed-off-by: Tim Chen <tim-chen(a)quanta.corp-partner.google.com> --- M src/mainboard/google/hatch/variants/duffy/overridetree.cb M src/mainboard/google/hatch/variants/faffy/overridetree.cb M src/mainboard/google/hatch/variants/kaisa/overridetree.cb 3 files changed, 207 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/43482/1 diff --git a/src/mainboard/google/hatch/variants/duffy/overridetree.cb b/src/mainboard/google/hatch/variants/duffy/overridetree.cb index 244e678..2f2b643 100644 --- a/src/mainboard/google/hatch/variants/duffy/overridetree.cb +++ b/src/mainboard/google/hatch/variants/duffy/overridetree.cb @@ -74,12 +74,76 @@ .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, }" # BT - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port 2 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port 3 - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port 1 + register "usb3_ports[0]" = "{ + .enable = 1, + .ocpin = OC2, + .tx_de_emp = 0x00, + .tx_downscale_amp = 0x00, + .gen2_tx_rate0_uniq_tran_enable = 0, + .gen2_tx_rate0_uniq_tran = 0x00, + .gen2_tx_rate1_uniq_tran_enable = 0, + .gen2_tx_rate1_uniq_tran = 0x00, + .gen2_tx_rate2_uniq_tran_enable = 1, + .gen2_tx_rate2_uniq_tran = 0x4c, + .gen2_tx_rate3_uniq_tran_enable = 0, + .gen2_tx_rate3_uniq_tran = 0x00, + .gen2_rx_tuning_enable = 0x0f, + .gen2_rx_tuning_params = 0x45, + .gen2_rx_filter_sel = 0x44, + }" # Type-A Port 2 + register "usb3_ports[1]" = "USB3_PORT_GEN2_DEFAULT(OC3)" # Type-A Port 3 + register "usb3_ports[2]" = "{ + .enable = 1, + .ocpin = OC1, + .tx_de_emp = 0x00, + .tx_downscale_amp = 0x00, + .gen2_tx_rate0_uniq_tran_enable = 0, + .gen2_tx_rate0_uniq_tran = 0x00, + .gen2_tx_rate1_uniq_tran_enable = 0, + .gen2_tx_rate1_uniq_tran = 0x00, + .gen2_tx_rate2_uniq_tran_enable = 1, + .gen2_tx_rate2_uniq_tran = 0x4c, + .gen2_tx_rate3_uniq_tran_enable = 0, + .gen2_tx_rate3_uniq_tran = 0x00, + .gen2_rx_tuning_enable = 0x0f, + .gen2_rx_tuning_params = 0x3d, + .gen2_rx_filter_sel = 0x44, + }" # Type-A Port 1 register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port 0 - register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port 4 + register "usb3_ports[4]" = "{ + .enable = 1, + .ocpin = OC0, + .tx_de_emp = 0x00, + .tx_downscale_amp = 0x00, + .gen2_tx_rate0_uniq_tran_enable = 0, + .gen2_tx_rate0_uniq_tran = 0x00, + .gen2_tx_rate1_uniq_tran_enable = 0, + .gen2_tx_rate1_uniq_tran = 0x00, + .gen2_tx_rate2_uniq_tran_enable = 1, + .gen2_tx_rate2_uniq_tran = 0x4c, + .gen2_tx_rate3_uniq_tran_enable = 0, + .gen2_tx_rate3_uniq_tran = 0x00, + .gen2_rx_tuning_enable = 0x0f, + .gen2_rx_tuning_params = 0x45, + .gen2_rx_filter_sel = 0x44, + }" # Type-A Port 0 + register "usb3_ports[5]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_de_emp = 0x00, + .tx_downscale_amp = 0x00, + .gen2_tx_rate0_uniq_tran_enable = 0, + .gen2_tx_rate0_uniq_tran = 0x00, + .gen2_tx_rate1_uniq_tran_enable = 0, + .gen2_tx_rate1_uniq_tran = 0x00, + .gen2_tx_rate2_uniq_tran_enable = 1, + .gen2_tx_rate2_uniq_tran = 0x4c, + .gen2_tx_rate3_uniq_tran_enable = 0, + .gen2_tx_rate3_uniq_tran = 0x00, + .gen2_rx_tuning_enable = 0x0f, + .gen2_rx_tuning_params = 0x45, + .gen2_rx_filter_sel = 0x44, + }" # Type-A Port 4 # Bitmap for Wake Enable on USB attach/detach register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ diff --git a/src/mainboard/google/hatch/variants/faffy/overridetree.cb b/src/mainboard/google/hatch/variants/faffy/overridetree.cb index fb4030b..8aff8d1 100644 --- a/src/mainboard/google/hatch/variants/faffy/overridetree.cb +++ b/src/mainboard/google/hatch/variants/faffy/overridetree.cb @@ -81,12 +81,76 @@ .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, }" # BT - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port 2 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port 3 - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port 1 + register "usb3_ports[0]" = "{ + .enable = 1, + .ocpin = OC2, + .tx_de_emp = 0x00, + .tx_downscale_amp = 0x00, + .gen2_tx_rate0_uniq_tran_enable = 0, + .gen2_tx_rate0_uniq_tran = 0x00, + .gen2_tx_rate1_uniq_tran_enable = 0, + .gen2_tx_rate1_uniq_tran = 0x00, + .gen2_tx_rate2_uniq_tran_enable = 1, + .gen2_tx_rate2_uniq_tran = 0x4c, + .gen2_tx_rate3_uniq_tran_enable = 0, + .gen2_tx_rate3_uniq_tran = 0x00, + .gen2_rx_tuning_enable = 0x0f, + .gen2_rx_tuning_params = 0x45, + .gen2_rx_filter_sel = 0x44, + }" # Type-A Port 2 + register "usb3_ports[1]" = "USB3_PORT_GEN2_DEFAULT(OC3)" # Type-A Port 3 + register "usb3_ports[2]" = "{ + .enable = 1, + .ocpin = OC1, + .tx_de_emp = 0x00, + .tx_downscale_amp = 0x00, + .gen2_tx_rate0_uniq_tran_enable = 0, + .gen2_tx_rate0_uniq_tran = 0x00, + .gen2_tx_rate1_uniq_tran_enable = 0, + .gen2_tx_rate1_uniq_tran = 0x00, + .gen2_tx_rate2_uniq_tran_enable = 1, + .gen2_tx_rate2_uniq_tran = 0x4c, + .gen2_tx_rate3_uniq_tran_enable = 0, + .gen2_tx_rate3_uniq_tran = 0x00, + .gen2_rx_tuning_enable = 0x0f, + .gen2_rx_tuning_params = 0x3d, + .gen2_rx_filter_sel = 0x44, + }" # Type-A Port 1 register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port 0 - register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port 4 + register "usb3_ports[4]" = "{ + .enable = 1, + .ocpin = OC0, + .tx_de_emp = 0x00, + .tx_downscale_amp = 0x00, + .gen2_tx_rate0_uniq_tran_enable = 0, + .gen2_tx_rate0_uniq_tran = 0x00, + .gen2_tx_rate1_uniq_tran_enable = 0, + .gen2_tx_rate1_uniq_tran = 0x00, + .gen2_tx_rate2_uniq_tran_enable = 1, + .gen2_tx_rate2_uniq_tran = 0x4c, + .gen2_tx_rate3_uniq_tran_enable = 0, + .gen2_tx_rate3_uniq_tran = 0x00, + .gen2_rx_tuning_enable = 0x0f, + .gen2_rx_tuning_params = 0x45, + .gen2_rx_filter_sel = 0x44, + }" # Type-A Port 0 + register "usb3_ports[5]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_de_emp = 0x00, + .tx_downscale_amp = 0x00, + .gen2_tx_rate0_uniq_tran_enable = 0, + .gen2_tx_rate0_uniq_tran = 0x00, + .gen2_tx_rate1_uniq_tran_enable = 0, + .gen2_tx_rate1_uniq_tran = 0x00, + .gen2_tx_rate2_uniq_tran_enable = 1, + .gen2_tx_rate2_uniq_tran = 0x4c, + .gen2_tx_rate3_uniq_tran_enable = 0, + .gen2_tx_rate3_uniq_tran = 0x00, + .gen2_rx_tuning_enable = 0x0f, + .gen2_rx_tuning_params = 0x45, + .gen2_rx_filter_sel = 0x44, + }" # Type-A Port 4 # Bitmap for Wake Enable on USB attach/detach register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ diff --git a/src/mainboard/google/hatch/variants/kaisa/overridetree.cb b/src/mainboard/google/hatch/variants/kaisa/overridetree.cb index eb177f2..01691ff 100644 --- a/src/mainboard/google/hatch/variants/kaisa/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kaisa/overridetree.cb @@ -74,12 +74,76 @@ .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, }" # BT - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port 2 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port 3 - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port 1 + register "usb3_ports[0]" = "{ + .enable = 1, + .ocpin = OC2, + .tx_de_emp = 0x00, + .tx_downscale_amp = 0x00, + .gen2_tx_rate0_uniq_tran_enable = 0, + .gen2_tx_rate0_uniq_tran = 0x00, + .gen2_tx_rate1_uniq_tran_enable = 0, + .gen2_tx_rate1_uniq_tran = 0x00, + .gen2_tx_rate2_uniq_tran_enable = 1, + .gen2_tx_rate2_uniq_tran = 0x4c, + .gen2_tx_rate3_uniq_tran_enable = 0, + .gen2_tx_rate3_uniq_tran = 0x00, + .gen2_rx_tuning_enable = 0x0f, + .gen2_rx_tuning_params = 0x45, + .gen2_rx_filter_sel = 0x44, + }" # Type-A Port 2 + register "usb3_ports[1]" = "USB3_PORT_GEN2_DEFAULT(OC3)" # Type-A Port 3 + register "usb3_ports[2]" = "{ + .enable = 1, + .ocpin = OC1, + .tx_de_emp = 0x00, + .tx_downscale_amp = 0x00, + .gen2_tx_rate0_uniq_tran_enable = 0, + .gen2_tx_rate0_uniq_tran = 0x00, + .gen2_tx_rate1_uniq_tran_enable = 0, + .gen2_tx_rate1_uniq_tran = 0x00, + .gen2_tx_rate2_uniq_tran_enable = 1, + .gen2_tx_rate2_uniq_tran = 0x4c, + .gen2_tx_rate3_uniq_tran_enable = 0, + .gen2_tx_rate3_uniq_tran = 0x00, + .gen2_rx_tuning_enable = 0x0f, + .gen2_rx_tuning_params = 0x3d, + .gen2_rx_filter_sel = 0x44, + }" # Type-A Port 1 register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port 0 - register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port 4 + register "usb3_ports[4]" = "{ + .enable = 1, + .ocpin = OC0, + .tx_de_emp = 0x00, + .tx_downscale_amp = 0x00, + .gen2_tx_rate0_uniq_tran_enable = 0, + .gen2_tx_rate0_uniq_tran = 0x00, + .gen2_tx_rate1_uniq_tran_enable = 0, + .gen2_tx_rate1_uniq_tran = 0x00, + .gen2_tx_rate2_uniq_tran_enable = 1, + .gen2_tx_rate2_uniq_tran = 0x4c, + .gen2_tx_rate3_uniq_tran_enable = 0, + .gen2_tx_rate3_uniq_tran = 0x00, + .gen2_rx_tuning_enable = 0x0f, + .gen2_rx_tuning_params = 0x45, + .gen2_rx_filter_sel = 0x44, + }" # Type-A Port 0 + register "usb3_ports[5]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_de_emp = 0x00, + .tx_downscale_amp = 0x00, + .gen2_tx_rate0_uniq_tran_enable = 0, + .gen2_tx_rate0_uniq_tran = 0x00, + .gen2_tx_rate1_uniq_tran_enable = 0, + .gen2_tx_rate1_uniq_tran = 0x00, + .gen2_tx_rate2_uniq_tran_enable = 1, + .gen2_tx_rate2_uniq_tran = 0x4c, + .gen2_tx_rate3_uniq_tran_enable = 0, + .gen2_tx_rate3_uniq_tran = 0x00, + .gen2_rx_tuning_enable = 0x0f, + .gen2_rx_tuning_params = 0x45, + .gen2_rx_filter_sel = 0x44, + }" # Type-A Port 4 # Bitmap for Wake Enable on USB attach/detach register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ -- To view, visit https://review.coreboot.org/c/coreboot/+/43482 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ec109871d682a1ae2fa4c22fdd6b87ad8a39e9e Gerrit-Change-Number: 43482 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Chen <Tim-Chen(a)quantatw.com> Gerrit-Reviewer: Tim Chen <tim-chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

23 minutes

1
0
0 0

Change in coreboot[master]: drivers/ocp/ipmi: Add ipmi set processor information

by Tim Chu (Code Review)

Tim Chu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42242 ) Change subject: drivers/ocp/ipmi: Add ipmi set processor information ...................................................................... drivers/ocp/ipmi: Add ipmi set processor information Implement setting processor information to BMC. TEST=Use get command in OpenBMC to check. Command and information are shown as below: root@bmc-oob:~# ipmi-util 1 0xd8 0x11 0x4c 0x1c 0x00 0 1 DC 11 00 47 65 6E 75 69 6E 65 20 49 6E 74 65 6C 28 52 29 20 43 50 55 20 30 30 30 30 25 40 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 root@bmc-oob:~# ipmi-util 1 0xd8 0x11 0x4c 0x1c 0x00 0 2 DC 11 00 1A 34 00 DC 05 58 58 root@bmc-oob:~# Signed-off-by: TimChu <Tim.Chu(a)quantatw.com> Change-Id: I3d53ac241a11ca962572816283a0c653fcde9f9e --- M src/drivers/ocp/ipmi/Kconfig M src/drivers/ocp/ipmi/ipmi_ocp.c M src/drivers/ocp/ipmi/ipmi_ocp.h 3 files changed, 138 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/42242/1 diff --git a/src/drivers/ocp/ipmi/Kconfig b/src/drivers/ocp/ipmi/Kconfig index 95c51c0..d4ebafe 100644 --- a/src/drivers/ocp/ipmi/Kconfig +++ b/src/drivers/ocp/ipmi/Kconfig @@ -1,3 +1,8 @@ config IPMI_OCP bool default n + +config MANU_ID + hex + default 0 + depends on IPMI_OCP diff --git a/src/drivers/ocp/ipmi/ipmi_ocp.c b/src/drivers/ocp/ipmi/ipmi_ocp.c index c1766d9..4ad710d 100644 --- a/src/drivers/ocp/ipmi/ipmi_ocp.c +++ b/src/drivers/ocp/ipmi/ipmi_ocp.c @@ -54,6 +54,108 @@ return 0; } +static int ipmi_set_processor_information_param1(struct device *dev) +{ + int ret; + struct ipmi_processor_info_param1_req req1 = {0}; + struct ipmi_rsp rsp; + + for (int index = 0; index < sizeof(req1.data.manufacturer_id); index++) { + req1.data.manufacturer_id[index] = (mfid >> (index * 8)) & 0xff; + } + printk(BIOS_DEBUG, "IPMI BMC manufacturer id: %02x%02x%02x\n", + req1.data.manufacturer_id[2], req1.data.manufacturer_id[1], + req1.data.manufacturer_id[0]); + + req1.data.index = 0; + req1.data.parameter_selector = 1; + + /* Get processor name. */ + fill_processor_name(req1.product_name); + printk(BIOS_DEBUG, "IPMI CPU NAME: %s.\n", req1.product_name); + + ret = ipmi_kcs_message(dev->path.pnp.port, IPMI_NETFN_OEM_COMMON, 0, + IPMI_BMC_SET_PROCESSOR_INFORMATION, (u8 *) &req1, + sizeof(req1), (u8 *) &rsp, sizeof(rsp)); + + if (ret < sizeof(struct ipmi_rsp) || rsp.completion_code) { + printk(BIOS_ERR, "IPMI BMC: %s command failed (ret=%d rsp=0x%x)\n", + __func__, ret, rsp.completion_code); + return CB_ERR; + } + return CB_SUCCESS; +} + +static int ipmi_set_processor_information_param2(struct device *dev) +{ + int ret; + struct ipmi_processor_info_param2_req req2 = {0}; + struct ipmi_rsp rsp; + struct cpuid_result regs; + msr_t msr; + uint8_t stepping_id; + + for (int index = 0; index < sizeof(req2.data.manufacturer_id); index++) { + req2.data.manufacturer_id[index] = (mfid >> (index * 8)) & 0xff; + } + printk(BIOS_DEBUG, "IPMI BMC manufacturer id: %02x%02x%02x\n", + req2.data.manufacturer_id[2], req2.data.manufacturer_id[1], + req2.data.manufacturer_id[0]); + + req2.data.index = 0; + req2.data.parameter_selector = 2; + + /* Get core number and thread number. */ + msr = rdmsr(MSR_CORE_THREAD_COUNT); + req2.thread_number = (msr.lo >> 0) & 0xffff; + req2.core_number = (msr.lo >> 16) & 0xffff; + printk(BIOS_DEBUG, "IPMI CPU has %u cores, %u threads enabled.\n", + req2.core_number, req2.thread_number); + + /* Get processor frequency. */ + msr = rdmsr(MSR_PLATFORM_INFO); + req2.processor_freq = 100 * ((msr.lo >> 8) & 0xff); + printk(BIOS_DEBUG, "IPMI CPU frequency is %u MHz.\n", + req2.processor_freq); + + /* Get revision. */ + regs = cpuid(0x01); + stepping_id = (regs.eax & 0xf); + printk(BIOS_DEBUG, "IPMI CPU stepping id is %x.\n", stepping_id); + switch (stepping_id) { + /* TBD */ + case 0xa: + req2.revision[0] = 'X'; + req2.revision[1] = 'X'; + break; + default: + req2.revision[0] = 'X'; + req2.revision[1] = 'X'; + } + + ret = ipmi_kcs_message(dev->path.pnp.port, IPMI_NETFN_OEM_COMMON, 0, + IPMI_BMC_SET_PROCESSOR_INFORMATION, (u8 *) &req2, + sizeof(req2), (u8 *) &rsp, sizeof(rsp)); + + if (ret < sizeof(struct ipmi_rsp) || rsp.completion_code) { + printk(BIOS_ERR, "IPMI: %s command failed (ret=%d rsp=0x%x)\n", + __func__, ret, rsp.completion_code); + return CB_ERR; + } + return CB_SUCCESS; +} + +static void ipmi_set_processor_information(struct device *dev) +{ + if (ipmi_set_processor_information_param1(dev)) { + printk(BIOS_ERR, "IPMI BMC set param 1 processor info failed\n"); + } + + if (ipmi_set_processor_information_param2(dev)) { + printk(BIOS_ERR, "IPMI BMC set param 2 processor info failed\n"); + } +} + static void ipmi_ocp_init(struct device *dev) { struct ipmi_rsp postrsp; @@ -67,6 +169,9 @@ { struct ipmi_rsp postrsp; + /* Send processor information */ + ipmi_set_processor_information(dev); + /* Send POST end to BMC. */ if (!ipmi_set_post_end(dev, &postrsp)) printk(BIOS_DEBUG, "IPMI BMC POST is ended\n"); diff --git a/src/drivers/ocp/ipmi/ipmi_ocp.h b/src/drivers/ocp/ipmi/ipmi_ocp.h index 1cdea2f..f04b5ba 100644 --- a/src/drivers/ocp/ipmi/ipmi_ocp.h +++ b/src/drivers/ocp/ipmi/ipmi_ocp.h @@ -3,8 +3,36 @@ #ifndef __IPMI_OCP_H #define __IPMI_OCP_H +#include <soc/msr.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/name.h> +#include "drivers/ipmi/ipmi_kcs.h" #define IPMI_NETFN_OEM 0x30 #define IPMI_BMC_SET_POST_START 0x73 #define IPMI_BMC_SET_POST_END 0x74 +#define IPMI_NETFN_OEM_COMMON 0x36 +#define IPMI_BMC_SET_PROCESSOR_INFORMATION 0x10 +#define IPMI_BMC_GET_PROCESSOR_INFORMATION 0x11 + +#define mfid CONFIG_MANU_ID + +struct ipmi_processor_info_req { + uint8_t manufacturer_id[3]; + uint8_t index; + uint8_t parameter_selector; +} __packed; + +struct ipmi_processor_info_param1_req { + struct ipmi_processor_info_req data; + char product_name[48]; +} __packed; + +struct ipmi_processor_info_param2_req { + struct ipmi_processor_info_req data; + uint8_t core_number; + uint16_t thread_number; + uint16_t processor_freq; + char revision[2]; +} __packed; #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/42242 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d53ac241a11ca962572816283a0c653fcde9f9e Gerrit-Change-Number: 42242 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

32 minutes

5
21
0 0

Change in coreboot[master]: soc/intel/tigerlake: Update Tigerlake SA IDs

by Derek Huang (Code Review)

Derek Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43061 ) Change subject: soc/intel/tigerlake: Update Tigerlake SA IDs ...................................................................... soc/intel/tigerlake: Update Tigerlake SA IDs This patch update Tigerlake SA DID and report platform. According to doc #626936: TGL-UP4(Y) (4+2): 9A12h TGL-UP4(Y) (2+2): 9A02h Signed-off-by: derek.huang <derek.huang(a)intel.corp-partner.google.com> Change-Id: Id9d9c9ac3bf39582b0da610e6ef912031939c763 --- M src/include/device/pci_ids.h M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/tigerlake/bootblock/report_platform.c M src/soc/intel/tigerlake/systemagent.c 4 files changed, 4 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/43061/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 4b17567..b8a7308 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3521,9 +3521,9 @@ #define PCI_DEVICE_ID_INTEL_CML_H_4_2 0x9B64 #define PCI_DEVICE_ID_INTEL_CML_H_8_2 0x9B44 #define PCI_DEVICE_ID_INTEL_TGL_ID_U 0x9A14 -#define PCI_DEVICE_ID_INTEL_TGL_ID_U_1 0x9A12 +#define PCI_DEVICE_ID_INTEL_TGL_ID_Y 0x9A12 #define PCI_DEVICE_ID_INTEL_TGL_ID_U_2_2 0x9A04 -#define PCI_DEVICE_ID_INTEL_TGL_ID_Y 0x9A10 +#define PCI_DEVICE_ID_INTEL_TGL_ID_Y_2_2 0x9A02 #define PCI_DEVICE_ID_INTEL_JSL_EHL 0x4532 #define PCI_DEVICE_ID_INTEL_EHL_ID_1 0x4510 #define PCI_DEVICE_ID_INTEL_JSL_ID_1 0x4e22 diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index e6bbfc7..b5d892b 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -391,9 +391,9 @@ PCI_DEVICE_ID_INTEL_CML_H_4_2, PCI_DEVICE_ID_INTEL_CML_H_8_2, PCI_DEVICE_ID_INTEL_TGL_ID_U, - PCI_DEVICE_ID_INTEL_TGL_ID_U_1, PCI_DEVICE_ID_INTEL_TGL_ID_U_2_2, PCI_DEVICE_ID_INTEL_TGL_ID_Y, + PCI_DEVICE_ID_INTEL_TGL_ID_Y_2_2, PCI_DEVICE_ID_INTEL_JSL_EHL, PCI_DEVICE_ID_INTEL_EHL_ID_1, PCI_DEVICE_ID_INTEL_JSL_ID_1, diff --git a/src/soc/intel/tigerlake/bootblock/report_platform.c b/src/soc/intel/tigerlake/bootblock/report_platform.c index a64738d..7693856 100644 --- a/src/soc/intel/tigerlake/bootblock/report_platform.c +++ b/src/soc/intel/tigerlake/bootblock/report_platform.c @@ -33,9 +33,9 @@ const char *name; } mch_table[] = { { PCI_DEVICE_ID_INTEL_TGL_ID_U, "Tigerlake-U-4-2" }, - { PCI_DEVICE_ID_INTEL_TGL_ID_U_1, "Tigerlake-U-4-3e" }, { PCI_DEVICE_ID_INTEL_TGL_ID_U_2_2, "Tigerlake-U-2-2" }, { PCI_DEVICE_ID_INTEL_TGL_ID_Y, "Tigerlake-Y-4-2" }, + { PCI_DEVICE_ID_INTEL_TGL_ID_Y_2_2, "Tigerlake-Y-2-2" }, { PCI_DEVICE_ID_INTEL_JSL_EHL, "Jasperlake Elkhartlake" }, { PCI_DEVICE_ID_INTEL_EHL_ID_1, "Elkhartlake-1" }, }; diff --git a/src/soc/intel/tigerlake/systemagent.c b/src/soc/intel/tigerlake/systemagent.c index e428365..c53cb98 100644 --- a/src/soc/intel/tigerlake/systemagent.c +++ b/src/soc/intel/tigerlake/systemagent.c @@ -79,7 +79,6 @@ */ switch (sa_pci_id) { case PCI_DEVICE_ID_INTEL_TGL_ID_U: - case PCI_DEVICE_ID_INTEL_TGL_ID_U_1: soc_config = &config->power_limits_config[POWER_LIMITS_U_4_CORE]; break; case PCI_DEVICE_ID_INTEL_TGL_ID_U_2_2: -- To view, visit https://review.coreboot.org/c/coreboot/+/43061 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9d9c9ac3bf39582b0da610e6ef912031939c763 Gerrit-Change-Number: 43061 Gerrit-PatchSet: 1 Gerrit-Owner: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-MessageType: newchange

1 hour, 5 minutes

5
6
0 0

Change in coreboot[master]: soc/intel/cannonlake: Add support for UART2 on PCH-H

by Patrick Rudolph (Code Review)

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40405 ) Change subject: soc/intel/cannonlake: Add support for UART2 on PCH-H ...................................................................... soc/intel/cannonlake: Add support for UART2 on PCH-H On PCH-H the UART2 can't be used as PCI device as the parent multi function device isn't available. As workaround add an ACPI driver for PCH-H UART2 that generates ACPI code for the Intel LPSS ACPI driver. Tested on Linux with Sunrise Point ACPI ID for UART2. Change-Id: I838d16322be38f5421c1f63b457a0af552e0ed96 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/cannonlake/Makefile.inc M src/soc/intel/cannonlake/acpi/serialio.asl A src/soc/intel/cannonlake/pch_h.c M src/soc/intel/common/block/include/intelblocks/uart.h M src/soc/intel/common/block/uart/uart.c 5 files changed, 98 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/40405/1 diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index c744e99..e263264 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -54,6 +54,11 @@ ramstage-y += vr_config.c ramstage-y += sd.c ramstage-y += xhci.c +ifeq ($(CONFIG_HAVE_ACPI_TABLES),y) +ifeq ($(CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS),y) +ramstage-$(CONFIG_SOC_INTEL_CANNONLAKE_PCH_H) += pch_h.c +endif +endif smm-y += elog.c smm-y += p2sb.c diff --git a/src/soc/intel/cannonlake/acpi/serialio.asl b/src/soc/intel/cannonlake/acpi/serialio.asl index 2785e3d..5e28b98 100644 --- a/src/soc/intel/cannonlake/acpi/serialio.asl +++ b/src/soc/intel/cannonlake/acpi/serialio.asl @@ -69,8 +69,11 @@ Name (_DDN, "Serial IO UART Controller 1") } + +#if !CONFIG(SOC_INTEL_CANNONLAKE_PCH_H) Device (UAR2) { Name (_ADR, 0x00190002) Name (_DDN, "Serial IO UART Controller 2") } +#endif diff --git a/src/soc/intel/cannonlake/pch_h.c b/src/soc/intel/cannonlake/pch_h.c new file mode 100644 index 0000000..84a75e8 --- /dev/null +++ b/src/soc/intel/cannonlake/pch_h.c @@ -0,0 +1,77 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <soc/irq.h> +#include <intelblocks/uart.h> +#include <console/console.h> + +/* + * On PCH-H the I2C4 0:19.0 device isn't usable and thus 0:19.2 isn't detected + * using standard PCI probing. + * Generate an ACPI entry if the device is enabled in devicetree for the ACPI + * LPSS driver. + */ +static void pch_h_uart2_fill_ssdt(struct device *dev) +{ + struct acpi_irq irq = ACPI_IRQ_LEVEL_LOW(LPSS_UART2_IRQ); + const char *scope = acpi_device_scope(dev); + printk(BIOS_ERR, "ACPIGEN: %s\n", acpi_device_name(dev)); + struct resource *res; + if (!scope) + return; + + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (!res) + return; + + /* Device */ + acpigen_write_scope(scope); + acpigen_write_device(acpi_device_name(dev)); + acpigen_write_name_string("_HID", acpi_device_hid(dev)); + /* + * INT344A is the Sunrise Point HID, as the Linux kernel doesn't support + * CannonPoint yet... + */ + acpigen_write_name_string("_CID", "INT344A"); + acpi_device_write_uid(dev); + acpigen_write_name_string("_DDN", "LPSS ACPI UART"); + acpigen_write_STA(acpi_device_status(dev)); + + /* Resources */ + acpigen_write_name("_CRS"); + acpigen_write_resourcetemplate_header(); + + acpi_device_write_interrupt(&irq); + acpigen_write_mem32fixed(1, res->base, res->size); + + acpigen_write_resourcetemplate_footer(); + + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ +} + +static const char *pch_h_uart2_acpi_hid(const struct device *dev) +{ + return "INT34BA"; +} + +static struct device_operations device_ops_cnp_h = { + .read_resources = uart_common_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = uart_common_enable_resources, + .ops_pci = &pci_dev_ops_pci, + .acpi_hid = pch_h_uart2_acpi_hid, + .acpi_fill_ssdt_generator = pch_h_uart2_fill_ssdt, +}; + +static const struct pci_driver pch_h_uart __pci_driver = { + .ops = &device_ops_cnp_h, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_CNP_H_UART2, +}; diff --git a/src/soc/intel/common/block/include/intelblocks/uart.h b/src/soc/intel/common/block/include/intelblocks/uart.h index cc27f0e..a51a739 100644 --- a/src/soc/intel/common/block/include/intelblocks/uart.h +++ b/src/soc/intel/common/block/include/intelblocks/uart.h @@ -31,6 +31,16 @@ void uart_common_init(const struct device *dev, uintptr_t baseaddr); /* + * Common routine to enable UART resources in PCI config space. + */ +void uart_common_enable_resources(struct device *dev); + +/* + * Common routine to read UART resources in PCI config space. + */ +void uart_common_read_resources(struct device *dev); + +/* * Check if UART debug controller is initialized * Returns: * true = If debug controller PCI config space is initialized and device is diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index 7d75bdd..3464571 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -143,7 +143,7 @@ #if ENV_RAMSTAGE -static void uart_read_resources(struct device *dev) +void uart_common_read_resources(struct device *dev) { pci_dev_read_resources(dev); @@ -213,7 +213,7 @@ return pch_uart_init_debug_controller_on_resume(); } -static void uart_common_enable_resources(struct device *dev) +void uart_common_enable_resources(struct device *dev) { pci_dev_enable_resources(dev); @@ -227,7 +227,7 @@ } static struct device_operations device_ops = { - .read_resources = uart_read_resources, + .read_resources = uart_common_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = uart_common_enable_resources, .ops_pci = &pci_dev_ops_pci, @@ -256,7 +256,6 @@ PCI_DEVICE_ID_INTEL_GLK_UART3, PCI_DEVICE_ID_INTEL_CNP_H_UART0, PCI_DEVICE_ID_INTEL_CNP_H_UART1, - PCI_DEVICE_ID_INTEL_CNP_H_UART2, PCI_DEVICE_ID_INTEL_ICP_UART0, PCI_DEVICE_ID_INTEL_ICP_UART1, PCI_DEVICE_ID_INTEL_ICP_UART2, -- To view, visit https://review.coreboot.org/c/coreboot/+/40405 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I838d16322be38f5421c1f63b457a0af552e0ed96 Gerrit-Change-Number: 40405 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

1 hour, 38 minutes

8
29
0 0

Change in coreboot[master]: mb/prodrive/hermes: Add multifunction device for UART2

by Christian Walter (Code Review)

Christian Walter has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43481 ) Change subject: mb/prodrive/hermes: Add multifunction device for UART2 ...................................................................... mb/prodrive/hermes: Add multifunction device for UART2 Multifunction device at 19.0 needs to be enabled such that 19.2 gets scanned. Change-Id: Ie77198cc0327414b9f88cf15ba4efaddb4f5cca4 Signed-off-by: Christian Walter <christian.walter(a)9elements.com> --- M src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/43481/1 diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb index 6c6fe2d..48ab0fe 100644 --- a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb +++ b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb @@ -177,7 +177,8 @@ device pci 14.3 on end # CNVi wifi end - device pci 19.2 on end # UART #2 + device pci 19.0 hidden end + device pci 19.2 on end # UART #2 device pci 1b.4 on smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT1" "SlotDataBusWidth4X" -- To view, visit https://review.coreboot.org/c/coreboot/+/43481 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie77198cc0327414b9f88cf15ba4efaddb4f5cca4 Gerrit-Change-Number: 43481 Gerrit-PatchSet: 1 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-MessageType: newchange

1 hour, 41 minutes

1
0
0 0

Change in coreboot[master]: mb/google/volteer: Create Mudada variant

by Kane Chen (Code Review)

Kane Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42301 ) Change subject: mb/google/volteer: Create Mudada variant ...................................................................... mb/google/volteer: Create Mudada variant Create the Mudada variant of the volteer. BUG=b:158797761 BRANCH=volteer TEST=emerge-volteer coreboot Signed-off-by: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Change-Id: I59ce4720e0ffeeeb2c9440bb300686def80211ea --- M src/mainboard/google/volteer/Kconfig M src/mainboard/google/volteer/Kconfig.name A src/mainboard/google/volteer/variants/mudada/Makefile.inc A src/mainboard/google/volteer/variants/mudada/gpio.c A src/mainboard/google/volteer/variants/mudada/include/variant/acpi/dptf.asl A src/mainboard/google/volteer/variants/mudada/include/variant/ec.h A src/mainboard/google/volteer/variants/mudada/include/variant/gpio.h A src/mainboard/google/volteer/variants/mudada/memory.c A src/mainboard/google/volteer/variants/mudada/memory/Makefile.inc A src/mainboard/google/volteer/variants/mudada/memory/dram_id.generated.txt A src/mainboard/google/volteer/variants/mudada/memory/mem_list_variant.txt A src/mainboard/google/volteer/variants/mudada/overridetree.cb 12 files changed, 650 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/42301/1 diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index 99a08a3..4092c5a 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -68,6 +68,7 @@ string default "Halvor" if BOARD_GOOGLE_HALVOR default "Malefor" if BOARD_GOOGLE_MALEFOR + default "Mudada" if BOARD_GOOGLE_MUDADA default "Ripto" if BOARD_GOOGLE_RIPTO default "Terrador" if BOARD_GOOGLE_TERRADOR default "Trondo" if BOARD_GOOGLE_TRONDO @@ -100,6 +101,7 @@ string default "halvor" if BOARD_GOOGLE_HALVOR default "malefor" if BOARD_GOOGLE_MALEFOR + default "mudada" if BOARD_GOOGLE_MUDADA default "ripto" if BOARD_GOOGLE_RIPTO default "terrador" if BOARD_GOOGLE_TERRADOR default "trondo" if BOARD_GOOGLE_TRONDO diff --git a/src/mainboard/google/volteer/Kconfig.name b/src/mainboard/google/volteer/Kconfig.name index 6920aaf..a680735 100644 --- a/src/mainboard/google/volteer/Kconfig.name +++ b/src/mainboard/google/volteer/Kconfig.name @@ -8,6 +8,10 @@ bool "-> Malefor" select BOARD_GOOGLE_BASEBOARD_VOLTEER +config BOARD_GOOGLE_MUDADA + bool "-> Mudada" + select BOARD_GOOGLE_BASEBOARD_VOLTEER + config BOARD_GOOGLE_RIPTO bool "-> Ripto" select BOARD_GOOGLE_BASEBOARD_VOLTEER diff --git a/src/mainboard/google/volteer/variants/mudada/Makefile.inc b/src/mainboard/google/volteer/variants/mudada/Makefile.inc new file mode 100644 index 0000000..343c7db --- /dev/null +++ b/src/mainboard/google/volteer/variants/mudada/Makefile.inc @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-only + +romstage-y += memory.c + +bootblock-y += gpio.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/volteer/variants/mudada/gpio.c b/src/mainboard/google/volteer/variants/mudada/gpio.c new file mode 100644 index 0000000..0e33926 --- /dev/null +++ b/src/mainboard/google/volteer/variants/mudada/gpio.c @@ -0,0 +1,438 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +/* Pad configuration in ramstage */ +/* Leave eSPI pins untouched from default settings */ +static const struct pad_config gpio_table[] = { + /* A0 thru A6 come configured out of reset, do not touch */ + /* A0 : ESPI_IO0 ==> ESPI_IO_0 */ + /* A1 : ESPI_IO1 ==> ESPI_IO_1 */ + /* A2 : ESPI_IO2 ==> ESPI_IO_2 */ + /* A3 : ESPI_IO3 ==> ESPI_IO_3 */ + /* A4 : ESPI_CS# ==> ESPI_CS_L */ + /* A5 : ESPI_CLK ==> ESPI_CLK */ + /* A6 : ESPI_RESET# ==> NC(TP764) */ + /* A7 : I2S2_SCLK ==> EN_PP3300_TRACKPAD */ + PAD_CFG_GPO(GPP_A7, 1, DEEP), + /* A8 : I2S2_SFRM ==> EN_PP3300_TOUCHSCREEN */ + PAD_CFG_GPO(GPP_A8, 0, DEEP), + /* A9 : I2S2_TXD ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_A9, NONE, DEEP), + /* A10 : I2S2_RXD ==> EN_SPKR_PA */ + PAD_CFG_GPO(GPP_A10, 1, DEEP), + /* A11 : PMC_I2C_SDA ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_A11, 1, DEEP), + /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), + /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ + PAD_CFG_GPO(GPP_A13, 1, DEEP), + /* A14 : USB_OC1# ==> USB_A0_OC_ODL */ + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), + /* A15 : USB_OC2# ==> USB_A1_OC_ODL */ + PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), + /* A16 : USB_OC3# ==> USB_C0_OC_ODL */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + /* A17 : DDSP_HPDC ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_A17, NONE, DEEP), + /* A18 : DDSP_HPDB ==> HDMI_HPD */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + /* A19 : DDSP_HPD1 ==> USB_C0_DP_HPD */ + PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), + /* A20 : DDSP_HPD2 ==> USB_C1_DP_HPD */ + PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), + /* A21 : DDPC_CTRCLK ==> NC */ + PAD_NC(GPP_A21, NONE), + /* A22 : DDPC_CTRLDATA ==> EN_HDMI_PWR */ + PAD_CFG_GPO(GPP_A22, 1, DEEP), + /* A23 : I2S1_SCLK ==> I2S1_SPKR_SCLK */ + PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), + + /* B0 : CORE_VID0 */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), + /* B1 : CORE_VID1 */ + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), + /* B2 : VRALERT# ==> NC */ + PAD_NC(GPP_B2, NONE), + /* B3 : CPU_GP2 ==> NC */ + PAD_NC(GPP_B3, NONE), + /* B4 : CPU_GP3 ==> NC */ + PAD_NC(GPP_B4, NONE), + /* B5 : ISH_I2C0_CVF_SDA == NC */ + PAD_NC(GPP_B5, NONE), + /* B6 : ISH_I2C0_CVF_SCL == NC */ + PAD_NC(GPP_B6, NONE), + /* B7 : ISH_12C1_SDA ==> NC */ + PAD_NC(GPP_B7, NONE), + /* B8 : ISH_I2C1_SCL ==> NC */ + PAD_NC(GPP_B8, NONE), + /* B9 : I2C5_SDA ==> PCH_I2C5_TRACKPAD_SDA */ + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + /* B10 : I2C5_SCL ==> PCH_I2C5_TRACKPAD_SCL */ + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), + /* B11 : PMCALERT# ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP), + /* B12 : SLP_S0# ==> SLP_S0_L */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + /* B13 : PLTRST# ==> PLT_RST_L */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + /* B14 : SPKR ==> GPP_B14_STRAP */ + PAD_NC(GPP_B14, NONE), + /* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : GSPI0_CLK ==> PCH_GSPI0_H1_TPM_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : GSPI0_MISO ==> PCH_GSPIO_H1_TPM_MISO */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* B19 : GSPI1_CS0# ==> NC */ + PAD_NC(GPP_B19, NONE), + /* B20 : GSPI1_CLK ==> NC */ + PAD_NC(GPP_B20, NONE), + /* B21 : GSPI1_MISO ==> NC */ + PAD_NC(GPP_B21, NONE), + /* B22 : GSPI1_MOSI ==> NC */ + PAD_NC(GPP_B22, NONE), + /* B23 : SML1ALERT# ==> GPP_B23_STRAP # */ + PAD_NC(GPP_B23, NONE), + + /* C0 : SMBCLK ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C1 : SMBDATA ==> NOT USED */ + PAD_NC(GPP_C1, NONE), + /* C2 : SMBALERT# ==> GPP_C2_STRAP */ + PAD_NC(GPP_C2, NONE), + /* C3 : SML0CLK ==> NC */ + PAD_NC(GPP_C3, NONE), + /* C4 : SML0DATA ==> NC */ + PAD_NC(GPP_C4, NONE), + /* C5 : SML0ALERT# ==> USB_SMB_INT_L_BOOT_STRAP0 */ + PAD_NC(GPP_C5, NONE), + /* C6 : SML1CLK ==> EC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C6, NONE, PLTRST, LEVEL, INVERT), + /* C7 : SML1DATA ==> NC */ + PAD_NC(GPP_C7, NONE), + /* C8 : UART0_RXD ==> UART_PCH_RX_DEBUG_TX */ + PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), + /* C9 : UART0_TXD ==> UART_PCH_TX_DEBUG_RX */ + PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), + /* C10 : UART0_RTS# ==> USI_RST_L */ + PAD_CFG_GPO(GPP_C10, 0, DEEP), + /* C11 : UART0_CTS# ==> NC */ + PAD_NC(GPP_C11, NONE), + /* C12 : UART1_RXD ==> MEM_STRAP_0 */ + PAD_CFG_GPI(GPP_C12, NONE, DEEP), + /* C13 : UART1_TXD ==> NC */ + PAD_NC(GPP_C13, NONE), + /* C14 : UART1_RTS# ==> MEM_STRAP_2 */ + PAD_CFG_GPI(GPP_C14, NONE, DEEP), + /* C15 : UART1_CTS# ==> MEM_STRAP_1 */ + PAD_CFG_GPI(GPP_C15, NONE, DEEP), + /* C16 : I2C0_SDA ==> PCH_I2C0_1V8_AUDIO_SDA */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + /* C17 : I2C0_SCL ==> PCH_I2C0_1V8_AUDIO_SCL */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + /* C18 : I2C1_SDA ==> PCH_I2C1_TOUCH_USI_SDA */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + /* C19 : I2C1_SCL ==> PCH_I2C1_TOUCH_USI_SCL */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + /* C20 : UART2_RXD ==> NC */ + PAD_NC(GPP_C20, NONE), + /* C21 : UART2_TXD ==> H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C22 : UART2_RTS# ==> NC */ + PAD_NC(GPP_C22, NONE), + /* C23 : UART2_CTS# ==> NC */ + PAD_NC(GPP_C23, NONE), + + /* D0 : ISH_GP0 ==> NC */ + PAD_NC(GPP_D0, NONE), + /* D1 : ISH_GP1 ==> NC */ + PAD_NC(GPP_D1, NONE), + /* D2 : ISH_GP2 ==> NC */ + PAD_NC(GPP_D2, NONE), + /* D3 : ISH_GP3 ==> NC */ + PAD_NC(GPP_D3, NONE), + /* D4 : IMGCLKOUT0 ==> NC */ + PAD_NC(GPP_D4, NONE), + /* D5 : SRCCLKREQ0$ ==> SSD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + /* D6 : SRCCLKREQ1# ==> NC */ + PAD_NC(GPP_D6, NONE), + /* D7 : SRCCLKREQ2# ==> NC */ + PAD_NC(GPP_D7, NONE), + /* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + /* D9 : ISH_SPI_CS# ==> NC */ + PAD_NC(GPP_D9, NONE), + /* D10 : ISH_SPI_CLK ==> PCH_GSPI2_CVF_CLK_STRAP */ + PAD_CFG_NF(GPP_D10, NONE, DEEP, NF7), + /* D11 : ISH_SPI_MISO ==> NC */ + PAD_NC(GPP_D11, NONE), + /* D12 : ISH_SPI_MOSI ==> PCH_GSPI2_CVF_MISO_STRAP */ + PAD_CFG_NF(GPP_D12, DN_20K, DEEP, NF7), + /* D13 : ISH_UART0_RXD ==> UART_ISH_RX_DEBUG_TX */ + PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), + /* D14 : ISH_UART0_TXD ==> UART_ISH_TX_DEBUG_RX */ + PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), + /* D15 : ISH_UART0_RTS# ==> MEM_STRAP_3 */ + PAD_CFG_GPI(GPP_D15, NONE, DEEP), + /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_D16, 1, DEEP), + /* D17 : ISH_GP4 ==> EN_FCAM_PWR */ + PAD_CFG_GPO(GPP_D17, 1, DEEP), + /* D18 : ISH_GP5 ==> NC */ + PAD_NC(GPP_D18, NONE), + /* D19 : I2S_MCLK1 ==> I2S_MCLK1 */ + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), + + /* E0 : SATAXPCIE0 ==> USB_A1_RT_RST_ODL */ + PAD_CFG_GPO(GPP_E0, 1, DEEP), + /* E1 : SPI1_IO2 ==> NC */ + PAD_NC(GPP_E1, NONE), + /* E2 : SPI1_IO3 ==> NC */ + PAD_NC(GPP_E2, NONE), + /* E3 : CPU_GP0 ==> USI_REPORT_EN */ + PAD_CFG_GPO(GPP_E3, 1, DEEP), + /* E4 : SATA_DEVSLP0 ==> M2_SSD_PE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E4, NONE, DEEP), + /* E5 : SATA_DEVSLP1 ==> M2_SSD_DEVSLP_OD */ + PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), + /* E6 : THC0_SPI1_RST# ==> GPPE6_STRAP */ + PAD_NC(GPP_E6, NONE), + /* E7 : CPU_GP1 ==> USI_INT */ + PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, LEVEL, NONE), + /* E8 : SPI1_CS1# ==> SLP_S0IX */ + PAD_CFG_GPO(GPP_E8, 0, DEEP), + /* E9 : USB2_OC0# ==> USB_C1_OC_ODL */ + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + /* E10 : SPI1_CS# ==> USB_C0_AUXP_DC */ + PAD_CFG_NF(GPP_E10, NONE, DEEP, NF6), + /* E11 : SPI1_CLK ==> SD_PE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E11, NONE, DEEP), + /* E12 : SPI1_MISO_IO1 ==> NC */ + PAD_NC(GPP_E12, NONE), + /* E13 : SPI1_MOSI_IO0 ==> USB_C0_AUXN_DC */ + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF6), + /* E14 : DDPC_HPDA ==> SOC_EDP_HPD */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + /* E15 : ISH_GP6 ==> TRACKPAD_INT_ODL */ + PAD_CFG_GPI_IRQ_WAKE(GPP_E15, NONE, DEEP, LEVEL, INVERT), + /* E16 : ISH_GP7 ==> NC */ + PAD_NC(GPP_E16, NONE), + /* E17 : THC0_SPI1_INT# ==> NC */ + PAD_NC(GPP_E17, NONE), + /* E18 : DDP1_CTRLCLK ==> NC */ + PAD_NC(GPP_E18, NONE), + /* E19 : DDP1_CTRLDATA ==> USB0_C0_LSX_SOC_RX_STRAP */ + PAD_CFG_NF(GPP_E19, NONE, DEEP, NF4), + /* E20 : DDP2_CTRLCLK ==> NC */ + PAD_NC(GPP_E20, NONE), + /* E21 : DDP2_CTRLDATA ==> USB_C1_LSX_SOC_RX_STRAP */ + PAD_CFG_NF(GPP_E21, NONE, DEEP, NF4), + /* E22 : DDPA_CTRLCLK ==> USB_C1_AUXP_DC: Retimer FW drives this pin */ + PAD_NC(GPP_E22, NONE), + /* E23 : DDPA_CTRLDATA ==> USB_C1_AUXN_DC: Retimer FW drives this pin */ + PAD_NC(GPP_E23, NONE), + + /* F0 : CNV_BRI_DT ==> CNV_BRI_DT_STRAP */ + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), + /* F1 : CNV_BRI_RSP ==> NCV_BRI_RSP */ + PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), + /* F2 : I2S2_TXD ==> CNV_RGI_DT_STRAP */ + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), + /* F3 : I2S2_RXD ==> CNV_RGI_RSP */ + PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), + /* F4 : CNV_RF_RESET# ==> CNV_RF_RST_L */ + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), + /* F5 : MODEM_CLKREQ ==> CNV_CLKREQ0 */ + PAD_CFG_NF(GPP_F5, NONE, DEEP, NF3), + /* F6 : CNV_PA_BLANKING ==> NC */ + PAD_NC(GPP_F6, NONE), + /* F7 : GPPF7_STRAP */ + PAD_NC(GPP_F7, NONE), + /* F8 : I2S_MCLK2_INOUT ==> HP_INT_L */ + PAD_CFG_GPI_INT(GPP_F8, NONE, PLTRST, EDGE_BOTH), + /* F9 : Reserved ==> NC */ + PAD_NC(GPP_F9, NONE), + /* F10 : GPPF10_STRAP */ + PAD_NC(GPP_F10, DN_20K), + /* F11 : GPPF11_THC1_SPI2_CLK ==> NC */ + PAD_NC(GPP_F11, NONE), + /* F12 : GSXDOUT ==> NC */ + PAD_NC(GPP_F12, NONE), + /* F13 : GSXDOUT ==> WiFi_DISABLE_L */ + PAD_CFG_GPO(GPP_F13, 1, DEEP), + /* F14 : GSXDIN ==> NC */ + PAD_NC(GPP_F14, NONE), + /* F15 : GSXSRESET# ==> NC */ + PAD_NC(GPP_F15, NONE), + /* F16 : GSXCLK ==> NC */ + PAD_NC(GPP_F16, NONE), + /* F17 : WWAN_RF_DISABLE_ODL == NC */ + PAD_NC(GPP_F17, NONE), + /* F18 : THC1_SPI2_INT# ==> NC */ + PAD_NC(GPP_F18, NONE), + /* F19 : SRCCLKREQ6# ==> NC */ + PAD_NC(GPP_F19, NONE), + /* F20 : EXT_PWR_GATE# ==> EXT_PWR_GATE_L */ + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), + /* F21 : EXT_PWR_GATE2# ==> EXT_PWR_GATE2_L */ + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), + /* F22 : VNN_CTRL */ + PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), + /* F23 : V1P05_CTRL */ + PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1), + + /* H0 : GPPH0_BOOT_STRAP1 */ + PAD_NC(GPP_H0, NONE), + /* H1 : GPPH1_BOOT_STRAP2 */ + PAD_NC(GPP_H1, NONE), + /* H2 : GPPH2_BOOT_STRAP3 */ + PAD_NC(GPP_H2, NONE), + /* H3 : SX_EXIT_HOLDOFF# ==> SD_PERST_L */ + PAD_CFG_GPO(GPP_H3, 1, DEEP), + /* H4 : I2C2_SDA ==> PCH_I2C2_MISC_SDA */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* H5 : I2C2_SCL ==> PCH_I2C2_MISC_SCL */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* H6 : I2C3_SDA ==> NC */ + PAD_NC(GPP_H6, NONE), + /* H7 : I2C3_SCL ==> NC */ + PAD_NC(GPP_H7, NONE), + /* H8 : I2C4_SDA ==> PCB_ID0 */ + PAD_CFG_GPI(GPP_H8, NONE, DEEP), + /* H9 : I2C4_SCL ==> PCB_ID1 */ + PAD_CFG_GPI(GPP_H9, NONE, DEEP), + /* H10 : SRCCLKREQ4# ==> NC */ + PAD_NC(GPP_H10, NONE), + /* H11 : SRCCLKREQ5# ==> NC */ + PAD_NC(GPP_H11, NONE), + /* H12 : M2_SKT2_CFG0 ==> NC */ + PAD_NC(GPP_H12, NONE), + /* H13 : M2_SKT2_CFG1 # ==> WWAN_CONFIG1 */ + PAD_CFG_GPI(GPP_H13, NONE, DEEP), + /* H14 : M2_SKT2_CFG2 # ==> NC */ + PAD_NC(GPP_H14, NONE), + /* H15 : M2_SKT2_CFG3 # ==> NC */ + PAD_NC(GPP_H15, NONE), + /* H16 : DDPB_CTRLCLK ==> DDPB_HDMI_CTRLCLK */ + PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), + /* H17 : DDPB_CTRLDATA ==> DDPB_HDMI_CTRLDATA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + /* H18 : CPU_C10_GATE# ==> CPU_C10_GATE_L */ + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), + /* H19 : TIME_SYNC0 ==> NC */ + PAD_NC(GPP_H19, NONE), + /* H20 : IMGCLKOUT1 ==> NC */ + PAD_NC(GPP_H20, NONE), + /* H21 : IMGCLKOUT2 ==> NC */ + PAD_NC(GPP_H21, NONE), + /* H22 : IMGCLKOUT3 ==> NC */ + PAD_NC(GPP_H22, NONE), + /* H23 : IMGCLKOUT4 ==> NC */ + PAD_NC(GPP_H23, NONE), + + /* R0 : HDA_BCLK ==> I2S0_HP_SCLK */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), + /* R1 : HDA_SYNC ==> I2S0_HP_SFRM */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), + /* R2 : HDA_SDO ==> I2S0_PCH_TX_HP_RX_STRAP */ + PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), + /* R3 : HDA_SDIO ==> I2S0_PCH_RX_HP_TX */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), + /* R4 : HDA_RST# ==> NC */ + PAD_NC(GPP_R4, NONE), + /* R5 : HDA_SDI1 ==> I2S1_PCH_RX_SPKR_TX */ + PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), + /* R6 : I2S1_TXD ==> I2S1_PCH_RX_SPKR_RX */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), + /* R7 : I2S1_SFRM ==> I2S1_SPKR_SFRM */ + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), + + /* S0 : SNDW0_CLK ==> SNDW0_HP_CLK */ + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1), + /* S1 : SNDW0_DATA ==> SNDW0_HP_DATA */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1), + /* S2 : SNDW1_CLK ==> SNDW1_SPKR_CLK */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF1), + /* S3 : SNDW1_DATA ==> SNDW1_SPKR_DATA */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF1), + /* S4 : SNDW2_CLK ==> NC */ + PAD_NC(GPP_S4, NONE), + /* S5 : SNDW2_DATA ==> NC */ + PAD_NC(GPP_S5, NONE), + /* S6 : SNDW3_CLK ==> DMIC_CLK0 */ + PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), + /* S7 : SNDW3_DATA ==> DMIC_DATA0 */ + PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), + + /* GPD0: BATLOW# ==> BATLOW_L */ + PAD_CFG_NF(GPD0, NONE, DEEP, NF1), + /* GPD1: ACPRESENT ==> PCH_ACPRESENT */ + PAD_CFG_NF(GPD1, NONE, DEEP, NF1), + /* GPD2: LAN_WAKE# ==> EC_PCH_WAKE_ODL */ + PAD_CFG_NF(GPD2, NONE, DEEP, NF1), + /* GPD3: PWRBTN# ==> EC_PCH_PWR_BTN_ODL */ + PAD_CFG_NF(GPD3, NONE, DEEP, NF1), + /* GPD4: SLP_S3# ==> SLP_S3_L */ + PAD_CFG_NF(GPD4, NONE, DEEP, NF1), + /* GPD5: SLP_S4# ==> SLP_S4_L */ + PAD_CFG_NF(GPD5, NONE, DEEP, NF1), + /* GPD6: SLP_A# ==> SLP_A_L */ + PAD_CFG_NF(GPD6, NONE, DEEP, NF1), + /* GPD7: GPD7_STRAP */ + PAD_CFG_GPI(GPD7, DN_20K, DEEP), + /* GPD8: SUSCLK ==> PCH_SUSCLK */ + PAD_CFG_NF(GPD8, NONE, DEEP, NF1), + /* GPD9: SLP_WLAN# ==> SLP_WLAN_L */ + PAD_CFG_NF(GPD9, NONE, DEEP, NF1), + /* GPD10: SLP_S5# ==> SLP_S5_L */ + PAD_CFG_NF(GPD10, NONE, DEEP, NF1), + /* GPD11: LANPHYC ==> NC */ +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), + + /* A17 : DDSP_HPDC ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_A17, NONE, DEEP), + + /* B11 : PMCALERT# ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP), + + /* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + + /* B16 : GSPI0_CLK ==> PCH_GSPI0_H1_TPM_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + + /* B17 : GSPI0_MISO ==> PCH_GSPIO_H1_TPM_MISO */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + + /* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + + /* C0 : SMBCLK ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + + /* C21 : UART2_TXD ==> H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), +}; + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/google/volteer/variants/mudada/include/variant/acpi/dptf.asl b/src/mainboard/google/volteer/variants/mudada/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..726e381 --- /dev/null +++ b/src/mainboard/google/volteer/variants/mudada/include/variant/acpi/dptf.asl @@ -0,0 +1,7 @@ +/* + * + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include <baseboard/acpi/dptf.asl> diff --git a/src/mainboard/google/volteer/variants/mudada/include/variant/ec.h b/src/mainboard/google/volteer/variants/mudada/include/variant/ec.h new file mode 100644 index 0000000..6e12175 --- /dev/null +++ b/src/mainboard/google/volteer/variants/mudada/include/variant/ec.h @@ -0,0 +1,12 @@ +/* + * + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/volteer/variants/mudada/include/variant/gpio.h b/src/mainboard/google/volteer/variants/mudada/include/variant/gpio.h new file mode 100644 index 0000000..c7e4605 --- /dev/null +++ b/src/mainboard/google/volteer/variants/mudada/include/variant/gpio.h @@ -0,0 +1,12 @@ +/* + * + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <baseboard/gpio.h> + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/volteer/variants/mudada/memory.c b/src/mainboard/google/volteer/variants/mudada/memory.c new file mode 100644 index 0000000..d0bfcb5 --- /dev/null +++ b/src/mainboard/google/volteer/variants/mudada/memory.c @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> + +static const struct lpddr4x_cfg malefor_memcfg = { + /* DQ byte map */ + .dq_map = { + [0] = { + { 3, 2, 1, 0, 4, 5, 7, 6, }, /* DDR0_DQ0[7:0] */ + { 12, 13, 14, 15, 11, 10, 9, 8 }, /* DDR0_DQ1[7:0] */ + }, + [1] = { + { 0, 7, 1, 6, 2, 5, 3, 4, }, /* DDR1_DQ0[7:0] */ + { 8, 15, 14, 9, 12, 10, 13, 11 }, /* DDR1_DQ1[7:0] */ + }, + [2] = { + { 2, 3, 0, 1, 4, 5, 6, 7, }, /* DDR2_DQ0[7:0] */ + { 12, 13, 15, 14, 11, 10, 9, 8 }, /* DDR2_DQ1[7:0] */ + }, + [3] = { + { 7, 0, 1, 6, 5, 4, 2, 3, }, /* DDR3_DQ0[7:0] */ + { 15, 14, 8, 9, 10, 13, 11, 12 }, /* DDR3_DQ1[7:0] */ + }, + [4] = { + { 4, 5, 2, 3, 7, 6, 0, 1, }, /* DDR4_DQ0[7:0] */ + { 12, 13, 15, 14, 11, 10, 8, 9 }, /* DDR4_DQ1[7:0] */ + }, + [5] = { + { 3, 4, 2, 5, 0, 6, 1, 7, }, /* DDR5_DQ0[7:0] */ + { 12, 13, 11, 10, 14, 15, 9, 8 }, /* DDR5_DQ1[7:0] */ + }, + [6] = { + { 3, 2, 1, 0, 7, 4, 5, 6, }, /* DDR6_DQ0[7:0] */ + { 15, 14, 13, 12, 8, 9, 10, 11 }, /* DDR6_DQ1[7:0] */ + }, + [7] = { + { 2, 4, 3, 5, 1, 0, 7, 6, }, /* DDR7_DQ0[7:0] */ + { 14, 15, 9, 8, 12, 10, 11, 13 }, /* DDR7_DQ1[7:0] */ + }, + }, + + /* DQS CPU<>DRAM map */ + .dqs_map = { + [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ + [1] = { 0, 1 }, /* DDR1_DQS[1:0] */ + [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ + [3] = { 0, 1 }, /* DDR3_DQS[1:0] */ + [4] = { 0, 1 }, /* DDR4_DQS[1:0] */ + [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ + [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ + [7] = { 0, 1 }, /* DDR7_DQS[1:0] */ + }, + + .ect = 1, /* Enable Early Command Training */ +}; + +const struct lpddr4x_cfg *variant_memory_params(void) +{ + return &malefor_memcfg; +} diff --git a/src/mainboard/google/volteer/variants/mudada/memory/Makefile.inc b/src/mainboard/google/volteer/variants/mudada/memory/Makefile.inc new file mode 100644 index 0000000..7aa547b --- /dev/null +++ b/src/mainboard/google/volteer/variants/mudada/memory/Makefile.inc @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! + +SPD_SOURCES = +SPD_SOURCES += spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, H9HCNNNBKMMLXR-NEE +SPD_SOURCES += spd-4.hex # ID = 1(0b0001) Parts = MT53E1G32D2NP-046 WT:A +SPD_SOURCES += spd-2.hex # ID = 2(0b0010) Parts = H9HCNNNCPMMLXR-NEE diff --git a/src/mainboard/google/volteer/variants/mudada/memory/dram_id.generated.txt b/src/mainboard/google/volteer/variants/mudada/memory/dram_id.generated.txt new file mode 100644 index 0000000..b5bd3ef --- /dev/null +++ b/src/mainboard/google/volteer/variants/mudada/memory/dram_id.generated.txt @@ -0,0 +1,5 @@ +DRAM Part Name ID to assign +MT53E512M32D2NP-046 WT:E 0 (0000) +MT53E1G32D2NP-046 WT:A 1 (0001) +H9HCNNNBKMMLXR-NEE 0 (0000) +H9HCNNNCPMMLXR-NEE 2 (0010) diff --git a/src/mainboard/google/volteer/variants/mudada/memory/mem_list_variant.txt b/src/mainboard/google/volteer/variants/mudada/memory/mem_list_variant.txt new file mode 100644 index 0000000..b99b811 --- /dev/null +++ b/src/mainboard/google/volteer/variants/mudada/memory/mem_list_variant.txt @@ -0,0 +1,4 @@ +MT53E512M32D2NP-046 WT:E +MT53E1G32D2NP-046 WT:A +H9HCNNNBKMMLXR-NEE +H9HCNNNCPMMLXR-NEE diff --git a/src/mainboard/google/volteer/variants/mudada/overridetree.cb b/src/mainboard/google/volteer/variants/mudada/overridetree.cb new file mode 100644 index 0000000..9e5ef4b --- /dev/null +++ b/src/mainboard/google/volteer/variants/mudada/overridetree.cb @@ -0,0 +1,92 @@ +chip soc/intel/tigerlake + device domain 0 on + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_F8)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on + probe AUDIO MAX98357_ALC5682I_I2S + probe AUDIO MAX98373_ALC5682I_I2S + end + end + chip drivers/i2c/max98373 + register "vmon_slot_no" = "0" + register "imon_slot_no" = "1" + register "uid" = "0" + register "desc" = ""Right Speaker Amp"" + register "name" = ""MAXR"" + device i2c 31 on + probe AUDIO MAX98373_ALC5682I_I2S + end + end + chip drivers/i2c/max98373 + register "vmon_slot_no" = "2" + register "imon_slot_no" = "3" + register "uid" = "1" + register "desc" = ""Left Speaker Amp"" + register "name" = ""MAXL"" + device i2c 32 on + probe AUDIO MAX98373_ALC5682I_I2S + end + end + end + device pci 1f.3 on + chip drivers/generic/max98357a + register "hid" = ""MX98357A"" + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)" + register "sdmode_delay" = "5" + device generic 0 on + probe AUDIO MAX98357_ALC5682I_I2S + end + end + chip drivers/intel/soundwire + device generic 0 on + probe AUDIO MAX98373_ALC5682_SNDW + chip drivers/soundwire/alc5682 + # SoundWire Link 0 ID 1 + register "desc" = ""Headset Codec"" + device generic 0.1 on end + end + chip drivers/soundwire/max98373 + # SoundWire Link 1 ID 3 + register "desc" = ""Left Speaker Amp"" + device generic 1.3 on end + end + chip drivers/soundwire/max98373 + # SoundWire Link 1 ID 7 + register "desc" = ""Right Speaker Amp"" + device generic 1.7 on end + end + end + end + end + device pci 1f.2 hidden + # The pmc_mux chip driver is a placeholder for the + # PMC.MUX device in the ACPI hierarchy. + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/con + register "usb2_port_number" = "9" + register "usb3_port_number" = "1" + # SBU & HSL follow CC + device generic 0 on end + end + chip drivers/intel/pmc_mux/con + register "usb2_port_number" = "4" + register "usb3_port_number" = "2" + # SBU is fixed, HSL follows CC + register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" + device generic 1 on end + end + end + end + end # PMC + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/42301 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I59ce4720e0ffeeeb2c9440bb300686def80211ea Gerrit-Change-Number: 42301 Gerrit-PatchSet: 1 Gerrit-Owner: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-MessageType: newchange

1 hour, 44 minutes

7
31
0 0

Change in coreboot[master]: Added GBYT4 port

by Máté Kukri (Code Review)

Máté Kukri has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43087 ) Change subject: Added GBYT4 port ...................................................................... Added GBYT4 port Change-Id: I99ed0c94c3255578151f940ad9b274e6f0816bfe --- A src/mainboard/unk/Kconfig A src/mainboard/unk/Kconfig.name A src/mainboard/unk/gbyt4/Kconfig A src/mainboard/unk/gbyt4/Kconfig.name A src/mainboard/unk/gbyt4/Makefile.inc A src/mainboard/unk/gbyt4/acpi/dptf.asl A src/mainboard/unk/gbyt4/acpi/ec.asl A src/mainboard/unk/gbyt4/acpi/mainboard.asl A src/mainboard/unk/gbyt4/acpi/superio.asl A src/mainboard/unk/gbyt4/acpi_tables.c A src/mainboard/unk/gbyt4/board_info.txt A src/mainboard/unk/gbyt4/cmos.layout A src/mainboard/unk/gbyt4/devicetree.cb A src/mainboard/unk/gbyt4/dsdt.asl A src/mainboard/unk/gbyt4/early_init.c A src/mainboard/unk/gbyt4/gpio.c A src/mainboard/unk/gbyt4/irqroute.c A src/mainboard/unk/gbyt4/irqroute.h A src/mainboard/unk/gbyt4/mainboard.c A src/mainboard/unk/gbyt4/romstage.c 20 files changed, 792 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/43087/1 diff --git a/src/mainboard/unk/Kconfig b/src/mainboard/unk/Kconfig new file mode 100644 index 0000000..86fe2d6 --- /dev/null +++ b/src/mainboard/unk/Kconfig @@ -0,0 +1,19 @@ +if VENDOR_UNK + +choice + prompt "Mainboard model" + +source "src/mainboard/unk/*/Kconfig.name" + +endchoice + +source "src/mainboard/unk/*/Kconfig" + +config MAINBOARD_VENDOR + default "Unknown" + +config MAINBOARD_FAMILY + string + default MAINBOARD_PART_NUMBER + +endif # VENDOR_UNK diff --git a/src/mainboard/unk/Kconfig.name b/src/mainboard/unk/Kconfig.name new file mode 100644 index 0000000..a5f8bf4 --- /dev/null +++ b/src/mainboard/unk/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_UNK + bool "Unknown" diff --git a/src/mainboard/unk/gbyt4/Kconfig b/src/mainboard/unk/gbyt4/Kconfig new file mode 100644 index 0000000..b57f977 --- /dev/null +++ b/src/mainboard/unk/gbyt4/Kconfig @@ -0,0 +1,24 @@ +if BOARD_UNK_GBYT4 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SOC_INTEL_BAYTRAIL + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_ACPI_RESUME + select SUPERIO_ITE_IT8728F + +config MAINBOARD_DIR + string + default "unk/gbyt4" + +config MAINBOARD_PART_NUMBER + string + default "GBYT4" + +config MAINBOARD_SMBIOS_MANUFACTURER + string + default "UNKNOWN" + +endif # BOARD_KM_GBYT4 diff --git a/src/mainboard/unk/gbyt4/Kconfig.name b/src/mainboard/unk/gbyt4/Kconfig.name new file mode 100644 index 0000000..29c4e9d --- /dev/null +++ b/src/mainboard/unk/gbyt4/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_UNK_GBYT4 + bool "GBYT4" diff --git a/src/mainboard/unk/gbyt4/Makefile.inc b/src/mainboard/unk/gbyt4/Makefile.inc new file mode 100644 index 0000000..2bde1bd --- /dev/null +++ b/src/mainboard/unk/gbyt4/Makefile.inc @@ -0,0 +1,10 @@ +## SPDX-License-Identifier: GPL-2.0-only + +ramstage-y += irqroute.c gpio.c +bootblock-y += early_init.c +romstage-y += early_init.c + +# Temporary shit to test MRC +cbfs-files-y += spd.bin +spd.bin-file := spd.bin +spd.bin-type := spd diff --git a/src/mainboard/unk/gbyt4/acpi/dptf.asl b/src/mainboard/unk/gbyt4/acpi/dptf.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/unk/gbyt4/acpi/dptf.asl diff --git a/src/mainboard/unk/gbyt4/acpi/ec.asl b/src/mainboard/unk/gbyt4/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/unk/gbyt4/acpi/ec.asl diff --git a/src/mainboard/unk/gbyt4/acpi/mainboard.asl b/src/mainboard/unk/gbyt4/acpi/mainboard.asl new file mode 100644 index 0000000..f343574 --- /dev/null +++ b/src/mainboard/unk/gbyt4/acpi/mainboard.asl @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Scope (\_SB.PCI0.LPEA) +{ + Name (GBUF, ResourceTemplate () + { + /* Jack Detect (index 0) */ + GpioInt (Level, ActiveHigh, Exclusive, PullNone,, + "\\_SB.GPSC") { 14 } + + /* Mic Detect (index 1) */ + GpioInt (Level, ActiveHigh, Exclusive, PullNone,, + "\\_SB.GPSC") { 15 } + }) +} diff --git a/src/mainboard/unk/gbyt4/acpi/superio.asl b/src/mainboard/unk/gbyt4/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/unk/gbyt4/acpi/superio.asl diff --git a/src/mainboard/unk/gbyt4/acpi_tables.c b/src/mainboard/unk/gbyt4/acpi_tables.c new file mode 100644 index 0000000..41ec5f9 --- /dev/null +++ b/src/mainboard/unk/gbyt4/acpi_tables.c @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <types.h> +#include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> +#include <arch/ioapic.h> +#include <device/device.h> +#include <soc/acpi.h> +#include <soc/nvs.h> +#include <soc/iomap.h> + +void acpi_create_gnvs(struct global_nvs *gnvs) +{ + acpi_init_gnvs(gnvs); + + /* Enable USB ports in S3 */ + gnvs->s3u0 = 1; + gnvs->s3u1 = 1; + + /* Disable USB ports in S5 */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + /* TPM Present */ + gnvs->tpmp = 0; + + /* Enable DPTF */ + gnvs->dpte = 0; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + 2, IO_APIC_ADDR, 0); + + current = acpi_madt_irq_overrides(current); + + return current; +} + +void mainboard_fill_fadt(acpi_fadt_t *fadt) +{ + fadt->preferred_pm_profile = PM_MOBILE; +} diff --git a/src/mainboard/unk/gbyt4/board_info.txt b/src/mainboard/unk/gbyt4/board_info.txt new file mode 100644 index 0000000..5152b2a --- /dev/null +++ b/src/mainboard/unk/gbyt4/board_info.txt @@ -0,0 +1,7 @@ +Vendor name: Unknown +Board name: GBYT4 +Category: desktop +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/unk/gbyt4/cmos.layout b/src/mainboard/unk/gbyt4/cmos.layout new file mode 100644 index 0000000..da1b185 --- /dev/null +++ b/src/mainboard/unk/gbyt4/cmos.layout @@ -0,0 +1,89 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +# Status Register A +# ----------------------------------------------------------------- +# Status Register B +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +#392 3 r 0 unused +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +#411 5 r 0 unused + +# coreboot config options: bootloader +#Used by ChromeOS: +416 128 r 0 vbnv +#544 440 r 0 unused + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/unk/gbyt4/devicetree.cb b/src/mainboard/unk/gbyt4/devicetree.cb new file mode 100644 index 0000000..d442127 --- /dev/null +++ b/src/mainboard/unk/gbyt4/devicetree.cb @@ -0,0 +1,94 @@ +chip soc/intel/baytrail + + register "usb2_comp_bg" = "0x4700" + + # Allow PCIe devices to wake system from suspend + register "pcie_wake_enable" = "1" + + # IGD Displays + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + + # SATA port enable mask (2 ports) + register "sata_port_map" = "0x1" + register "sata_ahci" = "0x1" + register "ide_legacy_combined" = "0x0" + + # Do not route USB ports to XHCI + register "usb_route_to_xhci" = "0" + + # USB Port Disable Mask + register "usb2_port_disable_mask" = "0x0" + register "usb3_port_disable_mask" = "0x0" + + # USB PHY settings + register "usb2_per_port_lane0" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d" + register "usb2_per_port_lane1" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d" + register "usb2_per_port_lane2" = "0x00049209" + register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015" + register "usb2_per_port_lane3" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d" + + # Disable SLP_X stretching after SUS power well fail. + register "disable_slp_x_stretch_sus_fail" = "1" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # SoC router + device pci 02.0 on end # GFX + device pci 10.0 off end # MMC + device pci 11.0 off end # SDIO + device pci 12.0 off end # SD + device pci 13.0 on end # SATA + device pci 14.0 off end # XHCI + device pci 15.0 off end # LPE + device pci 17.0 off end # MMC45 + device pci 18.0 off end # SIO_DMA1 + device pci 18.1 off end # I2C1 + device pci 18.2 off end # I2C2 + device pci 18.3 off end # I2C3 + device pci 18.4 off end # I2C4 + device pci 18.5 off end # I2C5 + device pci 18.6 off end # I2C6 + device pci 18.7 off end # I2C7 + device pci 1a.0 on end # TXE + device pci 1b.0 off end # HDA + device pci 1c.0 on end # PCI-e #1 (LAN1) + device pci 1c.1 on end # PCI-e #2 (LAN2) + device pci 1c.2 on end # PCI-e #3 (LAN3) + device pci 1c.3 on end # PCI-e #4 (LAN4) + device pci 1d.0 on end # EHCI + device pci 1e.0 off end # SIO_DMA2 + device pci 1e.1 off end # PWM1 + device pci 1e.2 off end # PWM2 + device pci 1e.3 off end # HSUART1 + device pci 1e.4 off end # HSUART2 + device pci 1e.5 off end # SPI + + device pci 1f.0 on # LPC + chip superio/ite/it8728f + device pnp 2e.0 off end # Floppy + device pnp 2e.1 on # COM1 + io 0x60 = 0x03f8 + irq 0x70 = 4 + end + device pnp 2e.2 off end # COM2 + device pnp 2e.3 off end # Parallel port + device pnp 2e.4 on # Environment Controller + io 0x60 = 0x0a30 + irq 0x70 = 9 + io 0x62 = 0x0a20 + end + device pnp 2e.5 off end # Keyboard + device pnp 2e.6 off end # Mouse + device pnp 2e.7 off end # GPIO + device pnp 2e.a off end # CIR + end + end + + device pci 1f.3 on end # SMBus + end +end diff --git a/src/mainboard/unk/gbyt4/dsdt.asl b/src/mainboard/unk/gbyt4/dsdt.asl new file mode 100644 index 0000000..fb037b1 --- /dev/null +++ b/src/mainboard/unk/gbyt4/dsdt.asl @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define ENABLE_TPM + +#include <acpi/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + #include <soc/intel/baytrail/acpi/platform.asl> + + // global NVS and variables + #include <soc/intel/baytrail/acpi/globalnvs.asl> + + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + //#include <soc/intel/baytrail/acpi/northcluster.asl> + #include <soc/intel/baytrail/acpi/southcluster.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + } + + /* Dynamic Platform Thermal Framework */ + #include "acpi/dptf.asl" + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/unk/gbyt4/early_init.c b/src/mainboard/unk/gbyt4/early_init.c new file mode 100644 index 0000000..89da435 --- /dev/null +++ b/src/mainboard/unk/gbyt4/early_init.c @@ -0,0 +1,11 @@ +#include <bootblock_common.h> +#include <superio/ite/common/ite.h> +#include <superio/ite/it8728f/it8728f.h> + +#define SERIAL_DEV PNP_DEV(0x2e, 0x01) + +void bootblock_mainboard_early_init(void) +{ + /* Enable serial port */ + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/unk/gbyt4/gpio.c b/src/mainboard/unk/gbyt4/gpio.c new file mode 100644 index 0000000..b5e68c1 --- /dev/null +++ b/src/mainboard/unk/gbyt4/gpio.c @@ -0,0 +1,211 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/gpio.h> +#include <mainboard/unk/gbyt4/irqroute.h> + +/* NCORE GPIOs */ +static const struct soc_gpio_map gpncore_gpio_map[] = { + GPIO_FUNC(2, PULL_UP, 20K), + GPIO_FUNC(2, PULL_DOWN, 20K), + GPIO_FUNC(2, PULL_UP, 20K), + GPIO_FUNC(0, PULL_DISABLE, 20K), + GPIO_FUNC(0, PULL_DISABLE, 20K), + GPIO_FUNC(0, PULL_DISABLE, 20K), + GPIO_FUNC(2, PULL_DISABLE, 20K), + GPIO_FUNC(2, PULL_DISABLE, 20K), + GPIO_FUNC(2, PULL_DISABLE, 20K), + GPIO_FUNC(2, PULL_DISABLE, 20K), + GPIO_FUNC(2, PULL_DISABLE, 20K), + GPIO_FUNC(2, PULL_DISABLE, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(0, PULL_DISABLE, 20K), + GPIO_FUNC(0, PULL_DISABLE, 20K), + GPIO_FUNC(1, PULL_DISABLE, 20K), + GPIO_FUNC(1, PULL_DISABLE, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DISABLE, 20K), + GPIO_FUNC(1, PULL_DISABLE, 20K), + GPIO_FUNC(1, PULL_DISABLE, 20K), + GPIO_FUNC(1, PULL_DISABLE, 20K), + GPIO_FUNC(1, PULL_DISABLE, 20K), + GPIO_FUNC(1, PULL_DISABLE, 20K), + GPIO_FUNC(1, PULL_DISABLE, 20K), + GPIO_FUNC(1, PULL_DISABLE, 20K), + GPIO_END +}; + +/* SCORE GPIOs */ +static const struct soc_gpio_map gpscore_gpio_map[] = { + GPIO_FUNC(0, PULL_DISABLE, 20K), + GPIO_FUNC(2, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(0, PULL_UP, 20K), + GPIO_FUNC(2, PULL_DOWN, 20K), + GPIO_FUNC(2, PULL_DOWN, 20K), + GPIO_FUNC(2, PULL_DOWN, 20K), + GPIO_FUNC(2, PULL_DOWN, 20K), + GPIO_FUNC(2, PULL_DOWN, 20K), + GPIO_FUNC(2, PULL_DOWN, 20K), + GPIO_FUNC(2, PULL_DOWN, 20K), + GPIO_FUNC(2, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(0, PULL_DOWN, 20K), + GPIO_FUNC(0, PULL_DOWN, 20K), + GPIO_FUNC(0, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(2, PULL_UP, 20K), + GPIO_FUNC(0, PULL_UP, 20K), + GPIO_FUNC(0, PULL_UP, 20K), + GPIO_FUNC(0, PULL_DOWN, 20K), + GPIO_FUNC(0, PULL_DISABLE, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_END +}; + +/* SSUS GPIOs */ +static const struct soc_gpio_map gpssus_gpio_map[] = { + GPIO_FUNC(0, PULL_UP, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(0, PULL_UP, 20K), + GPIO_FUNC(0, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(0, PULL_DOWN, 20K), + GPIO_FUNC(0, PULL_DOWN, 20K), + GPIO_FUNC(0, PULL_DISABLE, 20K), + GPIO_FUNC(0, PULL_DISABLE, 20K), + GPIO_FUNC(0, PULL_UP, 20K), + GPIO_FUNC(0, PULL_DOWN, 20K), + GPIO_FUNC(0, PULL_DOWN, 20K), + GPIO_FUNC(0, PULL_DOWN, 20K), + GPIO_FUNC(2, PULL_DISABLE, 20K), + GPIO_FUNC(0, PULL_UP, 20K), + GPIO_FUNC(0, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(0, PULL_DOWN, 20K), + GPIO_FUNC(0, PULL_UP, 20K), + GPIO_FUNC(0, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(0, PULL_DISABLE, 20K), + GPIO_FUNC(0, PULL_DOWN, 20K), + GPIO_FUNC(0, PULL_DOWN, 20K), + GPIO_FUNC(0, PULL_DOWN, 20K), + GPIO_FUNC(0, PULL_DOWN, 20K), + GPIO_FUNC(0, PULL_UP, 20K), + GPIO_FUNC(2, PULL_UP, 20K), + GPIO_FUNC(0, PULL_DISABLE, 20K), + GPIO_FUNC(0, PULL_DISABLE, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DISABLE, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_END +}; + +static const u8 core_dedicated_irq[GPIO_MAX_DIRQS] = { +}; + +static const u8 sus_dedicated_irq[GPIO_MAX_DIRQS] = { +}; + +static struct soc_gpio_config gpio_config = { + .ncore = gpncore_gpio_map, + .score = gpscore_gpio_map, + .ssus = gpssus_gpio_map, + .core_dirq = &core_dedicated_irq, + .sus_dirq = &sus_dedicated_irq, +}; + +struct soc_gpio_config* mainboard_get_gpios(void) +{ + return &gpio_config; +} diff --git a/src/mainboard/unk/gbyt4/irqroute.c b/src/mainboard/unk/gbyt4/irqroute.c new file mode 100644 index 0000000..6fa0366 --- /dev/null +++ b/src/mainboard/unk/gbyt4/irqroute.c @@ -0,0 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "irqroute.h" + +DEFINE_IRQ_ROUTES; diff --git a/src/mainboard/unk/gbyt4/irqroute.h b/src/mainboard/unk/gbyt4/irqroute.h new file mode 100644 index 0000000..7dd9ad2 --- /dev/null +++ b/src/mainboard/unk/gbyt4/irqroute.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/irq.h> +#include <soc/pci_devs.h> +#include <soc/pmc.h> + +#define PCI_DEV_PIRQ_ROUTES \ + PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(SATA_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(TXE_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(PCIE_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(EHCI_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(PCU_DEV, A, B, C, D) + +#define PIRQ_PIC_ROUTES \ + PIRQ_PIC(A, DISABLE), \ + PIRQ_PIC(B, DISABLE), \ + PIRQ_PIC(C, DISABLE), \ + PIRQ_PIC(D, DISABLE), \ + PIRQ_PIC(E, DISABLE), \ + PIRQ_PIC(F, DISABLE), \ + PIRQ_PIC(G, DISABLE), \ + PIRQ_PIC(H, DISABLE) diff --git a/src/mainboard/unk/gbyt4/mainboard.c b/src/mainboard/unk/gbyt4/mainboard.c new file mode 100644 index 0000000..b6ccc7f --- /dev/null +++ b/src/mainboard/unk/gbyt4/mainboard.c @@ -0,0 +1,131 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <types.h> +#include <device/device.h> +#include <console/console.h> +#if CONFIG(VGA_ROM_RUN) +#include <x86emu/x86emu.h> +#endif +#include <acpi/acpi.h> +#include <arch/interrupt.h> +#include <smbios.h> +#include <soc/gpio.h> +#include <bootstate.h> + +void mainboard_suspend_resume(void) +{ +} + +#if CONFIG(VGA_ROM_RUN) +static int int15_handler(void) +{ + int res = 1; + + printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n", + __func__, X86_AX, X86_BX, X86_CX, X86_DX); + + switch (X86_AX) { + case 0x5f34: + /* + * Set Panel Fitting Hook: + * bit 2 = Graphics Stretching + * bit 1 = Text Stretching + * bit 0 = Centering (do not set with bit1 or bit2) + * 0 = video BIOS default + */ + X86_AX = 0x005f; + X86_CX = 0x0001; + res = 1; + break; + case 0x5f35: + /* + * Boot Display Device Hook: + * bit 0 = CRT + * bit 1 = TV + * bit 2 = EFP (HDMI) + * bit 3 = LFP (eDP)* + * bit 4 = CRT2 + * bit 5 = TV2 + * bit 6 = EFP2 + * bit 7 = LFP2 + */ + X86_AX = 0x005f; + X86_CX = 0x0008; + res = 1; + break; + case 0x5f51: + /* + * Hook to select active LFP configuration: + * 00h = No LVDS, VBIOS does not enable LVDS + * 01h = Int-LVDS, LFP driven by integrated LVDS decoder + * 02h = SVDO-LVDS, LFP driven by SVDO decoder + * 03h = eDP, LFP Driven by Int-DisplayPort encoder + */ + X86_AX = 0x005f; + X86_CX = 0x0003; + res = 1; + break; + case 0x5f70: + switch ((X86_CX >> 8) & 0xff) { + case 0: + /* Get Mux */ + X86_AX = 0x005f; + X86_CX = 0x0000; + res = 1; + break; + case 1: + /* Set Mux */ + X86_AX = 0x005f; + X86_CX = 0x0000; + res = 1; + break; + case 2: + /* Get SG/Non-SG mode */ + X86_AX = 0x005f; + X86_CX = 0x0000; + res = 1; + break; + default: + /* Interrupt was not handled */ + printk(BIOS_DEBUG, + "Unknown INT15 5f70 function: 0x%02x\n", + ((X86_CX >> 8) & 0xff)); + break; + } + break; + + default: + printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_AX); + break; + } + return res; +} +#endif + +static void mainboard_init(struct device *dev) +{ + +} + +static int mainboard_smbios_data(struct device *dev, int *handle, + unsigned long *current) +{ + return 0; +} + +// mainboard_enable is executed as first thing after +// enumerate_buses(). + +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = mainboard_init; + dev->ops->get_smbios_data = mainboard_smbios_data; +#if CONFIG(VGA_ROM_RUN) + /* Install custom int15 handler for VGA OPROM */ + mainboard_interrupt_handlers(0x15, &int15_handler); +#endif +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/unk/gbyt4/romstage.c b/src/mainboard/unk/gbyt4/romstage.c new file mode 100644 index 0000000..3ca7f77 --- /dev/null +++ b/src/mainboard/unk/gbyt4/romstage.c @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <cbfs.h> +#include <console/console.h> +#include <soc/gpio.h> +#include <soc/mrc_wrapper.h> +#include <soc/romstage.h> + +//static void *get_spd_pointer(char *spd_file_content, int total_spds, int *dual) +//{ +// int ram_id = 0; +// +// /* The ram_id[2:0] pullups are too large for the default 20K +// * pulldown on the pad. Therefore, disable the internal pull resistor to +// * read high values correctly. */ +// ssus_disable_internal_pull(GPIO_SSUS_37_PAD); +// ssus_disable_internal_pull(GPIO_SSUS_38_PAD); +// ssus_disable_internal_pull(GPIO_SSUS_39_PAD); +//#ifdef GPIO_SSUS_40_PAD_USE_PULLDOWN +// /* To prevent floating pin on shipped systems. */ +// ssus_enable_internal_pull(GPIO_SSUS_40_PAD, PAD_PULL_DOWN | PAD_PU_20K); +//#elif defined(GPIO_SSUS_40_PAD) +// ssus_disable_internal_pull(GPIO_SSUS_40_PAD); +//#endif +// ram_id |= (ssus_get_gpio(GPIO_SSUS_37_PAD) << 0); +// ram_id |= (ssus_get_gpio(GPIO_SSUS_38_PAD) << 1); +// ram_id |= (ssus_get_gpio(GPIO_SSUS_39_PAD) << 2); +//#ifdef GPIO_SSUS_40_PAD +// ram_id |= (ssus_get_gpio(GPIO_SSUS_40_PAD) << 3); +//#endif +// printk(BIOS_DEBUG, "ram_id=%d, total_spds: %d\n", ram_id, total_spds); +// +// if (ram_id >= total_spds) +// return NULL; +// +// /* Single channel configs */ +// if (dual_channel_config & (1 << ram_id)) +// *dual = 1; +// +// return &spd_file_content[SPD_SIZE * ram_id]; +//} + +void mainboard_fill_mrc_params(struct mrc_params *mp) +{ + /*void *spd_content;*/ + int dual_channel = 0; + void *spd_file; + size_t spd_fsize; + + spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, + &spd_fsize); + if (!spd_file) + die("SPD data not found."); + + /*spd_content = get_spd_pointer(spd_file, spd_fsize / SPD_SIZE, + &dual_channel);*/ + + mp->mainboard.dram_type = DRAM_DDR3L; + mp->mainboard.dram_info_location = DRAM_INFO_SPD_MEM; + mp->mainboard.dram_is_slotted = 1; + + mp->mainboard.dram_data[0] = spd_file; + if (dual_channel) + mp->mainboard.dram_data[1] = spd_file; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/43087 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I99ed0c94c3255578151f940ad9b274e6f0816bfe Gerrit-Change-Number: 43087 Gerrit-PatchSet: 1 Gerrit-Owner: Máté Kukri Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

1 hour, 46 minutes

5
45
0 0

Change in coreboot[master]: drivers/ipmi: Add Supermicro OEM commands

by Patrick Rudolph (Code Review)

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38002 ) Change subject: drivers/ipmi: Add Supermicro OEM commands ...................................................................... drivers/ipmi: Add Supermicro OEM commands Add a new driver for OEM commands an select if from x11-lga1151-series. The driver communicates the BIOS version and date to the BMC using OEM commands. The command should be supported on all X11 series, but might work with older BMC, too. Tested on X11SSH-TF: The BIOS version strings are updated on boot and are visible in the BMC web UI. Change-Id: I51c22f83383affb70abb0efbcdc33ea925b5ff9f Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/drivers/ipmi/Kconfig M src/drivers/ipmi/Makefile.inc M src/drivers/ipmi/ipmi_kcs_ops.c A src/drivers/ipmi/ipmi_supermicro_oem.h A src/drivers/ipmi/supermicro_oem.c M src/mainboard/supermicro/x11-lga1151-series/Kconfig 6 files changed, 121 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/38002/1 diff --git a/src/drivers/ipmi/Kconfig b/src/drivers/ipmi/Kconfig index 0f7152d..e098bc8 100644 --- a/src/drivers/ipmi/Kconfig +++ b/src/drivers/ipmi/Kconfig @@ -8,3 +8,14 @@ depends on IPMI_KCS help KCS status and command register IO port address spacing + +config DRIVER_SUPERMICRO_IPMI_OEM + bool "Supermicro IPMI OEM BMC support" + depends on IPMI_KCS + default n + help + Tested on X11SSH only. Different BMCs might have different OEM + commands. + The following features are implemented: + * Communicates the BIOS version to the BMC + * Communicates the BIOS date to the BMC diff --git a/src/drivers/ipmi/Makefile.inc b/src/drivers/ipmi/Makefile.inc index 9d5b3d4..9fccccf 100644 --- a/src/drivers/ipmi/Makefile.inc +++ b/src/drivers/ipmi/Makefile.inc @@ -1,3 +1,4 @@ ramstage-$(CONFIG_IPMI_KCS) += ipmi_kcs.c ramstage-$(CONFIG_IPMI_KCS) += ipmi_kcs_ops.c ramstage-$(CONFIG_IPMI_KCS) += ipmi_ops.c +ramstage-$(CONFIG_DRIVER_SUPERMICRO_IPMI_OEM) += supermicro_oem.c diff --git a/src/drivers/ipmi/ipmi_kcs_ops.c b/src/drivers/ipmi/ipmi_kcs_ops.c index 5cb8995..ba8487f 100644 --- a/src/drivers/ipmi/ipmi_kcs_ops.c +++ b/src/drivers/ipmi/ipmi_kcs_ops.c @@ -34,6 +34,7 @@ #include <delay.h> #include <timer.h> #include "ipmi_kcs.h" +#include "ipmi_supermicro_oem.h" #include "chip.h" /* 4 bit encoding */ @@ -170,6 +171,12 @@ /* Don't write tables if communication failed */ dev->enabled = 0; } + + if (!dev->enabled) + return; + + if (CONFIG(DRIVER_SUPERMICRO_IPMI_OEM)) + supermicro_ipmi_oem(dev->path.pnp.port); } #if CONFIG(HAVE_ACPI_TABLES) diff --git a/src/drivers/ipmi/ipmi_supermicro_oem.h b/src/drivers/ipmi/ipmi_supermicro_oem.h new file mode 100644 index 0000000..742b97d --- /dev/null +++ b/src/drivers/ipmi/ipmi_supermicro_oem.h @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __IPMI_SUPERMICRO_OEM_H +#define __IPMI_SUPERMICRO_OEM_H + +void supermicro_ipmi_oem(const uint16_t kcs_port); + +#endif /* __IPMI_SUPERMICRO_OEM_H */ diff --git a/src/drivers/ipmi/supermicro_oem.c b/src/drivers/ipmi/supermicro_oem.c new file mode 100644 index 0000000..ea01fef --- /dev/null +++ b/src/drivers/ipmi/supermicro_oem.c @@ -0,0 +1,81 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <types.h> + +#include <console/console.h> +#include <drivers/ipmi/ipmi_kcs.h> +#include <string.h> +#include <build.h> +#include "ipmi_supermicro_oem.h" + +#define IPMI_NETFN_OEM 0x30 +#define IPMI_LUN0_AC_SET_BIOS_VER 0x100 +#define IPMI_LUN0_AC_SET_BIOS_DATE 0x101 +#define IPMI_LUN0_SET_BIOS_STRING 0xac + +struct ipmi_oem_set_bios_str { + uint16_t ver; + char str[16]; // NULL terminated string +} __packed; + +static void set_coreboot_ver(const uint16_t kcs_port) +{ + const char *coreboot_ver = COREBOOT_VERSION; + struct ipmi_oem_set_bios_str bios_ver; + struct ipmi_rsp rsp; + int ret; + size_t i; + + /* Only 8 charactars are visible in UI. Cut of on first dash */ + for (i = 0; i < 15; i++) { + if (coreboot_ver[i] == '-') + break; + bios_ver.str[i] = coreboot_ver[i]; + } + bios_ver.str[i] = 0; + bios_ver.ver = IPMI_LUN0_AC_SET_BIOS_VER; + + ret = ipmi_kcs_message(kcs_port, IPMI_NETFN_OEM, 0, IPMI_LUN0_SET_BIOS_STRING, + (const unsigned char *) &bios_ver, sizeof(bios_ver), + (unsigned char *) &rsp, sizeof(rsp)); + if (ret < sizeof(rsp) || rsp.completion_code) { + printk(BIOS_ERR, "BMC_IPMI: %s command failed (ret=%d resp=0x%x)\n", + __func__, ret, rsp.completion_code); + } +} + +static void set_coreboot_date(const uint16_t kcs_port) +{ + struct ipmi_oem_set_bios_str bios_ver; + struct ipmi_rsp rsp; + int ret; + + strncpy(bios_ver.str, COREBOOT_DMI_DATE, 15); + bios_ver.str[15] = 0; + bios_ver.ver = IPMI_LUN0_AC_SET_BIOS_DATE; + + ret = ipmi_kcs_message(kcs_port, IPMI_NETFN_OEM, 0, IPMI_LUN0_SET_BIOS_STRING, + (const unsigned char *) &bios_ver, sizeof(bios_ver), + (unsigned char *) &rsp, sizeof(rsp)); + if (ret < sizeof(rsp) || rsp.completion_code) { + printk(BIOS_ERR, "BMC_IPMI: %s command failed (ret=%d resp=0x%x)\n", + __func__, ret, rsp.completion_code); + } +} + +void supermicro_ipmi_oem(const uint16_t kcs_port) +{ + set_coreboot_ver(kcs_port); + set_coreboot_date(kcs_port); +} diff --git a/src/mainboard/supermicro/x11-lga1151-series/Kconfig b/src/mainboard/supermicro/x11-lga1151-series/Kconfig index 5a99f7a..53ae398 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/Kconfig +++ b/src/mainboard/supermicro/x11-lga1151-series/Kconfig @@ -12,6 +12,7 @@ select SUPERIO_ASPEED_AST2400 select GENERATE_SMBIOS_TABLES select IPMI_KCS + select DRIVER_SUPERMICRO_IPMI_OEM select MAINBOARD_NO_FSP_GOP select SUPERIO_ASPEED_HAS_UART_DELAY_WORKAROUND select NO_FADT_8042 -- To view, visit https://review.coreboot.org/c/coreboot/+/38002 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51c22f83383affb70abb0efbcdc33ea925b5ff9f Gerrit-Change-Number: 38002 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

1 hour, 54 minutes

9
16
0 0

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit