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Change in coreboot[master]: mb/google/brya: Initiate peripheral buses

by EricR Lai (Code Review)

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49007 ) Change subject: mb/google/brya: Initiate peripheral buses ...................................................................... mb/google/brya: Initiate peripheral buses Initiate peripheral buses based on latest schematic. BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: Ibf48aceca7ac8774b0353e31bd81e1880c4066ea --- M src/mainboard/google/brya/variants/baseboard/devicetree.cb 1 file changed, 107 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/49007/1 diff --git a/src/mainboard/google/brya/variants/baseboard/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/devicetree.cb index 479a7ee..96e0a9d 100644 --- a/src/mainboard/google/brya/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/devicetree.cb @@ -3,6 +3,113 @@ device lapic 0 on end end + register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # USB2_C0 + register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # USB2_C1 + register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # USB2_C2 + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera + register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0 + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port A0 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN + + # Enable WLAN PCIE 5 using clk 2 + register "pch_pcie_rp[PCH_RP(5)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_ENABLED, + }" + + # Enable WWAN PCIE 6 using clk 5 + register "pch_pcie_rp[PCH_RP(6)]" = "{ + .clk_src = 5, + .clk_req = 5, + .flags = PCIE_RP_ENABLED, + }" + + # Enable SD Card PCIE 8 using clk 3 + register "pch_pcie_rp[PCH_RP(8)]" = "{ + .clk_src = 3, + .clk_req = 3, + .flags = PCIE_RP_ENABLED | PCIE_RP_HOTPLUG_ENABLED | PCIE_RP_LTR_ENABLED, + }" + + # Enable NVMe PCIE 9 using clk 1 + register "pch_pcie_rp[PCH_RP(9)]" = "{ + .clk_src = 1, + .clk_req = 1, + .flags = PCIE_RP_ENABLED | PCIE_RP_LTR_ENABLED, + }" + + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + + register "SerialIoGSpiMode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI1] = PchSerialIoPci, + }" + + register "SerialIoGSpiCsMode" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 1, + }" + + register "SerialIoGSpiCsState" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 1, + }" + + register "SerialIoUartMode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoPci, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | + #| GSPI1 | Fingerprint MCU | + #| I2C0 | Audio | + #| I2C1 | Touchscreen | + #| I2C2 | SAR0 | + #| I2C3 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| I2C4 | CAM | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .early_init = 1, + .speed = I2C_SPEED_FAST, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, + }" + device domain 0 on device ref igpu on end device ref dtt on end @@ -30,7 +137,6 @@ device ref pcie_rp8 on end #PCIE8 SD card device ref pcie_rp9 on end #PCIE9-12 SSD device ref uart0 on end - device ref gspi0 on end device ref gspi1 on end device ref pch_espi on chip ec/google/chromeec -- To view, visit https://review.coreboot.org/c/coreboot/+/49007 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf48aceca7ac8774b0353e31bd81e1880c4066ea Gerrit-Change-Number: 49007 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

1 hour, 5 minutes

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Change in coreboot[master]: WIP: soc/mediatek/mt8192: add mt6359p efuse setting

by hsin-hsiung wang (Code Review)

hsin-hsiung wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49006 ) Change subject: WIP: soc/mediatek/mt8192: add mt6359p efuse setting ...................................................................... WIP: soc/mediatek/mt8192: add mt6359p efuse setting Some efuse settings would not be applied automatically, so we need set the settings manually. BUG=b:172636735 BRANCH=none TEST=boot asurada correctly Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang(a)mediatek.com> Change-Id: Ideb862c3cb0f1fee183804aed74fcf141bf1f5df --- M src/soc/mediatek/mt8192/include/soc/mt6359p.h M src/soc/mediatek/mt8192/mt6359p.c 2 files changed, 101 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/49006/1 diff --git a/src/soc/mediatek/mt8192/include/soc/mt6359p.h b/src/soc/mediatek/mt8192/include/soc/mt6359p.h index b90e0f5..1d01d71 100644 --- a/src/soc/mediatek/mt8192/include/soc/mt6359p.h +++ b/src/soc/mediatek/mt8192/include/soc/mt6359p.h @@ -8,8 +8,15 @@ enum { PMIC_HWCID = 0x0008, PMIC_SWCID = 0x000a, + PMIC_TOP_CKPDN_CON0 = 0x010c, + PMIC_TOP_CKHWEN_CON0 = 0x012a, PMIC_TOP_RST_MISC_SET = 0x014c, PMIC_TOP_RST_MISC_CLR = 0x014e, + PMIC_OTP_CON0 = 0x038a, + PMIC_OTP_CON8 = 0x039a, + PMIC_OTP_CON11 = 0x03a0, + PMIC_OTP_CON12 = 0x03a2, + PMIC_OTP_CON13 = 0x03a4, PMIC_PWRHOLD = 0x0a08, PMIC_VGPU11_DBG0 = 0x15a6, PMIC_VGPU11_ELR0 = 0x15b4, @@ -30,6 +37,13 @@ unsigned char shift; }; +struct pmic_efuse { + unsigned short efuse_bit; + unsigned short addr; + unsigned short mask; + unsigned char shift; +}; + enum { MT6359P_GPU11 = 0, MT6359P_SRAM_PROC1, @@ -40,6 +54,8 @@ #define VM18_VOL_REG_SHIFT 8 #define VM18_VOL_OFFSET 600 +#define EFUSE_WAIT_US 5000 +#define EFUSE_BUSY 1 void mt6359p_init(void); void mt6359p_romstage_init(void); void mt6359p_buck_set_voltage(u32 buck_id, u32 buck_uv); diff --git a/src/soc/mediatek/mt8192/mt6359p.c b/src/soc/mediatek/mt8192/mt6359p.c index 18513a0..908ce30 100644 --- a/src/soc/mediatek/mt8192/mt6359p.c +++ b/src/soc/mediatek/mt8192/mt6359p.c @@ -5,6 +5,7 @@ #include <delay.h> #include <soc/pmif.h> #include <soc/mt6359p.h> +#include <timer.h> static const struct pmic_setting key_protect_setting[] = { {0x3A8, 0x9CA6, 0xFFFF, 0}, @@ -287,6 +288,32 @@ {0x1d14, 0x1, 0x1, 0x2}, }; +static const struct pmic_efuse efuse_setting[] = { + {79, 0xa0e, 0x1, 0xf}, + {886, 0x198c, 0xf, 0x8}, + {890, 0x198e, 0xf, 0x0}, + {902, 0x1998, 0xf, 0x8}, + {906, 0x1998, 0xf, 0xc}, + {918, 0x19a2, 0xf, 0x8}, + {922, 0x19a2, 0xf, 0xc}, + {1014, 0x19ae, 0xf, 0x7}, + {1018, 0x19ae, 0xf, 0xb}, + {1158, 0x1a0a, 0xf, 0x7}, + {1162, 0x1a0a, 0xf, 0xb}, + {1206, 0x1a16, 0xf, 0x7}, + {1210, 0x1a16, 0xf, 0xb}, + {1254, 0x1a22, 0xf, 0x7}, + {1258, 0x1a22, 0xf, 0xb}, + {1304, 0x1a2c, 0x7, 0x4}, + {1307, 0x1a32, 0x7, 0x8}, + {1336, 0x1a34, 0x7, 0x4}, + {1339, 0x1a3a, 0x7, 0x8}, + {1683, 0x79c, 0xf, 0x4}, + {1688, 0xc8a, 0x1, 0x3}, + {1689, 0xc88, 0x1, 0x3}, + {1690, 0xc88, 0x7, 0x0}, +}; + static struct pmif *pmif_arb = NULL; static void mt6359p_write(u32 reg, u32 data) { @@ -318,6 +345,52 @@ mt6359p_write_field(PMIC_TOP_RST_MISC_SET, 0x01, 0xFFFF, 0); } +static int check_idle(u32 addr, u32 mask) +{ + u32 reg_rdata; + struct stopwatch sw; + + stopwatch_init_usecs_expire(&sw, EFUSE_WAIT_US); + do { + reg_rdata = mt6359p_read_field(addr, mask, 0); + if (stopwatch_expired(&sw)) + return -1; + } while (reg_rdata); + + return 0; +} + +static u32 pmic_read_efuse(u32 efuse_bit, u32 mask) +{ + u32 efuse_data = 0; + int ret, index, shift; + + index = efuse_bit / 16; + shift = efuse_bit % 16; + mt6359p_write_field(PMIC_TOP_CKHWEN_CON0, 0, 0x1, 2); + mt6359p_write_field(PMIC_TOP_CKPDN_CON0, 0, 0x1, 4); + mt6359p_write_field(PMIC_OTP_CON11, 1, 0x1, 0); + mt6359p_write_field(PMIC_OTP_CON0, index * 2, 0xFF, 0); + if (mt6359p_read_field(PMIC_OTP_CON8, 1, 0)) + mt6359p_write_field(PMIC_OTP_CON8, 0, 1, 0); + else + mt6359p_write_field(PMIC_OTP_CON8, 1, 1, 0); + + udelay(300); + ret = check_idle(PMIC_OTP_CON13, EFUSE_BUSY); + if (ret) + die("ERROR: Read efuse data timeout"); + udelay(100); + + efuse_data = mt6359p_read_field(PMIC_OTP_CON12, 0xFFFF, 0); + + mt6359p_write_field(PMIC_TOP_CKHWEN_CON0, 1, 0x1, 2); + mt6359p_write_field(PMIC_TOP_CKPDN_CON0, 1, 0x1, 4); + + efuse_data = (efuse_data >> shift) & mask; + return efuse_data; +} + static void pmic_protect_key_set(bool lock) { if (lock) { @@ -343,6 +416,17 @@ lp_setting[i].mask, lp_setting[i].shift); } +static void pmic_efuse_setting(void) +{ + u32 efuse_data; + + for (int i = 0; i < ARRAY_SIZE(efuse_setting); i++) { + efuse_data = pmic_read_efuse(efuse_setting[i].efuse_bit, efuse_setting[i].mask); + mt6359p_write_field(efuse_setting[i].addr, efuse_data, + efuse_setting[i].mask, efuse_setting[i].shift); + } +} + static void pmic_wk_vs2_voter_setting(void) { /* @@ -463,6 +547,7 @@ pmic_protect_key_set(false); pmic_init_setting(); pmic_lp_setting(); + pmic_efuse_setting(); pmic_protect_key_set(true); pmic_wk_vs2_voter_setting(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/49006 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ideb862c3cb0f1fee183804aed74fcf141bf1f5df Gerrit-Change-Number: 49006 Gerrit-PatchSet: 1 Gerrit-Owner: hsin-hsiung wang <hsin-hsiung.wang(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

1 hour, 11 minutes

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Change in coreboot[master]: soc/amd/picasso/Kconfig: drop EHCI_BAR

by Kyösti Mälkki (Code Review)

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49729 ) Change subject: soc/amd/picasso/Kconfig: drop EHCI_BAR ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/49729 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e904c160c68805a8606a8b2d1ab4fb6172066e7 Gerrit-Change-Number: 49729 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 20 Jan 2021 03:46:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 hour, 12 minutes

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Change in coreboot[master]: soc/amd/picasso: Use option instead of hardcode to location UCODE

by Bao Zheng (Code Review)

Attention is currently required from: Bao Zheng, Jason Glenesk, Martin Roth, Marshall Dawson, Zheng Bao, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Patrick Georgi, Martin Roth, Marshall Dawson, Zheng Bao, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/49734 to look at the new patch set (#2). Change subject: soc/amd/picasso: Use option instead of hardcode to location UCODE ...................................................................... soc/amd/picasso: Use option instead of hardcode to location UCODE Change-Id: Iae3d159aa5413a416c54935ab7a809d0f4ff776f Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/soc/amd/picasso/Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/49734/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/49734 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae3d159aa5413a416c54935ab7a809d0f4ff776f Gerrit-Change-Number: 49734 Gerrit-PatchSet: 2 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

1 hour, 30 minutes

1
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Change in coreboot[master]: ec/google/chromeec: Provide EC access for Retimer firmware update

by Duncan Laurie (Code Review)

Attention is currently required from: John Zhao, Tim Wawrzynczak, Brandon Breitenstein, Rajmohan Mani. Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49257 ) Change subject: ec/google/chromeec: Provide EC access for Retimer firmware update ...................................................................... Patch Set 5: (1 comment) File src/ec/google/chromeec/ec_acpi.c: https://review.coreboot.org/c/coreboot/+/49257/comment/a82d4333_1394ff1c PS4, Line 242: \\_SB_.PCI0.LPCB.EC0_. > oh that's right, there is no struct/device in the hierarchy right now which will resolve to an ACPI […] Ah well, sorry for the diversion. I'll add cleaning up the EC ACPI path to the endless todo list.. -- To view, visit https://review.coreboot.org/c/coreboot/+/49257 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3817d93cfdeedf15825dab6c537b151fd063338b Gerrit-Change-Number: 49257 Gerrit-PatchSet: 5 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Rajmohan Mani <rajmohan.mani(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: John Zhao <john.zhao(a)intel.corp-partner.google.com> Gerrit-Attention: John Zhao <john.zhao(a)intel.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: John Zhao <john.zhao(a)intel.com> Gerrit-Attention: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Attention: Rajmohan Mani <rajmohan.mani(a)intel.com> Gerrit-Comment-Date: Wed, 20 Jan 2021 03:12:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: John Zhao <john.zhao(a)intel.corp-partner.google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: John Zhao <john.zhao(a)intel.com> Comment-In-Reply-To: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: comment

1 hour, 46 minutes

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Change in coreboot[master]: WIP: drivers/intel/usb4/mux_retimer: Enable retimer FW upgrade mux in...

by Brandon Breitenstein (Code Review)

Brandon Breitenstein has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48630 ) Change subject: WIP: drivers/intel/usb4/mux_retimer: Enable retimer FW upgrade mux interaction ...................................................................... WIP: drivers/intel/usb4/mux_retimer: Enable retimer FW upgrade mux interaction In order to update the BB retimers for usb4/tbt they need to be turned on and in a specific mode. This DSM allows for the use of an EC RAM Byte to get the current state of each port and wether or not it has a retimer. It also allows Kernel to issue a state for the retimer to be put into for firmware updates. Change-Id: I768cfb56790049c231173b0ea0f8e08fe6b64b93 Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> --- A src/drivers/intel/usb4/mux_retimer/Kconfig A src/drivers/intel/usb4/mux_retimer/Makefile.inc A src/drivers/intel/usb4/mux_retimer/mux_retimer.c M src/ec/google/chromeec/acpi/emem.asl M src/mainboard/google/volteer/Kconfig 5 files changed, 119 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/48630/1 diff --git a/src/drivers/intel/usb4/mux_retimer/Kconfig b/src/drivers/intel/usb4/mux_retimer/Kconfig new file mode 100644 index 0000000..d5dc3f9 --- /dev/null +++ b/src/drivers/intel/usb4/mux_retimer/Kconfig @@ -0,0 +1,6 @@ +config DRIVERS_INTEL_USB4_MUX_RETIMER + bool + depends on HAVE_ACPI_TABLES + help + The mux retimer driver is required when synchronization is needed + between the EC and Kernel on the retimer upgrade path for BB retimer diff --git a/src/drivers/intel/usb4/mux_retimer/Makefile.inc b/src/drivers/intel/usb4/mux_retimer/Makefile.inc new file mode 100644 index 0000000..bca87fc --- /dev/null +++ b/src/drivers/intel/usb4/mux_retimer/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_INTEL_USB4_MUX_RETIMER) += mux_retimer.c diff --git a/src/drivers/intel/usb4/mux_retimer/mux_retimer.c b/src/drivers/intel/usb4/mux_retimer/mux_retimer.c new file mode 100644 index 0000000..de538e2 --- /dev/null +++ b/src/drivers/intel/usb4/mux_retimer/mux_retimer.c @@ -0,0 +1,110 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpigen.h> +#include <acpi/acpi_device.h> +#include <console/console.h> +#include <device/device.h> +#include <device/path.h> +#include <gpio.h> +#include <string.h> + +/* Unique ID for the Mux Retimer Upgrade _DSM. */ +#define INTEL_USB4_MUX_RETIMER_DSM_UUID "5e7fb958-b2c5-49dc-90b9-f95b1275e824" + +/* + * Arg0: UUID + * Arg1: Revision ID (set to 1) + * Arg2: Function Index + * 0: Query command implemented + * 1: Query current MUX state and ports with retimers + * 2: Set MUX state for retimer upgrade + * Arg3: A package containing parameters for the function specified by the UUID + * revision ID and function index. + * Function 2: Value to set EC RAM + */ + +static void usb4_mux_cb_standard_query(void *arg) +{ + /* + * ToInteger (Arg1, Local2) + * If (Local2 == 1) { + * Return(Buffer() {0x07}) + * } + * Return (Buffer() {0x01}) + */ + acpigen_write_to_integer(ARG1_OP, LOCAL2_OP); + + /* Revision 1 supports 2 Functions beyond the standard query */ + acpigen_write_if_lequal_op_int(LOCAL2_OP, 1); + acpigen_write_return_singleton_buffer(0x07); + acpigen_pop_len(); /* If */ + + /* Other revisions support no additional functions */ + acpigen_write_return_singleton_buffer(0); +} + +static void usb4_mux_cb_get_mux_state(void *arg) +{ + /* + * // Read Mux Retimer info from EC RAM + * Return RFWU + */ + acpigen_write_return_namestr("RFWU"); +} + +static void usb4_mux_cb_set_mux_state(void *arg) +{ + /* + * // Get argument for on/off from Arg3[0] + * Local0 = DeRefOf (Arg3[0]) + */ + acpigen_get_package_op_element(ARG3_OP, 0, LOCAL0_OP); + + /* + * // write the EC RAM for Retimer Upgrade + * RFWU = LOCAL0 + */ + acpigen_write_name_byte("RFWU", LOCAL0_OP); + + /* Return (Zero) */ + acpigen_write_return_integer(0); +} + +static void (*usb4_mux_callbacks[3])(void *) = { + usb4_mux_cb_standard_query, /* Function 0 */ + usb4_mux_cb_get_mux_state, /* Function 1 */ + usb4_mux_cb_set_mux_state, /* Function 2 */ +}; + +static void usb4_mux_fill_ssdt(const struct device *dev) +{ + const char *scope = acpi_device_scope(dev); + + if (!scope) + return; + + /* Write the _DSM that toggles ack with provided GPIO. */ + acpigen_write_scope(scope); + acpigen_write_dsm(INTEL_USB4_MUX_RETIMER_DSM_UUID, usb4_mux_callbacks, + ARRAY_SIZE(usb4_mux_callbacks), NULL); + acpigen_pop_len(); /* Scope */ + + printk(BIOS_INFO, "%s: %s at %s\n", acpi_device_path(dev), dev->chip_ops->name, + dev_path(dev)); +} + +static struct device_operations usb4_mux_dev_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .acpi_fill_ssdt = usb4_mux_fill_ssdt, +}; + +static void usb4_mux_retimer_enable(struct device *dev) +{ + dev->ops = &usb4_mux_dev_ops; +} + +struct chip_operations drivers_intel_usb4_mux_ops = { + CHIP_NAME("Intel USB4 Mux Retimer Upgrade") + .enable_dev = usb4_mux_retimer_enable +}; diff --git a/src/ec/google/chromeec/acpi/emem.asl b/src/ec/google/chromeec/acpi/emem.asl index 2a556ed..ee50796 100644 --- a/src/ec/google/chromeec/acpi/emem.asl +++ b/src/ec/google/chromeec/acpi/emem.asl @@ -18,7 +18,7 @@ FAN0, 16, // Fan Speed 0 Offset (0x24), BTVR, 8, // Battery structure version -Offset (0x30), +RFWU, 8, // Retimer FW Update LIDS, 1, // Lid Switch State PBTN, 1, // Power Button Pressed WPDI, 1, // Write Protect Disabled diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index c776ba1..5e185a7 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -12,6 +12,7 @@ select DRIVERS_INTEL_USB4_RETIMER select DRIVERS_I2C_MAX98373 select DRIVERS_INTEL_SOUNDWIRE + select DRIVERS_INTEL_USB4_MUX_RETIMER select DRIVERS_SPI_ACPI select DRIVERS_SOUNDWIRE_ALC5682 select DRIVERS_SOUNDWIRE_MAX98373 -- To view, visit https://review.coreboot.org/c/coreboot/+/48630 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I768cfb56790049c231173b0ea0f8e08fe6b64b93 Gerrit-Change-Number: 48630 Gerrit-PatchSet: 1 Gerrit-Owner: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-MessageType: newchange

1 hour, 47 minutes

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Change in coreboot[master]: soc/amd/picasso: Use option instead of hardcode to location UCODE

by Bao Zheng (Code Review)

Attention is currently required from: Zheng Bao. Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/49734 to review the following change. Change subject: soc/amd/picasso: Use option instead of hardcode to location UCODE ...................................................................... soc/amd/picasso: Use option instead of hardcode to location UCODE Change-Id: Iae3d159aa5413a416c54935ab7a809d0f4ff776f Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/soc/amd/picasso/Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/49734/1 diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index a0f3ec4..acf4e93 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -305,6 +305,6 @@ $(call strip_quotes,$(CONFIG_FSP_M_CBFS))-options := -b $(CONFIG_FSP_M_ADDR) -cpu_microcode_bins += $(wildcard 3rdparty/amd_blobs/picasso/PSP/UcodePatch_*.bin) +cpu_microcode_bins += $(wildcard {FIRMWARE_LOCATION}/UcodePatch_*.bin) endif # ($(CONFIG_SOC_AMD_PICASSO),y) -- To view, visit https://review.coreboot.org/c/coreboot/+/49734 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae3d159aa5413a416c54935ab7a809d0f4ff776f Gerrit-Change-Number: 49734 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Attention: Zheng Bao Gerrit-MessageType: newchange

1 hour, 51 minutes

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Change in coreboot[master]: mb/google/dedede/var/drawcia: Add support to handle pen detection

by Chen Wisley (Code Review)

Attention is currently required from: Martin Roth, Henry Sun, Evan Green. Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Henry Sun, Evan Green, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/49469 to look at the new patch set (#7). Change subject: mb/google/dedede/var/drawcia: Add support to handle pen detection ...................................................................... mb/google/dedede/var/drawcia: Add support to handle pen detection Drawlat/Drawman/Drawcia share the same AP firmware, and only Drawcia is convertible. So, use tablet mode bit of fw config to override GPP_C12. BUG=b:177618684 TEST=emerge-dedede coreboot, check evtest if SW_PEN_INSERTED event (value:1/0) when insert/eject pen, and eject pen to wake system from s0ix Signed-off-by: Wisley Chen <wisley.chen(a)quantatw.com> Change-Id: I503873afb48384168dcd8a822c7246655898356e --- M src/mainboard/google/dedede/variants/drawcia/Makefile.inc A src/mainboard/google/dedede/variants/drawcia/gpio.c M src/mainboard/google/dedede/variants/drawcia/overridetree.cb 3 files changed, 32 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/49469/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/49469 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I503873afb48384168dcd8a822c7246655898356e Gerrit-Change-Number: 49469 Gerrit-PatchSet: 7 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Evan Green <evgreen(a)chromium.org> Gerrit-MessageType: newpatchset

1 hour, 59 minutes

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Change in coreboot[master]: mb/google/dedede/var/drawcia: Add support to handle pen detection

by build bot (Jenkins) (Code Review)

Attention is currently required from: Martin Roth, Henry Sun, Evan Green. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49469 ) Change subject: mb/google/dedede/var/drawcia: Add support to handle pen detection ...................................................................... Patch Set 6: (2 comments) File src/mainboard/google/dedede/variants/drawcia/gpio.c: https://review.coreboot.org/c/coreboot/+/49469/comment/1918cacc_4057c800 PS6, Line 17: if (fw_config_probe(FW_CONFIG(TABLETMODE, TABLETMODE_ENABLED))){ space required before the open brace '{' https://review.coreboot.org/c/coreboot/+/49469/comment/66a02546_f79c1de8 PS6, Line 17: if (fw_config_probe(FW_CONFIG(TABLETMODE, TABLETMODE_ENABLED))){ braces {} are not necessary for single statement blocks -- To view, visit https://review.coreboot.org/c/coreboot/+/49469 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I503873afb48384168dcd8a822c7246655898356e Gerrit-Change-Number: 49469 Gerrit-PatchSet: 6 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Evan Green <evgreen(a)chromium.org> Gerrit-Comment-Date: Wed, 20 Jan 2021 02:54:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

2 hours, 4 minutes

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Change in coreboot[master]: mb/google/dedede/var/drawcia: Add support to handle pen detection

by Chen Wisley (Code Review)

Attention is currently required from: Martin Roth, Henry Sun, Evan Green. Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Henry Sun, Evan Green, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/49469 to look at the new patch set (#6). Change subject: mb/google/dedede/var/drawcia: Add support to handle pen detection ...................................................................... mb/google/dedede/var/drawcia: Add support to handle pen detection Drawlat/Drawman/Drawcia share the same AP firmware, and only Drawcia is convertible. So, use tablet mode bit of fw config to override GPP_C12. BUG=b:177618684 TEST=emerge-dedede coreboot, check evtest if SW_PEN_INSERTED event (value:1/0) when insert/eject pen, and eject pen to wake system from s0ix Signed-off-by: Wisley Chen <wisley.chen(a)quantatw.com> Change-Id: I503873afb48384168dcd8a822c7246655898356e --- M src/mainboard/google/dedede/variants/drawcia/Makefile.inc A src/mainboard/google/dedede/variants/drawcia/gpio.c M src/mainboard/google/dedede/variants/drawcia/overridetree.cb 3 files changed, 34 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/49469/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/49469 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I503873afb48384168dcd8a822c7246655898356e Gerrit-Change-Number: 49469 Gerrit-PatchSet: 6 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Evan Green <evgreen(a)chromium.org> Gerrit-MessageType: newpatchset

2 hours, 11 minutes

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