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[S] Change in coreboot[master]: soc/intel/meteorlake: Add timestamp for cse_fw_sync
by Subrata Banik (Code Review) 05 Dec '22

05 Dec '22

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/70172 ) ( 10 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/meteorlake: Add timestamp for cse_fw_sync ...................................................................... soc/intel/meteorlake: Add timestamp for cse_fw_sync The patch adds timestamp around cse_fw_sync(). BUG=none TEST=Verified on rex, cbmem -t: 948:starting CSE firmware sync 1,340,551 (50,657) 949:finished CSE firmware sync 1,379,348 (38,797) Port of 'commit b647e35119c1 ("soc/intel/alderlake: Add timestamp for cse_fw_sync")' Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> Change-Id: I6cfbf84018e312fbf9482f0fba05b444603cd4b9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70172 Reviewed-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/meteorlake/romstage/romstage.c 1 file changed, 30 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Sridhar Siricilla: Looks good to me, approved Kapil Porwal: Looks good to me, approved diff --git a/src/soc/intel/meteorlake/romstage/romstage.c b/src/soc/intel/meteorlake/romstage/romstage.c index bac3caf..ba0079c 100644 --- a/src/soc/intel/meteorlake/romstage/romstage.c +++ b/src/soc/intel/meteorlake/romstage/romstage.c @@ -15,6 +15,7 @@ #include <soc/pm.h> #include <soc/romstage.h> #include <soc/soc_chip.h> +#include <timestamp.h> #include <string.h> #define FSP_SMBIOS_MEMORY_INFO_GUID \ @@ -130,8 +131,11 @@ s3wake = pmc_fill_power_state(ps) == ACPI_S3; if (!s3wake) { - if (CONFIG(SOC_INTEL_CSE_LITE_SKU)) + if (CONFIG(SOC_INTEL_CSE_LITE_SKU)) { + timestamp_add_now(TS_CSE_FW_SYNC_START); cse_fw_sync(); + timestamp_add_now(TS_CSE_FW_SYNC_END); + } } /* -- To view, visit https://review.coreboot.org/c/coreboot/+/70172 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6cfbf84018e312fbf9482f0fba05b444603cd4b9 Gerrit-Change-Number: 70172 Gerrit-PatchSet: 12 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/alderlake: make SOC_INTEL_CSE_SEND_EOP_EARLY per-board conf...
by Subrata Banik (Code Review) 05 Dec '22

05 Dec '22

Attention is currently required from: Tarun Tuli, Michał Kopeć. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69953 ) Change subject: soc/intel/alderlake: make SOC_INTEL_CSE_SEND_EOP_EARLY per-board configurable ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69953 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7febf7c029e7eac94052cc3a8142949d6813c1bc Gerrit-Change-Number: 69953 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Comment-Date: Mon, 05 Dec 2022 11:22:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: Add basic support for Raptor Lake S CPUs on Alder Lake PCH (#640555 R...
by Michał Żygowski (Code Review) 05 Dec '22

05 Dec '22

Attention is currently required from: Bora Guvendik, Subrata Banik, Name of user not set #1004406, Michal Zygowski. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69798 ) Change subject: Add basic support for Raptor Lake S CPUs on Alder Lake PCH (#640555 Rev. 2.2) ...................................................................... Patch Set 4: (8 comments) File src/include/cpu/intel/cpu_ids.h: https://review.coreboot.org/c/coreboot/+/69798/comment/74e390c8_611d09f6 PS3, Line 67: #define CPUID_RAPTORLAKE_S_S0 0xb0671 > CPUID_RAPTORLAKE_S_B0 it is B0 stepping according to the datasheet. And if so, I would also add: […] Ack File src/soc/intel/alderlake/bootblock/report_platform.c: https://review.coreboot.org/c/coreboot/+/69798/comment/f8562f72_31e026ac PS3, Line 37: { CPUID_RAPTORLAKE_S_S0, "Raptorlake-S S0 Platform" }, > { CPUID_RAPTORLAKE_S_B0, "Raptorlake-S B0 Platform" }, Ack https://review.coreboot.org/c/coreboot/+/69798/comment/75ca1d29_f01e2575 PS3, Line 207: { PCI_DID_INTEL_RPL_S_GT1, "Raptorlake S GT1(32EU)" }, : { PCI_DID_INTEL_RPL_S_GT2, "Raptorlake S GT2(24EU)" }, : { PCI_DID_INTEL_RPL_S_GT3, "Raptorlake S GT3(16EU)" }, > Let's stick with previous convention and omit execution units. Ack File src/soc/intel/alderlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/69798/comment/4cfd96d1_0c7635cd PS3, Line 544: return ICC_MAX_ADL_S; > Isn't it 36A for RPL-S? Ack File src/soc/intel/alderlake/include/soc/cpu.h: https://review.coreboot.org/c/coreboot/+/69798/comment/cf4d391a_0fb41070 PS3, Line 28: RPL_S, > Please add it as a last item in the enum Ack File src/soc/intel/alderlake/vr_config.c: https://review.coreboot.org/c/coreboot/+/69798/comment/bb2ce447_8d9c3dd3 PS3, Line 174: { PCI_DID_INTEL_RPL_S_ID_1, 125, VR_CFG_ALL_DOMAINS_ICC(280, 30) }, : { PCI_DID_INTEL_RPL_S_ID_2, 125, VR_CFG_ALL_DOMAINS_ICC(280, 30) }, > RPL-S 8+16 and 8+8 have 307A ICCmax for IA domain. Ack https://review.coreboot.org/c/coreboot/+/69798/comment/36313269_16e8eb8a PS3, Line 176: { PCI_DID_INTEL_RPL_S_ID_3, 125, VR_CFG_ALL_DOMAINS_ICC(280, 30) }, > RPL-S 6+8 has 200A ICCmax for IA domain Ack File src/soc/intel/common/block/cpu/mp_init.c: https://review.coreboot.org/c/coreboot/+/69798/comment/2ff1ce4a_577ba1a2 PS3, Line 84: { X86_VENDOR_INTEL, CPUID_RAPTORLAKE_S_S0 }, > { X86_VENDOR_INTEL, CPUID_RAPTORLAKE_S_B0 }, Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/69798 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I767dd08a169a6af59188d9ecd73520b916f69155 Gerrit-Change-Number: 69798 Gerrit-PatchSet: 4 Gerrit-Owner: Name of user not set #1004406 Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Michal Zygowski <miczyg94(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Name of user not set #1004406 Gerrit-Attention: Michal Zygowski <miczyg94(a)gmail.com> Gerrit-Comment-Date: Mon, 05 Dec 2022 11:17:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: security/tpm: replace CONFIG(TPMx) checks with runtime check
by Michał Żygowski (Code Review) 05 Dec '22

05 Dec '22

Attention is currently required from: Lance Zhao, Christian Walter, Tim Wawrzynczak, Julius Werner, Krystian Hebel, Yu-Ping Wu, Sergii Dmytruk. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69161 ) Change subject: security/tpm: replace CONFIG(TPMx) checks with runtime check ...................................................................... Patch Set 10: (1 comment) File src/drivers/crb/tis.c: https://review.coreboot.org/c/coreboot/+/69161/comment/2165ad1e_b40fec9e PS6, Line 144: if (tlcl_get_family() == TPM_1) : return get_smbios_data(dev, handle, current); > It was done this way, because the function is invoked like: […] CRB is always TPM 2.0 AFAIK, thus TPM_1 is not a valid family to run this function. Thus we should return 0 and leave handle and current unmodfied. -- To view, visit https://review.coreboot.org/c/coreboot/+/69161 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9cc25aad8d1d7bfad12b7a92059b1b3641bbfa9 Gerrit-Change-Number: 69161 Gerrit-PatchSet: 10 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Comment-Date: Mon, 05 Dec 2022 11:14:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: util/amdfwtool: Deal with psp position in flash offset directly
by Christopher Meis (Code Review) 05 Dec '22

05 Dec '22

Attention is currently required from: Bao Zheng, Jason Glenesk, Raul Rangel, Jason Nien, Matt DeVillier, Arthur Heymans, Martin Roth, Fred Reitberger, Marvin Drees, Karthik Ramasubramanian, Felix Held. Christopher Meis has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69852 ) Change subject: util/amdfwtool: Deal with psp position in flash offset directly ...................................................................... Patch Set 4: (1 comment) File src/soc/amd/common/Makefile.inc: https://review.coreboot.org/c/coreboot/+/69852/comment/07d626a7_e428dc82 PS4, Line 25: $(call int-subtract, 0xffffffff $(CONFIG_ROM_SIZE)) 1 $(CONFIG_AMD_FWM_POSITION)) > This also is not exactly correct. > > When looking for the EFS location, the PSP only cares about flash offsets. > In EFT, again, addresses to PSP and BIOS directories are set in flash offsets. > > PSP and BIOS directory headers have a indicator to provide information about address mode to expect from each entry. Entries inherit this information if not overwritten by entry configuration from the outside/user. Addition: This is also true, when placing the EFT and/or binaries in upper/lower flash if ROM is larger than 16Mb. Note: I observed serveral aspects of the documentation as invalid, untrue, unspecific and/or mutual exclusive. Stuff which might work for servers do not work for client platform and vice versa. Basically everything can be right or wrong at the same time, depending on the platform we're talking about. -- To view, visit https://review.coreboot.org/c/coreboot/+/69852 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I89c9e73e7db748379c97e3c0ad69af3faedc8d66 Gerrit-Change-Number: 69852 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: Christopher Meis <christopher.meis(a)9elements.com> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 05 Dec 2022 11:12:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Christopher Meis <christopher.meis(a)9elements.com> Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Comment-In-Reply-To: Marvin Drees <marvin.drees(a)9elements.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: security/tpm: support compiling in multiple TPM drivers
by Michał Żygowski (Code Review) 05 Dec '22

05 Dec '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Christian Walter, Julius Werner, Krystian Hebel, Fred Reitberger, Sergii Dmytruk, Felix Held. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69162 ) Change subject: security/tpm: support compiling in multiple TPM drivers ...................................................................... Patch Set 11: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/69162/comment/52a4922d_80b6e224 PS7, Line 12: Making probe functions static and always using them uncovered that : bootblock stage included TPM driver which it didn't use. This is why : Makefile.inc files were updated to replace `all-*` with : romstage, ramstage and verstage. > (Apparently my yesterday's reply to this was somehow lost. […] TPM is also setup in verstage which doesn't have to be a separate stage and may run/start in bootblock instead. Then I think the drivers might be needed. -- To view, visit https://review.coreboot.org/c/coreboot/+/69162 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44c5a1d825afe414c2f5c2c90f4cfe41ba9bef5f Gerrit-Change-Number: 69162 Gerrit-PatchSet: 11 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 05 Dec 2022 11:11:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/alderlake: make SOC_INTEL_CSE_SEND_EOP_EARLY per-board conf...
by Michał Żygowski (Code Review) 05 Dec '22

05 Dec '22

Attention is currently required from: Tarun Tuli, Subrata Banik, Michał Kopeć. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69953 ) Change subject: soc/intel/alderlake: make SOC_INTEL_CSE_SEND_EOP_EARLY per-board configurable ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69953 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7febf7c029e7eac94052cc3a8142949d6813c1bc Gerrit-Change-Number: 69953 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Comment-Date: Mon, 05 Dec 2022 11:09:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/common/block/fast_spi: Add SPI BIOS decode lock
by Shuming Chu (Shuming) (Code Review) 05 Dec '22

05 Dec '22

Hello Marc Jones, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/70348 to look at the new patch set (#2). Change subject: soc/intel/common/block/fast_spi: Add SPI BIOS decode lock ...................................................................... soc/intel/common/block/fast_spi: Add SPI BIOS decode lock Add fast_spi_set_bde() to be called by the SOC lockdown function. The lock is SOC specific, so it can't be called in common PCH lockdown function. Change-Id: I3f7cca671250996a6be7b5b28437c3e1bf777678 Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com> --- M src/soc/intel/common/block/fast_spi/fast_spi.c M src/soc/intel/common/block/fast_spi/fast_spi_def.h M src/soc/intel/common/block/include/intelblocks/fast_spi.h 3 files changed, 30 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/70348/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/70348 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f7cca671250996a6be7b5b28437c3e1bf777678 Gerrit-Change-Number: 70348 Gerrit-PatchSet: 2 Gerrit-Owner: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-CC: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-CC: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/common/block/fast_spi: Add SPI BIOS decode lock
by build bot (Jenkins) (Code Review) 05 Dec '22

05 Dec '22

Attention is currently required from: Marc Jones. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70348 ) Change subject: soc/intel/common/block/fast_spi: Add SPI BIOS decode lock ...................................................................... Patch Set 1: (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-165227): https://review.coreboot.org/c/coreboot/+/70348/comment/174d66b8_9d349a8e PS1, Line 9: Add fast_spi_set_bde() to be called by the SOC lockdown function. Possible unwrapped commit description (prefer a maximum 72 chars per line) -- To view, visit https://review.coreboot.org/c/coreboot/+/70348 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f7cca671250996a6be7b5b28437c3e1bf777678 Gerrit-Change-Number: 70348 Gerrit-PatchSet: 1 Gerrit-Owner: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-CC: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Comment-Date: Mon, 05 Dec 2022 10:57:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[master]: soc/intel/common/block/oc_wdt: Add OC watchdog common block
by Michał Żygowski (Code Review) 05 Dec '22

05 Dec '22

Attention is currently required from: Martin L Roth, Michał Kopeć. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68944 ) Change subject: soc/intel/common/block/oc_wdt: Add OC watchdog common block ...................................................................... Patch Set 7: (1 comment) File src/soc/intel/common/block/oc_wdt/Kconfig: https://review.coreboot.org/c/coreboot/+/68944/comment/f22d5bff_d9a00da6 PS7, Line 10: HAVE_CF9_RESET_PREPARE > This seems wrong to me. […] Any other ideas how to hook into reset functions? Create yet another hook? The reason behind hooking into reset is to distinguish from expected resets and unexpected resets. Also we can ignore this as well and do not implement any unexpected reset detection logic for now. -- To view, visit https://review.coreboot.org/c/coreboot/+/68944 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib494aa0c7581351abca8b496fc5895b2c7cbc5bc Gerrit-Change-Number: 68944 Gerrit-PatchSet: 7 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Comment-Date: Mon, 05 Dec 2022 10:56:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: comment

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