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Change in coreboot[master]: mb/google/brya: Add 5G WWAN ACPI support for brya4es and redrix4es

by Cliff Huang (Code Review)

Cliff Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61355 ) Change subject: mb/google/brya: Add 5G WWAN ACPI support for brya4es and redrix4es ...................................................................... mb/google/brya: Add 5G WWAN ACPI support for brya4es and redrix4es Add FM350GL 5G WWAN support using drivers/wwan/fm and addtional PM features from rtd3. Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: I6413f106ce6ef6c895d4861f4dbe26ac9a507d25 --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb M src/mainboard/google/brya/variants/brya4es/overridetree.cb M src/mainboard/google/brya/variants/redrix4es/overridetree.cb 4 files changed, 23 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/61355/1 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 9bfee76..9c83d82 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -18,6 +18,7 @@ select DRIVERS_SOUNDWIRE_MAX98373 select DRIVERS_SPI_ACPI select DRIVERS_WIFI_GENERIC + select DRIVERS_WWAN_FM350GL select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_ACPI_MEMMAP select EC_GOOGLE_CHROMEEC_BOARDID diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb index 7323b10..ec2a9c9 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb @@ -156,7 +156,11 @@ # Enable WWAN PCIE 6 using clk 5 chip soc/intel/common/block/pcie/rtd3 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E0)" + register "reset_off_delay_ms" = "20" + register "reset_delay_ms" = "1000" register "srcclk_pin" = "5" + register "ext_pm_support" = "true" + register "skip_on_off_support" = "true" device generic 0 on end end register "pch_pcie_rp[PCH_RP(6)]" = "{ diff --git a/src/mainboard/google/brya/variants/brya4es/overridetree.cb b/src/mainboard/google/brya/variants/brya4es/overridetree.cb index cae2257..125edd4 100644 --- a/src/mainboard/google/brya/variants/brya4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/brya4es/overridetree.cb @@ -189,6 +189,15 @@ end device ref pcie_rp6 on probe DB_LTE LTE_PCIE + chip drivers/wwan/fm + register "fcpo" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F21)" + register "reset" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E16)" + register "perst" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E0)" + register "wake" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A7)" + device generic 0 on + probe DB_LTE LTE_PCIE + end + end end device ref tcss_dma0 on chip drivers/intel/usb4/retimer diff --git a/src/mainboard/google/brya/variants/redrix4es/overridetree.cb b/src/mainboard/google/brya/variants/redrix4es/overridetree.cb index 72f1da2..303ce3b 100644 --- a/src/mainboard/google/brya/variants/redrix4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/redrix4es/overridetree.cb @@ -153,6 +153,15 @@ end device ref pcie_rp6 on probe DB_LTE LTE_PCIE + chip drivers/wwan/fm + register "fcpo" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F21)" + register "reset" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E16)" + register "perst" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E0)" + register "wake" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A7)" + device generic 0 on + probe DB_LTE LTE_PCIE + end + end end device ref tcss_dma0 on chip drivers/intel/usb4/retimer -- To view, visit https://review.coreboot.org/c/coreboot/+/61355 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6413f106ce6ef6c895d4861f4dbe26ac9a507d25 Gerrit-Change-Number: 61355 Gerrit-PatchSet: 1 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-MessageType: newchange

3 minutes

Change in coreboot[master]: drivers/wwan/fm: Add Fibocom 5G WWAN ACPI support

by Cliff Huang (Code Review)

Cliff Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61354 ) Change subject: drivers/wwan/fm: Add Fibocom 5G WWAN ACPI support ...................................................................... drivers/wwan/fm: Add Fibocom 5G WWAN ACPI support Support PXSX._RST and PXSX.MRST._RST for warm and cold reset. PXSX._RST is invoked when driver removal. Test: Add chip entry to the corresponding root port and check PXSX Device is generated in ssdt. Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: I1e0b9fd405f6cfb1e216ea27558bb9299a09e566 --- A src/drivers/wwan/fm/Kconfig A src/drivers/wwan/fm/Makefile.inc A src/drivers/wwan/fm/acpi_fm350gl.c A src/drivers/wwan/fm/chip.h 4 files changed, 223 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/61354/1 diff --git a/src/drivers/wwan/fm/Kconfig b/src/drivers/wwan/fm/Kconfig new file mode 100644 index 0000000..4ad94a5 --- /dev/null +++ b/src/drivers/wwan/fm/Kconfig @@ -0,0 +1,8 @@ +config DRIVERS_WWAN_FM350GL + bool + default n + depends on SOC_INTEL_COMMON_BLOCK_PCIE_RTD3 + help + This driver is for Fibocom FM350-GL PCIe 5G WWAN. + When enabled, this driver will add support for ACPI controlled + WWAN using GPIOs for power/reset control of the device. diff --git a/src/drivers/wwan/fm/Makefile.inc b/src/drivers/wwan/fm/Makefile.inc new file mode 100644 index 0000000..8074a08 --- /dev/null +++ b/src/drivers/wwan/fm/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_WWAN_FM350GL) += acpi_fm350gl.c diff --git a/src/drivers/wwan/fm/acpi_fm350gl.c b/src/drivers/wwan/fm/acpi_fm350gl.c new file mode 100644 index 0000000..5438225 --- /dev/null +++ b/src/drivers/wwan/fm/acpi_fm350gl.c @@ -0,0 +1,181 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpigen.h> +#include <acpi/acpi_device.h> +#include "chip.h" + +/* FCPO# to RESET# delay time during WWAN ON */ +#define FM350GL_TN2B 20 +/* RESET# to PERST# delay time during WWAN ON */ +#define FM350GL_TB2R 80 +/* The delay between de-assertion of PERST# to change of PDS state from 0 to 1 during WWAN ON */ +#define FM350GL_TR2P 0 +/* RESET# to FCPO# delay time during WWAN OFF */ +#define FM350GL_TB2F 10 +/* Time to allow the WWAN module to fully discharge any residual voltages before FCPO# could be + de-asserted again. */ +#define FM350GL_TFDI 500 +/* The delay between assertion and de-assertion RESET# during FLDR */ +#define FM350GL_TBTG 10 +/* The delay between de-assertion of RESET# and change of PDS state from 0 to 1 after FLDR */ +#define FM350GL_TBTP 170 +/* PERST# to RESET# delay time during WWAN OFF */ +#define FM350GL_TR2B 10 +/* 20s HW initialization needed after de-assertion of PERST# + However, it is not required and is not proper place to ensure HW initializatioin in ACPI. The + delay here is to ensure the following reset or rtd3 _OFF method won't be called immediately. + */ +#define FM350GL_TIME_HW_INIT 100 + +static void wwan_fm350gl_acpi_method_fhrf(const struct device *parent_dev, + const struct drivers_wwan_fm_config *config) +{ + acpigen_write_method_serialized("FHRF", 1); + /* LOCAL0 = PERST# */ + acpigen_get_tx_gpio(&config->perst); + acpigen_write_if_lequal_op_int(LOCAL0_OP, 0); + acpigen_emit_namestring(acpi_device_path_join(parent_dev, "DL23")); + /* assert PERST# pin */ + acpigen_enable_tx_gpio(&config->perst); + acpigen_pop_len(); /* If */ + acpigen_write_sleep(FM350GL_TR2B); + /* assert RESET# pin */ + acpigen_enable_tx_gpio(&config->reset); + /* warm reset */ + acpigen_write_if_lequal_op_int(ARG0_OP, 0); + acpigen_write_sleep(FM350GL_TBTG); + /* cold reset */ + acpigen_write_else(); + acpigen_write_if_lequal_op_int(ARG0_OP, 1); + /* disable source clock */ + acpigen_emit_namestring(acpi_device_path_join(parent_dev, "SRCK")); + acpigen_emit_byte(ZERO_OP); + acpigen_write_sleep(FM350GL_TB2F); + /* assert FCPO# pin */ + acpigen_enable_tx_gpio(&config->fcpo); + acpigen_write_sleep(FM350GL_TFDI); + acpigen_pop_len(); /* If */ + acpigen_pop_len(); /* Else */ + acpigen_pop_len(); /* Method */ +} + +static void wwan_fm350gl_acpi_method_shrf(const struct device *parent_dev, + const struct drivers_wwan_fm_config *config) +{ + acpigen_write_method_serialized("SHRF", 0); + /* call rtd3 method to Disable ModPHY Power Gating. */ + acpigen_emit_namestring(acpi_device_path_join(parent_dev, "PSD0")); + /* call rtd3 method to Enable SRC Clock. */ + acpigen_emit_namestring(acpi_device_path_join(parent_dev, "SRCK")); + acpigen_emit_byte(ONE_OP); + /* De-assert FCPO# GPIO. */ + acpigen_disable_tx_gpio(&config->fcpo); + acpigen_write_sleep(FM350GL_TN2B); + /* De-assert RESET# GPIO. */ + acpigen_disable_tx_gpio(&config->reset); + acpigen_write_sleep(FM350GL_TB2R); + /* De-assert PERST# GPIO. */ + acpigen_disable_tx_gpio(&config->perst); + /* Call rtd3 method to trigger L2/L3 ready exit flow in root port */ + acpigen_emit_namestring(acpi_device_path_join(parent_dev, "L23D")); + acpigen_write_sleep(FM350GL_TIME_HW_INIT); + acpigen_pop_len(); /* Method */ +} + +static void wwan_fm350gl_acpi_method_rst(const struct device *parent_dev, + const struct drivers_wwan_fm_config *config) +{ + acpigen_write_method_serialized("_RST", 0); + /* Indicates that the following _Off will be skipped. */ + acpigen_write_store_int_to_namestr(1, acpi_device_path_join(parent_dev, "RTD3._OFS")); + /* Perform 1st Half of FLDR Flow for soft reset: FHRF(0) */ + acpigen_emit_namestring("FHRF"); + acpigen_emit_byte(ZERO_OP); + /* Perform 2nd Half of FLDR Flow: SHRF() */ + acpigen_emit_namestring("SHRF"); + /* Indicates that the following _Off will be skipped. */ + acpigen_write_store_int_to_namestr(1, acpi_device_path_join(parent_dev, "RTD3._OFS")); + acpigen_pop_len(); /* Method */ +} + +static void wwan_fm350gl_acpi_method_mrst_rst(const struct device *parent_dev, + const struct drivers_wwan_fm_config *config) +{ + acpigen_write_method_serialized("_RST", 0); + /* Indicates that the following _Off will be skipped once. */ + acpigen_write_store_int_to_namestr(1, acpi_device_path_join(parent_dev, "RTD3._OFS")); + /* Perform 1st Half of FLDR Flow for cold reset: FHRF (1) */ + acpigen_emit_namestring("FHRF"); + acpigen_emit_byte(ONE_OP); + /* Perform 2nd Half of FLDR Flow: SHRF () */ + acpigen_emit_namestring("SHRF"); + /* Indicate kernel ACPI PM to skip _off RTD3 after reset at the end of driver removal */ + acpigen_write_store_int_to_namestr(1, acpi_device_path_join(parent_dev, "RTD3._OFS")); + acpigen_pop_len(); /* Method */ +} + +static const char *wwan_fm350gl_acpi_name(const struct device *dev) +{ + /* Attached device name must be "PXSX" for the Linux Kernel to recognize it. */ + return "PXSX"; +} + +static void wwan_fm350gl_acpi_fill_ssdt(const struct device *dev) +{ + const struct drivers_wwan_fm_config *config = config_of(dev); + const struct device *parent = dev->bus->dev; + const char *scope = acpi_device_path(parent); + + if (!is_dev_enabled(parent)) { + printk(BIOS_ERR, "%s: root port not enabled\n", __func__); + return; + } + if (!scope) { + printk(BIOS_ERR, "%s: root port scope not found\n", __func__); + return; + } + if (!config->fcpo.pin_count && !config->reset.pin_count && + !config->perst.pin_count) { + printk(BIOS_ERR, "%s: FCPO, RESET, PERST GPIO required for %s.\n", + __func__, scope); + return; + } + printk(BIOS_INFO, "%s: Enable WWAN for %s (%s)\n", scope, dev_path(parent), + config->desc ?: dev->chip_ops->name); + acpigen_write_scope(scope); + acpigen_write_device(wwan_fm350gl_acpi_name(dev)); + acpigen_write_ADR(0); + if (config->name) + acpigen_write_name_string("_DDN", config->name); + if (config->desc) + acpigen_write_name_unicode("_STR", config->desc); + wwan_fm350gl_acpi_method_fhrf(parent, config); + wwan_fm350gl_acpi_method_shrf(parent, config); + wwan_fm350gl_acpi_method_rst(parent, config); + /* NOTE: the 5G driver is looking for MRST._RST for cold reset called during + * firmware update. + */ + acpigen_write_device("MRST"); + acpigen_write_ADR(0); + wwan_fm350gl_acpi_method_mrst_rst(parent, config); + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ +} + +static struct device_operations wwan_fm350gl_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .acpi_fill_ssdt = wwan_fm350gl_acpi_fill_ssdt, + .acpi_name = wwan_fm350gl_acpi_name, +}; + +static void wwan_fm350gl_acpi_enable(struct device *dev) +{ + dev->ops = &wwan_fm350gl_ops; +} + +struct chip_operations drivers_wwan_fm_ops = { + CHIP_NAME("Fibocom FM-350-GL") + .enable_dev = wwan_fm350gl_acpi_enable +}; diff --git a/src/drivers/wwan/fm/chip.h b/src/drivers/wwan/fm/chip.h new file mode 100644 index 0000000..8f7f147 --- /dev/null +++ b/src/drivers/wwan/fm/chip.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __DRIVERS_WWAN_FM_CHIP_H__ +#define __DRIVERS_WWAN_FM_CHIP_H__ + +struct drivers_wwan_fm_config { + const char *name; + const char *desc; + /* GPIO used for FULL_CARD_POWER_OFF# */ + struct acpi_gpio fcpo; + /* Delay to be inserted after fcpo is deasserted. */ + unsigned int fcpo_asserted_delay_ms; + /* Delay to be inserted after fcpo is asserted. */ + unsigned int fcpo_deasserted_delay_ms; + + /* GPIO used for RESET# */ + struct acpi_gpio reset; + /* Delay to be inserted after reset is deasserted. */ + unsigned int reset_asserted_delay_ms; + /* Delay to be inserted after reset is asserted. */ + unsigned int reset_deasserted_delay_ms; + + /* GPIO used for PERST# */ + struct acpi_gpio perst; + /* Delay to be inserted after perst is deasserted. */ + unsigned int perst_asserted_delay_ms; + /* Delay to be inserted after perst is asserted. */ + unsigned int perst_deasserted_delay_ms; + + struct acpi_gpio wake; +}; + +#endif /* __DRIVERS_WWAN_FM_CHIP_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/61354 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e0b9fd405f6cfb1e216ea27558bb9299a09e566 Gerrit-Change-Number: 61354 Gerrit-PatchSet: 1 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-MessageType: newchange

5 minutes

Change in coreboot[master]: soc/intel/common/block/pcie/rtd3: Add optional _OFF and _ON skip control

by Cliff Huang (Code Review)

Cliff Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61353 ) Change subject: soc/intel/common/block/pcie/rtd3: Add optional _OFF and _ON skip control ...................................................................... soc/intel/common/block/pcie/rtd3: Add optional _OFF and _ON skip control - Optional feature to provide mechanism to skip _OFF and _On execution. - It is used for the device to skip _OFF and _ON during device driver reload. - _OFS is used to skip _OFF Method at the end of device driver removal. - _ONS is used to skip _ON Method at the beginning of driver loading. - General flow use case: 1. Device driver is removed by 'rmmod' command. 2. Device _RST is called. _RST perform reset. 3. Device sets _OFS in _RST to skip the following _OFF invoked by OSPM. 4. OSPM invokes _OFF at the end of driver removal. 5. _OFF sees _OFS and skips current execution and clears _OFS so that _OFF will be executed normally next time. 6. _OFF sets _ONS to skip the following _ON invoked by OSPM. 7. Device driver is reloading by 'insmod/modprobe' command. 8. OSPM invokes _ON at the beginning of driver loading. 9. _ON sees _ONS and skip current execution and clears _ONS so that _ON will be executed normally next time. - In normal case: When supspend, OSPM invokes _OFF and _OFS is not set, so the device go to deeper state as expected. When resume, OSPM invokes _ON and _ONS is not set, so the device go to active state as expected. - Generated changes: PowerResource (RTD3, 0x00, 0x0000) Name (_ONS, Zero) Name (_OFS, Zero) ... Method (_ON, 0, Serialized) // _ON_: Power On { If ((_ONS == Zero)) { ... } ElseIf ((_ONS == One)) { _ONS = Zero } } Method (_OFF, 0, Serialized) // _OFF: Power Off { If ((_OFS == Zero)) { ... } ElseIf ((_OFS == One)) { _OFS = Zero _ONS = One } } Test: Enable and verify _OFS and _ONS Name objects and the if-condition logic inside _OFF and _ON metheds is added. Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: Ic32d151d65107bfc220258c383a575e40a496b6f --- M src/soc/intel/common/block/pcie/rtd3/chip.h M src/soc/intel/common/block/pcie/rtd3/rtd3.c 2 files changed, 58 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/61353/1 diff --git a/src/soc/intel/common/block/pcie/rtd3/chip.h b/src/soc/intel/common/block/pcie/rtd3/chip.h index c2bad63..10470fe 100644 --- a/src/soc/intel/common/block/pcie/rtd3/chip.h +++ b/src/soc/intel/common/block/pcie/rtd3/chip.h @@ -51,6 +51,12 @@ * connected root port, mainly used in the device ACPI methods such as reset. */ bool ext_pm_support; + + /* + * Add support to skip _OFF and _ON execution when needed, such as reloading + * the device driver. + */ + bool skip_on_off_support; }; #endif /* __SOC_INTEL_COMMON_BLOCK_PCIE_RTD3_CHIP_H__ */ diff --git a/src/soc/intel/common/block/pcie/rtd3/rtd3.c b/src/soc/intel/common/block/pcie/rtd3/rtd3.c index a9df72a..0a96574 100644 --- a/src/soc/intel/common/block/pcie/rtd3/rtd3.c +++ b/src/soc/intel/common/block/pcie/rtd3/rtd3.c @@ -151,6 +151,13 @@ { acpigen_write_method_serialized("_ON", 0); + /* When this feature is enabled, _ONS indicates if the previous _OFF was + * skipped. If so, since the device was not in Off state, and the current + * _ON can be skipped as well. + */ + if (config->skip_on_off_support) + acpigen_write_if_lequal_namestr_int("_ONS", 0); + /* Disable modPHY power gating for PCH RPs. */ if (rp_type == PCIE_RP_PCH) pcie_rtd3_enable_modphy_pg(pcie_rp, PG_DISABLE); @@ -177,6 +184,17 @@ if (!config->disable_l23) pcie_rtd3_acpi_l23_exit(); + if (config->skip_on_off_support) { + /* If current _ON is skipped, _ONS is clear so that _ON will be + * executed normally until _OFF is skipped again. + */ + acpigen_write_else(); + acpigen_write_if_lequal_namestr_int("_ONS", 1); + acpigen_write_store_int_to_namestr(0, "_ONS"); + + acpigen_pop_len(); /* If */ + acpigen_pop_len(); /* Else */ + } acpigen_pop_len(); /* Method */ } @@ -187,6 +205,14 @@ { acpigen_write_method_serialized("_OFF", 0); + /* When this feature is enabled, _ONS is checked to see if the device + * wants _OFF to be skipped for once. _ONS is normally set in the device + * method, such as reset _RST, which is invoked during driver reload. In + * such case, _OFF needs to be avoided at the end of driver removal. + */ + if (config->skip_on_off_support) + acpigen_write_if_lequal_namestr_int("_OFS", 0); + /* Trigger L23 ready entry flow unless disabled by config. */ if (!config->disable_l23) pcie_rtd3_acpi_l23_entry(); @@ -213,6 +239,18 @@ acpigen_write_sleep(config->enable_off_delay_ms); } + if (config->skip_on_off_support) { + /* If current _OFF is skipped, _ONS is set so that the following _ON + * will also be skipped. In addition, _OFS is clear so that next _OFF + * will be executed normally until the device method sets _OFS again. + */ + acpigen_write_else(); + acpigen_write_if_lequal_namestr_int("_OFS", 1); + acpigen_write_store_int_to_namestr(0, "_OFS"); + acpigen_write_store_int_to_namestr(1, "_ONS"); + acpigen_pop_len(); /* If */ + acpigen_pop_len(); /* Else */ + } acpigen_pop_len(); /* Method */ } @@ -377,6 +415,20 @@ /* ACPI Power Resource for controlling the attached device power. */ acpigen_write_power_res("RTD3", 0, 0, power_res_states, ARRAY_SIZE(power_res_states)); + + if (config->skip_on_off_support) { + /* _OFS: 0 = _OFF Method will be executed normally when called; + * 1 = _OFF will be skipped once. + * _OFF Method to clear _OFS and set _ONS if the current execution + * is skipped. + * _ONS: 0 = _ON Method will be executed normally when called; + * 1 = _ONF will be skipped once. + * _ON Method to clear _ONS if the current execution is skipped. + */ + acpigen_write_name_integer("_ONS", 0); + acpigen_write_name_integer("_OFS", 0); + } + pcie_rtd3_acpi_method_status(config); pcie_rtd3_acpi_method_on(pcie_rp, config, rp_type); pcie_rtd3_acpi_method_off(pcie_rp, config, rp_type); -- To view, visit https://review.coreboot.org/c/coreboot/+/61353 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic32d151d65107bfc220258c383a575e40a496b6f Gerrit-Change-Number: 61353 Gerrit-PatchSet: 1 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-MessageType: newchange

7 minutes

Change in coreboot[master]: soc/intel/common/block/pcie/rtd3: Add PM methods to the device.

by Cliff Huang (Code Review)

Cliff Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61352 ) Change subject: soc/intel/common/block/pcie/rtd3: Add PM methods to the device. ...................................................................... soc/intel/common/block/pcie/rtd3: Add PM methods to the device. Add L23 enter/exit, modPHY power gate, and source clock control methods. DL23: method for L2/L3 entry. L23D: method for L2/L3 exit. PSD0: method for modPHY power gate. SRCK: method for enabling/disable source clock. These optional methods are to be used in the device ACPI to construct flows with root port's power management functions. Test: Enable and verify DL23, L23D, PSD0, SRCK methods in ssdt. Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: I79de76f26c8424b036cb7d2719df68937599ca2f --- M src/soc/intel/common/block/pcie/rtd3/chip.h M src/soc/intel/common/block/pcie/rtd3/rtd3.c 2 files changed, 62 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/61352/1 diff --git a/src/soc/intel/common/block/pcie/rtd3/chip.h b/src/soc/intel/common/block/pcie/rtd3/chip.h index 15b8f64..c2bad63 100644 --- a/src/soc/intel/common/block/pcie/rtd3/chip.h +++ b/src/soc/intel/common/block/pcie/rtd3/chip.h @@ -45,6 +45,12 @@ * Disable the ACPI-driven L23 Ready-to-Detect transition for the root port. */ bool disable_l23; + + /* + * Provides L23, modPHY gating, source clock enabling methods to the device + * connected root port, mainly used in the device ACPI methods such as reset. + */ + bool ext_pm_support; }; #endif /* __SOC_INTEL_COMMON_BLOCK_PCIE_RTD3_CHIP_H__ */ diff --git a/src/soc/intel/common/block/pcie/rtd3/rtd3.c b/src/soc/intel/common/block/pcie/rtd3/rtd3.c index 9f91d21..a9df72a 100644 --- a/src/soc/intel/common/block/pcie/rtd3/rtd3.c +++ b/src/soc/intel/common/block/pcie/rtd3/rtd3.c @@ -100,6 +100,50 @@ acpigen_emit_namestring(RTD3_MUTEX_PATH); } +/* Method to enter L2/L3 */ +static void +pcie_rtd3_acpi_method_dl23(void) +{ + acpigen_write_method_serialized("DL23", 0); + pcie_rtd3_acpi_l23_entry(); + acpigen_pop_len(); /* Method */ +} + +/* Method to exit L2/L3 */ +static void +pcie_rtd3_acpi_method_l23d(void) +{ + acpigen_write_method_serialized("L23D", 0); + pcie_rtd3_acpi_l23_exit(); + acpigen_pop_len(); /* Method */ +} + +/* Method to disable PCH modPHY power gating */ +static void +pcie_rtd3_acpi_method_pds0(unsigned int pcie_rp) +{ + acpigen_write_method_serialized("PSD0", 0); + pcie_rtd3_enable_modphy_pg(pcie_rp, PG_DISABLE); + acpigen_pop_len(); /* Method */ +} + +/* Method to enable/disable the source clock */ +static void +pcie_rtd3_acpi_method_srck(unsigned int pcie_rp, + const struct soc_intel_common_block_pcie_rtd3_config *config) +{ + acpigen_write_method_serialized("SRCK", 1); + + if (config->srcclk_pin >= 0) { + acpigen_write_if_lequal_op_op(ARG0_OP, 0); + pmc_ipc_acpi_set_pci_clock(pcie_rp, config->srcclk_pin, false); + acpigen_write_else(); + pmc_ipc_acpi_set_pci_clock(pcie_rp, config->srcclk_pin, true); + acpigen_pop_len(); /* If */ + } + acpigen_pop_len(); /* Method */ +} + static void pcie_rtd3_acpi_method_on(unsigned int pcie_rp, const struct soc_intel_common_block_pcie_rtd3_config *config, @@ -316,9 +360,20 @@ acpigen_write_field("PXCS", fieldlist, ARRAY_SIZE(fieldlist), FIELD_ANYACC | FIELD_NOLOCK | FIELD_PRESERVE); + if (config->ext_pm_support) { + pcie_rtd3_acpi_method_dl23(); + pcie_rtd3_acpi_method_l23d(); + } + /* Create the OpRegion to access the ModPHY PG registers (PCH RPs only) */ - if (rp_type == PCIE_RP_PCH) + if (rp_type == PCIE_RP_PCH) { write_modphy_opregion(pcie_rp); + if (config->ext_pm_support) + pcie_rtd3_acpi_method_pds0(pcie_rp); + } + + if (config->ext_pm_support && config->srcclk_pin) + pcie_rtd3_acpi_method_srck(pcie_rp, config); /* ACPI Power Resource for controlling the attached device power. */ acpigen_write_power_res("RTD3", 0, 0, power_res_states, ARRAY_SIZE(power_res_states)); -- To view, visit https://review.coreboot.org/c/coreboot/+/61352 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79de76f26c8424b036cb7d2719df68937599ca2f Gerrit-Change-Number: 61352 Gerrit-PatchSet: 1 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-MessageType: newchange

10 minutes

Change in coreboot[master]: mb/google/brya/var/brask: set tcc offset value to 10℃

by David Wu (Code Review)

Attention is currently required from: Paul Menzel, Tim Wawrzynczak, Ren Kuo, Sumeet R Pawnikar, Nick Vaccaro, Alan Huang. David Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61142 ) Change subject: mb/google/brya/var/brask: set tcc_offset value to 10℃ ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/61142/comment/fcabdec7_f0e25987 PS4, Line 7: mb/google/brya/var/brask: set tcc_offset value to 10 > Volts: 10 V This is 10℃ (degrees Celsius). -- To view, visit https://review.coreboot.org/c/coreboot/+/61142 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I86acb172ed427d45973b9360e0413978cbd46645 Gerrit-Change-Number: 61142 Gerrit-PatchSet: 5 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Peter Ou <peter.ou(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Tue, 25 Jan 2022 02:22:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

16 minutes

Change in coreboot[master]: mb/google/brya/var/brask: set tcc offset value to 10℃

by David Wu (Code Review)

Attention is currently required from: David Wu, Tim Wawrzynczak, Ren Kuo, Sumeet R Pawnikar, Nick Vaccaro, Alan Huang. Hello build bot (Jenkins), Ren Kuo, Tim Wawrzynczak, Sumeet R Pawnikar, Nick Vaccaro, Zhuohao Lee, Alan Huang, Peter Ou, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61142 to look at the new patch set (#5). Change subject: mb/google/brya/var/brask: set tcc_offset value to 10℃ ...................................................................... mb/google/brya/var/brask: set tcc_offset value to 10℃ Set tcc_offset value to 10 in devicetree for Thermal Control Circuit (TCC) activation feature. This value is suggested by Thermal team. BUG=b:214890058 BRANCH=None TEST=build pass Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: I86acb172ed427d45973b9360e0413978cbd46645 --- M src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/61142/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/61142 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I86acb172ed427d45973b9360e0413978cbd46645 Gerrit-Change-Number: 61142 Gerrit-PatchSet: 5 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Peter Ou <peter.ou(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

18 minutes

Change in coreboot[master]: mb/google/brya/var/brask: set tcc_offset value to 10

by Peter Ou (Code Review)

Attention is currently required from: David Wu, Tim Wawrzynczak, Ren Kuo, Sumeet R Pawnikar, Nick Vaccaro, Alan Huang. Peter Ou has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61142 ) Change subject: mb/google/brya/var/brask: set tcc_offset value to 10 ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: > This seems conservative value. But, looks fine for me. […] This is final value for Brask, for OEM should be fine tune. -- To view, visit https://review.coreboot.org/c/coreboot/+/61142 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I86acb172ed427d45973b9360e0413978cbd46645 Gerrit-Change-Number: 61142 Gerrit-PatchSet: 4 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Peter Ou <peter.ou(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Tue, 25 Jan 2022 02:15:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: comment

23 minutes

Change in coreboot[master]: soc/amd/cezanne: Fix incorrect values of CBFS amdfw position makefile...

by Felix Held (Code Review)

Attention is currently required from: Robert Zieba, Jason Glenesk, Raul Rangel, Marshall Dawson, Rob Barnes. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61349 ) Change subject: soc/amd/cezanne: Fix incorrect values of CBFS amdfw position makefile variables ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: soc/amd/picasso and mb/google/zork use hard-coded offsets for this that are non-zero and have an offset of 0x40 bytes into the a/b rw sections cbfs region to take the cbfs header into account. not sure which is correct, but it's different on those two platforms that should be relatively similar. not having some hard-coed values that need to match up with the fmap layout is definitely an advantage though -- To view, visit https://review.coreboot.org/c/coreboot/+/61349 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If1c2b61c5be0bcab52e19349dacbcc391e8aa909 Gerrit-Change-Number: 61349 Gerrit-PatchSet: 1 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Comment-Date: Tue, 25 Jan 2022 02:10:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

28 minutes

Change in coreboot[master]: soc/mediatek/mt8186: Use macro define BIT for arbit enable bit

by Rex-BC Chen (Code Review)

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Hello Hung-Te Lin, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61351 to look at the new patch set (#2). Change subject: soc/mediatek/mt8186: Use macro define BIT for arbit enable bit ...................................................................... soc/mediatek/mt8186: Use macro define BIT for arbit enable bit Replace (1 << x) with BIT(x) in pmic_wrap.h. BUG=none TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I463589f02065a228a8af74447b4586e5b54e0b3b --- M src/soc/mediatek/mt8186/include/soc/pmic_wrap.h 1 file changed, 20 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/61351/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61351 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I463589f02065a228a8af74447b4586e5b54e0b3b Gerrit-Change-Number: 61351 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

38 minutes

Change in coreboot[master]: soc/mediatek: Save dramc_param header to mrc_cache

by Rex-BC Chen (Code Review)

Attention is currently required from: Xi Chen, Hung-Te Lin, Paul Menzel, Rex-BC Chen. Rex-BC Chen has uploaded a new patch set (#9) to the change originally created by Xixi Chen. ( https://review.coreboot.org/c/coreboot/+/61294 ) Change subject: soc/mediatek: Save dramc_param header to mrc_cache ...................................................................... soc/mediatek: Save dramc_param header to mrc_cache Fast-k flow may need to re-init header because mrc_cache doesn't store header. Storing header together with dparam data is better for data consistancy. TEST=fast calibration pass on Corsola BUG=b:204226005 Signed-off-by: Xi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Change-Id: I22982923dce06c9e770aa4f20f3dcd2f33685d84 --- M src/soc/mediatek/common/memory.c 1 file changed, 5 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/61294/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/61294 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22982923dce06c9e770aa4f20f3dcd2f33685d84 Gerrit-Change-Number: 61294 Gerrit-PatchSet: 9 Gerrit-Owner: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-MessageType: newpatchset

38 minutes

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