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[S] Change in coreboot[main]: spd/lp5: Add SPD for K3KL8L80EM-MGCU
by Subrata Banik (Code Review) 21 Apr '25

21 Apr '25

Attention is currently required from: Jian Tong, Kapil Porwal, Rui Zhou. Subrata Banik has posted comments on this change by Rui Zhou. ( https://review.coreboot.org/c/coreboot/+/87395?usp=email ) Change subject: spd/lp5: Add SPD for K3KL8L80EM-MGCU ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87395?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I34c8d8e1fc7b8aa107bc181f51b5dc2ff287aa4c Gerrit-Change-Number: 87395 Gerrit-PatchSet: 1 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Jian Tong <tongjian(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Jian Tong <tongjian(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Mon, 21 Apr 2025 08:31:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/rex: Generate RAM IDs
by Subrata Banik (Code Review) 21 Apr '25

21 Apr '25

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub "Kuba" Czapiga, Kapil Porwal, Rui Zhou, Tarun. Subrata Banik has posted comments on this change by Rui Zhou. ( https://review.coreboot.org/c/coreboot/+/87396?usp=email ) Change subject: mb/google/rex: Generate RAM IDs ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87396?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie3f87f5920942060e8e9f8fcf34c3124ba79f3da Gerrit-Change-Number: 87396 Gerrit-PatchSet: 1 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Mon, 21 Apr 2025 08:07:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/rex: Generate RAM IDs
by Rui Zhou (Code Review) 21 Apr '25

21 Apr '25

Rui Zhou has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87396?usp=email ) Change subject: mb/google/rex: Generate RAM IDs ...................................................................... mb/google/rex: Generate RAM IDs Generate RAM IDs for K3KL8L80DM-MGCU BUG=b:412237636 BRANCH=None TEST=Run part_id_gen tool without any errors Change-Id: Ie3f87f5920942060e8e9f8fcf34c3124ba79f3da Signed-off-by: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/rex/variants/screebo/memory/Makefile.mk M src/mainboard/google/rex/variants/screebo/memory/dram_id.generated.txt M src/mainboard/google/rex/variants/screebo/memory/mem_parts_used.txt 3 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/87396/1 diff --git a/src/mainboard/google/rex/variants/screebo/memory/Makefile.mk b/src/mainboard/google/rex/variants/screebo/memory/Makefile.mk index 5b38bfc..d633b43 100644 --- a/src/mainboard/google/rex/variants/screebo/memory/Makefile.mk +++ b/src/mainboard/google/rex/variants/screebo/memory/Makefile.mk @@ -8,3 +8,4 @@ SPD_SOURCES += spd/lp5/set-0/spd-7.hex # ID = 1(0b0001) Parts = MT62F1G32D2DS-026 WT:B, H58G56BK7BX068, K3KL8L80CM-MGCT SPD_SOURCES += spd/lp5/set-0/spd-8.hex # ID = 2(0b0010) Parts = K3KL9L90CM-MGCT SPD_SOURCES += spd/lp5/set-0/spd-9.hex # ID = 3(0b0011) Parts = K3KL6L60GM-MGCT +SPD_SOURCES += spd/lp5/set-0/spd-11.hex # ID = 4(0b0100) Parts = K3KL8L80EM-MGCU diff --git a/src/mainboard/google/rex/variants/screebo/memory/dram_id.generated.txt b/src/mainboard/google/rex/variants/screebo/memory/dram_id.generated.txt index b1172e6..a7e4fe6 100644 --- a/src/mainboard/google/rex/variants/screebo/memory/dram_id.generated.txt +++ b/src/mainboard/google/rex/variants/screebo/memory/dram_id.generated.txt @@ -11,3 +11,4 @@ K3KL9L90CM-MGCT 2 (0010) K3KL6L60GM-MGCT 3 (0011) K3KL8L80CM-MGCT 1 (0001) +K3KL8L80EM-MGCU 4 (0100) diff --git a/src/mainboard/google/rex/variants/screebo/memory/mem_parts_used.txt b/src/mainboard/google/rex/variants/screebo/memory/mem_parts_used.txt index 5757ad7..7d8cfba 100644 --- a/src/mainboard/google/rex/variants/screebo/memory/mem_parts_used.txt +++ b/src/mainboard/google/rex/variants/screebo/memory/mem_parts_used.txt @@ -16,3 +16,4 @@ K3KL9L90CM-MGCT K3KL6L60GM-MGCT K3KL8L80CM-MGCT +K3KL8L80EM-MGCU -- To view, visit https://review.coreboot.org/c/coreboot/+/87396?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie3f87f5920942060e8e9f8fcf34c3124ba79f3da Gerrit-Change-Number: 87396 Gerrit-PatchSet: 1 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com>

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[S] Change in coreboot[main]: mb/google/skywalker: Implement sku_id()
by Yu-Ping Wu (Code Review) 21 Apr '25

21 Apr '25

Attention is currently required from: Hung-Te Lin, Vince Liu, Wentao Qin, Yidi Lin. Yu-Ping Wu has posted comments on this change by Vince Liu. ( https://review.coreboot.org/c/coreboot/+/87359?usp=email ) Change subject: mb/google/skywalker: Implement sku_id() ...................................................................... Patch Set 1: Code-Review+2 (1 comment) File src/mainboard/google/skywalker/boardid.c: https://review.coreboot.org/c/coreboot/+/87359/comment/932b508d_74e2381f?us… : PS1, Line 17: cached_sku_code == CROS_SKU_UNPROVISIONED) { align -- To view, visit https://review.coreboot.org/c/coreboot/+/87359?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6f1343f127537f97bfa4e1f2cfef7db5d46fab67 Gerrit-Change-Number: 87359 Gerrit-PatchSet: 1 Gerrit-Owner: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Mon, 21 Apr 2025 08:02:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/google/skywalker: Enable ChromeOS EC
by Yu-Ping Wu (Code Review) 21 Apr '25

21 Apr '25

Attention is currently required from: Hung-Te Lin, Vince Liu, Wentao Qin, Yidi Lin. Yu-Ping Wu has posted comments on this change by Vince Liu. ( https://review.coreboot.org/c/coreboot/+/87358?usp=email ) Change subject: mb/google/skywalker: Enable ChromeOS EC ...................................................................... Patch Set 1: Code-Review+1 (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/87358/comment/183e033e_e8e15c61?us… : PS1, Line 11: Chrome ChromeOS File src/mainboard/google/skywalker/Kconfig: https://review.coreboot.org/c/coreboot/+/87358/comment/de27ef98_6f30205d?us… : PS1, Line 42: default 0x0 a blank line below File src/mainboard/google/skywalker/chromeos.c: https://review.coreboot.org/c/coreboot/+/87358/comment/9f3e8dba_0ec28dd3?us… : PS1, Line 13: gpio_output(GPIO_XHCI_INIT_DONE, 0); This seems unrelated to EC. Please create a separate patch for this. -- To view, visit https://review.coreboot.org/c/coreboot/+/87358?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id3d53dfa8e1fdee5f04f01197592d31fee146299 Gerrit-Change-Number: 87358 Gerrit-PatchSet: 1 Gerrit-Owner: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Mon, 21 Apr 2025 08:00:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: spd/lp5: Add SPD for K3KL8L80EM-MGCU
by Rui Zhou (Code Review) 21 Apr '25

21 Apr '25

Rui Zhou has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87395?usp=email ) Change subject: spd/lp5: Add SPD for K3KL8L80EM-MGCU ...................................................................... spd/lp5: Add SPD for K3KL8L80EM-MGCU Add K3KL8L80DM-MGCU in the memory_parts.json and re-generate the SPD Samsung:K3KL8L80EM-MGCU BUG=b:412237636 TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 Change-Id: I34c8d8e1fc7b8aa107bc181f51b5dc2ff287aa4c Signed-off-by: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> --- M spd/lp5/memory_parts.json M spd/lp5/set-0/parts_spd_manifest.generated.txt M spd/lp5/set-1/parts_spd_manifest.generated.txt 3 files changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/87395/1 diff --git a/spd/lp5/memory_parts.json b/spd/lp5/memory_parts.json index 2e00140..1c34505 100644 --- a/spd/lp5/memory_parts.json +++ b/spd/lp5/memory_parts.json @@ -284,6 +284,17 @@ "speedMbps": 8533, "lp5x": true } + }， + { + "name": "K3KL8L80EM-MGCU", + "attribs": { + "densityPerDieGb": 16, + "diesPerPackage": 2, + "bitWidthPerChannel": 16, + "ranksPerChannel": 1, + "speedMbps": 8533, + "lp5x": true + } } ] } diff --git a/spd/lp5/set-0/parts_spd_manifest.generated.txt b/spd/lp5/set-0/parts_spd_manifest.generated.txt index 6af57e2..f560ba3 100644 --- a/spd/lp5/set-0/parts_spd_manifest.generated.txt +++ b/spd/lp5/set-0/parts_spd_manifest.generated.txt @@ -28,3 +28,4 @@ K3KL8L80DM-MGCU,spd-11.hex MT62F2G32D4DS-020 WT:F,spd-10.hex H58G56CK8BX146,spd-11.hex +K3KL8L80EM-MGCU,spd-11.hex diff --git a/spd/lp5/set-1/parts_spd_manifest.generated.txt b/spd/lp5/set-1/parts_spd_manifest.generated.txt index 6af57e2..f560ba3 100644 --- a/spd/lp5/set-1/parts_spd_manifest.generated.txt +++ b/spd/lp5/set-1/parts_spd_manifest.generated.txt @@ -28,3 +28,4 @@ K3KL8L80DM-MGCU,spd-11.hex MT62F2G32D4DS-020 WT:F,spd-10.hex H58G56CK8BX146,spd-11.hex +K3KL8L80EM-MGCU,spd-11.hex -- To view, visit https://review.coreboot.org/c/coreboot/+/87395?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I34c8d8e1fc7b8aa107bc181f51b5dc2ff287aa4c Gerrit-Change-Number: 87395 Gerrit-PatchSet: 1 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com>

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[M] Change in coreboot[main]: soc/intel: Add Wildcat Lake CPU and PCIE device IDs
by Avi Uday (Code Review) 21 Apr '25

21 Apr '25

Attention is currently required from: Appukuttan V K, Intel coreboot Reviewers, Nick Vaccaro, Sowmya Aralguppe, Usha P, Varun Upadhyay. Avi Uday has posted comments on this change by Appukuttan V K. ( https://review.coreboot.org/c/coreboot/+/87262?usp=email ) Change subject: soc/intel: Add Wildcat Lake CPU and PCIE device IDs ...................................................................... Patch Set 10: (2 comments) File src/include/device/pci_ids.h: https://review.coreboot.org/c/coreboot/+/87262/comment/c0e687ab_48207195?us… : PS10, Line 4830: #define PCI_DID_INTEL_WCL_XDCI 0x4d7e This has not been added to pci_device_ids of src/third_party/coreboot/src/soc/intel/common/block/xdci/xdci.c Is this intentional? https://review.coreboot.org/c/coreboot/+/87262/comment/880c46c1_af83366b?us… : PS10, Line 5009: #define PCI_DID_INTEL_WCL_CNVI_BT 0x4d76 This has not been added in pci_device_ids of src/third_party/coreboot/src/soc/intel/common/block/cnvi/cnvi.c is this intentional too? -- To view, visit https://review.coreboot.org/c/coreboot/+/87262?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4bc7a8ea898ee30d565a95b9f85d6f19886bcffb Gerrit-Change-Number: 87262 Gerrit-PatchSet: 10 Gerrit-Owner: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Reviewer: Avi Uday <aviuday(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-Attention: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Attention: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Comment-Date: Mon, 21 Apr 2025 06:38:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: soc/intel: Add Wildcat Lake CPU and PCIE device IDs
by Appukuttan V K (Code Review) 21 Apr '25

21 Apr '25

Attention is currently required from: Avi Uday, Intel coreboot Reviewers, Nick Vaccaro, Sowmya Aralguppe, Usha P, Varun Upadhyay. Appukuttan V K has posted comments on this change by Appukuttan V K. ( https://review.coreboot.org/c/coreboot/+/87262?usp=email ) Change subject: soc/intel: Add Wildcat Lake CPU and PCIE device IDs ...................................................................... Patch Set 9: (2 comments) File src/include/device/pci_ids.h: https://review.coreboot.org/c/coreboot/+/87262/comment/1071b025_195d1c66?us… : PS8, Line 4804: > I see that some devices like these ones have not been added to the corresponding pci_device_ids[]. […] Thankyou. Removed other CSE function device IDs, we are using only function 0. File src/soc/intel/common/block/uart/uart.c: https://review.coreboot.org/c/coreboot/+/87262/comment/4946bfbf_39310102?us… : PS8, Line 362: static const unsigned short pci_device_ids[] = { > Should the UART devices not be added here too? Done. Missed to add this earlier. -- To view, visit https://review.coreboot.org/c/coreboot/+/87262?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4bc7a8ea898ee30d565a95b9f85d6f19886bcffb Gerrit-Change-Number: 87262 Gerrit-PatchSet: 9 Gerrit-Owner: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Reviewer: Avi Uday <aviuday(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-Attention: Avi Uday <aviuday(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Attention: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Comment-Date: Mon, 21 Apr 2025 06:31:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Avi Uday <aviuday(a)google.com>

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[M] Change in coreboot[main]: soc/intel: Add Wildcat Lake CPU and PCIE device IDs
by Appukuttan V K (Code Review) 21 Apr '25

21 Apr '25

Attention is currently required from: Appukuttan V K, Intel coreboot Reviewers, Nick Vaccaro, Sowmya Aralguppe, Usha P, Varun Upadhyay. Hello Avi Uday, Intel coreboot Reviewers, Nick Vaccaro, Sowmya Aralguppe, Subrata Banik, Usha P, Varun Upadhyay, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/87262?usp=email to look at the new patch set (#9). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel: Add Wildcat Lake CPU and PCIE device IDs ...................................................................... soc/intel: Add Wildcat Lake CPU and PCIE device IDs This patch adds Wildcat Lake-specific CPU and PCIE device IDs to the header files. Reference: Wildcat Lake Processor Prelim External Device IDs (820363) BUG=b:394208231 TEST=Verified on Wildcat Lake Simulation Platform Change-Id: I4bc7a8ea898ee30d565a95b9f85d6f19886bcffb Signed-off-by: Appukuttan V K <appukuttan.vk(a)intel.com> --- M src/drivers/intel/ish/ish.c M src/drivers/intel/touch/touch.c M src/include/cpu/intel/cpu_ids.h M src/include/device/pci_ids.h M src/soc/intel/common/block/cnvi/cnvi.c M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/dsp/dsp.c M src/soc/intel/common/block/dtt/dtt.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/hda/hda.c M src/soc/intel/common/block/i2c/i2c.c M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/common/block/p2sb/ioe_p2sb.c M src/soc/intel/common/block/p2sb/p2sb.c M src/soc/intel/common/block/pcie/pcie.c M src/soc/intel/common/block/pmc/pmc.c M src/soc/intel/common/block/smbus/smbus.c M src/soc/intel/common/block/spi/spi.c M src/soc/intel/common/block/sram/sram.c M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/common/block/tracehub/tracehub.c M src/soc/intel/common/block/uart/uart.c M src/soc/intel/common/block/usb4/usb4.c M src/soc/intel/common/block/usb4/xhci.c M src/soc/intel/common/block/xhci/xhci.c 26 files changed, 192 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/87262/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/87262?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4bc7a8ea898ee30d565a95b9f85d6f19886bcffb Gerrit-Change-Number: 87262 Gerrit-PatchSet: 9 Gerrit-Owner: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Reviewer: Avi Uday <aviuday(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-Attention: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Attention: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Usha P <usha.p(a)intel.com>

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[L] Change in coreboot[main]: cpu/x86/smm/smm_module_handler: Protect SMM using Nx bit
by Patrick Rudolph (Code Review) 21 Apr '25

21 Apr '25

Attention is currently required from: Jérémy Compostella, Shuo Liu. Patrick Rudolph has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/87357?usp=email ) Change subject: cpu/x86/smm/smm_module_handler: Protect SMM using Nx bit ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/87357/comment/eb12197e_84cf9c4e?us… : PS3, Line 31: TEST: Booted on qemu x86_64 enabled. > Were you able, through hack and dedicated tests, to verify that the policies are set up properly? Fo […] I confirmed that NX bit is working. Stack and heap are no longer executable. My tests also showed that RO memory is still writable. Will investigate why (if that's an QEMU issue or a bug in the code). -- To view, visit https://review.coreboot.org/c/coreboot/+/87357?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I49d513e53e6f96449bdc92cc0335247df7aa7871 Gerrit-Change-Number: 87357 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Comment-Date: Mon, 21 Apr 2025 06:23:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com>

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