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Change in coreboot[master]: soc/mediatek/mt8192: Add dpm loader

by Yidi Lin (Code Review)

Hello Duan huayang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46393 to review the following change. Change subject: soc/mediatek/mt8192: Add dpm loader ...................................................................... soc/mediatek/mt8192: Add dpm loader BUG=none TEST=Boots correctly on Asurada Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> Change-Id: I16b341ad63940b45b886c4a7fd733c1970624e40 --- M src/mainboard/google/asurada/mainboard.c M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/dpm.c M src/soc/mediatek/mt8192/include/soc/addressmap.h A src/soc/mediatek/mt8192/include/soc/dpm.h 5 files changed, 136 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/46393/1 diff --git a/src/mainboard/google/asurada/mainboard.c b/src/mainboard/google/asurada/mainboard.c index 7b3ef22..677e917 100644 --- a/src/mainboard/google/asurada/mainboard.c +++ b/src/mainboard/google/asurada/mainboard.c @@ -5,6 +5,7 @@ #include <device/device.h> #include <device/mmio.h> #include <lib.h> +#include <soc/dpm.h> #include <soc/gpio_common.h> #include <soc/spm.h> #include <soc/usb.h> @@ -79,6 +80,9 @@ register_reset_to_bl31(); + if (dpm_init()) + printk(BIOS_ERR, "dpm init fail, system can't do DVFS switch\n"); + if (spm_init()) printk(BIOS_ERR, "spm init fail, system suspend may stuck\n"); } diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index 59d105c..5fc90a8 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -37,6 +37,7 @@ ramstage-y += ../common/gpio.c gpio.c ramstage-y += emi.c ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c +ramstage-y += dpm.c ramstage-y += spm.c ramstage-y += ../common/mmu_operations.c mmu_operations.c ramstage-y += ../common/mtcmos.c mtcmos.c @@ -48,6 +49,16 @@ MT8192_BLOB_DIR := 3rdparty/blobs/soc/mediatek/mt8192 +cbfs-files-y += dpm.dm +dpm.dm-file := $(MT8192_BLOB_DIR)/dpm.dm +dpm.dm-type := raw +dpm.dm-compression := $(CBFS_COMPRESS_FLAG) + +cbfs-files-y += dpm.pm +dpm.pm-file := $(MT8192_BLOB_DIR)/dpm.pm +dpm.pm-type := raw +dpm.pm-compression := $(CBFS_COMPRESS_FLAG) + cbfs-files-y += spm_firmware.bin spm_firmware.bin-file := $(MT8192_BLOB_DIR)/spm_firmware.bin spm_firmware.bin-type := raw diff --git a/src/soc/mediatek/mt8192/dpm.c b/src/soc/mediatek/mt8192/dpm.c new file mode 100644 index 0000000..7e018b5 --- /dev/null +++ b/src/soc/mediatek/mt8192/dpm.c @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <cbfs.h> +#include <console/console.h> +#include <delay.h> +#include <device/mmio.h> +#include <soc/dpm.h> +#include <timer.h> + +#define DM_BUF_SIZE (2 * KiB) +#define PM_BUF_SIZE (20 * KiB) + +static u8 dpm_dm_bin[DM_BUF_SIZE] __aligned(8); +static u8 dpm_pm_bin[PM_BUF_SIZE] __aligned(8); +static void *dpm_pm_reg = (void *)DPM_PM_SRAM_BASE; +static void *dpm_dm_reg = (void *)DPM_DM_SRAM_BASE; + +static int dpm_load_firmware(void) +{ + const char *dm_file_name = "dpm.dm"; + const char *pm_file_name = "dpm.pm"; + size_t dm_file_size, pm_file_size; + + dm_file_size = cbfs_boot_load_file(dm_file_name, dpm_dm_bin, + sizeof(dpm_dm_bin), CBFS_TYPE_RAW); + if (dm_file_size == 0) { + printk(BIOS_ERR, "binary %s not found\n", dm_file_name); + return -1; + } + + pm_file_size = cbfs_boot_load_file(pm_file_name, dpm_pm_bin, + sizeof(dpm_pm_bin), CBFS_TYPE_RAW); + if (pm_file_size == 0) { + printk(BIOS_ERR, "binary %s not found\n", pm_file_name); + return -2; + } + printk(BIOS_INFO, "dm_file_size:%d, pm_file_size:%d\n", + (int)dm_file_size, (int)pm_file_size); + + /* config DPM SRAM layout */ + write32(&mtk_dpm->sw_rstn, read32(&mtk_dpm->sw_rstn) | 0x10000000); + + /* copy PM DM to DPM_SRAM */ + memcpy(dpm_pm_reg, dpm_pm_bin, pm_file_size); + memcpy(dpm_dm_reg, dpm_dm_bin, dm_file_size); + + /* write bootargs */ + write32(&mtk_dpm->twam_window_len, 0x0); + write32(&mtk_dpm->twam_mon_type, 0x0); + + /* free RST */ + write32(&mtk_dpm->sw_rstn, read32(&mtk_dpm->sw_rstn) | 0x1); + + return 0; +} + +int dpm_init(void) +{ + struct stopwatch sw; + stopwatch_init(&sw); + + if (dpm_load_firmware()) { + printk(BIOS_ERR, "DPM: firmware is not ready\n"); + return -1; + } + + printk(BIOS_INFO, "DPM: load finish in %ld msecs\n", + stopwatch_duration_msecs(&sw)); + + return 0; +} diff --git a/src/soc/mediatek/mt8192/include/soc/addressmap.h b/src/soc/mediatek/mt8192/include/soc/addressmap.h old mode 100755 new mode 100644 index 9864e5b..5f49fe5 --- a/src/soc/mediatek/mt8192/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8192/include/soc/addressmap.h @@ -29,6 +29,9 @@ PMICSPI_MST_BASE = IO_PHYS + 0x00028000, SPMI_MST_BASE = IO_PHYS + 0x00029000, AUXADC_BASE = IO_PHYS + 0x01001000, + DPM_PM_SRAM_BASE = IO_PHYS + 0x00900000, + DPM_DM_SRAM_BASE = IO_PHYS + 0x00920000, + DPM_CFG_BASE = IO_PHYS + 0x00940000, UART0_BASE = IO_PHYS + 0x01002000, SPI0_BASE = IO_PHYS + 0x0100A000, SPI1_BASE = IO_PHYS + 0x01010000, diff --git a/src/soc/mediatek/mt8192/include/soc/dpm.h b/src/soc/mediatek/mt8192/include/soc/dpm.h new file mode 100644 index 0000000..5763dab --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/dpm.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8192_DPM_H__ +#define __SOC_MEDIATEK_MT8192_DPM_H__ + +#include <soc/addressmap.h> +#include <stdint.h> +#include <types.h> + +#define DPM_DM_OFFSET 0x8000 /* 32KB */ + +struct dpm_regs { + u32 sw_rstn; + u32 rsvd_0[3072]; + u32 mclk_div; + u32 rsvd_1[3071]; + u32 twam_window_len; + u32 twam_mon_type; + u32 rsvd_2[1022]; + u32 low_power_cfg_0; + u32 low_power_cfg_1; + u32 rsvd_3[1]; + u32 fsm_out_ctrl_0; + u32 rsvd_4[8]; + u32 fsm_cfg_1; + u32 low_power_cfg_3; + u32 dfd_dbug_0; + u32 rsvd_5[28]; + u32 status_4; +}; + +check_member(dpm_regs, mclk_div, 0x3004); +check_member(dpm_regs, twam_window_len, 0x6004); +check_member(dpm_regs, low_power_cfg_0, 0x7004); +check_member(dpm_regs, low_power_cfg_1, 0x7008); +check_member(dpm_regs, fsm_out_ctrl_0, 0x7010); +check_member(dpm_regs, fsm_cfg_1, 0x7034); +check_member(dpm_regs, low_power_cfg_3, 0x7038); +check_member(dpm_regs, dfd_dbug_0, 0x703C); +check_member(dpm_regs, status_4, 0x70B0);; + +int dpm_init(void); + +#define mtk_dpm ((struct dpm_regs *)DPM_CFG_BASE) + +#endif /* __SOC_MEDIATEK_MT8192_DPM_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/46393 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I16b341ad63940b45b886c4a7fd733c1970624e40 Gerrit-Change-Number: 46393 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: dedede: Create metaknight variant

by Tim Chen (Code Review)

Hello Tim Chen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46568 to review the following change. Change subject: dedede: Create metaknight variant ...................................................................... dedede: Create metaknight variant Create the metaknight variant of the waddledee reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.2.0). BUG=b:169813211 BRANCH=None TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_METAKNIGHT Signed-off-by: Tim Chen <tim-chen(a)quanta.corp-partner.google.com> Change-Id: Ia2e473eb1d0a2c819b874e497de0823fca75645a --- M src/mainboard/google/dedede/Kconfig M src/mainboard/google/dedede/Kconfig.name A src/mainboard/google/dedede/variants/metaknight/include/variant/ec.h A src/mainboard/google/dedede/variants/metaknight/include/variant/gpio.h A src/mainboard/google/dedede/variants/metaknight/memory/Makefile.inc A src/mainboard/google/dedede/variants/metaknight/memory/dram_id.generated.txt A src/mainboard/google/dedede/variants/metaknight/memory/mem_parts_used.txt A src/mainboard/google/dedede/variants/metaknight/overridetree.cb 8 files changed, 77 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/46568/1 diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index 377702d..a273c9c 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -94,6 +94,7 @@ default "Waddledee" if BOARD_GOOGLE_WADDLEDEE default "Wheelie" if BOARD_GOOGLE_WHEELIE default "Magolor" if BOARD_GOOGLE_MAGOLOR + default "Metaknight" if BOARD_GOOGLE_METAKNIGHT config MAX_CPUS int @@ -123,5 +124,6 @@ default "waddledee" if BOARD_GOOGLE_WADDLEDEE default "wheelie" if BOARD_GOOGLE_WHEELIE default "magolor" if BOARD_GOOGLE_MAGOLOR + default "metaknight" if BOARD_GOOGLE_METAKNIGHT endif #BOARD_GOOGLE_BASEBOARD_DEDEDE diff --git a/src/mainboard/google/dedede/Kconfig.name b/src/mainboard/google/dedede/Kconfig.name index 563a309..689df68 100644 --- a/src/mainboard/google/dedede/Kconfig.name +++ b/src/mainboard/google/dedede/Kconfig.name @@ -63,3 +63,8 @@ select BASEBOARD_DEDEDE_LAPTOP select DRIVERS_INTEL_MIPI_CAMERA select SOC_INTEL_COMMON_BLOCK_IPU + +config BOARD_GOOGLE_METAKNIGHT + bool "-> Metaknight" + select BOARD_GOOGLE_BASEBOARD_DEDEDE + select BASEBOARD_DEDEDE_LAPTOP diff --git a/src/mainboard/google/dedede/variants/metaknight/include/variant/ec.h b/src/mainboard/google/dedede/variants/metaknight/include/variant/ec.h new file mode 100644 index 0000000..08870e0 --- /dev/null +++ b/src/mainboard/google/dedede/variants/metaknight/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/dedede/variants/metaknight/include/variant/gpio.h b/src/mainboard/google/dedede/variants/metaknight/include/variant/gpio.h new file mode 100644 index 0000000..9078664 --- /dev/null +++ b/src/mainboard/google/dedede/variants/metaknight/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <baseboard/gpio.h> + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/dedede/variants/metaknight/memory/Makefile.inc b/src/mainboard/google/dedede/variants/metaknight/memory/Makefile.inc new file mode 100644 index 0000000..b0ca222 --- /dev/null +++ b/src/mainboard/google/dedede/variants/metaknight/memory/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! +## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. + +SPD_SOURCES = placeholder.spd.hex diff --git a/src/mainboard/google/dedede/variants/metaknight/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/metaknight/memory/dram_id.generated.txt new file mode 100644 index 0000000..fa24790 --- /dev/null +++ b/src/mainboard/google/dedede/variants/metaknight/memory/dram_id.generated.txt @@ -0,0 +1 @@ +DRAM Part Name ID to assign diff --git a/src/mainboard/google/dedede/variants/metaknight/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/metaknight/memory/mem_parts_used.txt new file mode 100644 index 0000000..59381dc --- /dev/null +++ b/src/mainboard/google/dedede/variants/metaknight/memory/mem_parts_used.txt @@ -0,0 +1,6 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# gen_part_id tool from util/spd_tools/lp4x +# See util/spd_tools/lp4x/README.md for more details and instructions. + +# Part Name diff --git a/src/mainboard/google/dedede/variants/metaknight/overridetree.cb b/src/mainboard/google/dedede/variants/metaknight/overridetree.cb new file mode 100644 index 0000000..404024b --- /dev/null +++ b/src/mainboard/google/dedede/variants/metaknight/overridetree.cb @@ -0,0 +1,42 @@ +chip soc/intel/jasperlake + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | Trackpad | + #| I2C1 | Digitizer | + #| I2C2 | Touchscreen | + #| I2C3 | Camera | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + }, + }" + + device domain 0 on + device pci 15.0 on end + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/46568 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia2e473eb1d0a2c819b874e497de0823fca75645a Gerrit-Change-Number: 46568 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Chen <Tim-Chen(a)quantatw.com> Gerrit-Reviewer: Tim Chen <tim-chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer/variants/eldrid: disable Fan Performance Control an...

by Nick Chen (Code Review)

Nick Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45860 ) Change subject: mb/google/volteer/variants/eldrid: disable Fan Performance Control and Passive Policy ...................................................................... mb/google/volteer/variants/eldrid: disable Fan Performance Control and Passive Policy add dptf option and disable fan relate control from overridetree.cb BUG=b:167931578 Signed-off-by: nick_xr_chen <nick_xr_chen(a)wistron.corp-partner.google.com> Change-Id: I99e429b90ed7de08385fe51ca742865b1266eef9 --- M src/mainboard/google/volteer/variants/eldrid/overridetree.cb 1 file changed, 69 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/45860/1 diff --git a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb index 6e9d743..1aef702 100644 --- a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb +++ b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb @@ -58,7 +58,75 @@ }" device domain 0 on - device pci 04.0 off end + device pci 04.0 on + # Default DPTF Policy for all Volteer boards if not overridden + chip drivers/intel/dptf + ## Active Policy + register "policies.active" = "{ + [0] = {.target = DPTF_CPU, + .thresholds = {TEMP_PCT(85, 90), + TEMP_PCT(80, 69), + TEMP_PCT(75, 56), + TEMP_PCT(70, 46), + TEMP_PCT(65, 36),}}, + [1] = {.target = DPTF_TEMP_SENSOR_0, + .thresholds = {TEMP_PCT(50, 90), + TEMP_PCT(47, 69), + TEMP_PCT(45, 56), + TEMP_PCT(42, 46), + TEMP_PCT(39, 36),}}, + [2] = {.target = DPTF_TEMP_SENSOR_1, + .thresholds = {TEMP_PCT(50, 90), + TEMP_PCT(47, 69), + TEMP_PCT(45, 56), + TEMP_PCT(42, 46), + TEMP_PCT(39, 36),}}, + [3] = {.target = DPTF_TEMP_SENSOR_2, + .thresholds = {TEMP_PCT(50, 90), + TEMP_PCT(47, 69), + TEMP_PCT(45, 56), + TEMP_PCT(42, 46), + TEMP_PCT(39, 36),}}, + [4] = {.target = DPTF_TEMP_SENSOR_3, + .thresholds = {TEMP_PCT(50, 90), + TEMP_PCT(47, 69), + TEMP_PCT(45, 56), + TEMP_PCT(42, 46), + TEMP_PCT(39, 36),}}}" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 75, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 75, SHUTDOWN), + [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 75, SHUTDOWN)}" + + ## Power Limits Control + # 10-15W PL1 in 200mW increments, avg over 28-32s interval + # PL2 is fixed at 64W, avg over 28-32s interval + register "controls.power_limits" = "{ + .pl1 = {.min_power = 3000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200,}, + .pl2 = {.min_power = 15000, + .max_power = 60000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000,}}" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 1700 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 }}" + + device generic 0 on end + end + end device pci 15.0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" -- To view, visit https://review.coreboot.org/c/coreboot/+/45860 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I99e429b90ed7de08385fe51ca742865b1266eef9 Gerrit-Change-Number: 45860 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Chen <nick_xr_chen(a)wistron.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer/var/terrador: Update DPTF parameters

by David Wu (Code Review)

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46487 ) Change subject: mb/google/volteer/var/terrador: Update DPTF parameters ...................................................................... mb/google/volteer/var/terrador: Update DPTF parameters Update DPTF parameters for terrador BUG=b:171019363,b:170699797 BRANCH=volteer TEST=build and verify by thermal team Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: I19935ca98ec7a078869e73d65ea471df70f37121 --- M src/mainboard/google/volteer/variants/terrador/overridetree.cb 1 file changed, 44 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/46487/1 diff --git a/src/mainboard/google/volteer/variants/terrador/overridetree.cb b/src/mainboard/google/volteer/variants/terrador/overridetree.cb index 1ccdb87..56b4fbd 100644 --- a/src/mainboard/google/volteer/variants/terrador/overridetree.cb +++ b/src/mainboard/google/volteer/variants/terrador/overridetree.cb @@ -17,6 +17,50 @@ register "SaGv" = "SaGv_Disabled" device domain 0 on + device pci 04.0 on + # Default DPTF Policy for all Volteer boards if not overridden + chip drivers/intel/dptf + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 89, 1000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 65, 6000), + [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_0, 65, 6000), + [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 65, 6000), + [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 65, 6000)}" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 100, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 75, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 75, SHUTDOWN), + [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 75, SHUTDOWN)}" + + ## Power Limits Control + # 3-9W PL1 in 200mW increments, avg over 28-32s interval + # PL2 ranges from 9 to 40W, avg over 28-32s interval + register "controls.power_limits" = "{ + .pl1 = {.min_power = 3000, + .max_power = 9000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200,}, + .pl2 = {.min_power = 9000, + .max_power = 40000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000,}}" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 1700 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 }}" + + device generic 0 on end + end + end # DPTF 0x9A03 device ref i2c0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" -- To view, visit https://review.coreboot.org/c/coreboot/+/46487 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19935ca98ec7a078869e73d65ea471df70f37121 Gerrit-Change-Number: 46487 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/zork: update USB 2.0 controller Lane Parameter for berknip

by Kevin Chiu (Code Review)

Kevin Chiu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46545 ) Change subject: mb/google/zork: update USB 2.0 controller Lane Parameter for berknip ...................................................................... mb/google/zork: update USB 2.0 controller Lane Parameter for berknip Enhance USB 2.0 C0/C1 A0/A1 HS DC Voltage Level. BUG=b:166398726 BRANCH=zork TEST=1. emerge-zork coreboot 2. check U2 register is set correctly. Change-Id: I69d942605c6d43ece0d71f67df3a5e00b998219b Signed-off-by: Kevin Chiu <kevin.chiu(a)quantatw.com> --- M src/mainboard/google/zork/variants/berknip/overridetree.cb 1 file changed, 48 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/46545/1 diff --git a/src/mainboard/google/zork/variants/berknip/overridetree.cb b/src/mainboard/google/zork/variants/berknip/overridetree.cb index 674d557..e294168 100644 --- a/src/mainboard/google/zork/variants/berknip/overridetree.cb +++ b/src/mainboard/google/zork/variants/berknip/overridetree.cb @@ -21,6 +21,54 @@ register "telemetry_vddcr_soc_offset" = "0" # End : OPN Performance Configuration + #USB 2.0 strength + register "usb_2_port_tune_params[0]" = "{ + .com_pds_tune = 0x03, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x03, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .rx_vref_tune = 0xf, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + + register "usb_2_port_tune_params[1]" = "{ + .com_pds_tune = 0x03, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x03, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .rx_vref_tune = 0xf, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + + register "usb_2_port_tune_params[2]" = "{ + .com_pds_tune = 0x03, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x03, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .rx_vref_tune = 0xf, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + + register "usb_2_port_tune_params[3]" = "{ + .com_pds_tune = 0x03, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x03, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .rx_vref_tune = 0xf, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" # Enable I2C2 for trackpad, touchscreen, pen at 400kHz register "i2c[2]" = "{ -- To view, visit https://review.coreboot.org/c/coreboot/+/46545 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69d942605c6d43ece0d71f67df3a5e00b998219b Gerrit-Change-Number: 46545 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/zork: update USB 2.0 controller Lane Parameter for morphius

by Kevin Chiu (Code Review)

Kevin Chiu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46537 ) Change subject: mb/google/zork: update USB 2.0 controller Lane Parameter for morphius ...................................................................... mb/google/zork: update USB 2.0 controller Lane Parameter for morphius Enhance USB 2.0 HS DC Voltage Level BUG=b:162614573 BRANCH=zork TEST=emerge-zork coreboot Signed-off-by: Kevin Chiu <kevin.chiu(a)quantatw.com> Change-Id: I278cc0aaddbc9fce595bf57ca69ee8abfc9f5659 --- M src/mainboard/google/zork/variants/morphius/overridetree.cb 1 file changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/46537/1 diff --git a/src/mainboard/google/zork/variants/morphius/overridetree.cb b/src/mainboard/google/zork/variants/morphius/overridetree.cb index ecadb07..62b08fb 100644 --- a/src/mainboard/google/zork/variants/morphius/overridetree.cb +++ b/src/mainboard/google/zork/variants/morphius/overridetree.cb @@ -35,6 +35,19 @@ .ports.xhci0_port2 = 1, /* Left USB3A port 2 */ }" + #USB 2.0 strength + register "usb_2_port_tune_params[3]" = "{ + .com_pds_tune = 0x03, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x03, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .rx_vref_tune = 0xf, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + # Enable I2C2 for trackpad, touchscreen, pen at 400kHz register "i2c[2]" = "{ .speed = I2C_SPEED_FAST, -- To view, visit https://review.coreboot.org/c/coreboot/+/46537 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I278cc0aaddbc9fce595bf57ca69ee8abfc9f5659 Gerrit-Change-Number: 46537 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-MessageType: newchange

2 hours, 15 minutes

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Change in coreboot[master]: soc/mediatek/mt8192: Do dramc software impedance calibration

by CK HU (Code Review)

Hello Duan huayang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44704 to review the following change. Change subject: soc/mediatek/mt8192: Do dramc software impedance calibration ...................................................................... soc/mediatek/mt8192: Do dramc software impedance calibration Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> Change-Id: I2c6ffe885717997540a0a9721310e355a3b6a87d --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/dramc_pi_calibration_api.c M src/soc/mediatek/mt8192/dramc_pi_main.c 3 files changed, 184 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/44704/1 diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index e82f182..bf819ec 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -16,7 +16,7 @@ verstage-y += ../common/uart.c romstage-y += ../common/cbmem.c -romstage-y += dramc_pi_main.c dramc_pi_basic_api.c dramc_utility.c +romstage-y += dramc_pi_main.c dramc_pi_basic_api.c dramc_pi_calibration_api.c dramc_utility.c romstage-y += emi.c romstage-y += flash_controller.c romstage-y += ../common/gpio.c gpio.c diff --git a/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c new file mode 100644 index 0000000..04ff5d7 --- /dev/null +++ b/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c @@ -0,0 +1,180 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <string.h> +#include <soc/dramc_pi_api.h> +#include <soc/dramc_register.h> +#include <timer.h> + +static const u8 imp_vref_sel[ODT_MAX][IMP_DRV_MAX] = { + /* DRVP DRVN ODTP ODTN */ + [ODT_OFF] = {0x37, 0x33, 0x00, 0x37}, + [ODT_ON] = {0x3a, 0x33, 0x00, 0x3a}, +}; + +static void dramc_imp_cal_vref_sel(dram_odt_state odt, imp_drv_type drv_type) +{ + u8 vref_tmp = 0; + vref_tmp = imp_vref_sel[odt][drv_type]; + + switch (drv_type) { + case DRVP: + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd12, + SHU_CA_CMD12_RG_RIMP_VREF_SEL_DRVP, vref_tmp); + break; + case DRVN: + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd12, + SHU_CA_CMD12_RG_RIMP_VREF_SEL_DRVN, vref_tmp); + break; + case ODTN: + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd12, + SHU_CA_CMD12_RG_RIMP_VREF_SEL_ODTN, vref_tmp); + break; + default: + die("Can't support drv_type %d\n", drv_type); + break; + } +} + +static u32 dramc_sw_imp_cal_result(imp_drv_type drv_type) +{ + u32 drive = 0, cal_res = 0; + u32 change = (drv_type == DRVP) ? 1: 0; + + const char *drv_str = NULL; + switch (drv_type) { + case DRVP: + drv_str = "DRVP"; + break; + case DRVN: + drv_str = "DRVN"; + break; + case ODTP: + drv_str = "ODTP"; + break; + case ODTN: + drv_str = "ODTN"; + break; + default: + die("Can't support drv_type %d\n", drv_type); + break; + } + + for (drive = 0; drive < 32; drive++) { + if (drv_type == DRVP) + SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_impcal1, + SHU_MISC_IMPCAL1_IMPDRVP, drive); + else if (drv_type == DRVN || drv_type == ODTN) + SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_impcal1, + SHU_MISC_IMPCAL1_IMPDRVN, drive); + + udelay(1); + cal_res = READ32_BITFIELD(&ch[0].phy_nao.misc_phy_rgs_cmd, + MISC_PHY_RGS_CMD_RGS_RIMPCALOUT); + dramc_dbg("OCD %s=%d ,CALOUT=%d\n", drv_str, drive, cal_res); + + if (cal_res == change) { + dramc_info("%s calibration OK! result=%d\n", drv_str, drive); + break; + } + } + + if (drive == 32) { + drive = 31; + dramc_err("OCD %s calibration FAIL! %s=%d\n", drv_str, drv_str, drive); + } + + return drive; +} + +void dramc_sw_impedance_cal(dram_odt_state odt, struct dram_impedance *imp) +{ + u8 chn = 0, i_chn, enp, enn; + u32 bc_bak, impcal_bak, cal_res = 0; + u32 drvp_result = 0xff, odtn_result = 0xff, drvn_result = 0xff; + + bc_bak = dramc_get_broadcast(); + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + for (i_chn = 0; i_chn < CHANNEL_MAX; i_chn++) { + SET32_BITFIELDS(&ch[i_chn].phy_ao.misc_lp_ctrl, + MISC_LP_CTRL_RG_ARDMSUS_10, 0x0, + MISC_LP_CTRL_RG_ARDMSUS_10_LP_SEL, 0x0, + MISC_LP_CTRL_RG_RIMP_DMSUS_10, 0x0, + MISC_LP_CTRL_RG_RIMP_DMSUS_10_LP_SEL, 0x0); + SET32_BITFIELDS(&ch[i_chn].phy_ao.misc_impcal, MISC_IMPCAL_IMPCAL_HW, 0); + } + + impcal_bak = read32(&ch[chn].phy_ao.misc_impcal); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_imp_ctrl1, MISC_IMP_CTRL1_RG_RIMP_PRE_EN, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_impcal, + MISC_IMPCAL_IMPCAL_CALI_ENN, 0, + MISC_IMPCAL_IMPCAL_IMPPDP, 1, + MISC_IMPCAL_IMPCAL_IMPPDN, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_imp_ctrl1, + MISC_IMP_CTRL1_RG_IMP_EN, 1, + MISC_IMP_CTRL1_RG_RIMP_DDR3_SEL, 0, + MISC_IMP_CTRL1_RG_RIMP_VREF_EN, 1, + MISC_IMP_CTRL1_RG_RIMP_DDR4_SEL, 1); + udelay(1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_impcal, MISC_IMPCAL_IMPCAL_CALI_EN, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_misc_impcal1, + SHU_MISC_IMPCAL1_IMPDRVN, 0, + SHU_MISC_IMPCAL1_IMPDRVP, 0); + + for (imp_drv_type drv_type = DRVP; drv_type < IMP_DRV_MAX; drv_type++) { + if (drv_type == ODTP) + continue; + dramc_imp_cal_vref_sel(odt, drv_type); + + switch (drv_type) { + case DRVP: + enp = 0x1; + enn = 0x0; + drvp_result = 0; + break; + case DRVN: + case ODTN: + enp = 0x0; + enn = (drv_type == DRVN) ? 0x0 : 0x1; + break; + default: + die("Can't support drv_type %d\n", drv_type); + break; + } + + SET32_BITFIELDS(&ch[chn].phy_ao.misc_impcal, + MISC_IMPCAL_IMPCAL_CALI_ENP, enp); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_impcal, + MISC_IMPCAL_IMPCAL_CALI_ENN, enn); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_misc_impcal1, + SHU_MISC_IMPCAL1_IMPDRVP, drvp_result); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_cmd12, + SHU_CA_CMD12_RG_RIMP_DRV05, 0); + + cal_res = dramc_sw_imp_cal_result(drv_type); + switch (drv_type) { + case DRVP: + drvp_result = cal_res; + break; + case DRVN: + drvn_result = cal_res; + break; + case ODTN: + odtn_result = cal_res; + break; + default: + die("Can't support drv_type %d\n", drv_type); + break; + } + } + + imp->result[odt][DRVP] = drvp_result; + imp->result[odt][DRVN] = drvn_result; + imp->result[odt][ODTP] = 0; + imp->result[odt][ODTN] = odtn_result; + + dramc_info("freq_region=%d, Reg: DRVP=%d, DRVN=%d, ODTN=%d\n", + odt, drvp_result, drvn_result, odtn_result); + + write32(&ch[chn].phy_ao.misc_impcal, impcal_bak); + dramc_set_broadcast(bc_bak); +} diff --git a/src/soc/mediatek/mt8192/dramc_pi_main.c b/src/soc/mediatek/mt8192/dramc_pi_main.c index 184479d..355cc9d 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_main.c +++ b/src/soc/mediatek/mt8192/dramc_pi_main.c @@ -73,6 +73,9 @@ emi_mdl_init(cali.emi_config); dramc_set_broadcast(bc_bak); + dramc_sw_impedance_cal(ODT_OFF, &cali.impedance); + dramc_sw_impedance_cal(ODT_ON, &cali.impedance); + if (ddr_info->config_dvfs == DRAMC_ENABLE_DVFS) k_shuffle_end = CALI_SEQ_MAX; else -- To view, visit https://review.coreboot.org/c/coreboot/+/44704 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2c6ffe885717997540a0a9721310e355a3b6a87d Gerrit-Change-Number: 44704 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

2 hours, 17 minutes

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Change in coreboot[master]: mb/google/asurada: Init dram in romstage

by CK HU (Code Review)

Hello Duan huayang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44568 to review the following change. Change subject: mb/google/asurada: Init dram in romstage ...................................................................... mb/google/asurada: Init dram in romstage Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> Change-Id: Ied350570a695cca1424a6562e41120bcaf467797 --- M src/mainboard/google/asurada/Makefile.inc A src/mainboard/google/asurada/romstage.c 2 files changed, 50 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/44568/1 diff --git a/src/mainboard/google/asurada/Makefile.inc b/src/mainboard/google/asurada/Makefile.inc index 8395e4a..c742539 100644 --- a/src/mainboard/google/asurada/Makefile.inc +++ b/src/mainboard/google/asurada/Makefile.inc @@ -8,6 +8,7 @@ romstage-y += memlayout.ld romstage-y += boardid.c +romstage-y += romstage.c romstage-y += sdram_configs.c ramstage-y += memlayout.ld diff --git a/src/mainboard/google/asurada/romstage.c b/src/mainboard/google/asurada/romstage.c new file mode 100644 index 0000000..8fa2f38 --- /dev/null +++ b/src/mainboard/google/asurada/romstage.c @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/stages.h> +#include <console/console.h> +#include <fmap.h> +#include <soc/dramc_param.h> +#include <soc/emi.h> +#include <soc/mmu_operations.h> + +/* This must be defined in chromeos.fmd in same name and size. */ +#define CALIBRATION_REGION "RW_DDR_TRAINING" +#define CALIBRATION_REGION_SIZE 0x2000 + +_Static_assert(sizeof(struct dramc_param) <= CALIBRATION_REGION_SIZE, + "sizeof(struct dramc_param) exceeds " CALIBRATION_REGION); + +static bool read_calibration_data_from_flash(struct dramc_param *dparam) +{ + const size_t length = sizeof(*dparam); + size_t ret = fmap_read_area(CALIBRATION_REGION, dparam, length); + printk(BIOS_DEBUG, "read data from flash, ret=%#lx, length=%#lx\n", ret, length); + + return ret == length; +} + +static bool write_calibration_data_to_flash(const struct dramc_param *dparam) +{ + const size_t length = sizeof(*dparam); + size_t ret = fmap_overwrite_area(CALIBRATION_REGION, dparam, length); + printk(BIOS_DEBUG, "write data from flash, ret=%#lx, length=%#lx\n", ret, length); + + return ret == length; +} + +/* dramc_param is ~2K and too large to fit in stack. */ +static struct dramc_param dramc_parameter = {0x0}; + +static struct dramc_param_ops dparam_ops = { + .param = &dramc_parameter, + .read_from_flash = &read_calibration_data_from_flash, + .write_to_flash = &write_calibration_data_to_flash, +}; + +void platform_romstage_main(void) +{ + mt_mem_init(&dparam_ops); + mtk_mmu_after_dram(); + printk(BIOS_WARNING, "after mt_mem_init\n"); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/44568 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied350570a695cca1424a6562e41120bcaf467797 Gerrit-Change-Number: 44568 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

2 hours, 19 minutes

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Change in coreboot[master]: ec/google/chromeec: Add wrappers to get/set the voltage

by Yidi Lin (Code Review)

Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46404 ) Change subject: ec/google/chromeec: Add wrappers to get/set the voltage ...................................................................... ec/google/chromeec: Add wrappers to get/set the voltage Add APIs to get and set the voltage for the target regulator. BUG=b:147789962 BRANCH=none TEST=emerge-asurada coreboot Change-Id: I0e56df45fc3309c387b9949534334eadefb616b2 Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> --- M src/ec/google/chromeec/ec.c M src/ec/google/chromeec/ec.h 2 files changed, 64 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/46404/1 diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 82de088..39cf895 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -1616,3 +1616,50 @@ return 0; } + +int google_chromeec_regulator_set_voltage(uint32_t index, uint32_t min_mv, + uint32_t max_mv) +{ + struct ec_params_regulator_set_voltage params = { + .index = index, + .min_mv = min_mv, + .max_mv = max_mv, + }; + struct chromeec_command cmd = { + .cmd_code = EC_CMD_REGULATOR_SET_VOLTAGE, + .cmd_version = 0, + .cmd_data_in = &params, + .cmd_size_in = sizeof(params), + .cmd_data_out = NULL, + .cmd_size_out = 0, + .cmd_dev_index = 0, + }; + + if (google_chromeec_command(&cmd)) + return -1; + + return 0; +} + +int google_chromeec_regulator_get_voltage(uint32_t index, uint32_t *voltage_mv) +{ + struct ec_params_regulator_get_voltage params = { + .index = index, + }; + struct ec_response_regulator_get_voltage resp = {}; + struct chromeec_command cmd = { + .cmd_code = EC_CMD_REGULATOR_GET_VOLTAGE, + .cmd_version = 0, + .cmd_data_in = &params, + .cmd_size_in = sizeof(params), + .cmd_data_out = &resp, + .cmd_size_out = sizeof(resp), + .cmd_dev_index = 0, + }; + + if (google_chromeec_command(&cmd)) + return -1; + + *voltage_mv = resp.voltage_mv; + return 0; +} diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index ad3768c..0e28344 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -353,6 +353,23 @@ */ int google_chromeec_ap_reset(void); +/** + * Set voltage for the voltage regulator within the range specified. + * @param index Regulator ID + * @param min_mv Minimum voltage + * @param max_mv Maximum voltage + * @return 0 on success, -1 on error + */ +int google_chromeec_regulator_set_voltage(uint32_t index, uint32_t min_mv, + uint32_t max_mv); +/** + * Get the currently configured voltage for the voltage regulator. + * @param index Regulator ID + * @param *voltage_mv If successful, voltage_mv is filled with current voltage + * @return 0 on success, -1 on error + */ +int google_chromeec_regulator_get_voltage(uint32_t index, uint32_t *voltage_mv); + #if CONFIG(HAVE_ACPI_TABLES) /** * Writes USB Type-C PD related information to the SSDT -- To view, visit https://review.coreboot.org/c/coreboot/+/46404 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e56df45fc3309c387b9949534334eadefb616b2 Gerrit-Change-Number: 46404 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-MessageType: newchange

2 hours, 21 minutes

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Change in coreboot[master]: soc/mediatek/mt8192: Do the dramc pinmux selection

by CK HU (Code Review)

Hello Duan huayang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44701 to review the following change. Change subject: soc/mediatek/mt8192: Do the dramc pinmux selection ...................................................................... soc/mediatek/mt8192: Do the dramc pinmux selection Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> Change-Id: I7bc1971646a65db8eef5eb5223c919645c6e8ed9 --- M src/soc/mediatek/mt8192/dramc_pi_basic_api.c 1 file changed, 100 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/44701/1 diff --git a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c index 9b1216c..08f3ea4 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c @@ -6,8 +6,108 @@ #include <string.h> #include <timer.h> +const u8 mrr_o1_pinmux_mapping[PINMUX_MAX][CHANNEL_MAX][DQ_DATA_WIDTH] = { + [PINMUX_DSC] = { + [CHANNEL_A] = {0, 1, 7, 6, 4, 5, 2, 3, 9, 8, 11, 10, 14, 15, 13, 12}, + [CHANNEL_B] = {1, 0, 5, 6, 3, 2, 7, 4, 8, 9, 11, 10, 12, 14, 13, 15}, + }, + [PINMUX_LPBK] = { + }, + [PINMUX_EMCP] = { + [CHANNEL_A] = {1, 0, 3, 2, 4, 7, 6, 5,8, 9, 10, 14, 11, 15, 13, 12}, + [CHANNEL_B] = {0, 1, 4, 7, 3, 5, 6, 2,9, 8, 10, 12, 11, 14, 13, 15} + }, +}; + +static void set_rank_info_to_conf(const struct ddr_cali *cali) +{ + u8 value = ((cali->emi_config->cona_val >> 17) & 0x1) ? 0 : 1; + + SET32_BITFIELDS(&ch[0].ao.sa_reserve, + SA_RESERVE_MODE_RK0, cali->cbt_mode[RANK_0], + SA_RESERVE_MODE_RK1, cali->cbt_mode[RANK_1], + SA_RESERVE_SINGLE_RANK, value); +} + +static void get_dram_pinmux_sel(struct ddr_cali *cali) +{ + u32 value = (read32(&mtk_gpio->dram_pinmux_trapping) >> 19) & 0x1; + + if (value) + cali->pinmux_type = PINMUX_DSC; + else + cali->pinmux_type = PINMUX_EMCP; +} + +static void set_MRR_pinmux_mapping(const struct ddr_cali *cali) +{ + const u8 *map; + u32 bc_bak = dramc_get_broadcast(); + + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + map = mrr_o1_pinmux_mapping[get_pinmux_type(cali)][chn]; + SET32_BITFIELDS(&ch[chn].ao.mrr_bit_mux1, + MRR_BIT_MUX1_MRR_BIT0_SEL, map[0], + MRR_BIT_MUX1_MRR_BIT1_SEL, map[1], + MRR_BIT_MUX1_MRR_BIT2_SEL, map[2], + MRR_BIT_MUX1_MRR_BIT3_SEL, map[3]); + SET32_BITFIELDS(&ch[chn].ao.mrr_bit_mux2, + MRR_BIT_MUX2_MRR_BIT4_SEL, map[4], + MRR_BIT_MUX2_MRR_BIT5_SEL, map[5], + MRR_BIT_MUX2_MRR_BIT6_SEL, map[6], + MRR_BIT_MUX2_MRR_BIT7_SEL, map[7]); + SET32_BITFIELDS(&ch[chn].ao.mrr_bit_mux3, + MRR_BIT_MUX3_MRR_BIT8_SEL, map[8], + MRR_BIT_MUX3_MRR_BIT9_SEL, map[9], + MRR_BIT_MUX3_MRR_BIT10_SEL, map[10], + MRR_BIT_MUX3_MRR_BIT11_SEL, map[11]); + SET32_BITFIELDS(&ch[chn].ao.mrr_bit_mux4, + MRR_BIT_MUX4_MRR_BIT12_SEL, map[12], + MRR_BIT_MUX4_MRR_BIT13_SEL, map[13], + MRR_BIT_MUX4_MRR_BIT14_SEL, map[14], + MRR_BIT_MUX4_MRR_BIT15_SEL, map[15]); + } + dramc_set_broadcast(bc_bak); +} + +static void set_dqO1_pinmux_mapping(const struct ddr_cali *cali) +{ + const u8 *map; + u32 bc_bak = dramc_get_broadcast(); + + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + map = mrr_o1_pinmux_mapping[get_pinmux_type(cali)][chn]; + SET32_BITFIELDS(&ch[chn].phy_ao.misc_dq_se_pinmux_ctrl0, + MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ0, map[0], + MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ1, map[1], + MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ2, map[2], + MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ3, map[3], + MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ4, map[4], + MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ5, map[5], + MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ6, map[6], + MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ7, map[7]); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_dq_se_pinmux_ctrl1, + MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ8, map[8], + MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ9, map[9], + MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ10, map[10], + MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ11, map[11], + MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ12, map[12], + MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ13, map[13], + MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ14, map[14], + MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ15, map[15]); + } + + dramc_set_broadcast(bc_bak); +} + void global_option_init(struct ddr_cali *cali) { + set_rank_info_to_conf(cali); + get_dram_pinmux_sel(cali); + set_MRR_pinmux_mapping(cali); + set_dqO1_pinmux_mapping(cali); } void dfs_init_for_calibration(const struct ddr_cali *cali) -- To view, visit https://review.coreboot.org/c/coreboot/+/44701 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7bc1971646a65db8eef5eb5223c919645c6e8ed9 Gerrit-Change-Number: 44701 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

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