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Change subject: mb/google/brox: Update configuration for USB ports
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/google/brox/variants/brox/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/79391/comment/8193f4ec_469a5bb0 :
PS1, Line 3: device ref pch_espi on
: chip ec/google/chromeec
: use conn0 as mux_conn[0]
: use conn1 as mux_conn[1]
: device pnp 0c09.0 on end
: end
: end
Mention that in the commit message?
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Change subject: mb/google/brox: Update configuration for USB ports
......................................................................
Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/79391/comment/d5a4cd7e_46bb792b :
PS1, Line 9: Update brox USB2/3 and TCP ports based on schematics.
Please mention the version.
https://review.coreboot.org/c/coreboot/+/79391/comment/7b0fd8b8_105f10b2 :
PS1, Line 9: and TCP
Also mention in the summary?
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Change subject: mb/google/brox: Update configuration for USB ports
......................................................................
Patch Set 1:
(3 comments)
File src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/79391/comment/aeb2e0f8_90bfe2c8 :
PS1, Line 31: OC_SKIP
OC2 here as well?
https://review.coreboot.org/c/coreboot/+/79391/comment/d4a782e2_2d06da1a :
PS1, Line 33: OC_SKIP
Is this supposed to be OC1? I see that in the schematics USB_OC1_L is attached to USB_A0_OC_ODL.
https://review.coreboot.org/c/coreboot/+/79391/comment/859c1c9c_7a36642b :
PS1, Line 36: DCI
Is this Type A port A0? Also should it be OC1 like previous comment above?
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Change subject: payloads: Add uefistub payload
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
> > Why do we need to pull pieces out of U-Boot to achieve this? It doesn't seem a very friendly appro […]
Hi Maximillian,
Re solution 2, let's work together on that, instead of this effort!
For 64-bit SMBIOS (I suppose the SMBIOS3 header) there is a patch[1] but it needs a bit of work, or perhaps that has already been done. In any case, I can help, or Heinrich / others on the ML.
For ACPI, can you share your working code? The ACPI code is now fairly generic so enabling it on ARM should not be difficult. Of course any new thing has challenges.
We have enough forking going on in private projects. I would really like to see more collaboration between coreboot and U-Boot.
I did do some fiddling on U-Boot as a library a while back. It is a big effort though...so using the existing payload seems a lot easier.
[1] https://patchwork.ozlabs.org/project/uboot/patch/20231008213646.622002-4-sj…
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Change subject: nb/amd/pi/00730F01/chipset.cb: don't call dummy function host bridge
......................................................................
Patch Set 2: Code-Review+2
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Change subject: soc/amd/*/chipset.cb: don't call dummy device functions host bridges
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Patch Set 2: Code-Review+2
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Change subject: acpi/acpi: make sure that table_ptr is non-NULL in acpidump_print
......................................................................
acpi/acpi: make sure that table_ptr is non-NULL in acpidump_print
While acpidump_print shouldn't be called with a NULL pointer as
table_ptr argument, better add a check to not end up dereferencing the
NULL pointer.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: Ic3cc103c8a47fb8c2fe4262236ea47013af27c4f
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---
M src/acpi/acpi.c
1 file changed, 2 insertions(+), 0 deletions(-)
Approvals:
Tim Wawrzynczak: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c
index e40d4ac..c4d55ab 100644
--- a/src/acpi/acpi.c
+++ b/src/acpi/acpi.c
@@ -1367,6 +1367,8 @@
static void acpidump_print(void *table_ptr)
{
+ if (table_ptr == NULL)
+ return;
const acpi_header_t *header = (acpi_header_t *)table_ptr;
const size_t table_size = header->length;
printk(BIOS_SPEW, "%.4s @ 0x0000000000000000\n", header->signature);
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Change subject: soc/amd/common/pci: Add weak impl. of get_pci_routing_table()
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/79018/comment/9ec53a66_5f047d34 :
PS1, Line 11: and make use of other functions provided therein.
Is this just a temporary change that's going to be removed? Would it be better just to implement an empty function directly in Genoa with the understanding that it needs to be filled in at some point?
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