Krishna P Bhat D has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39147 )
Change subject: soc/intel/{icl,tgl}: Make use of print_me_fw_version() from CSE lib
......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39147/5//COMMIT_MSG
Commit Message:
https://review.coreboot.org/c/coreboot/+/39147/5//COMMIT_MSG@14
PS5, Line 14: TEST=Build and boot iclrvp, tglrvp boards.
> I see that you have included these files in a Makefile in the subsequent patch, you have to do that […]
Yes, has been tested with both patches together.
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Mimoja has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37582 )
Change subject: drivers/intel: Make FSP_USE_REPO an SOC optin instead of list dependency
......................................................................
drivers/intel: Make FSP_USE_REPO an SOC optin instead of list dependency
For quite a bit now we are extending the FSP_USE_REPO option to be
available for all Intel SOCs. This results in an list beeing not only
hard to maintain but also prune to errors.
To change that behaviour this commit is introducing the
HAVE_INTEL_FSP_REPO config for SOCs that are supported from withing
3rdparty/fsp.
All other interactions with FSP_USE_REPO stay the same.
Change-Id: I68ae373ce591f06073064aa75aac32ceca8fa1cc
Signed-off-by: Johanna Schander <coreboot(a)mimoja.de>
---
M src/drivers/intel/fsp2_0/Kconfig
M src/soc/intel/Kconfig
M src/soc/intel/apollolake/Kconfig
M src/soc/intel/cannonlake/Kconfig
M src/soc/intel/denverton_ns/Kconfig
M src/soc/intel/icelake/Kconfig
M src/soc/intel/skylake/Kconfig
7 files changed, 11 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/37582/1
diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig
index 8c8ac59..9d1aa88 100644
--- a/src/drivers/intel/fsp2_0/Kconfig
+++ b/src/drivers/intel/fsp2_0/Kconfig
@@ -53,10 +53,7 @@
config FSP_USE_REPO
bool "Use the IntelFSP based binaries"
depends on ADD_FSP_BINARIES
- depends on SOC_INTEL_APOLLOLAKE || SOC_INTEL_SKYLAKE || \
- SOC_INTEL_KABYLAKE || SOC_INTEL_COFFEELAKE || \
- SOC_INTEL_ICELAKE || SOC_INTEL_WHISKEYLAKE || \
- SOC_INTEL_DENVERTON_NS
+ depends on HAVE_INTEL_FSP_REPO
help
When selecting this option, the SoC must set FSP_HEADER_PATH
and FSP_FD_PATH correctly so FSP splitting works.
diff --git a/src/soc/intel/Kconfig b/src/soc/intel/Kconfig
index 1eebeb6..16f43df 100644
--- a/src/soc/intel/Kconfig
+++ b/src/soc/intel/Kconfig
@@ -46,3 +46,8 @@
than the one in non-topswap bootblock. This string will be passed
onto ifittool (-A -n option). ifittool will not parse the region for MCU
entries, and only locate the region and insert its address into FIT.
+
+config HAVE_INTEL_FSP_REPO
+ bool "Use FSP Blobs from fsp submodule"
+ help
+ This SOC has FSP binaries living in 3rdparty/fsp.
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index 0b3b30a..8dc7628 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -44,6 +44,7 @@
select GENERIC_GPIO_LIB
select INTEL_DESCRIPTOR_MODE_CAPABLE
select HAVE_SMI_HANDLER
+ select HAVE_INTEL_FSP_REPO
select MRC_SETTINGS_PROTECT
select MRC_SETTINGS_VARIABLE_DATA
select NO_FIXED_XIP_ROM_SIZE
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index 40c2fd7..8b55ac7 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -64,6 +64,7 @@
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
select FSP_M_XIP
select GENERIC_GPIO_LIB
+ select HAVE_INTEL_FSP_REPO
select HAVE_FSP_GOP
select INTEL_DESCRIPTOR_MODE_CAPABLE
select HAVE_SMI_HANDLER
diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig
index 9445977..0289cf4 100644
--- a/src/soc/intel/denverton_ns/Kconfig
+++ b/src/soc/intel/denverton_ns/Kconfig
@@ -33,6 +33,7 @@
select SOC_INTEL_COMMON_RESET
select PLATFORM_USES_FSP2_0
select IOAPIC
+ select HAVE_INTEL_FSP_REPO
select HAVE_SMI_HANDLER
select CACHE_MRC_SETTINGS
select PARALLEL_MP
diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig
index 4077619..1dd8bf1 100644
--- a/src/soc/intel/icelake/Kconfig
+++ b/src/soc/intel/icelake/Kconfig
@@ -20,6 +20,7 @@
select FSP_M_XIP
select GENERIC_GPIO_LIB
select HAVE_FSP_GOP
+ select HAVE_INTEL_FSP_REPO
select INTEL_DESCRIPTOR_MODE_CAPABLE
select HAVE_SMI_HANDLER
select IDT_IN_EVERY_STAGE
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 31f809a..cde9909 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -38,6 +38,7 @@
select INTEL_CAR_NEM_ENHANCED
select INTEL_GMA_ACPI
select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
+ select HAVE_INTEL_FSP_REPO
select IOAPIC
select MRC_SETTINGS_PROTECT
select NO_FIXED_XIP_ROM_SIZE
--
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Krishna P Bhat D has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39127 )
Change subject: soc/intel/tigerlake: Add function to dump ME firmware status information
......................................................................
Patch Set 9:
(3 comments)
https://review.coreboot.org/c/coreboot/+/39127/8/src/soc/intel/tigerlake/Ma…
File src/soc/intel/tigerlake/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/39127/8/src/soc/intel/tigerlake/Ma…
PS8, Line 52: ramstage-y += me.c
> You have to do this in the previous patch in the train
Done
https://review.coreboot.org/c/coreboot/+/39127/8/src/soc/intel/tigerlake/me…
File src/soc/intel/tigerlake/me.c:
https://review.coreboot.org/c/coreboot/+/39127/8/src/soc/intel/tigerlake/me…
PS8, Line 144: spi_protection_mode
> This bit should be cleared to indicate that SPI protection is in place? in that case the name signif […]
It is to keep the naming inline with ME document.
https://review.coreboot.org/c/coreboot/+/39127/8/src/soc/intel/tigerlake/me…
PS8, Line 145: "NO" : "YES")
> Is it correct? […]
When these two criteria are satisfied, it means end of manufacturing. It is no more in manufacturing mode (Manufacturing mode = “NO”).
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Bill XIE has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39906 )
Change subject: drivers/pc80/rtc: Always load cmos.default to satisfy measured boot
......................................................................
drivers/pc80/rtc: Always load cmos.default to satisfy measured boot
cmos.default used to be loaded only when cmos is needed to be reset,
but conditional loading of CBFS files may break measured boot if
measurement is hooked on each loading.
In order to resolve this, loadings should be made unconditional, but
the use of loaded data remains conditional, so cmos.default should
always be loaded (with cbfs_boot_map_with_leak() which is further
hooked with measurement), but cmos resetting remains conditional.
Change-Id: If6ea0d1cbaa7d96f7dea7e77b7548ca2b30efe9e
Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org>
---
M src/drivers/pc80/rtc/option.c
1 file changed, 7 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/39906/1
diff --git a/src/drivers/pc80/rtc/option.c b/src/drivers/pc80/rtc/option.c
index bb697df..5bf2fc9 100644
--- a/src/drivers/pc80/rtc/option.c
+++ b/src/drivers/pc80/rtc/option.c
@@ -239,7 +239,7 @@
return cmos_checksum_valid(LB_CKS_RANGE_START, LB_CKS_RANGE_END, LB_CKS_LOC);
}
-static void cmos_load_defaults(void)
+void sanitize_cmos(void)
{
size_t length = 128;
size_t i;
@@ -250,14 +250,10 @@
if (!cmos_default)
return;
- u8 control_state = cmos_disable_rtc();
- for (i = 14; i < MIN(128, length); i++)
- cmos_write_inner(cmos_default[i], i);
- cmos_restore_rtc(control_state);
-}
-
-void sanitize_cmos(void)
-{
- if (cmos_error() || !cmos_lb_cks_valid() || CONFIG(STATIC_OPTION_TABLE))
- cmos_load_defaults();
+ if (cmos_error() || !cmos_lb_cks_valid() || CONFIG(STATIC_OPTION_TABLE)) {
+ u8 control_state = cmos_disable_rtc();
+ for (i = 14; i < MIN(128, length); i++)
+ cmos_write_inner(cmos_default[i], i);
+ cmos_restore_rtc(control_state);
+ }
}
--
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Marcello Sylvester Bauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39603 )
Change subject: Documentation/mb/lenovo: Test shruken ME on Ivy Bridge
......................................................................
Documentation/mb/lenovo: Test shruken ME on Ivy Bridge
Update the Lenovo Ivy Bridge documentation that no issues could be
observed on W530.
Tested on Lenovo W530 with stripped ME and found no issues:
* USB
* Bluetooth
* Wifi
* Wifi-kill switch
* libgfxinit
* SATA
* mSATA
* Audio
* SD-card
* Ethernet
* Keyboard
* Fn-Keys
* Display brightness
* ACPI S3 resume
* CPU temperature reporting
* Stress test stable (intel_pstate no_turbo due to W530 overheating bug)
* Youtube videos
* stress -c 8 -m 1 -t 3600
Change-Id: I46d23d41cc6ade5e641a6ddb3f357a6036002edc
Signed-off-by: Marcello Sylvester Bauer <sylv(a)sylv.io>
---
M Documentation/mainboard/lenovo/Ivy_Bridge_series.md
1 file changed, 12 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/39603/1
diff --git a/Documentation/mainboard/lenovo/Ivy_Bridge_series.md b/Documentation/mainboard/lenovo/Ivy_Bridge_series.md
index 2f83ffa..7dec44d 100644
--- a/Documentation/mainboard/lenovo/Ivy_Bridge_series.md
+++ b/Documentation/mainboard/lenovo/Ivy_Bridge_series.md
@@ -76,3 +76,15 @@
[fl]: flashlayout_Ivy_Bridge.svg
+## Reducing Intel Managment Engine firmware size
+
+It is possible to reduce the Intel ME firmware size to free additional
+space for the `bios` region. This is usually refered to as *cleaning the ME* or
+*stripping the ME*.
+After reducing the Intel ME firmware size you must modify the original IFD,
+split the resulting coreboot ROM (See: Splitting the coreboot.rom)
+and then write each ROM using an [external programmer].
+Have a look at the [me_cleaner] for more information.
+
+Tests on Lenovo W530 showed no issues with a stripped ME firmware.
+
--
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Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39910 )
Change subject: device/Kconfig: fix circular dependency for RUN_FSP_GOP
......................................................................
device/Kconfig: fix circular dependency for RUN_FSP_GOP
Change Graphics Init default for RUN_FSP_GOP to depend on
INTEL_GMA_HAVE_VBT rather than INTEL_GMA_ADD_VBT, since
RUN_FSP_GOP selects INTEL_GMA_ADD_VBT for several Intel SoC's.
Test: create default config for gogle/cyan, RUN_FSP_GOP
still default display init selection but no more circular
dependency warning from config.
Change-Id: I8b978d9938c3d0024d4dd40000b988430664cee7
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
M src/device/Kconfig
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/39910/1
diff --git a/src/device/Kconfig b/src/device/Kconfig
index 64f1693..951062c 100644
--- a/src/device/Kconfig
+++ b/src/device/Kconfig
@@ -69,7 +69,7 @@
default VGA_ROM_RUN if VGA_BIOS
default MAINBOARD_DO_NATIVE_VGA_INIT
default MAINBOARD_USE_LIBGFXINIT
- default RUN_FSP_GOP if INTEL_GMA_ADD_VBT
+ default RUN_FSP_GOP if INTEL_GMA_HAVE_VBT
config MAINBOARD_DO_NATIVE_VGA_INIT
bool "Use native graphics init"
--
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