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[M] Change in coreboot[main]: mb/amd/birman: Factor out get_dd1_type
by Ana Carolina Cabral (Code Review) 15 Oct '24

15 Oct '24

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk. Ana Carolina Cabral has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84777?usp=email ) Change subject: mb/amd/birman: Factor out get_dd1_type ...................................................................... mb/amd/birman: Factor out get_dd1_type Use the now common get_ddi1_type function to update the connector type of the DDI1 port to match the display output extension card plugged into the reference board. Change-Id: I5b5a07a19d7dd2ab0adce7d597215ebe1bf51b9f Signed-off-by: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> --- M src/mainboard/amd/birman/Kconfig M src/mainboard/amd/birman/Makefile.mk D src/mainboard/amd/birman/display_card_type.c D src/mainboard/amd/birman/display_card_type.h M src/mainboard/amd/birman/port_descriptors_glinda.c M src/mainboard/amd/birman/port_descriptors_phoenix.c M src/mainboard/amd/birman/update_devicetree_phoenix_opensil.c 7 files changed, 12 insertions(+), 67 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/84777/1 diff --git a/src/mainboard/amd/birman/Kconfig b/src/mainboard/amd/birman/Kconfig index 9fafae1..fc79766 100644 --- a/src/mainboard/amd/birman/Kconfig +++ b/src/mainboard/amd/birman/Kconfig @@ -2,6 +2,7 @@ config BOARD_AMD_BIRMAN_COMMON def_bool n + select MAINBOARD_AMD_COMMON select BOARD_ROMSIZE_KB_16384 # Birman actually has a 32MiB ROM select EC_ACPI select SOC_AMD_COMMON_BLOCK_USE_ESPI if !SOC_AMD_COMMON_BLOCK_SIMNOW_BUILD diff --git a/src/mainboard/amd/birman/Makefile.mk b/src/mainboard/amd/birman/Makefile.mk index a784d1a..2df1f59 100644 --- a/src/mainboard/amd/birman/Makefile.mk +++ b/src/mainboard/amd/birman/Makefile.mk @@ -4,12 +4,10 @@ bootblock-y += early_gpio.c bootblock-y += ec.c -romstage-y += display_card_type.c romstage-$(CONFIG_BOARD_AMD_BIRMAN_PHOENIX_FSP) += port_descriptors_phoenix.c romstage-$(CONFIG_BOARD_AMD_BIRMAN_GLINDA) += port_descriptors_glinda.c ramstage-y += chromeos.c -ramstage-y += display_card_type.c ramstage-y += gpio.c ramstage-$(CONFIG_BOARD_AMD_BIRMAN_PHOENIX_OPENSIL) += update_devicetree_phoenix_opensil.c ramstage-$(CONFIG_BOARD_AMD_BIRMAN_PHOENIX_FSP) += port_descriptors_phoenix.c diff --git a/src/mainboard/amd/birman/display_card_type.c b/src/mainboard/amd/birman/display_card_type.c deleted file mode 100644 index 21f536f..0000000 --- a/src/mainboard/amd/birman/display_card_type.c +++ /dev/null @@ -1,49 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <console/console.h> -#include <device/i2c_simple.h> -#if CONFIG(PLATFORM_USES_FSP2_0) -#include <soc/platform_descriptors.h> -#else -#include <soc/amd/phoenix/chip_opensil.h> -#endif -#include <types.h> -#include "display_card_type.h" - -uint8_t get_ddi1_type(void) -{ - const uint8_t eeprom_i2c_bus = 2; - const uint8_t eeprom_i2c_address = 0x55; - const uint16_t eeprom_connector_type_offset = 2; - uint8_t eeprom_connector_type_data[2]; - uint16_t connector_type; - - if (i2c_2ba_read_bytes(eeprom_i2c_bus, eeprom_i2c_address, - eeprom_connector_type_offset, eeprom_connector_type_data, - sizeof(eeprom_connector_type_data))) { - printk(BIOS_NOTICE, - "Display connector type couldn't be determined. Disabling DDI1.\n"); - return DDI_UNUSED_TYPE; - } - - connector_type = eeprom_connector_type_data[1] | eeprom_connector_type_data[0] << 8; - - switch (connector_type) { - case 0x0c: - printk(BIOS_DEBUG, "Configuring DDI1 as HDMI.\n"); - return DDI_HDMI; - case 0x13: - printk(BIOS_DEBUG, "Configuring DDI1 as DP.\n"); - return DDI_DP; - case 0x14: - printk(BIOS_DEBUG, "Configuring DDI1 as eDP.\n"); - return DDI_EDP; - case 0x17: - printk(BIOS_DEBUG, "Configuring DDI1 as USB-C.\n"); - return DDI_DP_W_TYPEC; - default: - printk(BIOS_WARNING, "Unexpected display connector type %x. Disabling DDI1.\n", - connector_type); - return DDI_UNUSED_TYPE; - } -} diff --git a/src/mainboard/amd/birman/display_card_type.h b/src/mainboard/amd/birman/display_card_type.h deleted file mode 100644 index 1ffb278..0000000 --- a/src/mainboard/amd/birman/display_card_type.h +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef MAINBOARD_DISPLAY_CARD_TYPE_H -#define MAINBOARD_DISPLAY_CARD_TYPE_H - -#include <types.h> - -uint8_t get_ddi1_type(void); - -#endif /* MAINBOARD_DISPLAY_CARD_TYPE_H */ diff --git a/src/mainboard/amd/birman/port_descriptors_glinda.c b/src/mainboard/amd/birman/port_descriptors_glinda.c index 2af7d26..31af855 100644 --- a/src/mainboard/amd/birman/port_descriptors_glinda.c +++ b/src/mainboard/amd/birman/port_descriptors_glinda.c @@ -3,7 +3,7 @@ #include <gpio.h> #include <soc/platform_descriptors.h> #include <types.h> -#include "display_card_type.h" +#include <nova_card.h> /* TODO: Update for birman */ @@ -82,7 +82,8 @@ const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num, const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) { - birman_ddi_descriptors[1].connector_type = get_ddi1_type(); + struct nova_eeprom_params eeprom_params = {.i2c_bus = 2, .i2c_address = 0x55, .connector_type_offset = 2}; + birman_ddi_descriptors[1].connector_type = get_ddi1_type(&eeprom_params); *dxio_descs = birman_dxio_descriptors; *dxio_num = ARRAY_SIZE(birman_dxio_descriptors); diff --git a/src/mainboard/amd/birman/port_descriptors_phoenix.c b/src/mainboard/amd/birman/port_descriptors_phoenix.c index da07e31..b805ac7 100644 --- a/src/mainboard/amd/birman/port_descriptors_phoenix.c +++ b/src/mainboard/amd/birman/port_descriptors_phoenix.c @@ -5,7 +5,7 @@ #include <soc/platform_descriptors.h> #include <soc/soc_util.h> #include <types.h> -#include "display_card_type.h" +#include <nova_card.h> #define phx_mxm_dxio_descriptor { \ .engine_type = PCIE_ENGINE, \ @@ -167,7 +167,9 @@ const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num, const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) { - birman_ddi_descriptors[1].connector_type = get_ddi1_type(); + + struct nova_eeprom_params eeprom_params = {.i2c_bus = 2, .i2c_address = 0x55, .connector_type_offset = 2}; + birman_ddi_descriptors[1].connector_type = get_ddi1_type(&eeprom_params); enum soc_type type = get_soc_type(); diff --git a/src/mainboard/amd/birman/update_devicetree_phoenix_opensil.c b/src/mainboard/amd/birman/update_devicetree_phoenix_opensil.c index 2640e74..0ab01ca 100644 --- a/src/mainboard/amd/birman/update_devicetree_phoenix_opensil.c +++ b/src/mainboard/amd/birman/update_devicetree_phoenix_opensil.c @@ -5,7 +5,7 @@ #include <soc/soc_util.h> #include <static.h> #include <vendorcode/amd/opensil/chip/mpio/chip.h> -#include "display_card_type.h" +#include <nova_card.h> #include "update_devicetree.h" static void mainboard_update_mpio(void) @@ -45,7 +45,9 @@ static void mainboard_update_ddi(void) { struct soc_amd_phoenix_config *cfg = config_of_soc(); - cfg->ddi[1].connector_type = get_ddi1_type(); + + struct nova_eeprom_params eeprom_params = {.i2c_bus = 2, .i2c_address = 0x55, .connector_type_offset = 2}; + cfg->ddi[1].connector_type = get_ddi1_type(&eeprom_params); } void mainboard_update_devicetree_opensil(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/84777?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5b5a07a19d7dd2ab0adce7d597215ebe1bf51b9f Gerrit-Change-Number: 84777 Gerrit-PatchSet: 1 Gerrit-Owner: Ana Carolina Cabral Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[M] Change in coreboot[main]: mb/amd/common: Add common directory
by Ana Carolina Cabral (Code Review) 15 Oct '24

15 Oct '24

Ana Carolina Cabral has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84776?usp=email ) Change subject: mb/amd/common: Add common directory ...................................................................... mb/amd/common: Add common directory Creates a common directory for amd/mainboard. As multiple boards use the NOVA daughter card, the function that detects the connector type has been moved to this common folder and will be refactored in the following patches. Change-Id: I5e9ded2090d6a5865e3330408f490e59fbf480f4 Signed-off-by: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> --- M Makefile.mk A src/mainboard/amd/common/Kconfig A src/mainboard/amd/common/Makefile.mk A src/mainboard/amd/common/nova/Kconfig A src/mainboard/amd/common/nova/Makefile.mk A src/mainboard/amd/common/nova/include/nova_card.h A src/mainboard/amd/common/nova/nova_card.c 7 files changed, 91 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/84776/1 diff --git a/Makefile.mk b/Makefile.mk index 4a2f191..2f6e130 100644 --- a/Makefile.mk +++ b/Makefile.mk @@ -118,7 +118,7 @@ subdirs-y += util/futility util/marvell util/bincfg util/supermicro util/qemu subdirs-y += util/ifdtool subdirs-y += $(wildcard src/arch/*) -subdirs-y += src/mainboard/$(MAINBOARDDIR) +subdirs-y += src/mainboard/$(MAINBOARDDIR) $(wildcard src/mainboard/*/common) subdirs-y += src/security subdirs-y += payloads payloads/external subdirs-$(CONFIG_SBOM) += src/sbom diff --git a/src/mainboard/amd/common/Kconfig b/src/mainboard/amd/common/Kconfig new file mode 100644 index 0000000..3660e47 --- /dev/null +++ b/src/mainboard/amd/common/Kconfig @@ -0,0 +1,10 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config MAINBOARD_AMD_COMMON + bool + +if MAINBOARD_AMD_COMMON + source "src/mainboard/amd/common/*/Kconfig" +endif #MAINBOARD_AMD_COMMON + + diff --git a/src/mainboard/amd/common/Makefile.mk b/src/mainboard/amd/common/Makefile.mk new file mode 100644 index 0000000..b80de88 --- /dev/null +++ b/src/mainboard/amd/common/Makefile.mk @@ -0,0 +1,8 @@ +## SPDX-License-Identifier: GPL-2.0-only + +ifeq ($(CONFIG_MAINBOARD_AMD_COMMON),y) + +subdirs-y += ./* +CPPFLAGS_common += -I$(src)/mainboard/amd/common/nova/include/ + +endif # ifeq ($(MAINBOARD_AMD_COMMON),y) diff --git a/src/mainboard/amd/common/nova/Kconfig b/src/mainboard/amd/common/nova/Kconfig new file mode 100644 index 0000000..e797fff --- /dev/null +++ b/src/mainboard/amd/common/nova/Kconfig @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config AMD_MAINBOARD_NOVA_CARD + bool "Enable NOVA Card" + help + This option enables Nova Card auto detection \ No newline at end of file diff --git a/src/mainboard/amd/common/nova/Makefile.mk b/src/mainboard/amd/common/nova/Makefile.mk new file mode 100644 index 0000000..4eda9971 --- /dev/null +++ b/src/mainboard/amd/common/nova/Makefile.mk @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-only + +romstage-$(CONFIG_AMD_MAINBOARD_NOVA_CARD) += nova_card.c +ramstage-$(CONFIG_AMD_MAINBOARD_NOVA_CARD) += nova_card.c + diff --git a/src/mainboard/amd/common/nova/include/nova_card.h b/src/mainboard/amd/common/nova/include/nova_card.h new file mode 100644 index 0000000..1bf6ef6 --- /dev/null +++ b/src/mainboard/amd/common/nova/include/nova_card.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MAINBOARD_DISPLAY_CARD_TYPE_H +#define MAINBOARD_DISPLAY_CARD_TYPE_H + +#include <types.h> + +struct nova_eeprom_params { + uint8_t i2c_bus; + uint8_t i2c_address; + uint16_t connector_type_offset; +}; + +uint8_t get_ddi1_type(struct nova_eeprom_params *eeprom_params); + +#endif /* MAINBOARD_DISPLAY_CARD_TYPE_H */ diff --git a/src/mainboard/amd/common/nova/nova_card.c b/src/mainboard/amd/common/nova/nova_card.c new file mode 100644 index 0000000..815c369 --- /dev/null +++ b/src/mainboard/amd/common/nova/nova_card.c @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <device/i2c_simple.h> +#if CONFIG(PLATFORM_USES_FSP2_0) +#include <soc/platform_descriptors.h> +#else +#include <soc/amd/phoenix/chip_opensil.h> +#endif +#include <types.h> +#include "nova_card.h" + +uint8_t get_ddi1_type(struct nova_eeprom_params *eeprom_params) +{ + uint8_t data[2] = {0}; + + if (i2c_2ba_read_bytes(eeprom_params->i2c_bus, eeprom_params->i2c_address, + eeprom_params->connector_type_offset, data, + sizeof(data))) { + printk(BIOS_NOTICE, + "Display connector type couldn't be determined. Disabling DDI1.\n"); + return DDI_UNUSED_TYPE; + } + + uint16_t connector_type = data[1] | data[0] << 8; + + switch (connector_type) { + case 0x0c: + printk(BIOS_DEBUG, "Configuring DDI1 as HDMI.\n"); + return DDI_HDMI; + case 0x13: + printk(BIOS_DEBUG, "Configuring DDI1 as DP.\n"); + return DDI_DP; + case 0x14: + printk(BIOS_DEBUG, "Configuring DDI1 as eDP.\n"); + return DDI_EDP; + case 0x17: + printk(BIOS_DEBUG, "Configuring DDI1 as USB-C.\n"); + return DDI_DP_W_TYPEC; + default: + printk(BIOS_WARNING, "Unexpected display connector type %x. Disabling DDI1.\n", + connector_type); + return DDI_UNUSED_TYPE; + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/84776?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5e9ded2090d6a5865e3330408f490e59fbf480f4 Gerrit-Change-Number: 84776 Gerrit-PatchSet: 1 Gerrit-Owner: Ana Carolina Cabral

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[S] Change in coreboot[main]: soc/intel/common/block/cpu: Add Kconfig for effective way size for NEM+
by Jérémy Compostella (Code Review) 15 Oct '24

15 Oct '24

Attention is currently required from: Ashish Kumar Mishra, Paul Menzel, Sowmya Aralguppe, Subrata Banik, Wonkyu Kim. Jérémy Compostella has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/83946?usp=email ) Change subject: soc/intel/common/block/cpu: Add Kconfig for effective way size for NEM+ ...................................................................... Patch Set 13: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/83946/comment/3304c150_88be27c9?us… : PS13, Line 28: 3 > > This is not how I interpret it and the experiment I performed demonstrate that my understanding is […] ``` The issue addressed by this commit can be observed with the following experiment: using a 18 MB LLC SKU, set `DCACHE_RAM_SIZE` to 0x400000 (4 MB). ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/83946?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5cb66da0aa977eecb64a0021268a6827747c521c Gerrit-Change-Number: 83946 Gerrit-PatchSet: 13 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Sowmya Aralguppe <sowmya.aralguppe(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.corp-partner.google.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 15 Oct 2024 19:05:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[XS] Change in coreboot[main]: payloads/libpayload: Add Wno-address-of-packed-member flag
by Elyes Haouas (Code Review) 15 Oct '24

15 Oct '24

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84756?usp=email ) Change subject: payloads/libpayload: Add Wno-address-of-packed-member flag ...................................................................... payloads/libpayload: Add Wno-address-of-packed-member flag Change-Id: I47d7b5af67563de96fb5d8c200ce186a3443728b Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84756 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jakub Czapiga <czapiga(a)google.com> --- M payloads/libpayload/Makefile.mk M payloads/libpayload/tests/Makefile.mk 2 files changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Jakub Czapiga: Looks good to me, approved diff --git a/payloads/libpayload/Makefile.mk b/payloads/libpayload/Makefile.mk index c9cefb3..079fa32 100644 --- a/payloads/libpayload/Makefile.mk +++ b/payloads/libpayload/Makefile.mk @@ -79,7 +79,7 @@ CFLAGS += -ffunction-sections -fdata-sections CFLAGS += -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes -Wvla CFLAGS += -Wwrite-strings -Wredundant-decls -Wimplicit-fallthrough -CFLAGS += -Wstrict-aliasing -Wshadow -Werror +CFLAGS += -Wstrict-aliasing -Wshadow -Wno-address-of-packed-member -Werror ifeq ($(CONFIG_LP_LTO),y) CFLAGS += -flto diff --git a/payloads/libpayload/tests/Makefile.mk b/payloads/libpayload/tests/Makefile.mk index 01f0a9e..a6cee5f 100644 --- a/payloads/libpayload/tests/Makefile.mk +++ b/payloads/libpayload/tests/Makefile.mk @@ -44,7 +44,7 @@ # Minimal subset of warnings and errors. Tests can be less strict than actual build. TEST_CFLAGS += -Wall -Wundef -Wstrict-prototypes -Wvla -TEST_CFLAGS += -Wwrite-strings -Wimplicit-fallthrough +TEST_CFLAGS += -Wwrite-strings -Wno-address-of-packed-member -Wimplicit-fallthrough TEST_CFLAGS += -Wstrict-aliasing -Wshadow -Werror TEST_CFLAGS += -Wno-unknown-warning-option -Wno-source-mgr -Wno-main-return-type -- To view, visit https://review.coreboot.org/c/coreboot/+/84756?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I47d7b5af67563de96fb5d8c200ce186a3443728b Gerrit-Change-Number: 84756 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[L] Change in coreboot[main]: mb/google/fatcat: add pre-mem GPIO pad configure based on fw_config
by Subrata Banik (Code Review) 15 Oct '24

15 Oct '24

Attention is currently required from: Cliff Huang, Jérémy Compostella. Subrata Banik has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84718?usp=email ) Change subject: mb/google/fatcat: add pre-mem GPIO pad configure based on fw_config ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/84718/comment/371c2721_994b2137?us… : PS4, Line 7: dd pre-mem GPIO pad configure based on fw_config > I am confused, we followed https://review.coreboot.org/c/coreboot/+/84718/comments/0401046a_46026bbd and as a result we pulled a bit from overridetree.cb to satisfy your request. My original request was to add the FW_CONFIG for pre-mem and get this CL landed ASAP. After that, we can add minimal override devicetree changes along with FW_CONFIG for advanced devices. We can always add devicetree/GPIO for ramstage incrementally. I never suggested pulling changes from CB:84408 to CB:84718. > > The commit message still is about configuring GPIO based on fw_config but having these changes without the device which go away do not make sense. ideally we add three changes together for any IP/device block 1. FW config 2. override tree 3. corresponding GPIO override using FW config Looking at CB:84718, I felt this CL was previously intended to perform early GPIO programming as per FW config and override tree was never the goal. Override tree was added with CB:84408 CL. > > Do you mean we should add a line stating that we are also providing the devicetree information for the relevant devices ? yes, as you have added both override tree and GPIO changes for pre-ram depending upon the FW config, you should mention the same rather saying this CL is just for pre-mem GPIO configuration based on FW config -- To view, visit https://review.coreboot.org/c/coreboot/+/84718?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iac1f637c21a9818512b224dc4cbe4a75dbc516ce Gerrit-Change-Number: 84718 Gerrit-PatchSet: 4 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Tue, 15 Oct 2024 18:19:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[L] Change in coreboot[main]: mb/google/fatcat: add pre-mem GPIO pad configure based on fw_config
by Jérémy Compostella (Code Review) 15 Oct '24

15 Oct '24

Attention is currently required from: Cliff Huang, Subrata Banik (OOO till 10/18). Jérémy Compostella has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84718?usp=email ) Change subject: mb/google/fatcat: add pre-mem GPIO pad configure based on fw_config ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/84718/comment/2631627c_a9b8c063?us… : PS4, Line 7: dd pre-mem GPIO pad configure based on fw_config > Since you've added more devices in this CL than the pre-mem device usage, I don't think this commit […] I am confused, we followed https://review.coreboot.org/c/coreboot/+/84718/comments/0401046a_46026bbd and as a result we pulled a bit from overridetree.cb to satisfy your request. The commit message still is about configuring GPIO based on fw_config but having these changes without the device which go away do not make sense. Do you mean we should add a line stating that we are also providing the devicetree information for the relevant devices ? -- To view, visit https://review.coreboot.org/c/coreboot/+/84718?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iac1f637c21a9818512b224dc4cbe4a75dbc516ce Gerrit-Change-Number: 84718 Gerrit-PatchSet: 4 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik (OOO till 10/18) <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Subrata Banik (OOO till 10/18) <subratabanik(a)google.com> Gerrit-Comment-Date: Tue, 15 Oct 2024 18:04:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik (OOO till 10/18) <subratabanik(a)google.com>

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[L] Change in coreboot[main]: mb/google/fatcat: add pre-mem GPIO pad configure based on fw_config
by Jérémy Compostella (Code Review) 15 Oct '24

15 Oct '24

Attention is currently required from: Cliff Huang, Subrata Banik (OOO till 10/18). Jérémy Compostella has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84718?usp=email ) Change subject: mb/google/fatcat: add pre-mem GPIO pad configure based on fw_config ...................................................................... Patch Set 4: (2 comments) File src/mainboard/google/fatcat/romstage.c: https://review.coreboot.org/c/coreboot/+/84718/comment/a730e095_afadb141?us… : PS1, Line 8: pre_mem > > @subratabanik@google.com, Cliff told me you request pre_mem instead of romstage. […] Done File src/mainboard/google/fatcat/variants/fatcat/fw_config.c: https://review.coreboot.org/c/coreboot/+/84718/comment/fbcf7bd9_d909a59b?us… : PS1, Line 464: }; > Remove `;` Done -- To view, visit https://review.coreboot.org/c/coreboot/+/84718?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iac1f637c21a9818512b224dc4cbe4a75dbc516ce Gerrit-Change-Number: 84718 Gerrit-PatchSet: 4 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik (OOO till 10/18) <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Subrata Banik (OOO till 10/18) <subratabanik(a)google.com> Gerrit-Comment-Date: Tue, 15 Oct 2024 18:00:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik (OOO till 10/18) <subratabanik(a)google.com> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[M] Change in coreboot[main]: soc/intel/*: Add debug prints for misaligned FSP and driver settings
by Yidi Lin (Code Review) 15 Oct '24

15 Oct '24

Attention is currently required from: Sean Rhodes. Yidi Lin has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/84716?usp=email ) Change subject: soc/intel/*: Add debug prints for misaligned FSP and driver settings ...................................................................... Patch Set 9: (1 comment) File src/soc/intel/alderlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/84716/comment/80950dbe_7b3a26b2?us… : PS9, Line 936: usb_cfg->cnvi_bt_audio_offload = 0; Hi, There is a potential error if `usb_cfg` is not assigned in the while loop. ``` src/soc/intel/cannonlake/fsp_params.c:569:48: error: 'usb_cfg' may be used uninitialized in this function [-Werror=maybe-uninitialized] ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/84716?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I449c43998dd379dc68a33db47a2fe51cfe5cda2f Gerrit-Change-Number: 84716 Gerrit-PatchSet: 9 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik (OOO till 10/18) <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Tue, 15 Oct 2024 14:04:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[L] Change in coreboot[main]: mb/google/brya: Create telith variant
by Dinesh Gehlot (Code Review) 15 Oct '24

15 Oct '24

Attention is currently required from: Jayvik Desai, Kapil Porwal, Kun Liu, Nick Vaccaro. Dinesh Gehlot has posted comments on this change by Kun Liu. ( https://review.coreboot.org/c/coreboot/+/84759?usp=email ) Change subject: mb/google/brya: Create telith variant ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84759?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4971b9691d3dd293ca640795967c36472afef9c9 Gerrit-Change-Number: 84759 Gerrit-PatchSet: 3 Gerrit-Owner: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jian Tong <tongjian(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik (OOO till 10/18) <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ginger Zhang <zhangqingchun(a)huaqin.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Tue, 15 Oct 2024 13:05:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: Documentation/tutorial/managing_local_additions.md: Add symlink info
by Ana Carolina Cabral (Code Review) 15 Oct '24

15 Oct '24

Attention is currently required from: Martin Roth, Matt DeVillier. Ana Carolina Cabral has posted comments on this change by Nick Kochlowski. ( https://review.coreboot.org/c/coreboot/+/84740?usp=email ) Change subject: Documentation/tutorial/managing_local_additions.md: Add symlink info ...................................................................... Patch Set 9: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/84740?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I75f9e9575005e9ee2f255848a21c5e57c30e9e72 Gerrit-Change-Number: 84740 Gerrit-PatchSet: 9 Gerrit-Owner: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Reviewer: Ana Carolina Cabral Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Tue, 15 Oct 2024 12:08:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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