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Change in coreboot[master]: vendorcode/siemens/hwilib: Fix current file string usage

by Arthur Heymans (Code Review)

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37077 ) Change subject: vendorcode/siemens/hwilib: Fix current file string usage ...................................................................... vendorcode/siemens/hwilib: Fix current file string usage The CAR_GLOBAL accessors likely hid a bug where strncmp/cpy was passed a pointer to a char array instead of the char array. Change-Id: I68788e47ef27a959d6e048e9385afcfb663cdebc Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/vendorcode/siemens/hwilib/hwilib.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/37077/1 diff --git a/src/vendorcode/siemens/hwilib/hwilib.c b/src/vendorcode/siemens/hwilib/hwilib.c index 35fb4ce..a4b8e54 100644 --- a/src/vendorcode/siemens/hwilib/hwilib.c +++ b/src/vendorcode/siemens/hwilib/hwilib.c @@ -476,7 +476,7 @@ return CB_ERR_ARG; /* Check if this file is already open. If yes, just leave as there is nothing left to do here. */ - if (!strncmp((char *)&current_hwi, hwi_filename, HWI_MAX_NAME_LEN)) { + if (!strncmp(current_hwi, hwi_filename, HWI_MAX_NAME_LEN)) { printk(BIOS_SPEW, "HWILIB: File \"%s\" already open.\n", hwi_filename); return CB_SUCCESS; @@ -543,7 +543,7 @@ if (all_blocks[BLK_HIB] || all_blocks[BLK_SIB] || all_blocks[BLK_EIB] || all_blocks[BLK_XIB]) { /* Save currently opened hwi filename. */ - strncpy((char *)&current_hwi, hwi_filename, HWI_MAX_NAME_LEN); + strncpy(current_hwi, hwi_filename, HWI_MAX_NAME_LEN); return CB_SUCCESS; } else -- To view, visit https://review.coreboot.org/c/coreboot/+/37077 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I68788e47ef27a959d6e048e9385afcfb663cdebc Gerrit-Change-Number: 37077 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common: Rename save state accessors

by Arthur Heymans (Code Review)

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37110 ) Change subject: soc/intel/common: Rename save state accessors ...................................................................... soc/intel/common: Rename save state accessors This avoids name collision with follow-up code that intends to reuse these names and replace this code. Change-Id: Ib24ab09e7f35bb231a8069905860c612d5e35454 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/apollolake/smihandler.c M src/soc/intel/cannonlake/smihandler.c M src/soc/intel/common/block/include/intelblocks/smihandler.h M src/soc/intel/common/block/smm/smihandler.c M src/soc/intel/common/block/smm/smitraphandler.c M src/soc/intel/icelake/smihandler.c M src/soc/intel/skylake/smihandler.c M src/soc/intel/tigerlake/smihandler.c 8 files changed, 71 insertions(+), 71 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/37110/1 diff --git a/src/soc/intel/apollolake/smihandler.c b/src/soc/intel/apollolake/smihandler.c index 53d2b7e..f26d8ba 100644 --- a/src/soc/intel/apollolake/smihandler.c +++ b/src/soc/intel/apollolake/smihandler.c @@ -29,7 +29,7 @@ return 1; } -const struct smm_save_state_ops *get_smm_save_state_ops(void) +const struct intel_smm_save_state_ops *get_smm_save_state_ops(void) { return &em64t100_smm_ops; } diff --git a/src/soc/intel/cannonlake/smihandler.c b/src/soc/intel/cannonlake/smihandler.c index 4d0b241..1d57c7e 100644 --- a/src/soc/intel/cannonlake/smihandler.c +++ b/src/soc/intel/cannonlake/smihandler.c @@ -32,7 +32,7 @@ #define CSME0_BAR 0x0 #define CSME0_FID 0xb0 -const struct smm_save_state_ops *get_smm_save_state_ops(void) +const struct intel_smm_save_state_ops *get_smm_save_state_ops(void) { return &em64t101_smm_ops; } diff --git a/src/soc/intel/common/block/include/intelblocks/smihandler.h b/src/soc/intel/common/block/include/intelblocks/smihandler.h index d8520f1..afe8505 100644 --- a/src/soc/intel/common/block/include/intelblocks/smihandler.h +++ b/src/soc/intel/common/block/include/intelblocks/smihandler.h @@ -25,32 +25,32 @@ /* * The register value is used with get_reg and set_reg */ -enum smm_reg { - RAX, - RBX, - RCX, - RDX, +enum intel_smm_reg { + SMM_RAX, + SMM_RBX, + SMM_RCX, + SMM_RDX, }; -struct smm_save_state_ops { +struct intel_smm_save_state_ops { /* return io_misc_info from SMM Save State Area */ uint32_t (*get_io_misc_info)(void *state); /* return value of the requested register from * SMM Save State Area */ - uint64_t (*get_reg)(void *state, enum smm_reg reg); + uint64_t (*get_reg)(void *state, enum intel_smm_reg reg); - void (*set_reg)(void *state, enum smm_reg reg, uint64_t val); + void (*set_reg)(void *state, enum intel_smm_reg reg, uint64_t val); }; -typedef void (*smi_handler_t)(const struct smm_save_state_ops *save_state_ops); +typedef void (*smi_handler_t)(const struct intel_smm_save_state_ops *save_state_ops); /* * SOC SMI Handler has to provide this structure which has methods to access * the SOC specific SMM Save State Area */ -const struct smm_save_state_ops *get_smm_save_state_ops(void); +const struct intel_smm_save_state_ops *get_smm_save_state_ops(void); /* * southbridge_smi should be defined inside SOC specific code and should have @@ -67,7 +67,7 @@ * soc/intel/common/block/smm/smihandler.c */ void smihandler_southbridge_sleep( - const struct smm_save_state_ops *save_state_ops); + const struct intel_smm_save_state_ops *save_state_ops); /* * This function should be implemented in SOC specific code to handle @@ -75,7 +75,7 @@ * soc/intel/common/block/smm/smihandler.c */ void smihandler_southbridge_apmc( - const struct smm_save_state_ops *save_state_ops); + const struct intel_smm_save_state_ops *save_state_ops); /* * This function should be implemented in SOC specific code to handle @@ -83,7 +83,7 @@ * soc/intel/common/block/smm/smihandler.c */ void smihandler_southbridge_pm1( - const struct smm_save_state_ops *save_state_ops); + const struct intel_smm_save_state_ops *save_state_ops); /* * This function should be implemented in SOC specific code to handle @@ -91,7 +91,7 @@ * soc/intel/common/block/smm/smihandler.c */ void smihandler_southbridge_gpe0( - const struct smm_save_state_ops *save_state_ops); + const struct intel_smm_save_state_ops *save_state_ops); /* * This function should be implemented in SOC specific code to handle @@ -99,7 +99,7 @@ * soc/intel/common/block/smm/smihandler.c */ void smihandler_southbridge_mc( - const struct smm_save_state_ops *save_state_ops); + const struct intel_smm_save_state_ops *save_state_ops); /* * This function should be implemented in SOC specific code to handle @@ -107,14 +107,14 @@ * soc/intel/common/block/smm/smihandler.c */ void smihandler_southbridge_monitor( - const struct smm_save_state_ops *save_state_ops); + const struct intel_smm_save_state_ops *save_state_ops); /* * This function should be implemented in SOC specific code to handle * SMI_TCO event. The default functionality is provided in * soc/intel/common/block/smm/smihandler.c */ void smihandler_southbridge_tco( - const struct smm_save_state_ops *save_state_ops); + const struct intel_smm_save_state_ops *save_state_ops); /* * This function should be implemented in SOC specific code to handle @@ -122,7 +122,7 @@ * soc/intel/common/block/smm/smihandler.c */ void smihandler_southbridge_periodic( - const struct smm_save_state_ops *save_state_ops); + const struct intel_smm_save_state_ops *save_state_ops); /* * This function should be implemented in SOC specific code to handle @@ -130,7 +130,7 @@ * soc/intel/common/block/smm/smihandler.c */ void smihandler_southbridge_gpi( - const struct smm_save_state_ops *save_state_ops); + const struct intel_smm_save_state_ops *save_state_ops); /* * This function should be implemented in SOC specific code to handle @@ -138,7 +138,7 @@ * soc/intel/common/block/smm/smihandler.c */ void smihandler_southbridge_espi( - const struct smm_save_state_ops *save_state_ops); + const struct intel_smm_save_state_ops *save_state_ops); /* * Returns gnvs pointer within SMM context @@ -173,7 +173,7 @@ /* Mainboard handler for ESPI EMIs */ void mainboard_smi_espi_handler(void); -extern const struct smm_save_state_ops em64t100_smm_ops; +extern const struct intel_smm_save_state_ops em64t100_smm_ops; -extern const struct smm_save_state_ops em64t101_smm_ops; +extern const struct intel_smm_save_state_ops em64t101_smm_ops; #endif diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c index 0581d23..d76fb0a 100644 --- a/src/soc/intel/common/block/smm/smihandler.c +++ b/src/soc/intel/common/block/smm/smihandler.c @@ -87,7 +87,7 @@ /* Common Functions */ -static void *find_save_state(const struct smm_save_state_ops *save_state_ops, +static void *find_save_state(const struct intel_smm_save_state_ops *save_state_ops, int cmd) { int node; @@ -111,7 +111,7 @@ if (((io_misc_info >> 16) & 0xff) != APM_CNT) continue; /* Check AL against the requested command */ - reg_al = save_state_ops->get_reg(state, RAX); + reg_al = save_state_ops->get_reg(state, SMM_RAX); if (reg_al != cmd) continue; break; @@ -179,7 +179,7 @@ void smihandler_southbridge_sleep( - const struct smm_save_state_ops *save_state_ops) + const struct intel_smm_save_state_ops *save_state_ops) { uint32_t reg32; uint8_t slp_typ; @@ -275,7 +275,7 @@ } static void southbridge_smi_gsmi( - const struct smm_save_state_ops *save_state_ops) + const struct intel_smm_save_state_ops *save_state_ops) { u8 sub_command, ret; void *io_smi = NULL; @@ -285,19 +285,19 @@ if (!io_smi) return; /* Command and return value in EAX */ - sub_command = (save_state_ops->get_reg(io_smi, RAX) >> 8) + sub_command = (save_state_ops->get_reg(io_smi, SMM_RAX) >> 8) & 0xff; /* Parameter buffer in EBX */ - reg_ebx = save_state_ops->get_reg(io_smi, RBX); + reg_ebx = save_state_ops->get_reg(io_smi, SMM_RBX); /* drivers/elog/gsmi.c */ ret = gsmi_exec(sub_command, &reg_ebx); - save_state_ops->set_reg(io_smi, RAX, ret); + save_state_ops->set_reg(io_smi, SMM_RAX, ret); } static void southbridge_smi_store( - const struct smm_save_state_ops *save_state_ops) + const struct intel_smm_save_state_ops *save_state_ops) { u8 sub_command, ret; void *io_smi; @@ -307,14 +307,14 @@ if (!io_smi) return; /* Command and return value in EAX */ - sub_command = (save_state_ops->get_reg(io_smi, RAX) >> 8) & 0xff; + sub_command = (save_state_ops->get_reg(io_smi, SMM_RAX) >> 8) & 0xff; /* Parameter buffer in EBX */ - reg_ebx = save_state_ops->get_reg(io_smi, RBX); + reg_ebx = save_state_ops->get_reg(io_smi, SMM_RBX); /* drivers/smmstore/smi.c */ ret = smmstore_exec(sub_command, (void *)reg_ebx); - save_state_ops->set_reg(io_smi, RAX, ret); + save_state_ops->set_reg(io_smi, SMM_RAX, ret); } static void finalize(void) @@ -336,7 +336,7 @@ } void smihandler_southbridge_apmc( - const struct smm_save_state_ops *save_state_ops) + const struct intel_smm_save_state_ops *save_state_ops) { uint8_t reg8; void *state = NULL; @@ -379,7 +379,7 @@ state = find_save_state(save_state_ops, reg8); if (state) { /* EBX in the state save contains the GNVS pointer */ - uint32_t reg_ebx = save_state_ops->get_reg(state, RBX); + uint32_t reg_ebx = save_state_ops->get_reg(state, SMM_RBX); gnvs = (struct global_nvs_t *)(uintptr_t)reg_ebx; smm_initialized = 1; printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); @@ -402,7 +402,7 @@ } void smihandler_southbridge_pm1( - const struct smm_save_state_ops *save_state_ops) + const struct intel_smm_save_state_ops *save_state_ops) { uint16_t pm1_sts = pmc_clear_pm1_status(); u16 pm1_en = pmc_read_pm1_enable(); @@ -420,13 +420,13 @@ } void smihandler_southbridge_gpe0( - const struct smm_save_state_ops *save_state_ops) + const struct intel_smm_save_state_ops *save_state_ops) { pmc_clear_all_gpe_status(); } void smihandler_southbridge_tco( - const struct smm_save_state_ops *save_state_ops) + const struct intel_smm_save_state_ops *save_state_ops) { uint32_t tco_sts = pmc_clear_tco_status(); @@ -443,7 +443,7 @@ } void smihandler_southbridge_periodic( - const struct smm_save_state_ops *save_state_ops) + const struct intel_smm_save_state_ops *save_state_ops) { uint32_t reg32; @@ -456,7 +456,7 @@ } void smihandler_southbridge_gpi( - const struct smm_save_state_ops *save_state_ops) + const struct intel_smm_save_state_ops *save_state_ops) { struct gpi_status smi_sts; @@ -468,7 +468,7 @@ } void smihandler_southbridge_espi( - const struct smm_save_state_ops *save_state_ops) + const struct intel_smm_save_state_ops *save_state_ops) { mainboard_smi_espi_handler(); } @@ -477,7 +477,7 @@ { int i; uint32_t smi_sts; - const struct smm_save_state_ops *save_state_ops; + const struct intel_smm_save_state_ops *save_state_ops; /* * We need to clear the SMI status registers, or we won't see what's @@ -519,22 +519,22 @@ return smm_state->io_misc_info; } -static uint64_t em64t100_smm_save_state_get_reg(void *state, enum smm_reg reg) +static uint64_t em64t100_smm_save_state_get_reg(void *state, enum intel_smm_reg reg) { uintptr_t value = 0; em64t100_smm_state_save_area_t *smm_state = state; switch (reg) { - case RAX: + case SMM_RAX: value = smm_state->rax; break; - case RBX: + case SMM_RBX: value = smm_state->rbx; break; - case RCX: + case SMM_RCX: value = smm_state->rcx; break; - case RDX: + case SMM_RDX: value = smm_state->rdx; break; default: @@ -543,21 +543,21 @@ return value; } -static void em64t100_smm_save_state_set_reg(void *state, enum smm_reg reg, +static void em64t100_smm_save_state_set_reg(void *state, enum intel_smm_reg reg, uint64_t val) { em64t100_smm_state_save_area_t *smm_state = state; switch (reg) { - case RAX: + case SMM_RAX: smm_state->rax = val; break; - case RBX: + case SMM_RBX: smm_state->rbx = val; break; - case RCX: + case SMM_RCX: smm_state->rcx = val; break; - case RDX: + case SMM_RDX: smm_state->rdx = val; break; default: @@ -571,22 +571,22 @@ return smm_state->io_misc_info; } -static uint64_t em64t101_smm_save_state_get_reg(void *state, enum smm_reg reg) +static uint64_t em64t101_smm_save_state_get_reg(void *state, enum intel_smm_reg reg) { uintptr_t value = 0; em64t101_smm_state_save_area_t *smm_state = state; switch (reg) { - case RAX: + case SMM_RAX: value = smm_state->rax; break; - case RBX: + case SMM_RBX: value = smm_state->rbx; break; - case RCX: + case SMM_RCX: value = smm_state->rcx; break; - case RDX: + case SMM_RDX: value = smm_state->rdx; break; default: @@ -595,21 +595,21 @@ return value; } -static void em64t101_smm_save_state_set_reg(void *state, enum smm_reg reg, +static void em64t101_smm_save_state_set_reg(void *state, enum intel_smm_reg reg, uint64_t val) { em64t101_smm_state_save_area_t *smm_state = state; switch (reg) { - case RAX: + case SMM_RAX: smm_state->rax = val; break; - case RBX: + case SMM_RBX: smm_state->rbx = val; break; - case RCX: + case SMM_RCX: smm_state->rcx = val; break; - case RDX: + case SMM_RDX: smm_state->rdx = val; break; default: @@ -617,13 +617,13 @@ } } -const struct smm_save_state_ops em64t100_smm_ops = { +const struct intel_smm_save_state_ops em64t100_smm_ops = { .get_io_misc_info = em64t100_smm_save_state_get_io_misc_info, .get_reg = em64t100_smm_save_state_get_reg, .set_reg = em64t100_smm_save_state_set_reg, }; -const struct smm_save_state_ops em64t101_smm_ops = { +const struct intel_smm_save_state_ops em64t101_smm_ops = { .get_io_misc_info = em64t101_smm_save_state_get_io_misc_info, .get_reg = em64t101_smm_save_state_get_reg, .set_reg = em64t101_smm_save_state_set_reg, diff --git a/src/soc/intel/common/block/smm/smitraphandler.c b/src/soc/intel/common/block/smm/smitraphandler.c index 974c489..b7e25e4 100644 --- a/src/soc/intel/common/block/smm/smitraphandler.c +++ b/src/soc/intel/common/block/smm/smitraphandler.c @@ -56,7 +56,7 @@ } void smihandler_southbridge_mc( - const struct smm_save_state_ops *save_state_ops) + const struct intel_smm_save_state_ops *save_state_ops) { u32 reg32 = inl(ACPI_BASE_ADDRESS + SMI_EN); @@ -68,7 +68,7 @@ } void smihandler_southbridge_monitor( - const struct smm_save_state_ops *save_state_ops) + const struct intel_smm_save_state_ops *save_state_ops) { #define IOTRAP(x) (trap_sts & (1 << x)) u32 trap_cycle; diff --git a/src/soc/intel/icelake/smihandler.c b/src/soc/intel/icelake/smihandler.c index b7c37d4..039900e 100644 --- a/src/soc/intel/icelake/smihandler.c +++ b/src/soc/intel/icelake/smihandler.c @@ -29,7 +29,7 @@ #define CSME0_BAR 0x0 #define CSME0_FID 0xb0 -const struct smm_save_state_ops *get_smm_save_state_ops(void) +const struct intel_smm_save_state_ops *get_smm_save_state_ops(void) { return &em64t101_smm_ops; } diff --git a/src/soc/intel/skylake/smihandler.c b/src/soc/intel/skylake/smihandler.c index 2e93075..50a82f9 100644 --- a/src/soc/intel/skylake/smihandler.c +++ b/src/soc/intel/skylake/smihandler.c @@ -20,7 +20,7 @@ #include <intelblocks/smihandler.h> #include <soc/pm.h> -const struct smm_save_state_ops *get_smm_save_state_ops(void) +const struct intel_smm_save_state_ops *get_smm_save_state_ops(void) { return &em64t101_smm_ops; } diff --git a/src/soc/intel/tigerlake/smihandler.c b/src/soc/intel/tigerlake/smihandler.c index bf07bea..25bdacc 100644 --- a/src/soc/intel/tigerlake/smihandler.c +++ b/src/soc/intel/tigerlake/smihandler.c @@ -29,7 +29,7 @@ #define CSME0_BAR 0x0 #define CSME0_FID 0xb0 -const struct smm_save_state_ops *get_smm_save_state_ops(void) +const struct intel_smm_save_state_ops *get_smm_save_state_ops(void) { return &em64t101_smm_ops; } -- To view, visit https://review.coreboot.org/c/coreboot/+/37110 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib24ab09e7f35bb231a8069905860c612d5e35454 Gerrit-Change-Number: 37110 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/intel/gen1/smmrelocate: Fix stale comment

by Arthur Heymans (Code Review)

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36659 ) Change subject: cpu/intel/gen1/smmrelocate: Fix stale comment ...................................................................... cpu/intel/gen1/smmrelocate: Fix stale comment Change-Id: I91ed5f7cbcfa5c510bb8e74049ec860397d7dbba Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/smm/gen1/smmrelocate.c 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/36659/1 diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c index 5350d1c..e3f934d 100644 --- a/src/cpu/intel/smm/gen1/smmrelocate.c +++ b/src/cpu/intel/smm/gen1/smmrelocate.c @@ -11,8 +11,7 @@ * GNU General Public License for more details. */ -/* SMM relocation with intention to work for i945-ivybridge. - Right now used for sandybridge and ivybridge. */ +/* SMM relocation for i945-ivybridge. */ #include <assert.h> #include <types.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/36659 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I91ed5f7cbcfa5c510bb8e74049ec860397d7dbba Gerrit-Change-Number: 36659 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/intel/smm: Drop em64t save state

by Arthur Heymans (Code Review)

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36660 ) Change subject: cpu/intel/smm: Drop em64t save state ...................................................................... cpu/intel/smm: Drop em64t save state This save state is just plainly wrong in many regards and em64t100 should be used. Checked with a model 17 core2 CPU. Change-Id: I4d89691e87c91dd12b34a44b74849b18b4ac5369 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/smm/smihandler.c M src/include/cpu/intel/em64t100_save_state.h D src/include/cpu/intel/em64t_save_state.h 3 files changed, 6 insertions(+), 109 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/36660/1 diff --git a/src/cpu/x86/smm/smihandler.c b/src/cpu/x86/smm/smihandler.c index 68b7859..3fd77b3 100644 --- a/src/cpu/x86/smm/smihandler.c +++ b/src/cpu/x86/smm/smihandler.c @@ -29,7 +29,7 @@ typedef enum { AMD64, - EM64T, + EM64T100, EM64T101, LEGACY } save_state_type_t; @@ -38,7 +38,7 @@ save_state_type_t type; union { amd64_smm_state_save_area_t *amd64_state_save; - em64t_smm_state_save_area_t *em64t_state_save; + em64t100_smm_state_save_area_t *em64t100_state_save; em64t101_smm_state_save_area_t *em64t101_state_save; legacy_smm_state_save_area_t *legacy_state_save; }; @@ -178,10 +178,10 @@ SMM_LEGACY_ARCH_OFFSET, node); break; case 0x00030100: - state_save.type = EM64T; + state_save.type = EM64T100; state_save.em64t_state_save = smm_save_state(smm_base, - SMM_EM64T_ARCH_OFFSET, node); + SMM_EM64T100_ARCH_OFFSET, node); break; case 0x00030101: /* SandyBridge, IvyBridge, and Haswell */ state_save.type = EM64T101; diff --git a/src/include/cpu/intel/em64t100_save_state.h b/src/include/cpu/intel/em64t100_save_state.h index f76fa4b..6e8e1d9 100644 --- a/src/include/cpu/intel/em64t100_save_state.h +++ b/src/include/cpu/intel/em64t100_save_state.h @@ -17,10 +17,8 @@ #include <types.h> #include <cpu/x86/smm.h> -/* Intel Revision 30100 SMM State-Save Area - * The following processor architectures use this: - * - Bay Trail - */ +/* Intel Revision 30100 SMM State-Save Area */ + #define SMM_EM64T100_ARCH_OFFSET 0x7c00 #define SMM_EM64T100_SAVE_STATE_OFFSET \ SMM_SAVE_STATE_BEGIN(SMM_EM64T100_ARCH_OFFSET) diff --git a/src/include/cpu/intel/em64t_save_state.h b/src/include/cpu/intel/em64t_save_state.h deleted file mode 100644 index 1dd01a6..0000000 --- a/src/include/cpu/intel/em64t_save_state.h +++ /dev/null @@ -1,101 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __EM64T_SAVE_STATE_H__ -#define __EM64T_SAVE_STATE_H__ - -#include <types.h> -#include <cpu/x86/smm.h> - -/* Intel Core 2 (EM64T) SMM State-Save Area - * starts @ 0x7c00 - */ -#define SMM_EM64T_ARCH_OFFSET 0x7c00 -#define SMM_EM64T_SAVE_STATE_OFFSET \ - SMM_SAVE_STATE_BEGIN(SMM_EM64T_ARCH_OFFSET) -typedef struct { - u8 reserved0[256]; - u8 reserved1[208]; - - u32 gdtr_upper_base; - u32 ldtr_upper_base; - u32 idtr_upper_base; - - u8 reserved2[4]; - - u64 io_rdi; - u64 io_rip; - u64 io_rcx; - u64 io_rsi; - u64 cr4; - - u8 reserved3[68]; - - u64 gdtr_base; - u64 idtr_base; - u64 ldtr_base; - - u8 reserved4[84]; - - u32 smm_revision; - u32 smbase; - - u16 io_restart; - u16 autohalt_restart; - - u8 reserved5[24]; - - u64 r15; - u64 r14; - u64 r13; - u64 r12; - u64 r11; - u64 r10; - u64 r9; - u64 r8; - - u64 rax; - u64 rcx; - u64 rdx; - u64 rbx; - - u64 rsp; - u64 rbp; - u64 rsi; - u64 rdi; - - - u64 io_mem_addr; - u32 io_misc_info; - - u32 es_sel; - u32 cs_sel; - u32 ss_sel; - u32 ds_sel; - u32 fs_sel; - u32 gs_sel; - - u32 ldtr_sel; - u32 tr_sel; - - u64 dr7; - u64 dr6; - u64 rip; - u64 efer; - u64 rflags; - - u64 cr3; - u64 cr0; -} __packed em64t_smm_state_save_area_t; - -#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/36660 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d89691e87c91dd12b34a44b74849b18b4ac5369 Gerrit-Change-Number: 36660 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: lib/fmap.c: Properly handle cache for !C_ENVIRONMENT_BOOTBLOCK

by Arthur Heymans (Code Review)

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36908 ) Change subject: lib/fmap.c: Properly handle cache for !C_ENVIRONMENT_BOOTBLOCK ...................................................................... lib/fmap.c: Properly handle cache for !C_ENVIRONMENT_BOOTBLOCK On platforms without C_ENVIRONMENT_BOOTBLOCK the first stage accessing FMAP is romstage. As on these platforms only romstage is expected to call setup_preram_cache() no further handling is needed. Change-Id: I7d70585b0c076707e73e20c2ed3f11e4c9ffdf37 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/lib/fmap.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/36908/1 diff --git a/src/lib/fmap.c b/src/lib/fmap.c index 4b4179c..f0fae55 100644 --- a/src/lib/fmap.c +++ b/src/lib/fmap.c @@ -78,7 +78,7 @@ } struct fmap *fmap = (struct fmap *)_fmap_cache; - if (!ENV_BOOTBLOCK) { + if (!ENV_BOOTBLOCK && CONFIG(C_ENVIRONMENT_BOOTBLOCK)) { /* NOTE: This assumes that for all platforms running this code, the bootblock is the first stage and the bootblock will make at least one FMAP access (usually from finding CBFS). */ -- To view, visit https://review.coreboot.org/c/coreboot/+/36908 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d70585b0c076707e73e20c2ed3f11e4c9ffdf37 Gerrit-Change-Number: 36908 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd: Move SCI enable outside table creation

by Kyösti Mälkki (Code Review)

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36811 ) Change subject: soc/amd: Move SCI enable outside table creation ...................................................................... soc/amd: Move SCI enable outside table creation Preferably, coreboot tables creation is kept hardware-invariant. Change-Id: Id7f79fc959766813d60f847482567579a02db124 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/picasso/acpi.c M src/soc/amd/picasso/finalize.c M src/soc/amd/stoneyridge/acpi.c M src/soc/amd/stoneyridge/finalize.c 4 files changed, 18 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/36811/1 diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index 8597c4e..2a7ae0b 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -98,15 +98,6 @@ fadt->s4bios_req = 0; /* Not supported */ fadt->pstate_cnt = 0; /* Not supported */ fadt->cst_cnt = 0; /* Not supported */ - acpi_disable_sci(); - } else { - fadt->smi_cmd = 0; /* disable system management mode */ - fadt->acpi_enable = 0; /* unused if SMI_CMD = 0 */ - fadt->acpi_disable = 0; /* unused if SMI_CMD = 0 */ - fadt->s4bios_req = 0; /* unused if SMI_CMD = 0 */ - fadt->pstate_cnt = 0; /* unused if SMI_CMD = 0 */ - fadt->cst_cnt = 0x00; /* unused if SMI_CMD = 0 */ - acpi_enable_sci(); } fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; diff --git a/src/soc/amd/picasso/finalize.c b/src/soc/amd/picasso/finalize.c index 0ec7bd9..3e66d88 100644 --- a/src/soc/amd/picasso/finalize.c +++ b/src/soc/amd/picasso/finalize.c @@ -13,12 +13,14 @@ * GNU General Public License for more details. */ +#include <arch/acpi.h> #include <cpu/x86/mp.h> #include <cpu/x86/msr.h> #include <cpu/amd/msr.h> #include <bootstate.h> #include <timer.h> #include <console/console.h> +#include <soc/acpi.h> static void per_core_finalize(void *unused) { @@ -53,6 +55,13 @@ { finalize_cores(); + if (!acpi_is_wakeup_s3()) { + if (CONFIG(HAVE_SMI_HANDLER)) + acpi_disable_sci(); + else + acpi_enable_sci(); + } + post_code(POST_OS_BOOT); } diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index d1ea24f..2327ed9 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -100,15 +100,6 @@ fadt->s4bios_req = 0; /* Not supported */ fadt->pstate_cnt = 0; /* Not supported */ fadt->cst_cnt = 0; /* Not supported */ - acpi_disable_sci(); - } else { - fadt->smi_cmd = 0; /* disable system management mode */ - fadt->acpi_enable = 0; /* unused if SMI_CMD = 0 */ - fadt->acpi_disable = 0; /* unused if SMI_CMD = 0 */ - fadt->s4bios_req = 0; /* unused if SMI_CMD = 0 */ - fadt->pstate_cnt = 0; /* unused if SMI_CMD = 0 */ - fadt->cst_cnt = 0x00; /* unused if SMI_CMD = 0 */ - acpi_enable_sci(); } fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; diff --git a/src/soc/amd/stoneyridge/finalize.c b/src/soc/amd/stoneyridge/finalize.c index 0ec7bd9..3e66d88 100644 --- a/src/soc/amd/stoneyridge/finalize.c +++ b/src/soc/amd/stoneyridge/finalize.c @@ -13,12 +13,14 @@ * GNU General Public License for more details. */ +#include <arch/acpi.h> #include <cpu/x86/mp.h> #include <cpu/x86/msr.h> #include <cpu/amd/msr.h> #include <bootstate.h> #include <timer.h> #include <console/console.h> +#include <soc/acpi.h> static void per_core_finalize(void *unused) { @@ -53,6 +55,13 @@ { finalize_cores(); + if (!acpi_is_wakeup_s3()) { + if (CONFIG(HAVE_SMI_HANDLER)) + acpi_disable_sci(); + else + acpi_enable_sci(); + } + post_code(POST_OS_BOOT); } -- To view, visit https://review.coreboot.org/c/coreboot/+/36811 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id7f79fc959766813d60f847482567579a02db124 Gerrit-Change-Number: 36811 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu,soc/intel: Refactor em64t101 SMI handlers

by Kyösti Mälkki (Code Review)

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37108 ) Change subject: cpu,soc/intel: Refactor em64t101 SMI handlers ...................................................................... cpu,soc/intel: Refactor em64t101 SMI handlers Change-Id: I177ca3b2966ccd985d72749ea2bd096ec4f233d6 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/intel/haswell/Makefile.inc M src/cpu/intel/haswell/haswell_init.c D src/cpu/intel/haswell/smmrelocate.c M src/cpu/intel/model_1067x/mp_init.c M src/cpu/intel/model_2065x/model_2065x_init.c M src/cpu/intel/model_206ax/model_206ax_init.c M src/cpu/intel/smm/Makefile.inc A src/cpu/intel/smm/em64t101.c M src/cpu/intel/smm/gen1/smmrelocate.c M src/cpu/intel/smm/smm_reloc.c A src/cpu/intel/smm/smmrelocate_cpu_save.c M src/include/cpu/intel/em64t101_save_state.h M src/include/cpu/intel/smm_reloc.h M src/soc/intel/broadwell/Makefile.inc M src/soc/intel/broadwell/cpu.c D src/soc/intel/broadwell/smmrelocate.c M src/soc/intel/cannonlake/Makefile.inc M src/soc/intel/cannonlake/cpu.c D src/soc/intel/cannonlake/smmrelocate.c M src/soc/intel/denverton_ns/Makefile.inc M src/soc/intel/denverton_ns/cpu.c M src/soc/intel/icelake/Makefile.inc M src/soc/intel/icelake/cpu.c D src/soc/intel/icelake/smmrelocate.c M src/soc/intel/skylake/Makefile.inc M src/soc/intel/skylake/cpu.c D src/soc/intel/skylake/smmrelocate.c M src/soc/intel/tigerlake/Makefile.inc D src/soc/intel/tigerlake/smmrelocate.c M src/southbridge/intel/lynxpoint/Makefile.inc 30 files changed, 459 insertions(+), 1,860 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/37108/1 diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc index aebeed4..8ae0a65 100644 --- a/src/cpu/intel/haswell/Makefile.inc +++ b/src/cpu/intel/haswell/Makefile.inc @@ -3,7 +3,6 @@ romstage-y += ../car/romstage.c ramstage-y += acpi.c -ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c smm-y += finalize.c diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 66dca28..e476a10 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -746,7 +746,7 @@ *parallel = 1; } -static void per_cpu_smm_trigger(void) +static void alt_per_cpu_smm_trigger(void) { /* Relocate the SMM handler. */ smm_relocate(); @@ -759,25 +759,27 @@ { /* Now that all APs have been relocated as well as the BSP let SMIs * start flowing. */ - smm_southbridge_enable_smi(); + if (CONFIG(HAVE_SMI_HANDLER)) + smm_southbridge_enable_smi(); /* Lock down the SMRAM space. */ smm_lock(); } -static const struct mp_ops mp_ops = { +static struct mp_ops mp_ops = { .pre_mp_init = pre_mp_init, .get_cpu_count = get_cpu_count, - .get_smm_info = smm_info, .get_microcode_info = get_microcode_info, - .pre_mp_smm_init = smm_initialize, - .per_cpu_smm_trigger = per_cpu_smm_trigger, - .relocation_handler = smm_relocation_handler, .post_mp_init = post_mp_init, }; void mp_init_cpus(struct bus *cpu_bus) { + if (CONFIG(HAVE_SMI_HANDLER)) { + select_mp_ops_em64t101_detect(&mp_ops); + mp_ops.per_cpu_smm_trigger = alt_per_cpu_smm_trigger; + } + if (mp_init_with_smm(cpu_bus, &mp_ops)) printk(BIOS_ERR, "MP initialization failure.\n"); } diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c deleted file mode 100644 index 88e5240..0000000 --- a/src/cpu/intel/haswell/smmrelocate.c +++ /dev/null @@ -1,290 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <types.h> -#include <string.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ops.h> -#include <cpu/x86/cache.h> -#include <cpu/x86/lapic.h> -#include <cpu/x86/mp.h> -#include <cpu/x86/msr.h> -#include <cpu/x86/mtrr.h> -#include <cpu/x86/smm.h> -#include <cpu/intel/em64t101_save_state.h> -#include <cpu/intel/smm_reloc.h> -#include <console/console.h> -#include <northbridge/intel/haswell/haswell.h> -#include <southbridge/intel/lynxpoint/pch.h> -#include "haswell.h" - -#define MSR_PRMRR_PHYS_BASE 0x1f4 -#define MSR_PRMRR_PHYS_MASK 0x1f5 -#define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4 -#define MSR_UNCORE_PRMRR_PHYS_MASK 0x2f5 -#define SMM_MCA_CAP_MSR 0x17d -#define SMM_CPU_SVRSTR_BIT 57 -#define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32)) -#define SMM_FEATURE_CONTROL_MSR 0x4e0 -#define SMM_CPU_SAVE_EN (1 << 1) -/* SMM save state MSRs */ -#define SMBASE_MSR 0xc20 -#define IEDBASE_MSR 0xc22 - -#define SMRR_SUPPORTED (1 << 11) -#define PRMRR_SUPPORTED (1 << 12) - - - -static void update_save_state(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase, - struct smm_relocation_params *relo_params) -{ - u32 smbase; - u32 iedbase; - - /* The relocated handler runs with all CPUs concurrently. Therefore - * stagger the entry points adjusting SMBASE downwards by save state - * size * CPU num. */ - smbase = staggered_smbase; - iedbase = relo_params->ied_base; - - printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x\n", - smbase, iedbase); - - /* All threads need to set IEDBASE and SMBASE to the relocated - * handler region. However, the save state location depends on the - * smm_save_state_in_msrs field in the relocation parameters. If - * smm_save_state_in_msrs is non-zero then the CPUs are relocating - * the SMM handler in parallel, and each CPUs save state area is - * located in their respective MSR space. If smm_save_state_in_msrs - * is zero then the SMM relocation is happening serially so the - * save state is at the same default location for all CPUs. */ - if (relo_params->smm_save_state_in_msrs) { - msr_t smbase_msr; - msr_t iedbase_msr; - - smbase_msr.lo = smbase; - smbase_msr.hi = 0; - - /* According the BWG the IEDBASE MSR is in bits 63:32. It's - * not clear why it differs from the SMBASE MSR. */ - iedbase_msr.lo = 0; - iedbase_msr.hi = iedbase; - - wrmsr(SMBASE_MSR, smbase_msr); - wrmsr(IEDBASE_MSR, iedbase_msr); - } else { - em64t101_smm_state_save_area_t *save_state; - - save_state = (void *)(curr_smbase + SMM_DEFAULT_SIZE - - sizeof(*save_state)); - - save_state->smbase = smbase; - save_state->iedbase = iedbase; - } -} - -/* Returns 1 if SMM MSR save state was set. */ -static int bsp_setup_msr_save_state(struct smm_relocation_params *relo_params) -{ - msr_t smm_mca_cap; - - smm_mca_cap = rdmsr(SMM_MCA_CAP_MSR); - if (smm_mca_cap.hi & SMM_CPU_SVRSTR_MASK) { - msr_t smm_feature_control; - - smm_feature_control = rdmsr(SMM_FEATURE_CONTROL_MSR); - smm_feature_control.hi = 0; - smm_feature_control.lo |= SMM_CPU_SAVE_EN; - wrmsr(SMM_FEATURE_CONTROL_MSR, smm_feature_control); - relo_params->smm_save_state_in_msrs = 1; - } - return relo_params->smm_save_state_in_msrs; -} - -/* The relocation work is actually performed in SMM context, but the code - * resides in the ramstage module. This occurs by trampolining from the default - * SMRAM entry point to here. */ -void smm_relocation_handler(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase) -{ - msr_t mtrr_cap; - struct smm_relocation_params *relo_params = &smm_reloc_params; - - printk(BIOS_DEBUG, "In relocation handler: cpu %d\n", cpu); - - /* Determine if the processor supports saving state in MSRs. If so, - * enable it before the non-BSPs run so that SMM relocation can occur - * in parallel in the non-BSP CPUs. */ - if (cpu == 0) { - /* If smm_save_state_in_msrs is 1 then that means this is the - * 2nd time through the relocation handler for the BSP. - * Parallel SMM handler relocation is taking place. However, - * it is desired to access other CPUs save state in the real - * SMM handler. Therefore, disable the SMM save state in MSRs - * feature. */ - if (relo_params->smm_save_state_in_msrs) { - msr_t smm_feature_control; - - smm_feature_control = rdmsr(SMM_FEATURE_CONTROL_MSR); - smm_feature_control.lo &= ~SMM_CPU_SAVE_EN; - wrmsr(SMM_FEATURE_CONTROL_MSR, smm_feature_control); - } else if (bsp_setup_msr_save_state(relo_params)) - /* Just return from relocation handler if MSR save - * state is enabled. In that case the BSP will come - * back into the relocation handler to setup the new - * SMBASE as well disabling SMM save state in MSRs. */ - return; - } - - /* Make appropriate changes to the save state map. */ - update_save_state(cpu, curr_smbase, staggered_smbase, relo_params); - - /* Write PRMRR and SMRR MSRs based on indicated support. */ - mtrr_cap = rdmsr(MTRR_CAP_MSR); - if (mtrr_cap.lo & SMRR_SUPPORTED) - write_smrr(relo_params); - - if (mtrr_cap.lo & PRMRR_SUPPORTED) { - write_prmrr(relo_params); - /* UNCORE_PRMRR msrs are package level. Therefore, only - * configure these MSRs on the BSP. */ - if (cpu == 0) - write_uncore_prmrr(relo_params); - } -} - -static void fill_in_relocation_params(struct smm_relocation_params *params) -{ - uintptr_t tseg_base; - size_t tseg_size; - - u32 prmrr_base; - u32 prmrr_size; - int phys_bits; - /* All range registers are aligned to 4KiB */ - const u32 rmask = ~((1 << 12) - 1); - - /* Some of the range registers are dependent on the number of physical - * address bits supported. */ - phys_bits = cpuid_eax(0x80000008) & 0xff; - - /* The range bounded by the TSEGMB and BGSM registers encompasses the - * SMRAM range as well as the IED range. However, the SMRAM available - * to the handler is 4MiB since the IEDRAM lives TSEGMB + 4MiB. - */ - smm_region(&tseg_base, &tseg_size); - - /* SMRR has 32-bits of valid address aligned to 4KiB. */ - params->smrr_base.lo = (tseg_base & rmask) | MTRR_TYPE_WRBACK; - params->smrr_base.hi = 0; - params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID; - params->smrr_mask.hi = 0; - - smm_subregion(SMM_SUBREGION_CHIPSET, &params->ied_base, &params->ied_size); - - /* The PRMRR and UNCORE_PRMRR are at IEDBASE + 2MiB */ - prmrr_base = (params->ied_base + (2 << 20)) & rmask; - prmrr_size = params->ied_size - (2 << 20); - - /* PRMRR has 46 bits of valid address aligned to 4KiB. It's dependent - * on the number of physical address bits supported. */ - params->prmrr_base.lo = prmrr_base | MTRR_TYPE_WRBACK; - params->prmrr_base.hi = 0; - params->prmrr_mask.lo = (~(prmrr_size - 1) & rmask) - | MTRR_PHYS_MASK_VALID; - params->prmrr_mask.hi = (1 << (phys_bits - 32)) - 1; - - /* UNCORE_PRMRR has 39 bits of valid address aligned to 4KiB. */ - params->uncore_prmrr_base.lo = prmrr_base; - params->uncore_prmrr_base.hi = 0; - params->uncore_prmrr_mask.lo = (~(prmrr_size - 1) & rmask) | - MTRR_PHYS_MASK_VALID; - params->uncore_prmrr_mask.hi = (1 << (39 - 32)) - 1; -} - -static void setup_ied_area(struct smm_relocation_params *params) -{ - char *ied_base; - - struct ied_header ied = { - .signature = "INTEL RSVD", - .size = params->ied_size, - .reserved = {0}, - }; - - ied_base = (void *)params->ied_base; - - /* Place IED header at IEDBASE. */ - memcpy(ied_base, &ied, sizeof(ied)); - - /* Zero out 32KiB at IEDBASE + 1MiB */ - memset(ied_base + (1 << 20), 0, (32 << 10)); - - /* According to the BWG MP init section 2MiB of memory at IEDBASE + - * 2MiB should be zeroed as well. However, I suspect what is intended - * is to clear the memory covered by PRMRR. TODO(adurbin): figure out if - * this is really required. - */ - //memset(ied_base + (2 << 20), 0, (2 << 20)); -} - -void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, - size_t *smm_save_state_size) -{ - printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); - - fill_in_relocation_params(&smm_reloc_params); - - smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); - - setup_ied_area(&smm_reloc_params); - - *smm_save_state_size = sizeof(em64t101_smm_state_save_area_t); -} - -void smm_initialize(void) -{ - /* Clear the SMM state in the southbridge. */ - smm_southbridge_clear_state(); - - /* - * Run the relocation handler for on the BSP to check and set up - * parallel SMM relocation. - */ - smm_initiate_relocation(); - - if (smm_reloc_params.smm_save_state_in_msrs) - printk(BIOS_DEBUG, "Doing parallel SMM relocation.\n"); -} - -/* The default SMM entry can happen in parallel or serially. If the - * default SMM entry is done in parallel the BSP has already setup - * the saving state to each CPU's MSRs. At least one save state size - * is required for the initial SMM entry for the BSP to determine if - * parallel SMM relocation is even feasible. */ -void smm_relocate(void) -{ - /* - * If smm_save_state_in_msrs is non-zero then parallel SMM relocation - * shall take place. Run the relocation handler a second time on the - * BSP to do * the final move. For APs, a relocation handler always - * needs to be run. - */ - if (smm_reloc_params.smm_save_state_in_msrs) - smm_initiate_relocation_parallel(); - else if (!boot_cpu()) - smm_initiate_relocation(); -} diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c index dd44582..6876e14 100644 --- a/src/cpu/intel/model_1067x/mp_init.c +++ b/src/cpu/intel/model_1067x/mp_init.c @@ -50,42 +50,6 @@ /* the SMRR enable and lock bit need to be set in IA32_FEATURE_CONTROL to enable SMRR so configure IA32_FEATURE_CONTROL early on */ -static void pre_mp_smm_init(void) -{ - smm_initialize(); -} - -#define SMRR_SUPPORTED (1 << 11) - -static void per_cpu_smm_trigger(void) -{ - msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR); - if (cpu_has_alternative_smrr() && mtrr_cap.lo & SMRR_SUPPORTED) { - set_feature_ctrl_vmx(); - msr_t ia32_ft_ctrl = rdmsr(IA32_FEATURE_CONTROL); - /* We don't care if the lock is already setting - as our smm relocation handler is able to handle - setups where SMRR is not enabled here. */ - if (ia32_ft_ctrl.lo & (1 << 0)) { - /* IA32_FEATURE_CONTROL locked. If we set it again we - get an illegal instruction. */ - printk(BIOS_DEBUG, "IA32_FEATURE_CONTROL already locked\n"); - printk(BIOS_DEBUG, "SMRR status: %senabled\n", - ia32_ft_ctrl.lo & (1 << 3) ? "" : "not "); - } else { - if (!CONFIG(SET_IA32_FC_LOCK_BIT)) - printk(BIOS_INFO, - "Overriding CONFIG_SET_IA32_FC_LOCK_BIT to enable SMRR\n"); - ia32_ft_ctrl.lo |= (1 << 3) | (1 << 0); - wrmsr(IA32_FEATURE_CONTROL, ia32_ft_ctrl); - } - } else { - set_vmx_and_lock(); - } - - /* Relocate the SMM handler. */ - smm_relocate(); -} static void post_mp_init(void) { @@ -97,14 +61,10 @@ smm_lock(); } -static const struct mp_ops mp_ops = { +static struct mp_ops mp_ops = { .pre_mp_init = pre_mp_init, .get_cpu_count = get_cpu_count, - .get_smm_info = smm_info, .get_microcode_info = get_microcode_info, - .pre_mp_smm_init = pre_mp_smm_init, - .per_cpu_smm_trigger = per_cpu_smm_trigger, - .relocation_handler = smm_relocation_handler, .post_mp_init = post_mp_init, }; @@ -112,6 +72,9 @@ { microcode_patch = intel_microcode_find(); + if (CONFIG(HAVE_SMI_HANDLER)) + select_mp_ops_em64t101_alt(&mp_ops); + if (mp_init_with_smm(cpu_bus, &mp_ops)) printk(BIOS_ERR, "MP initialization failure.\n"); } diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index d7e84ec..cd93b19 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -300,7 +300,7 @@ *parallel = 1; } -static void per_cpu_smm_trigger(void) +static void alt_per_cpu_smm_trigger(void) { /* Relocate the SMM handler. */ smm_relocate(); @@ -320,19 +320,20 @@ } -static const struct mp_ops mp_ops = { +static struct mp_ops mp_ops = { .pre_mp_init = pre_mp_init, .get_cpu_count = get_cpu_count, - .get_smm_info = smm_info, .get_microcode_info = get_microcode_info, - .pre_mp_smm_init = smm_initialize, - .per_cpu_smm_trigger = per_cpu_smm_trigger, - .relocation_handler = smm_relocation_handler, .post_mp_init = post_mp_init, }; void mp_init_cpus(struct bus *cpu_bus) { + if (CONFIG(HAVE_SMI_HANDLER)) { + select_mp_ops_em64t101(&mp_ops); + mp_ops.per_cpu_smm_trigger = alt_per_cpu_smm_trigger; + } + if (mp_init_with_smm(cpu_bus, &mp_ops)) printk(BIOS_ERR, "MP initialization failure.\n"); } diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index cc20676..41ef411 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -526,7 +526,7 @@ *parallel = 1; } -static void per_cpu_smm_trigger(void) +static void alt_per_cpu_smm_trigger(void) { /* Relocate the SMM handler. */ smm_relocate(); @@ -546,19 +546,20 @@ } -static const struct mp_ops mp_ops = { +static struct mp_ops mp_ops = { .pre_mp_init = pre_mp_init, .get_cpu_count = get_cpu_count, - .get_smm_info = smm_info, .get_microcode_info = get_microcode_info, - .pre_mp_smm_init = smm_initialize, - .per_cpu_smm_trigger = per_cpu_smm_trigger, - .relocation_handler = smm_relocation_handler, .post_mp_init = post_mp_init, }; void mp_init_cpus(struct bus *cpu_bus) { + if (CONFIG(HAVE_SMI_HANDLER)) { + select_mp_ops_em64t101(&mp_ops); + mp_ops.per_cpu_smm_trigger = alt_per_cpu_smm_trigger; + } + if (mp_init_with_smm(cpu_bus, &mp_ops)) printk(BIOS_ERR, "MP initialization failure.\n"); } diff --git a/src/cpu/intel/smm/Makefile.inc b/src/cpu/intel/smm/Makefile.inc index 97fedc9..5fc801f 100644 --- a/src/cpu/intel/smm/Makefile.inc +++ b/src/cpu/intel/smm/Makefile.inc @@ -1,2 +1,4 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smm_reloc.c +ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate_cpu_save.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += em64t100.c +ramstage-$(CONFIG_HAVE_SMI_HANDLER) += em64t101.c diff --git a/src/cpu/intel/smm/em64t101.c b/src/cpu/intel/smm/em64t101.c new file mode 100644 index 0000000..9d1003f --- /dev/null +++ b/src/cpu/intel/smm/em64t101.c @@ -0,0 +1,88 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <types.h> +#include <cpu/x86/mp.h> +#include <cpu/intel/em64t101_save_state.h> +#include <cpu/intel/smm_reloc.h> + +/* + * ice, sky, cannon : without ied + * fsp_broadwell_de : ied with prmrr + * haswell, broadwell : ied with prmrr and uncore_prmrr + */ + +static void std_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, + size_t *smm_save_state_size) +{ + fill_in_smrr(&smm_reloc_params); + fill_in_ied_params(&smm_reloc_params, 0); + + smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); + *smm_save_state_size = sizeof(em64t101_smm_state_save_area_t); +} + +static void std_smm_initialize(void) +{ + /* Clear the SMM state in the southbridge. */ + smm_southbridge_clear_state(); + + /* Run the relocation handler for on the BSP to check and set up + parallel SMM relocation. */ + smm_initiate_relocation(); + + if (smm_reloc_params.smm_save_state_in_msrs) + printk(BIOS_DEBUG, "Doing parallel SMM relocation.\n"); +} + +/* The relocation work is actually performed in SMM context, but the code + * resides in the ramstage module. This occurs by trampolining from the default + * SMRAM entry point to here. */ +static void std_smm_relocation_handler(int cpu, uintptr_t curr_smbase, + uintptr_t staggered_smbase) +{ + struct smm_relocation_params *relo_params = &smm_reloc_params; + em64t101_smm_state_save_area_t *save_state; + + printk(BIOS_DEBUG, "In relocation handler: cpu %d SMBASE=0x%08x\n", cpu, + (u32)staggered_smbase); + + /* Make appropriate changes to the save state map. */ + save_state = (void *)(curr_smbase + SMM_DEFAULT_SIZE - sizeof(*save_state)); + save_state->smbase = staggered_smbase; + save_state->iedbase = relo_params->ied_base; + + /* Write SMRR MSRs based on indicated support. */ + write_smm_msrs(cpu, relo_params); +} + +void select_mp_ops_em64t101(struct mp_ops *mp_ops) +{ + mp_ops->get_smm_info = std_smm_info; + mp_ops->relocation_handler = std_smm_relocation_handler; + + mp_ops->pre_mp_smm_init = std_smm_initialize; + mp_ops->per_cpu_smm_trigger = smm_relocate; +} + +void select_mp_ops_em64t101_alt(struct mp_ops *mp_ops) +{ + select_mp_ops_em64t101(mp_ops); + detect_em64t101_alternative_smrr(mp_ops); +} + +void select_mp_ops_em64t101_detect(struct mp_ops *mp_ops) +{ + select_mp_ops_em64t101(mp_ops); + detect_em64t101_cpu_save(mp_ops); +} diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c index df54c3c..81eb17a 100644 --- a/src/cpu/intel/smm/gen1/smmrelocate.c +++ b/src/cpu/intel/smm/gen1/smmrelocate.c @@ -32,39 +32,71 @@ #define SMRR_SUPPORTED (1 << 11) - - -/* On model_6fx, model_1067x and model_106cx SMRR functions slightly - differently. The MSR are at different location from the rest - and need to be explicitly enabled in IA32_FEATURE_CONTROL MSR. */ -bool cpu_has_alternative_smrr(void) +static void alt_1_per_cpu_smm_trigger(void) { - struct cpuinfo_x86 c; - get_fms(&c, cpuid_eax(1)); - if (c.x86 != 6) - return false; - switch (c.x86_model) { - case 0xf: - case 0x17: /* core2 */ - case 0x1c: /* Bonnell */ - return true; - default: - return false; - } + set_vmx_and_lock(); + + /* Relocate the SMM handler. */ + smm_relocate(); } -static void write_smrr_alt(struct smm_relocation_params *relo_params) +static void alt_2_per_cpu_smm_trigger(void) { - msr_t msr; + msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR); + if (mtrr_cap.lo & SMRR_SUPPORTED) { + set_feature_ctrl_vmx(); + msr_t ia32_ft_ctrl = rdmsr(IA32_FEATURE_CONTROL); + /* We don't care if the lock is already setting + as our smm relocation handler is able to handle + setups where SMRR is not enabled here. */ + if (ia32_ft_ctrl.lo & (1 << 0)) { + /* IA32_FEATURE_CONTROL locked. If we set it again we + get an illegal instruction. */ + printk(BIOS_DEBUG, "IA32_FEATURE_CONTROL already locked\n"); + printk(BIOS_DEBUG, "SMRR status: %senabled\n", + ia32_ft_ctrl.lo & (1 << 3) ? "" : "not "); + } else { + if (!CONFIG(SET_IA32_FC_LOCK_BIT)) + printk(BIOS_INFO, + "Overriding CONFIG_SET_IA32_FC_LOCK_BIT to enable SMRR\n"); + ia32_ft_ctrl.lo |= (1 << 3) | (1 << 0); + wrmsr(IA32_FEATURE_CONTROL, ia32_ft_ctrl); + } + } + + /* Relocate the SMM handler. */ + smm_relocate(); +} + +static void alt_smm_relocation_handler(int cpu, uintptr_t curr_smbase, + uintptr_t staggered_smbase) +{ + struct smm_relocation_params *relo_params = &smm_reloc_params; + em64t101_smm_state_save_area_t *save_state; + msr_t mtrr_cap, msr; + + printk(BIOS_DEBUG, "In relocation handler: cpu %d SMBASE=0x%08x\n", cpu, + (u32)staggered_smbase); + + /* Make appropriate changes to the save state map. */ + save_state = (void *)(curr_smbase + SMM_DEFAULT_SIZE - sizeof(*save_state)); + save_state->smbase = staggered_smbase; + save_state->iedbase = relo_params->ied_base; + + /* Write SMRR MSRs based on indicated support. */ + mtrr_cap = rdmsr(MTRR_CAP_MSR); + if (!(mtrr_cap & SMRR_SUPPORTED)) + return; + msr = rdmsr(IA32_FEATURE_CONTROL); /* SMRR enabled and feature locked */ - if (!((msr.lo & SMRR_ENABLE) - && (msr.lo & FEATURE_CONTROL_LOCK_BIT))) { - printk(BIOS_WARNING, - "SMRR not enabled, skip writing SMRR...\n"); + if (!((msr.lo & SMRR_ENABLE) && (msr.lo & FEATURE_CONTROL_LOCK_BIT))) { + printk(BIOS_WARNING, "SMRR not enabled, skip writing SMRR...\n"); return; } + relo_params->smrr_mask.lo &= ~((1 << 12) - 1); + printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", relo_params->smrr_base.lo, relo_params->smrr_mask.lo); @@ -72,142 +104,28 @@ wrmsr(MSR_SMRR_PHYS_MASK, relo_params->smrr_mask); } -static void fill_in_relocation_params(struct smm_relocation_params *params) +/* On model_6fx, model_1067x and model_106cx SMRR functions slightly + differently. The MSR are at different location from the rest + and need to be explicitly enabled in IA32_FEATURE_CONTROL MSR. */ +void detect_em64t101_alternative_smrr(struct mp_ops *mp_ops) { - uintptr_t tseg_base; - size_t tseg_size; + struct cpuinfo_x86 c; - /* All range registers are aligned to 4KiB */ - const u32 rmask = ~((1 << 12) - 1); + mp_ops->per_cpu_smm_trigger = alt_1_per_cpu_smm_trigger; - smm_region(&tseg_base, &tseg_size); + get_fms(&c, cpuid_eax(1)); + if (c.x86 != 6) + return; - if (!IS_ALIGNED(tseg_base, tseg_size)) { - printk(BIOS_WARNING, - "TSEG base not aligned with TSEG SIZE! Not setting SMRR\n"); + switch (c.x86_model) { + case 0xf: + case 0x17: /* core2 */ + case 0x1c: /* Bonnell */ + break; + default: return; } - /* SMRR has 32-bits of valid address aligned to 4KiB. */ - params->smrr_base.lo = (tseg_base & rmask) | MTRR_TYPE_WRBACK; - params->smrr_base.hi = 0; - params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID; - params->smrr_mask.hi = 0; - - /* On model_6fx and model_1067x bits [0:11] on smrr_base are reserved */ - if (cpu_has_alternative_smrr()) - params->smrr_base.lo &= rmask; - - smm_subregion(SMM_SUBREGION_CHIPSET, &params->ied_base, &params->ied_size); -} - -static void setup_ied_area(struct smm_relocation_params *params) -{ - char *ied_base; - - struct ied_header ied = { - .signature = "INTEL RSVD", - .size = params->ied_size, - .reserved = {0}, - }; - - ied_base = (void *)params->ied_base; - - /* Place IED header at IEDBASE. */ - memcpy(ied_base, &ied, sizeof(ied)); - - /* Zero out 32KiB at IEDBASE + 1MiB */ - memset(ied_base + (1 << 20), 0, (32 << 10)); -} - -void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, - size_t *smm_save_state_size) -{ - printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); - - fill_in_relocation_params(&smm_reloc_params); - - smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); - - if (smm_reloc_params.ied_size) - setup_ied_area(&smm_reloc_params); - - /* This may not be be correct for older CPU's supported by this code, - but given that em64t101_smm_state_save_area_t is larger than the - save_state of these CPU's it works. */ - *smm_save_state_size = sizeof(em64t101_smm_state_save_area_t); -} - -void smm_initialize(void) -{ - /* Clear the SMM state in the southbridge. */ - smm_southbridge_clear_state(); - - /* - * Run the relocation handler for on the BSP to check and set up - * parallel SMM relocation. - */ - smm_initiate_relocation(); -} - -/* The relocation work is actually performed in SMM context, but the code - * resides in the ramstage module. This occurs by trampolining from the default - * SMRAM entry point to here. */ -void smm_relocation_handler(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase) -{ - msr_t mtrr_cap; - struct smm_relocation_params *relo_params = &smm_reloc_params; - /* The em64t101 save state is sufficiently compatible with older - save states with regards of smbase, smm_revision. */ - em64t101_smm_state_save_area_t *save_state; - u32 smbase = staggered_smbase; - u32 iedbase = relo_params->ied_base; - - printk(BIOS_DEBUG, "In relocation handler: cpu %d\n", cpu); - - /* Make appropriate changes to the save state map. */ - if (relo_params->ied_size) - printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x\n", - smbase, iedbase); - else - printk(BIOS_DEBUG, "New SMBASE=0x%08x\n", - smbase); - - save_state = (void *)(curr_smbase + SMM_DEFAULT_SIZE - - sizeof(*save_state)); - save_state->smbase = smbase; - - printk(BIOS_SPEW, "SMM revision: 0x%08x\n", save_state->smm_revision); - if (save_state->smm_revision == 0x00030101) - save_state->iedbase = iedbase; - - /* Write EMRR and SMRR MSRs based on indicated support. */ - mtrr_cap = rdmsr(MTRR_CAP_MSR); - if (!(mtrr_cap.lo & SMRR_SUPPORTED)) - return; - - if (cpu_has_alternative_smrr()) - write_smrr_alt(relo_params); - else - write_smrr(relo_params); -} - -/* - * The default SMM entry can happen in parallel or serially. If the - * default SMM entry is done in parallel the BSP has already setup - * the saving state to each CPU's MSRs. At least one save state size - * is required for the initial SMM entry for the BSP to determine if - * parallel SMM relocation is even feasible. - */ -void smm_relocate(void) -{ - /* - * If smm_save_state_in_msrs is non-zero then parallel SMM relocation - * shall take place. Run the relocation handler a second time on the - * BSP to do the final move. For APs, a relocation handler always - * needs to be run. - */ - if (!boot_cpu()) - smm_initiate_relocation(); + mp_ops->relocation_handler = alt_smm_relocation_handler; + mp_ops->per_cpu_smm_trigger = alt_2_per_cpu_smm_trigger; } diff --git a/src/cpu/intel/smm/smm_reloc.c b/src/cpu/intel/smm/smm_reloc.c index 860c095..74908af 100644 --- a/src/cpu/intel/smm/smm_reloc.c +++ b/src/cpu/intel/smm/smm_reloc.c @@ -11,6 +11,142 @@ * GNU General Public License for more details. */ +#include <string.h> +#include <types.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/smm.h> #include <cpu/intel/smm_reloc.h> struct smm_relocation_params smm_reloc_params; + +void fill_in_smrr(struct smm_relocation_params *params) +{ + uintptr_t tseg_base; + size_t tseg_size; + + /* All range registers are aligned to 4KiB */ + const u32 rmask = ~((4 * KiB) - 1); + + smm_region(&tseg_base, &tseg_size); + + /* SMRR has 32-bits of valid address aligned to 4KiB. */ + params->smrr_base.lo = (tseg_base & rmask) | MTRR_TYPE_WRBACK; + params->smrr_base.hi = 0; + params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID; + params->smrr_mask.hi = 0; +} + +/* The default SMM entry can happen in parallel or serially. If the + * default SMM entry is done in parallel the BSP has already setup + * the saving state to each CPU's MSRs. At least one save state size + * is required for the initial SMM entry for the BSP to determine if + * parallel SMM relocation is even feasible. */ +void smm_relocate(void) +{ + /* + * If smm_save_state_in_msrs is non-zero then parallel SMM relocation + * shall take place. Run the relocation handler a second time on the + * BSP to do * the final move. For APs, a relocation handler always + * needs to be run. + */ + if (smm_reloc_params.smm_save_state_in_msrs) + smm_initiate_relocation_parallel(); + else if (!boot_cpu()) + smm_initiate_relocation(); +} + +static void setup_ied_region(char *ied_base, size_t ied_size) +{ + struct ied_header ied = { + .signature = "INTEL RSVD", + .size = ied_size, + .reserved = {0}, + }; + + /* Place IED header at IEDBASE. */ + memcpy(ied_base, &ied, sizeof(ied)); + + /* Zero out 32KiB at IEDBASE + 1MiB */ + memset(ied_base + (1 << 20), 0, (32 << 10)); +} + +void fill_in_ied_params(struct smm_relocation_params *params) +{ + u32 prmrr_base; + u32 prmrr_size; + int phys_bits; + + smm_subregion(SMM_SUBREGION_CHIPSET, &params->ied_base, &params->ied_size); + if (!params->ied_size) + return; + + setup_ied_region((char *)params->ied_base, params->ied_size); + + if (!(caps & PRMRR_SUPPORTED)) + return; + + /* Some of the range registers are dependent on the number of physical + address bits supported. */ + phys_bits = cpuid_eax(0x80000008) & 0xff; + + /* The PRMRR is at IEDBASE + 2MiB */ + prmrr_base = (params->ied_base + (2 << 20)) & rmask; + prmrr_size = params->ied_size - (2 << 20); + + /* PRMRR has 46 bits of valid address aligned to 4KiB. It's dependent + on the number of physical address bits supported. */ + params->prmrr_base.lo = prmrr_base | MTRR_TYPE_WRBACK; + params->prmrr_base.hi = 0; + params->prmrr_mask.lo = (~(prmrr_size - 1) & rmask) | MTRR_PHYS_MASK_VALID; + params->prmrr_mask.hi = (1 << (phys_bits - 32)) - 1; + + /* UNCORE_PRMRR has 39 bits of valid address aligned to 4KiB. */ + params->uncore_prmrr_base.lo = prmrr_base; + params->uncore_prmrr_base.hi = 0; + params->uncore_prmrr_mask.lo = (~(prmrr_size - 1) & rmask) | MTRR_PHYS_MASK_VALID; + params->uncore_prmrr_mask.hi = (1 << (39 - 32)) - 1; + + return; +} + +#define MSR_PRMRR_PHYS_BASE 0x1f4 +#define MSR_PRMRR_PHYS_MASK 0x1f5 +#define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4 +#define MSR_UNCORE_PRMRR_PHYS_MASK 0x2f5 + +void write_smm_msrs(int cpu, struct smm_relocation_params *relo_params) +{ + msr_t mtrr_cap; + mtrr_cap = rdmsr(MTRR_CAP_MSR); + if (mtrr_cap.lo & SMRR_SUPPORTED) { + if (!cpu) { + printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", + relo_params->smrr_base.lo, relo_params->smrr_mask.lo); + } + wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base); + wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); + } + + if (mtrr_cap.lo & PRMRR_SUPPORTED) { + + if (!cpu) { + printk(BIOS_DEBUG, "Writing PRMRR. base = 0x%08x, mask=0x%08x\n", + relo_params->prmrr_base.lo, relo_params->prmrr_mask.lo); + } + wrmsr(MSR_PRMRR_PHYS_BASE, relo_params->prmrr_base); + wrmsr(MSR_PRMRR_PHYS_MASK, relo_params->prmrr_mask); + + if (cpu) + return; + + /* UNCORE_PRMRR msrs are package level. Therefore, only + * configure these MSRs on the BSP. */ + printk(BIOS_DEBUG, + "Writing UNCORE_PRMRR. base = 0x%08x, mask=0x%08x\n", + relo_params->uncore_prmrr_base.lo, + relo_params->uncore_prmrr_mask.lo); + wrmsr(MSR_UNCORE_PRMRR_PHYS_BASE, relo_params->uncore_prmrr_base); + wrmsr(MSR_UNCORE_PRMRR_PHYS_MASK, relo_params->uncore_prmrr_mask); + } +} diff --git a/src/cpu/intel/smm/smmrelocate_cpu_save.c b/src/cpu/intel/smm/smmrelocate_cpu_save.c new file mode 100644 index 0000000..b1a04a1 --- /dev/null +++ b/src/cpu/intel/smm/smmrelocate_cpu_save.c @@ -0,0 +1,97 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <types.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mp.h> +#include <cpu/intel/smm_reloc.h> + +/* All threads need to set IEDBASE and SMBASE to the relocated + * handler region. However, the save state location depends on the + * smm_save_state_in_msrs field in the relocation parameters. If + * smm_save_state_in_msrs is non-zero then the CPUs are relocating + * the SMM handler in parallel, and each CPUs save state area is + * located in their respective MSR space. If smm_save_state_in_msrs + * is zero then the SMM relocation is happening serially so the + * save state is at the same default location for all CPUs. */ + +static int switch_to_cpu_save(struct smm_relocation_params *relo_params) +{ + msr_t smm_feature_control; + + /* If smm_save_state_in_msrs is 1 then that means this is the + * 2nd time through the relocation handler for the BSP. + * Parallel SMM handler relocation is taking place. However, + * it is desired to access other CPUs save state in the real + * SMM handler. Therefore, disable the SMM save state in MSRs + * feature. */ + smm_feature_control = rdmsr(SMM_FEATURE_CONTROL_MSR); + if (!relo_params->smm_save_state_in_msrs) { + smm_feature_control.hi = 0; + smm_feature_control.lo |= SMM_CPU_SAVE_EN; + wrmsr(SMM_FEATURE_CONTROL_MSR, smm_feature_control); + relo_params->smm_save_state_in_msrs = 1; + return relo_params->smm_save_state_in_msrs; + } else { + smm_feature_control.lo &= ~SMM_CPU_SAVE_EN; + wrmsr(SMM_FEATURE_CONTROL_MSR, smm_feature_control); + return 0; + } +} + +/* The relocation work is actually performed in SMM context, but the code + * resides in the ramstage module. This occurs by trampolining from the default + * SMRAM entry point to here. */ +static void std_smm_relocation_handler(int cpu, uintptr_t curr_smbase, + uintptr_t staggered_smbase) +{ + struct smm_relocation_params *relo_params = &smm_reloc_params; + msr_t base_msr; + + printk(BIOS_DEBUG, "In relocation handler: cpu %d SMBASE=0x%08x\n", cpu, + (u32)staggered_smbase); + + /* The processor supports saving state in MSRs. Enable it before the non-BSPs + * run so that SMM relocation can occur in parallel in the non-BSP CPUs. */ + + /* If MSR save state was enabled, just return. In that case the BSP will come + * back into the relocation handler to setup the new SMBASE as well disabling + * SMM save state in MSRs. */ + if ((cpu == 0) && switch_cpu_save_en(relo_params)) + return; + + /* The relocated handler runs with all CPUs concurrently. Therefore + * stagger the entry points adjusting SMBASE downwards by save state + * size * CPU num. */ + + base_msr.lo = staggered_smbase; + base_msr.hi = 0; + wrmsr(SMBASE_MSR, base_msr); + + /* According the BWG the IEDBASE MSR is in bits 63:32. It's + * not clear why it differs from the SMBASE MSR. */ + base_msr.lo = 0; + base_msr.hi = relo_params->ied_base; + wrmsr(IEDBASE_MSR, base_msr); + + /* Write SMRR MSRs based on indicated support. */ + write_smm_msrs(cpu, relo_params); +} + +void detect_smm_cpu_svrstr(struct mp_ops *mp_ops) +{ + smm_mca_cap = rdmsr(SMM_MCA_CAP_MSR); + + if (smm_mca_cap.hi & SMM_CPU_SVRSTR_MASK) + mp_ops->relocation_handler = std_smm_relocation_handler; +} diff --git a/src/include/cpu/intel/em64t101_save_state.h b/src/include/cpu/intel/em64t101_save_state.h index 7493c85..cb896ef 100644 --- a/src/include/cpu/intel/em64t101_save_state.h +++ b/src/include/cpu/intel/em64t101_save_state.h @@ -118,4 +118,8 @@ u64 cr0; } __packed em64t101_smm_state_save_area_t; +struct mp_ops; +void select_mp_ops_em64t101(struct mp_ops *mp_ops); +void select_mp_ops_em64t101_alt(struct mp_ops *mp_ops); + #endif diff --git a/src/include/cpu/intel/smm_reloc.h b/src/include/cpu/intel/smm_reloc.h index 68fe33f..49333eb 100644 --- a/src/include/cpu/intel/smm_reloc.h +++ b/src/include/cpu/intel/smm_reloc.h @@ -17,7 +17,6 @@ #include <console/console.h> #include <types.h> #include <cpu/x86/msr.h> -#include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> struct smm_relocation_params { @@ -46,6 +45,7 @@ } __packed; void fill_in_smrr(struct smm_relocation_params *params); +void fill_in_ied_params(struct smm_relocation_params *params); /* These helpers are for performing SMM relocation. */ void smm_relocate(void); @@ -80,42 +80,4 @@ void smm_southbridge_enable_smi(void); void smm_southbridge_enable(uint16_t pm1_events); -/* To be removed. */ -void smm_initialize(void); -void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size); -void smm_relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase); - -bool cpu_has_alternative_smrr(void); - -#define MSR_PRMRR_PHYS_BASE 0x1f4 -#define MSR_PRMRR_PHYS_MASK 0x1f5 -#define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4 -#define MSR_UNCORE_PRMRR_PHYS_MASK 0x2f5 - -static inline void write_smrr(struct smm_relocation_params *relo_params) -{ - printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->smrr_base.lo, relo_params->smrr_mask.lo); - wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base); - wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); -} - -static inline void write_prmrr(struct smm_relocation_params *relo_params) -{ - printk(BIOS_DEBUG, "Writing PRMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->prmrr_base.lo, relo_params->prmrr_mask.lo); - wrmsr(MSR_PRMRR_PHYS_BASE, relo_params->prmrr_base); - wrmsr(MSR_PRMRR_PHYS_MASK, relo_params->prmrr_mask); -} - -static inline void write_uncore_prmrr(struct smm_relocation_params *relo_params) -{ - printk(BIOS_DEBUG, - "Writing UNCORE_PRMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->uncore_prmrr_base.lo, - relo_params->uncore_prmrr_mask.lo); - wrmsr(MSR_UNCORE_PRMRR_PHYS_BASE, relo_params->uncore_prmrr_base); - wrmsr(MSR_UNCORE_PRMRR_PHYS_MASK, relo_params->uncore_prmrr_mask); -} - #endif diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index 03aa3fb..692dc1c 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -57,7 +57,11 @@ romstage-y += smbus_common.c ramstage-y += smi.c smm-y += smihandler.c -ramstage-y += smmrelocate.c +bootblock-y += spi.c +romstage-y += spi.c +postcar-y += spi.c +ramstage-y += spi.c +smm-$(CONFIG_SPI_FLASH_SMM) += spi.c ramstage-y += systemagent.c bootblock-y += tsc_freq.c ramstage-y += tsc_freq.c diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c index 287b5b5..48bfdfc 100644 --- a/src/soc/intel/broadwell/cpu.c +++ b/src/soc/intel/broadwell/cpu.c @@ -635,7 +635,7 @@ *parallel = 1; } -static void per_cpu_smm_trigger(void) +static void alt_per_cpu_smm_trigger(void) { /* Relocate the SMM handler. */ smm_relocate(); @@ -651,20 +651,17 @@ /* Now that all APs have been relocated as well as the BSP let SMIs * start flowing. */ - smm_southbridge_enable_smi(); + if (CONFIG(HAVE_SMI_HANDLER)) + smm_southbridge_enable_smi(); /* Lock down the SMRAM space. */ smm_lock(); } -static const struct mp_ops mp_ops = { +static struct mp_ops mp_ops = { .pre_mp_init = pre_mp_init, .get_cpu_count = get_cpu_count, - .get_smm_info = smm_info, .get_microcode_info = get_microcode_info, - .pre_mp_smm_init = smm_initialize, - .per_cpu_smm_trigger = per_cpu_smm_trigger, - .relocation_handler = smm_relocation_handler, .post_mp_init = post_mp_init, }; @@ -672,6 +669,11 @@ { struct bus *cpu_bus = dev->link_list; + if (CONFIG(HAVE_SMI_HANDLER)) { + select_mp_ops_em64t101_detect(&mp_ops); + mp_ops.per_cpu_smm_trigger = alt_per_cpu_smm_trigger; + } + if (mp_init_with_smm(cpu_bus, &mp_ops)) printk(BIOS_ERR, "MP initialization failure.\n"); } diff --git a/src/soc/intel/broadwell/smmrelocate.c b/src/soc/intel/broadwell/smmrelocate.c deleted file mode 100644 index 0df9289..0000000 --- a/src/soc/intel/broadwell/smmrelocate.c +++ /dev/null @@ -1,268 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <types.h> -#include <string.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ops.h> -#include <cpu/x86/cache.h> -#include <cpu/x86/lapic.h> -#include <cpu/x86/mp.h> -#include <cpu/x86/msr.h> -#include <cpu/x86/mtrr.h> -#include <cpu/x86/smm.h> -#include <cpu/intel/em64t101_save_state.h> -#include <cpu/intel/smm_reloc.h> -#include <console/console.h> -#include <soc/cpu.h> -#include <soc/msr.h> -#include <soc/pci_devs.h> -#include <soc/systemagent.h> - - -static void update_save_state(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase, - struct smm_relocation_params *relo_params) -{ - u32 smbase; - u32 iedbase; - - /* The relocated handler runs with all CPUs concurrently. Therefore - * stagger the entry points adjusting SMBASE downwards by save state - * size * CPU num. */ - smbase = staggered_smbase; - iedbase = relo_params->ied_base; - - printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x\n", - smbase, iedbase); - - /* All threads need to set IEDBASE and SMBASE to the relocated - * handler region. However, the save state location depends on the - * smm_save_state_in_msrs field in the relocation parameters. If - * smm_save_state_in_msrs is non-zero then the CPUs are relocating - * the SMM handler in parallel, and each CPUs save state area is - * located in their respective MSR space. If smm_save_state_in_msrs - * is zero then the SMM relocation is happening serially so the - * save state is at the same default location for all CPUs. */ - if (relo_params->smm_save_state_in_msrs) { - msr_t smbase_msr; - msr_t iedbase_msr; - - smbase_msr.lo = smbase; - smbase_msr.hi = 0; - - /* According the BWG the IEDBASE MSR is in bits 63:32. It's - * not clear why it differs from the SMBASE MSR. */ - iedbase_msr.lo = 0; - iedbase_msr.hi = iedbase; - - wrmsr(SMBASE_MSR, smbase_msr); - wrmsr(IEDBASE_MSR, iedbase_msr); - } else { - em64t101_smm_state_save_area_t *save_state; - - save_state = (void *)(curr_smbase + SMM_DEFAULT_SIZE - - sizeof(*save_state)); - - save_state->smbase = smbase; - save_state->iedbase = iedbase; - } -} - -/* Returns 1 if SMM MSR save state was set. */ -static int bsp_setup_msr_save_state(struct smm_relocation_params *relo_params) -{ - msr_t smm_mca_cap; - - smm_mca_cap = rdmsr(SMM_MCA_CAP_MSR); - if (smm_mca_cap.hi & SMM_CPU_SVRSTR_MASK) { - msr_t smm_feature_control; - - smm_feature_control = rdmsr(SMM_FEATURE_CONTROL_MSR); - smm_feature_control.hi = 0; - smm_feature_control.lo |= SMM_CPU_SAVE_EN; - wrmsr(SMM_FEATURE_CONTROL_MSR, smm_feature_control); - relo_params->smm_save_state_in_msrs = 1; - } - return relo_params->smm_save_state_in_msrs; -} - -/* The relocation work is actually performed in SMM context, but the code - * resides in the ramstage module. This occurs by trampolining from the default - * SMRAM entry point to here. */ -void smm_relocation_handler(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase) -{ - msr_t mtrr_cap; - struct smm_relocation_params *relo_params = &smm_reloc_params; - - printk(BIOS_DEBUG, "In relocation handler: CPU %d\n", cpu); - - /* Determine if the processor supports saving state in MSRs. If so, - * enable it before the non-BSPs run so that SMM relocation can occur - * in parallel in the non-BSP CPUs. */ - if (cpu == 0) { - /* If smm_save_state_in_msrs is 1 then that means this is the - * 2nd time through the relocation handler for the BSP. - * Parallel SMM handler relocation is taking place. However, - * it is desired to access other CPUs save state in the real - * SMM handler. Therefore, disable the SMM save state in MSRs - * feature. */ - if (relo_params->smm_save_state_in_msrs) { - msr_t smm_feature_control; - - smm_feature_control = rdmsr(SMM_FEATURE_CONTROL_MSR); - smm_feature_control.lo &= ~SMM_CPU_SAVE_EN; - wrmsr(SMM_FEATURE_CONTROL_MSR, smm_feature_control); - } else if (bsp_setup_msr_save_state(relo_params)) - /* Just return from relocation handler if MSR save - * state is enabled. In that case the BSP will come - * back into the relocation handler to setup the new - * SMBASE as well disabling SMM save state in MSRs. */ - return; - } - - /* Make appropriate changes to the save state map. */ - update_save_state(cpu, curr_smbase, staggered_smbase, relo_params); - - /* Write PRMRR and SMRR MSRs based on indicated support. */ - mtrr_cap = rdmsr(MTRR_CAP_MSR); - if (mtrr_cap.lo & SMRR_SUPPORTED) - write_smrr(relo_params); - - if (mtrr_cap.lo & PRMRR_SUPPORTED) { - write_prmrr(relo_params); - /* UNCORE_PRMRR msrs are package level. Therefore, only - * configure these MSRs on the BSP. */ - if (cpu == 0) - write_uncore_prmrr(relo_params); - } -} - -static void fill_in_relocation_params(struct smm_relocation_params *params) -{ - uintptr_t tseg_base; - size_t tseg_size; - u32 prmrr_base; - u32 prmrr_size; - int phys_bits; - /* All range registers are aligned to 4KiB */ - const u32 rmask = ~((1 << 12) - 1); - - /* Some of the range registers are dependent on the number of physical - * address bits supported. */ - phys_bits = cpuid_eax(0x80000008) & 0xff; - - /* The range bounded by the TSEGMB and BGSM registers encompasses the - * SMRAM range as well as the IED range. However, the SMRAM available - * to the handler is 4MiB since the IEDRAM lives TSEGMB + 4MiB. - */ - smm_region(&tseg_base, &tseg_size); - - /* SMRR has 32-bits of valid address aligned to 4KiB. */ - params->smrr_base.lo = (tseg_base & rmask) | MTRR_TYPE_WRBACK; - params->smrr_base.hi = 0; - params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID; - params->smrr_mask.hi = 0; - - smm_subregion(SMM_SUBREGION_CHIPSET, &params->ied_base, &params->ied_size); - - /* The PRMRR and UNCORE_PRMRR are at IEDBASE + 2MiB */ - prmrr_base = (params->ied_base + (2 << 20)) & rmask; - prmrr_size = params->ied_size - (2 << 20); - - /* PRMRR has 46 bits of valid address aligned to 4KiB. It's dependent - * on the number of physical address bits supported. */ - params->prmrr_base.lo = prmrr_base | MTRR_TYPE_WRBACK; - params->prmrr_base.hi = 0; - params->prmrr_mask.lo = (~(prmrr_size - 1) & rmask) - | MTRR_PHYS_MASK_VALID; - params->prmrr_mask.hi = (1 << (phys_bits - 32)) - 1; - - /* UNCORE_PRMRR has 39 bits of valid address aligned to 4KiB. */ - params->uncore_prmrr_base.lo = prmrr_base; - params->uncore_prmrr_base.hi = 0; - params->uncore_prmrr_mask.lo = (~(prmrr_size - 1) & rmask) | - MTRR_PHYS_MASK_VALID; - params->uncore_prmrr_mask.hi = (1 << (39 - 32)) - 1; -} - -static void setup_ied_area(struct smm_relocation_params *params) -{ - char *ied_base; - - struct ied_header ied = { - .signature = "INTEL RSVD", - .size = params->ied_size, - .reserved = {0}, - }; - - ied_base = (void *)params->ied_base; - - /* Place IED header at IEDBASE. */ - memcpy(ied_base, &ied, sizeof(ied)); - - /* Zero out 32KiB at IEDBASE + 1MiB */ - memset(ied_base + (1 << 20), 0, (32 << 10)); -} - -void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, - size_t *smm_save_state_size) -{ - printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); - - fill_in_relocation_params(&smm_reloc_params); - - smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); - - setup_ied_area(&smm_reloc_params); - - *smm_save_state_size = sizeof(em64t101_smm_state_save_area_t); -} - -void smm_initialize(void) -{ - /* Clear the SMM state in the southbridge. */ - smm_southbridge_clear_state(); - - /* - * Run the relocation handler for on the BSP to check and set up - * parallel SMM relocation. - */ - smm_initiate_relocation(); - - if (smm_reloc_params.smm_save_state_in_msrs) - printk(BIOS_DEBUG, "Doing parallel SMM relocation.\n"); -} - -/* The default SMM entry can happen in parallel or serially. If the - * default SMM entry is done in parallel the BSP has already setup - * the saving state to each CPU's MSRs. At least one save state size - * is required for the initial SMM entry for the BSP to determine if - * parallel SMM relocation is even feasible. */ -void smm_relocate(void) -{ - /* - * If smm_save_state_in_msrs is non-zero then parallel SMM relocation - * shall take place. Run the relocation handler a second time on the - * BSP to do * the final move. For APs, a relocation handler always - * needs to be run. - */ - if (smm_reloc_params.smm_save_state_in_msrs) - smm_initiate_relocation_parallel(); - else if (!boot_cpu()) - smm_initiate_relocation(); -} diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 0fcbcd1..0e6e297 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -47,7 +47,6 @@ ramstage-y += pmc.c ramstage-y += pmutil.c ramstage-y += reset.c -ramstage-y += smmrelocate.c ramstage-y += spi.c ramstage-y += systemagent.c ramstage-y += uart.c diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index f01b499..96d544e 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -441,12 +441,6 @@ set_vmx_and_lock(); } -static void per_cpu_smm_trigger(void) -{ - /* Relocate the SMM handler. */ - smm_relocate(); -} - static void post_mp_init(void) { /* Set Max Ratio */ @@ -462,7 +456,7 @@ smm_lock(); } -static const struct mp_ops mp_ops = { +static struct mp_ops mp_ops = { /* * Skip Pre MP init MTRR programming as MTRRs are mirrored from BSP, * that are set prior to ramstage. @@ -470,16 +464,15 @@ */ .pre_mp_init = soc_fsp_load, .get_cpu_count = get_cpu_count, - .get_smm_info = smm_info, .get_microcode_info = get_microcode_info, - .pre_mp_smm_init = smm_initialize, - .per_cpu_smm_trigger = per_cpu_smm_trigger, - .relocation_handler = smm_relocation_handler, .post_mp_init = post_mp_init, }; void soc_init_cpus(struct bus *cpu_bus) { + if (CONFIG(HAVE_SMI_HANDLER)) + select_mp_ops_em64t101_detect(&mp_ops); + if (mp_init_with_smm(cpu_bus, &mp_ops)) printk(BIOS_ERR, "MP initialization failure.\n"); diff --git a/src/soc/intel/cannonlake/smmrelocate.c b/src/soc/intel/cannonlake/smmrelocate.c deleted file mode 100644 index 7239e6f..0000000 --- a/src/soc/intel/cannonlake/smmrelocate.c +++ /dev/null @@ -1,244 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2017 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <types.h> -#include <string.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ops.h> -#include <cpu/x86/cache.h> -#include <cpu/x86/lapic.h> -#include <cpu/x86/mp.h> -#include <cpu/x86/msr.h> -#include <cpu/x86/mtrr.h> -#include <cpu/x86/smm.h> -#include <cpu/intel/em64t101_save_state.h> -#include <cpu/intel/smm_reloc.h> -#include <console/console.h> -#include <soc/cpu.h> -#include <soc/msr.h> -#include <soc/pci_devs.h> -#include <soc/systemagent.h> -#include "chip.h" - - -static void update_save_state(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase, - struct smm_relocation_params *relo_params) -{ - u32 smbase; - u32 iedbase; - - /* - * The relocated handler runs with all CPUs concurrently. Therefore - * stagger the entry points adjusting SMBASE downwards by save state - * size * CPU num. - */ - smbase = staggered_smbase; - iedbase = relo_params->ied_base; - - printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x\n", - smbase, iedbase); - - /* - * All threads need to set IEDBASE and SMBASE to the relocated - * handler region. However, the save state location depends on the - * smm_save_state_in_msrs field in the relocation parameters. If - * smm_save_state_in_msrs is non-zero then the CPUs are relocating - * the SMM handler in parallel, and each CPUs save state area is - * located in their respective MSR space. If smm_save_state_in_msrs - * is zero then the SMM relocation is happening serially so the - * save state is at the same default location for all CPUs. - */ - if (relo_params->smm_save_state_in_msrs) { - msr_t smbase_msr; - msr_t iedbase_msr; - - smbase_msr.lo = smbase; - smbase_msr.hi = 0; - - /* - * According the BWG the IEDBASE MSR is in bits 63:32. It's - * not clear why it differs from the SMBASE MSR. - */ - iedbase_msr.lo = 0; - iedbase_msr.hi = iedbase; - - wrmsr(SMBASE_MSR, smbase_msr); - wrmsr(IEDBASE_MSR, iedbase_msr); - } else { - em64t101_smm_state_save_area_t *save_state; - - save_state = (void *)(curr_smbase + SMM_DEFAULT_SIZE - - sizeof(*save_state)); - - save_state->smbase = smbase; - save_state->iedbase = iedbase; - } -} - -/* Returns 1 if SMM MSR save state was set. */ -static int bsp_setup_msr_save_state(struct smm_relocation_params *relo_params) -{ - msr_t smm_mca_cap; - - smm_mca_cap = rdmsr(SMM_MCA_CAP_MSR); - if (smm_mca_cap.hi & SMM_CPU_SVRSTR_MASK) { - msr_t smm_feature_control; - - smm_feature_control = rdmsr(SMM_FEATURE_CONTROL_MSR); - smm_feature_control.hi = 0; - smm_feature_control.lo |= SMM_CPU_SAVE_EN; - wrmsr(SMM_FEATURE_CONTROL_MSR, smm_feature_control); - relo_params->smm_save_state_in_msrs = 1; - } - return relo_params->smm_save_state_in_msrs; -} - -/* - * The relocation work is actually performed in SMM context, but the code - * resides in the ramstage module. This occurs by trampolining from the default - * SMRAM entry point to here. - */ -void smm_relocation_handler(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase) -{ - msr_t mtrr_cap; - struct smm_relocation_params *relo_params = &smm_reloc_params; - - printk(BIOS_DEBUG, "In relocation handler: CPU %d\n", cpu); - - /* - * Determine if the processor supports saving state in MSRs. If so, - * enable it before the non-BSPs run so that SMM relocation can occur - * in parallel in the non-BSP CPUs. - */ - if (cpu == 0) { - /* - * If smm_save_state_in_msrs is 1 then that means this is the - * 2nd time through the relocation handler for the BSP. - * Parallel SMM handler relocation is taking place. However, - * it is desired to access other CPUs save state in the real - * SMM handler. Therefore, disable the SMM save state in MSRs - * feature. - */ - if (relo_params->smm_save_state_in_msrs) { - msr_t smm_feature_control; - - smm_feature_control = rdmsr(SMM_FEATURE_CONTROL_MSR); - smm_feature_control.lo &= ~SMM_CPU_SAVE_EN; - wrmsr(SMM_FEATURE_CONTROL_MSR, smm_feature_control); - } else if (bsp_setup_msr_save_state(relo_params)) - /* - * Just return from relocation handler if MSR save - * state is enabled. In that case the BSP will come - * back into the relocation handler to setup the new - * SMBASE as well disabling SMM save state in MSRs. - */ - return; - } - - /* Make appropriate changes to the save state map. */ - update_save_state(cpu, curr_smbase, staggered_smbase, relo_params); - - /* Write SMRR MSRs based on indicated support. */ - mtrr_cap = rdmsr(MTRR_CAP_MSR); - if (mtrr_cap.lo & SMRR_SUPPORTED) - write_smrr(relo_params); -} - -static void fill_in_relocation_params(struct smm_relocation_params *params) -{ - uintptr_t tseg_base; - size_t tseg_size; - /* All range registers are aligned to 4KiB */ - const u32 rmask = ~(4 * KiB - 1); - - smm_region(&tseg_base, &tseg_size); - smm_subregion(SMM_SUBREGION_CHIPSET, &params->ied_base, &params->ied_size); - - /* SMRR has 32-bits of valid address aligned to 4KiB. */ - params->smrr_base.lo = (tseg_base & rmask) | MTRR_TYPE_WRBACK; - params->smrr_base.hi = 0; - params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID; - params->smrr_mask.hi = 0; -} - -static void setup_ied_area(struct smm_relocation_params *params) -{ - char *ied_base; - - struct ied_header ied = { - .signature = "INTEL RSVD", - .size = params->ied_size, - .reserved = {0}, - }; - - ied_base = (void *)params->ied_base; - - printk(BIOS_DEBUG, "IED base = 0x%08x\n", (u32)params->ied_base); - printk(BIOS_DEBUG, "IED size = 0x%08x\n", (u32)params->ied_size); - - /* Place IED header at IEDBASE. */ - memcpy(ied_base, &ied, sizeof(ied)); - - /* Zero out 32KiB at IEDBASE + 1MiB */ - memset(ied_base + 1 * MiB, 0, 32 * KiB); -} - -void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, - size_t *smm_save_state_size) -{ - printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); - - fill_in_relocation_params(&smm_reloc_params); - - smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); - - if (smm_reloc_params.ied_size) - setup_ied_area(&smm_reloc_params); - - *smm_save_state_size = sizeof(em64t101_smm_state_save_area_t); -} - -void smm_initialize(void) -{ - /* Clear the SMM state in the southbridge. */ - smm_southbridge_clear_state(); - - /* - * Run the relocation handler for on the BSP to check and set up - * parallel SMM relocation. - */ - smm_initiate_relocation(); - - if (smm_reloc_params.smm_save_state_in_msrs) - printk(BIOS_DEBUG, "Doing parallel SMM relocation.\n"); -} - -void smm_relocate(void) -{ - /* - * If smm_save_state_in_msrs is non-zero then parallel SMM relocation - * shall take place. Run the relocation handler a second time on the - * BSP to do * the final move. For APs, a relocation handler always - * needs to be run. - */ - if (smm_reloc_params.smm_save_state_in_msrs) - smm_initiate_relocation_parallel(); - else if (!boot_cpu()) - smm_initiate_relocation(); -} diff --git a/src/soc/intel/denverton_ns/Makefile.inc b/src/soc/intel/denverton_ns/Makefile.inc index 4050f61..b52c209 100644 --- a/src/soc/intel/denverton_ns/Makefile.inc +++ b/src/soc/intel/denverton_ns/Makefile.inc @@ -67,8 +67,8 @@ ramstage-y += hob_mem.c ramstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart_debug.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c -ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smm.c -ramstage-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c +ramstage-y += smm.c +ramstage-y += pmutil.c ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c index 1363d35..3365091 100644 --- a/src/soc/intel/denverton_ns/cpu.c +++ b/src/soc/intel/denverton_ns/cpu.c @@ -183,7 +183,6 @@ ((perf_ctl.lo >> 8) & 0xff) * CPU_BCLK); } - /* * Do essential initialization tasks before APs can be fired up * diff --git a/src/soc/intel/icelake/Makefile.inc b/src/soc/intel/icelake/Makefile.inc index 67a3a71..e114f7e 100644 --- a/src/soc/intel/icelake/Makefile.inc +++ b/src/soc/intel/icelake/Makefile.inc @@ -39,8 +39,9 @@ ramstage-y += lockdown.c ramstage-y += p2sb.c ramstage-y += pmc.c +ramstage-y += pmutil.c ramstage-y += reset.c -ramstage-y += smmrelocate.c +ramstage-y += spi.c ramstage-y += systemagent.c ramstage-y += sd.c diff --git a/src/soc/intel/icelake/cpu.c b/src/soc/intel/icelake/cpu.c index e058442..a92ccd0 100644 --- a/src/soc/intel/icelake/cpu.c +++ b/src/soc/intel/icelake/cpu.c @@ -217,12 +217,6 @@ enable_turbo(); } -static void per_cpu_smm_trigger(void) -{ - /* Relocate the SMM handler. */ - smm_relocate(); -} - static void post_mp_init(void) { /* Set Max Ratio */ @@ -238,7 +232,7 @@ smm_lock(); } -static const struct mp_ops mp_ops = { +static struct mp_ops mp_ops = { /* * Skip Pre MP init MTRR programming as MTRRs are mirrored from BSP, * that are set prior to ramstage. @@ -246,16 +240,15 @@ */ .pre_mp_init = soc_fsp_load, .get_cpu_count = get_cpu_count, - .get_smm_info = smm_info, .get_microcode_info = get_microcode_info, - .pre_mp_smm_init = smm_initialize, - .per_cpu_smm_trigger = per_cpu_smm_trigger, - .relocation_handler = smm_relocation_handler, .post_mp_init = post_mp_init, }; void soc_init_cpus(struct bus *cpu_bus) { + if (CONFIG(HAVE_SMI_HANDLER)) + select_mp_ops_em64t101_detect(&mp_ops); + if (mp_init_with_smm(cpu_bus, &mp_ops)) printk(BIOS_ERR, "MP initialization failure.\n"); } diff --git a/src/soc/intel/icelake/smmrelocate.c b/src/soc/intel/icelake/smmrelocate.c deleted file mode 100644 index 7bfdd53..0000000 --- a/src/soc/intel/icelake/smmrelocate.c +++ /dev/null @@ -1,250 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <types.h> -#include <string.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ops.h> -#include <cpu/x86/cache.h> -#include <cpu/x86/lapic.h> -#include <cpu/x86/mp.h> -#include <cpu/x86/msr.h> -#include <cpu/x86/mtrr.h> -#include <cpu/x86/smm.h> -#include <cpu/intel/em64t101_save_state.h> -#include <cpu/intel/smm_reloc.h> -#include <console/console.h> -#include <soc/cpu.h> -#include <soc/msr.h> -#include <soc/pci_devs.h> -#include <soc/soc_chip.h> -#include <soc/systemagent.h> - - -static void update_save_state(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase, - struct smm_relocation_params *relo_params) -{ - u32 smbase; - u32 iedbase; - - /* - * The relocated handler runs with all CPUs concurrently. Therefore - * stagger the entry points adjusting SMBASE downwards by save state - * size * CPU num. - */ - smbase = staggered_smbase; - iedbase = relo_params->ied_base; - - printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x\n", - smbase, iedbase); - - /* - * All threads need to set IEDBASE and SMBASE to the relocated - * handler region. However, the save state location depends on the - * smm_save_state_in_msrs field in the relocation parameters. If - * smm_save_state_in_msrs is non-zero then the CPUs are relocating - * the SMM handler in parallel, and each CPUs save state area is - * located in their respective MSR space. If smm_save_state_in_msrs - * is zero then the SMM relocation is happening serially so the - * save state is at the same default location for all CPUs. - */ - if (relo_params->smm_save_state_in_msrs) { - msr_t smbase_msr; - msr_t iedbase_msr; - - smbase_msr.lo = smbase; - smbase_msr.hi = 0; - - /* - * According the BWG the IEDBASE MSR is in bits 63:32. It's - * not clear why it differs from the SMBASE MSR. - */ - iedbase_msr.lo = 0; - iedbase_msr.hi = iedbase; - - wrmsr(SMBASE_MSR, smbase_msr); - wrmsr(IEDBASE_MSR, iedbase_msr); - } else { - em64t101_smm_state_save_area_t *save_state; - - save_state = (void *)(curr_smbase + SMM_DEFAULT_SIZE - - sizeof(*save_state)); - - save_state->smbase = smbase; - save_state->iedbase = iedbase; - } -} - -/* Returns 1 if SMM MSR save state was set. */ -static int bsp_setup_msr_save_state(struct smm_relocation_params *relo_params) -{ - msr_t smm_mca_cap; - - smm_mca_cap = rdmsr(SMM_MCA_CAP_MSR); - if (smm_mca_cap.hi & SMM_CPU_SVRSTR_MASK) { - msr_t smm_feature_control; - - smm_feature_control = rdmsr(SMM_FEATURE_CONTROL_MSR); - smm_feature_control.hi = 0; - smm_feature_control.lo |= SMM_CPU_SAVE_EN; - wrmsr(SMM_FEATURE_CONTROL_MSR, smm_feature_control); - relo_params->smm_save_state_in_msrs = 1; - } - return relo_params->smm_save_state_in_msrs; -} - -/* - * The relocation work is actually performed in SMM context, but the code - * resides in the ramstage module. This occurs by trampolining from the default - * SMRAM entry point to here. - */ -void smm_relocation_handler(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase) -{ - msr_t mtrr_cap; - struct smm_relocation_params *relo_params = &smm_reloc_params; - - printk(BIOS_DEBUG, "In relocation handler: CPU %d\n", cpu); - - /* - * Determine if the processor supports saving state in MSRs. If so, - * enable it before the non-BSPs run so that SMM relocation can occur - * in parallel in the non-BSP CPUs. - */ - if (cpu == 0) { - /* - * If smm_save_state_in_msrs is 1 then that means this is the - * 2nd time through the relocation handler for the BSP. - * Parallel SMM handler relocation is taking place. However, - * it is desired to access other CPUs save state in the real - * SMM handler. Therefore, disable the SMM save state in MSRs - * feature. - */ - if (relo_params->smm_save_state_in_msrs) { - msr_t smm_feature_control; - - smm_feature_control = rdmsr(SMM_FEATURE_CONTROL_MSR); - smm_feature_control.lo &= ~SMM_CPU_SAVE_EN; - wrmsr(SMM_FEATURE_CONTROL_MSR, smm_feature_control); - } else if (bsp_setup_msr_save_state(relo_params)) - /* - * Just return from relocation handler if MSR save - * state is enabled. In that case the BSP will come - * back into the relocation handler to setup the new - * SMBASE as well disabling SMM save state in MSRs. - */ - return; - } - - /* Make appropriate changes to the save state map. */ - update_save_state(cpu, curr_smbase, staggered_smbase, relo_params); - - /* Write SMRR MSRs based on indicated support. */ - mtrr_cap = rdmsr(MTRR_CAP_MSR); - if (mtrr_cap.lo & SMRR_SUPPORTED) - write_smrr(relo_params); -} - -static void fill_in_relocation_params(struct smm_relocation_params *params) -{ - uintptr_t tseg_base; - size_t tseg_size; - /* All range registers are aligned to 4KiB */ - const u32 rmask = ~(4 * KiB - 1); - - smm_region(&tseg_base, &tseg_size); - - if (!IS_ALIGNED(tseg_base, tseg_size)) { - printk(BIOS_WARNING, - "TSEG base not aligned with TSEG SIZE! Not setting SMRR\n"); - return; - } - - smm_subregion(SMM_SUBREGION_CHIPSET, &params->ied_base, &params->ied_size); - - /* SMRR has 32-bits of valid address aligned to 4KiB. */ - params->smrr_base.lo = (tseg_base & rmask) | MTRR_TYPE_WRBACK; - params->smrr_base.hi = 0; - params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID; - params->smrr_mask.hi = 0; -} - -static void setup_ied_area(struct smm_relocation_params *params) -{ - char *ied_base; - - struct ied_header ied = { - .signature = "INTEL RSVD", - .size = params->ied_size, - .reserved = {0}, - }; - - ied_base = (void *)params->ied_base; - - printk(BIOS_DEBUG, "IED base = 0x%08x\n", (u32)params->ied_base); - printk(BIOS_DEBUG, "IED size = 0x%08x\n", (u32)params->ied_size); - - /* Place IED header at IEDBASE. */ - memcpy(ied_base, &ied, sizeof(ied)); - - /* Zero out 32KiB at IEDBASE + 1MiB */ - memset(ied_base + 1 * MiB, 0, 32 * KiB); -} - -void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, - size_t *smm_save_state_size) -{ - printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); - - fill_in_relocation_params(&smm_reloc_params); - - smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); - - if (smm_reloc_params.ied_size) - setup_ied_area(&smm_reloc_params); - - *smm_save_state_size = sizeof(em64t101_smm_state_save_area_t); -} - -void smm_initialize(void) -{ - /* Clear the SMM state in the southbridge. */ - smm_southbridge_clear_state(); - - /* - * Run the relocation handler for on the BSP to check and set up - * parallel SMM relocation. - */ - smm_initiate_relocation(); - - if (smm_reloc_params.smm_save_state_in_msrs) - printk(BIOS_DEBUG, "Doing parallel SMM relocation.\n"); -} - -void smm_relocate(void) -{ - /* - * If smm_save_state_in_msrs is non-zero then parallel SMM relocation - * shall take place. Run the relocation handler a second time on the - * BSP to do * the final move. For APs, a relocation handler always - * needs to be run. - */ - if (smm_reloc_params.smm_save_state_in_msrs) - smm_initiate_relocation_parallel(); - else if (!boot_cpu()) - smm_initiate_relocation(); -} diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index b049e84..56aa7f1 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -58,7 +58,6 @@ ramstage-y += pmutil.c ramstage-y += reset.c ramstage-y += sd.c -ramstage-y += smmrelocate.c ramstage-y += spi.c ramstage-y += systemagent.c ramstage-y += uart.c diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 9a487c6..fde37ee 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -479,12 +479,6 @@ prmrr_core_configure(); } -static void per_cpu_smm_trigger(void) -{ - /* Relocate the SMM handler. */ - smm_relocate(); -} - static void vmx_configure(void *unused) { set_feature_ctrl_vmx(); @@ -522,7 +516,7 @@ printk(BIOS_CRIT, "CRITICAL ERROR: MP post init failed\n"); } -static const struct mp_ops mp_ops = { +static struct mp_ops mp_ops = { /* * Skip Pre MP init MTRR programming as MTRRs are mirrored from BSP, * that are set prior to ramstage. @@ -530,16 +524,15 @@ */ .pre_mp_init = soc_fsp_load, .get_cpu_count = get_cpu_count, - .get_smm_info = smm_info, .get_microcode_info = get_microcode_info, - .pre_mp_smm_init = smm_initialize, - .per_cpu_smm_trigger = per_cpu_smm_trigger, - .relocation_handler = smm_relocation_handler, .post_mp_init = post_mp_init, }; void soc_init_cpus(struct bus *cpu_bus) { + if (CONFIG(HAVE_SMI_HANDLER)) + select_mp_ops_em64t101_detect(&mp_ops); + if (mp_init_with_smm(cpu_bus, &mp_ops)) printk(BIOS_ERR, "MP initialization failure.\n"); diff --git a/src/soc/intel/skylake/smmrelocate.c b/src/soc/intel/skylake/smmrelocate.c deleted file mode 100644 index ba98730..0000000 --- a/src/soc/intel/skylake/smmrelocate.c +++ /dev/null @@ -1,244 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <types.h> -#include <string.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ops.h> -#include <cpu/x86/cache.h> -#include <cpu/x86/lapic.h> -#include <cpu/x86/mp.h> -#include <cpu/x86/msr.h> -#include <cpu/x86/mtrr.h> -#include <cpu/x86/smm.h> -#include <cpu/intel/em64t101_save_state.h> -#include <cpu/intel/smm_reloc.h> -#include <console/console.h> -#include <soc/cpu.h> -#include <soc/msr.h> -#include <soc/pci_devs.h> -#include <soc/systemagent.h> -#include "chip.h" - - -static void update_save_state(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase, - struct smm_relocation_params *relo_params) -{ - u32 smbase; - u32 iedbase; - - /* - * The relocated handler runs with all CPUs concurrently. Therefore - * stagger the entry points adjusting SMBASE downwards by save state - * size * CPU num. - */ - smbase = staggered_smbase; - iedbase = relo_params->ied_base; - - printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x\n", - smbase, iedbase); - - /* - * All threads need to set IEDBASE and SMBASE to the relocated - * handler region. However, the save state location depends on the - * smm_save_state_in_msrs field in the relocation parameters. If - * smm_save_state_in_msrs is non-zero then the CPUs are relocating - * the SMM handler in parallel, and each CPUs save state area is - * located in their respective MSR space. If smm_save_state_in_msrs - * is zero then the SMM relocation is happening serially so the - * save state is at the same default location for all CPUs. - */ - if (relo_params->smm_save_state_in_msrs) { - msr_t smbase_msr; - msr_t iedbase_msr; - - smbase_msr.lo = smbase; - smbase_msr.hi = 0; - - /* - * According the BWG the IEDBASE MSR is in bits 63:32. It's - * not clear why it differs from the SMBASE MSR. - */ - iedbase_msr.lo = 0; - iedbase_msr.hi = iedbase; - - wrmsr(SMBASE_MSR, smbase_msr); - wrmsr(IEDBASE_MSR, iedbase_msr); - } else { - em64t101_smm_state_save_area_t *save_state; - - save_state = (void *)(curr_smbase + SMM_DEFAULT_SIZE - - sizeof(*save_state)); - - save_state->smbase = smbase; - save_state->iedbase = iedbase; - } -} - -/* Returns 1 if SMM MSR save state was set. */ -static int bsp_setup_msr_save_state(struct smm_relocation_params *relo_params) -{ - msr_t smm_mca_cap; - - smm_mca_cap = rdmsr(SMM_MCA_CAP_MSR); - if (smm_mca_cap.hi & SMM_CPU_SVRSTR_MASK) { - msr_t smm_feature_control; - - smm_feature_control = rdmsr(SMM_FEATURE_CONTROL_MSR); - smm_feature_control.hi = 0; - smm_feature_control.lo |= SMM_CPU_SAVE_EN; - wrmsr(SMM_FEATURE_CONTROL_MSR, smm_feature_control); - relo_params->smm_save_state_in_msrs = 1; - } - return relo_params->smm_save_state_in_msrs; -} - -/* - * The relocation work is actually performed in SMM context, but the code - * resides in the ramstage module. This occurs by trampolining from the default - * SMRAM entry point to here. - */ -void smm_relocation_handler(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase) -{ - msr_t mtrr_cap; - struct smm_relocation_params *relo_params = &smm_reloc_params; - - printk(BIOS_DEBUG, "In relocation handler: CPU %d\n", cpu); - - /* - * Determine if the processor supports saving state in MSRs. If so, - * enable it before the non-BSPs run so that SMM relocation can occur - * in parallel in the non-BSP CPUs. - */ - if (cpu == 0) { - /* - * If smm_save_state_in_msrs is 1 then that means this is the - * 2nd time through the relocation handler for the BSP. - * Parallel SMM handler relocation is taking place. However, - * it is desired to access other CPUs save state in the real - * SMM handler. Therefore, disable the SMM save state in MSRs - * feature. - */ - if (relo_params->smm_save_state_in_msrs) { - msr_t smm_feature_control; - - smm_feature_control = rdmsr(SMM_FEATURE_CONTROL_MSR); - smm_feature_control.lo &= ~SMM_CPU_SAVE_EN; - wrmsr(SMM_FEATURE_CONTROL_MSR, smm_feature_control); - } else if (bsp_setup_msr_save_state(relo_params)) - /* - * Just return from relocation handler if MSR save - * state is enabled. In that case the BSP will come - * back into the relocation handler to setup the new - * SMBASE as well disabling SMM save state in MSRs. - */ - return; - } - - /* Make appropriate changes to the save state map. */ - update_save_state(cpu, curr_smbase, staggered_smbase, relo_params); - - /* Write SMRR MSRs based on indicated support. */ - mtrr_cap = rdmsr(MTRR_CAP_MSR); - if (mtrr_cap.lo & SMRR_SUPPORTED) - write_smrr(relo_params); -} - -static void fill_in_relocation_params(struct smm_relocation_params *params) -{ - uintptr_t tseg_base; - size_t tseg_size; - /* All range registers are aligned to 4KiB */ - const u32 rmask = ~((1 << 12) - 1); - - smm_region(&tseg_base, &tseg_size); - smm_subregion(SMM_SUBREGION_CHIPSET, &params->ied_base, &params->ied_size); - - /* SMRR has 32-bits of valid address aligned to 4KiB. */ - params->smrr_base.lo = (tseg_base & rmask) | MTRR_TYPE_WRBACK; - params->smrr_base.hi = 0; - params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID; - params->smrr_mask.hi = 0; -} - -static void setup_ied_area(struct smm_relocation_params *params) -{ - char *ied_base; - - struct ied_header ied = { - .signature = "INTEL RSVD", - .size = params->ied_size, - .reserved = {0}, - }; - - ied_base = (void *)params->ied_base; - - printk(BIOS_DEBUG, "IED base = 0x%08x\n", (u32) params->ied_base); - printk(BIOS_DEBUG, "IED size = 0x%08x\n", (u32) params->ied_size); - - /* Place IED header at IEDBASE. */ - memcpy(ied_base, &ied, sizeof(ied)); - - /* Zero out 32KiB at IEDBASE + 1MiB */ - memset(ied_base + (1 << 20), 0, (32 << 10)); -} - -void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, - size_t *smm_save_state_size) -{ - printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); - - fill_in_relocation_params(&smm_reloc_params); - - smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); - - if (smm_reloc_params.ied_size) - setup_ied_area(&smm_reloc_params); - - *smm_save_state_size = sizeof(em64t101_smm_state_save_area_t); -} - -void smm_initialize(void) -{ - /* Clear the SMM state in the southbridge. */ - smm_southbridge_clear_state(); - - /* - * Run the relocation handler for on the BSP to check and set up - * parallel SMM relocation. - */ - smm_initiate_relocation(); - - if (smm_reloc_params.smm_save_state_in_msrs) - printk(BIOS_DEBUG, "Doing parallel SMM relocation.\n"); -} - -void smm_relocate(void) -{ - /* - * If smm_save_state_in_msrs is non-zero then parallel SMM relocation - * shall take place. Run the relocation handler a second time on the - * BSP to do * the final move. For APs, a relocation handler always - * needs to be run. - */ - if (smm_reloc_params.smm_save_state_in_msrs) - smm_initiate_relocation_parallel(); - else if (!boot_cpu()) - smm_initiate_relocation(); -} diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc index b402fa0..4d5b9f5 100644 --- a/src/soc/intel/tigerlake/Makefile.inc +++ b/src/soc/intel/tigerlake/Makefile.inc @@ -40,7 +40,6 @@ ramstage-y += p2sb.c ramstage-y += pmc.c ramstage-y += reset.c -ramstage-y += smmrelocate.c ramstage-y += systemagent.c ramstage-y += sd.c diff --git a/src/soc/intel/tigerlake/smmrelocate.c b/src/soc/intel/tigerlake/smmrelocate.c deleted file mode 100644 index 023f04b..0000000 --- a/src/soc/intel/tigerlake/smmrelocate.c +++ /dev/null @@ -1,260 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2019 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <types.h> -#include <string.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ops.h> -#include <cpu/x86/cache.h> -#include <cpu/x86/lapic.h> -#include <cpu/x86/mp.h> -#include <cpu/x86/msr.h> -#include <cpu/x86/mtrr.h> -#include <cpu/x86/smm.h> -#include <cpu/intel/em64t101_save_state.h> -#include <cpu/intel/smm_reloc.h> -#include <console/console.h> -#include <soc/cpu.h> -#include <soc/msr.h> -#include <soc/pci_devs.h> -#include <soc/soc_chip.h> -#include <soc/systemagent.h> - -/* This gets filled in and used during relocation. */ -static struct smm_relocation_params smm_reloc_params; - -static inline void write_smrr(struct smm_relocation_params *relo_params) -{ - printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->smrr_base.lo, relo_params->smrr_mask.lo); - wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base); - wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); -} - -static void update_save_state(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase, - struct smm_relocation_params *relo_params) -{ - u32 smbase; - u32 iedbase; - - /* - * The relocated handler runs with all CPUs concurrently. Therefore - * stagger the entry points adjusting SMBASE downwards by save state - * size * CPU num. - */ - smbase = staggered_smbase; - iedbase = relo_params->ied_base; - - printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x\n", - smbase, iedbase); - - /* - * All threads need to set IEDBASE and SMBASE to the relocated - * handler region. However, the save state location depends on the - * smm_save_state_in_msrs field in the relocation parameters. If - * smm_save_state_in_msrs is non-zero then the CPUs are relocating - * the SMM handler in parallel, and each CPUs save state area is - * located in their respective MSR space. If smm_save_state_in_msrs - * is zero then the SMM relocation is happening serially so the - * save state is at the same default location for all CPUs. - */ - if (relo_params->smm_save_state_in_msrs) { - msr_t smbase_msr; - msr_t iedbase_msr; - - smbase_msr.lo = smbase; - smbase_msr.hi = 0; - - /* - * According the BWG the IEDBASE MSR is in bits 63:32. It's - * not clear why it differs from the SMBASE MSR. - */ - iedbase_msr.lo = 0; - iedbase_msr.hi = iedbase; - - wrmsr(SMBASE_MSR, smbase_msr); - wrmsr(IEDBASE_MSR, iedbase_msr); - } else { - em64t101_smm_state_save_area_t *save_state; - - save_state = (void *)(curr_smbase + SMM_DEFAULT_SIZE - - sizeof(*save_state)); - - save_state->smbase = smbase; - save_state->iedbase = iedbase; - } -} - -/* Returns 1 if SMM MSR save state was set. */ -static int bsp_setup_msr_save_state(struct smm_relocation_params *relo_params) -{ - msr_t smm_mca_cap; - - smm_mca_cap = rdmsr(SMM_MCA_CAP_MSR); - if (smm_mca_cap.hi & SMM_CPU_SVRSTR_MASK) { - msr_t smm_feature_control; - - smm_feature_control = rdmsr(SMM_FEATURE_CONTROL_MSR); - smm_feature_control.hi = 0; - smm_feature_control.lo |= SMM_CPU_SAVE_EN; - wrmsr(SMM_FEATURE_CONTROL_MSR, smm_feature_control); - relo_params->smm_save_state_in_msrs = 1; - } - return relo_params->smm_save_state_in_msrs; -} - -/* - * The relocation work is actually performed in SMM context, but the code - * resides in the ramstage module. This occurs by trampolining from the default - * SMRAM entry point to here. - */ -void smm_relocation_handler(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase) -{ - msr_t mtrr_cap; - struct smm_relocation_params *relo_params = &smm_reloc_params; - - printk(BIOS_DEBUG, "In relocation handler: CPU %d\n", cpu); - - /* - * Determine if the processor supports saving state in MSRs. If so, - * enable it before the non-BSPs run so that SMM relocation can occur - * in parallel in the non-BSP CPUs. - */ - if (cpu == 0) { - /* - * If smm_save_state_in_msrs is 1 then that means this is the - * 2nd time through the relocation handler for the BSP. - * Parallel SMM handler relocation is taking place. However, - * it is desired to access other CPUs save state in the real - * SMM handler. Therefore, disable the SMM save state in MSRs - * feature. - */ - if (relo_params->smm_save_state_in_msrs) { - msr_t smm_feature_control; - - smm_feature_control = rdmsr(SMM_FEATURE_CONTROL_MSR); - smm_feature_control.lo &= ~SMM_CPU_SAVE_EN; - wrmsr(SMM_FEATURE_CONTROL_MSR, smm_feature_control); - } else if (bsp_setup_msr_save_state(relo_params)) - /* - * Just return from relocation handler if MSR save - * state is enabled. In that case the BSP will come - * back into the relocation handler to setup the new - * SMBASE as well disabling SMM save state in MSRs. - */ - return; - } - - /* Make appropriate changes to the save state map. */ - update_save_state(cpu, curr_smbase, staggered_smbase, relo_params); - - /* Write SMRR MSRs based on indicated support. */ - mtrr_cap = rdmsr(MTRR_CAP_MSR); - if (mtrr_cap.lo & SMRR_SUPPORTED) - write_smrr(relo_params); -} - -static void fill_in_relocation_params(struct smm_relocation_params *params) -{ - uintptr_t tseg_base; - size_t tseg_size; - /* All range registers are aligned to 4KiB */ - const u32 rmask = ~(4 * KiB - 1); - - smm_region(&tseg_base, &tseg_size); - - if (!IS_ALIGNED(tseg_base, tseg_size)) { - printk(BIOS_WARNING, - "TSEG base not aligned with TSEG SIZE! Not setting SMRR\n"); - return; - } - - smm_subregion(SMM_SUBREGION_CHIPSET, &params->ied_base, &params->ied_size); - - /* SMRR has 32-bits of valid address aligned to 4KiB. */ - params->smrr_base.lo = (tseg_base & rmask) | MTRR_TYPE_WRBACK; - params->smrr_base.hi = 0; - params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID; - params->smrr_mask.hi = 0; -} - -static void setup_ied_area(struct smm_relocation_params *params) -{ - char *ied_base; - - struct ied_header ied = { - .signature = "INTEL RSVD", - .size = params->ied_size, - .reserved = {0}, - }; - - ied_base = (void *)params->ied_base; - - printk(BIOS_DEBUG, "IED base = 0x%08x\n", (u32)params->ied_base); - printk(BIOS_DEBUG, "IED size = 0x%08x\n", (u32)params->ied_size); - - /* Place IED header at IEDBASE. */ - memcpy(ied_base, &ied, sizeof(ied)); - - /* Zero out 32KiB at IEDBASE + 1MiB */ - memset(ied_base + 1 * MiB, 0, 32 * KiB); -} - -void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, - size_t *smm_save_state_size) -{ - printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); - - fill_in_relocation_params(&smm_reloc_params); - - smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); - - if (smm_reloc_params.ied_size) - setup_ied_area(&smm_reloc_params); - - *smm_save_state_size = sizeof(em64t101_smm_state_save_area_t); -} - -void smm_initialize(void) -{ - /* Clear the SMM state in the southbridge. */ - smm_southbridge_clear_state(); - - /* - * Run the relocation handler for on the BSP to check and set up - * parallel SMM relocation. - */ - smm_initiate_relocation(); - - if (smm_reloc_params.smm_save_state_in_msrs) - printk(BIOS_DEBUG, "Doing parallel SMM relocation.\n"); -} - -void smm_relocate(void) -{ - /* - * If smm_save_state_in_msrs is non-zero then parallel SMM relocation - * shall take place. Run the relocation handler a second time on the - * BSP to do * the final move. For APs, a relocation handler always - * needs to be run. - */ - if (smm_reloc_params.smm_save_state_in_msrs) - smm_initiate_relocation_parallel(); - else if (!boot_cpu()) - smm_initiate_relocation(); -} diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc index e53ed8d..2c0cb3b 100644 --- a/src/southbridge/intel/lynxpoint/Makefile.inc +++ b/src/southbridge/intel/lynxpoint/Makefile.inc @@ -38,10 +38,10 @@ ramstage-y += rcba.c ramstage-y += me_status.c ramstage-y += acpi.c +ramstage-y += smi.c pmutil.c ramstage-$(CONFIG_ELOG) += elog.c -ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c pmutil.c smm-y += smihandler.c me_9.x.c pch.c smm-y += pmutil.c usb_ehci.c usb_xhci.c -- To view, visit https://review.coreboot.org/c/coreboot/+/37108 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I177ca3b2966ccd985d72749ea2bd096ec4f233d6 Gerrit-Change-Number: 37108 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: intel/smm/em64t100: Have explicit pre_mp_smm_init()

by Kyösti Mälkki (Code Review)

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37132 ) Change subject: intel/smm/em64t100: Have explicit pre_mp_smm_init() ...................................................................... intel/smm/em64t100: Have explicit pre_mp_smm_init() Change-Id: Iac2aa793bfea8238c8f4b8aef55b5c53b8a9fcd3 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/intel/smm/em64t100.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/37132/1 diff --git a/src/cpu/intel/smm/em64t100.c b/src/cpu/intel/smm/em64t100.c index ff79337..2c1b293 100644 --- a/src/cpu/intel/smm/em64t100.c +++ b/src/cpu/intel/smm/em64t100.c @@ -34,6 +34,11 @@ smm_southbridge_clear_state(); } +static void per_cpu_smm_trigger(void) +{ + smm_initiate_relocation(); +} + /* The relocation work is actually performed in SMM context, but the code * resides in the ramstage module. This occurs by trampolining from the default * SMRAM entry point to here. */ @@ -61,5 +66,6 @@ { mp_ops->get_smm_info = get_smm_info; mp_ops->pre_mp_smm_init = pre_mp_smm_init; + mp_ops->per_cpu_smm_trigger = per_cpu_smm_trigger; mp_ops->relocation_handler = relocation_handler; } -- To view, visit https://review.coreboot.org/c/coreboot/+/37132 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iac2aa793bfea8238c8f4b8aef55b5c53b8a9fcd3 Gerrit-Change-Number: 37132 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel: Refactor em64t100 SMI handlers

by Kyösti Mälkki (Code Review)

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34841 ) Change subject: soc/intel: Refactor em64t100 SMI handlers ...................................................................... soc/intel: Refactor em64t100 SMI handlers Change-Id: I739940f9de97ad0392f9e7765d038ef6bf97b818 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/intel/smm/Makefile.inc A src/cpu/intel/smm/em64t100.c M src/cpu/intel/smm/smm_reloc.c M src/include/cpu/intel/em64t100_save_state.h M src/include/cpu/intel/smm_reloc.h M src/soc/intel/apollolake/cpu.c M src/soc/intel/baytrail/cpu.c M src/soc/intel/braswell/cpu.c M src/soc/intel/denverton_ns/cpu.c M src/soc/intel/denverton_ns/include/soc/smm.h M src/soc/intel/fsp_baytrail/cpu.c 11 files changed, 101 insertions(+), 248 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/34841/1 diff --git a/src/cpu/intel/smm/Makefile.inc b/src/cpu/intel/smm/Makefile.inc index a49b796..97fedc9 100644 --- a/src/cpu/intel/smm/Makefile.inc +++ b/src/cpu/intel/smm/Makefile.inc @@ -1 +1,2 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smm_reloc.c +ramstage-$(CONFIG_HAVE_SMI_HANDLER) += em64t100.c diff --git a/src/cpu/intel/smm/em64t100.c b/src/cpu/intel/smm/em64t100.c new file mode 100644 index 0000000..dcd0c0e --- /dev/null +++ b/src/cpu/intel/smm/em64t100.c @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <types.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mp.h> +#include <cpu/intel/em64t100_save_state.h> +#include <cpu/intel/smm_reloc.h> + +static void std_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, + size_t *smm_save_state_size) +{ + fill_in_smrr(&smm_reloc_params); + + smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); + *smm_save_state_size = sizeof(em64t100_smm_state_save_area_t); +} + +static void std_relocation_handler(int cpu, uintptr_t curr_smbase, + uintptr_t staggered_smbase) +{ + struct smm_relocation_params *relo_params = &smm_reloc_params; + em64t100_smm_state_save_area_t *smm_state; + + printk(BIOS_DEBUG, "In relocation handler: cpu %d SMBASE=0x%08x\n", cpu, + (u32)staggered_smbase); + + /* Make appropriate changes to the save state map. */ + smm_state = (void *)(SMM_EM64T100_SAVE_STATE_OFFSET + curr_smbase); + smm_state->smbase = staggered_smbase; + + printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", + relo_params->smrr_base.lo, relo_params->smrr_mask.lo); + + wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base); + wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); +} + +void select_mp_ops_em64t100(struct mp_ops *mp_ops) +{ + mp_ops->get_smm_info = std_smm_info; + mp_ops->relocation_handler = std_relocation_handler; +} diff --git a/src/cpu/intel/smm/smm_reloc.c b/src/cpu/intel/smm/smm_reloc.c index 860c095..78222c0 100644 --- a/src/cpu/intel/smm/smm_reloc.c +++ b/src/cpu/intel/smm/smm_reloc.c @@ -11,6 +11,27 @@ * GNU General Public License for more details. */ +#include <types.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/smm.h> #include <cpu/intel/smm_reloc.h> struct smm_relocation_params smm_reloc_params; + +void fill_in_smrr(struct smm_relocation_params *params) +{ + uintptr_t tseg_base; + size_t tseg_size; + + /* All range registers are aligned to 4KiB */ + const u32 rmask = ~((4 * KiB) - 1); + + smm_region(&tseg_base, &tseg_size); + + /* SMRR has 32-bits of valid address aligned to 4KiB. */ + params->smrr_base.lo = (tseg_base & rmask) | MTRR_TYPE_WRBACK; + params->smrr_base.hi = 0; + params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID; + params->smrr_mask.hi = 0; +} diff --git a/src/include/cpu/intel/em64t100_save_state.h b/src/include/cpu/intel/em64t100_save_state.h index f76fa4b..f0bdd32 100644 --- a/src/include/cpu/intel/em64t100_save_state.h +++ b/src/include/cpu/intel/em64t100_save_state.h @@ -103,4 +103,7 @@ u64 cr0; } __packed em64t100_smm_state_save_area_t; +struct mp_ops; +void select_mp_ops_em64t100(struct mp_ops *mp_ops); + #endif diff --git a/src/include/cpu/intel/smm_reloc.h b/src/include/cpu/intel/smm_reloc.h index 9b6473b..cbcdb56 100644 --- a/src/include/cpu/intel/smm_reloc.h +++ b/src/include/cpu/intel/smm_reloc.h @@ -37,6 +37,8 @@ extern struct smm_relocation_params smm_reloc_params; +void fill_in_smrr(struct smm_relocation_params *params); + #define MSR_PRMRR_PHYS_BASE 0x1f4 #define MSR_PRMRR_PHYS_MASK 0x1f5 #define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4 diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index e834142..834896e 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -134,13 +134,6 @@ /* * MP and SMM loading initialization. */ -struct smm_relocation_attrs { - uint32_t smbase; - uint32_t smrr_base; - uint32_t smrr_mask; -}; - -static struct smm_relocation_attrs relo_attrs; /* * Do essential initialization tasks before APs can be fired up. @@ -204,46 +197,6 @@ } #endif -static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, - size_t *smm_save_state_size) -{ - uintptr_t smm_base; - size_t smm_size; - uintptr_t handler_base; - size_t handler_size; - - /* All range registers are aligned to 4KiB */ - const uint32_t rmask = ~((1 << 12) - 1); - - /* Initialize global tracking state. */ - smm_region(&smm_base, &smm_size); - smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size); - - relo_attrs.smbase = smm_base; - relo_attrs.smrr_base = relo_attrs.smbase | MTRR_TYPE_WRBACK; - relo_attrs.smrr_mask = ~(smm_size - 1) & rmask; - relo_attrs.smrr_mask |= MTRR_PHYS_MASK_VALID; - - *perm_smbase = handler_base; - *perm_smsize = handler_size; - *smm_save_state_size = sizeof(em64t100_smm_state_save_area_t); -} - -static void relocation_handler(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase) -{ - msr_t smrr; - em64t100_smm_state_save_area_t *smm_state; - /* Set up SMRR. */ - smrr.lo = relo_attrs.smrr_base; - smrr.hi = 0; - wrmsr(IA32_SMRR_PHYS_BASE, smrr); - smrr.lo = relo_attrs.smrr_mask; - smrr.hi = 0; - wrmsr(IA32_SMRR_PHYS_MASK, smrr); - smm_state = (void *)(SMM_EM64T100_SAVE_STATE_OFFSET + curr_smbase); - smm_state->smbase = staggered_smbase; -} /* * CPU initialization recipe * @@ -260,18 +213,19 @@ mp_run_on_all_cpus(sgx_configure, NULL, 2000); } -static const struct mp_ops mp_ops = { +static struct mp_ops mp_ops = { .pre_mp_init = pre_mp_init, .get_cpu_count = get_cpu_count, - .get_smm_info = get_smm_info, .get_microcode_info = get_microcode_info, .pre_mp_smm_init = smm_southbridge_clear_state, - .relocation_handler = relocation_handler, .post_mp_init = post_mp_init, }; void soc_init_cpus(struct bus *cpu_bus) { + if (CONFIG(HAVE_SMI_HANDLER)) + select_mp_ops_em64t100(&mp_ops); + /* Clear for take-off */ if (mp_init_with_smm(cpu_bus, &mp_ops)) printk(BIOS_ERR, "MP initialization failure.\n"); diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c index 0f6969c..7f3e00d 100644 --- a/src/soc/intel/baytrail/cpu.c +++ b/src/soc/intel/baytrail/cpu.c @@ -83,7 +83,6 @@ .id_table = cpu_table, }; - /* * MP and SMM loading initialization. */ @@ -132,35 +131,6 @@ return pattrs->num_cpus; } -static void fill_in_relocation_params(struct smm_relocation_params *params) -{ - uintptr_t tseg_base; - size_t tseg_size; - - /* All range registers are aligned to 4KiB */ - const u32 rmask = ~((1 << 12) - 1); - - smm_region(&tseg_base, &tseg_size); - - /* SMRR has 32-bits of valid address aligned to 4KiB. */ - params->smrr_base.lo = (tseg_base & rmask) | MTRR_TYPE_WRBACK; - params->smrr_base.hi = 0; - params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID; - params->smrr_mask.hi = 0; -} - -static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, - size_t *smm_save_state_size) -{ - printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); - - fill_in_relocation_params(&smm_reloc_params); - - smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); - - *smm_save_state_size = sizeof(em64t100_smm_state_save_area_t); -} - static void get_microcode_info(const void **microcode, int *parallel) { const struct pattrs *pattrs = pattrs_get(); @@ -180,28 +150,12 @@ intel_microcode_load_unlocked(pattrs->microcode_patch); } -static void relocation_handler(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase) -{ - struct smm_relocation_params *relo_params = &smm_reloc_params; - em64t100_smm_state_save_area_t *smm_state; - - /* Set up SMRR. */ - wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base); - wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); - - smm_state = (void *)(SMM_EM64T100_SAVE_STATE_OFFSET + curr_smbase); - smm_state->smbase = staggered_smbase; -} - -static const struct mp_ops mp_ops = { +static struct mp_ops mp_ops = { .pre_mp_init = pre_mp_init, .get_cpu_count = get_cpu_count, - .get_smm_info = get_smm_info, .get_microcode_info = get_microcode_info, .pre_mp_smm_init = southcluster_smm_clear_state, .per_cpu_smm_trigger = per_cpu_smm_trigger, - .relocation_handler = relocation_handler, .post_mp_init = southcluster_smm_enable_smi, }; @@ -209,6 +163,9 @@ { struct bus *cpu_bus = dev->link_list; + if (CONFIG(HAVE_SMI_HANDLER)) + select_mp_ops_em64t100(&mp_ops); + if (mp_init_with_smm(cpu_bus, &mp_ops)) { printk(BIOS_ERR, "MP initialization failure.\n"); } diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c index abf6a99..75bc45f 100644 --- a/src/soc/intel/braswell/cpu.c +++ b/src/soc/intel/braswell/cpu.c @@ -91,7 +91,6 @@ .id_table = cpu_table, }; - /* * MP and SMM loading initialization. */ @@ -140,35 +139,6 @@ return pattrs->num_cpus; } -static void fill_in_relocation_params(struct smm_relocation_params *params) -{ - uintptr_t tseg_base; - size_t tseg_size; - - /* All range registers are aligned to 4KiB */ - const u32 rmask = ~((1 << 12) - 1); - - smm_region(&tseg_base, &tseg_size); - - /* SMRR has 32-bits of valid address aligned to 4KiB. */ - params->smrr_base.lo = (tseg_base & rmask) | MTRR_TYPE_WRBACK; - params->smrr_base.hi = 0; - params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID; - params->smrr_mask.hi = 0; -} - -static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, - size_t *smm_save_state_size) -{ - printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); - - fill_in_relocation_params(&smm_reloc_params); - - smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); - - *smm_save_state_size = sizeof(em64t100_smm_state_save_area_t); -} - static void get_microcode_info(const void **microcode, int *parallel) { const struct pattrs *pattrs = pattrs_get(); @@ -194,28 +164,12 @@ intel_microcode_load_unlocked(pattrs->microcode_patch); } -static void relocation_handler(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase) -{ - struct smm_relocation_params *relo_params = &smm_reloc_params; - em64t100_smm_state_save_area_t *smm_state; - - /* Set up SMRR. */ - wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base); - wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); - - smm_state = (void *)(SMM_EM64T100_SAVE_STATE_OFFSET + curr_smbase); - smm_state->smbase = staggered_smbase; -} - -static const struct mp_ops mp_ops = { +static struct mp_ops mp_ops = { .pre_mp_init = pre_mp_init, .get_cpu_count = get_cpu_count, - .get_smm_info = get_smm_info, .get_microcode_info = get_microcode_info, .pre_mp_smm_init = southcluster_smm_clear_state, .per_cpu_smm_trigger = per_cpu_smm_trigger, - .relocation_handler = relocation_handler, .post_mp_init = southcluster_smm_enable_smi, }; @@ -226,6 +180,9 @@ printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); + if (CONFIG(HAVE_SMI_HANDLER)) + select_mp_ops_em64t100(&mp_ops); + if (mp_init_with_smm(cpu_bus, &mp_ops)) printk(BIOS_ERR, "MP initialization failure.\n"); } diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c index bda6d1d..684b0d7 100644 --- a/src/soc/intel/denverton_ns/cpu.c +++ b/src/soc/intel/denverton_ns/cpu.c @@ -35,8 +35,6 @@ #include <soc/smm.h> #include <soc/soc_util.h> -static struct smm_relocation_attrs relo_attrs; - static void dnv_configure_mca(void) { msr_t msr; @@ -102,53 +100,6 @@ .id_table = cpu_table, }; -/* - * MP and SMM loading initialization. - */ - -static void relocation_handler(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase) -{ - msr_t smrr; - em64t100_smm_state_save_area_t *smm_state; - (void)cpu; - - /* Set up SMRR. */ - smrr.lo = relo_attrs.smrr_base; - smrr.hi = 0; - wrmsr(IA32_SMRR_PHYS_BASE, smrr); - smrr.lo = relo_attrs.smrr_mask; - smrr.hi = 0; - wrmsr(IA32_SMRR_PHYS_MASK, smrr); - smm_state = (void *)(SMM_EM64T100_SAVE_STATE_OFFSET + curr_smbase); - smm_state->smbase = staggered_smbase; -} - -static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, - size_t *smm_save_state_size) -{ - uintptr_t smm_base; - size_t smm_size; - uintptr_t handler_base; - size_t handler_size; - - /* All range registers are aligned to 4KiB */ - const uint32_t rmask = ~((1 << 12) - 1); - - /* Initialize global tracking state. */ - smm_region(&smm_base, &smm_size); - smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size); - - relo_attrs.smbase = smm_base; - relo_attrs.smrr_base = relo_attrs.smbase | MTRR_TYPE_WRBACK; - relo_attrs.smrr_mask = ~(smm_size - 1) & rmask; - relo_attrs.smrr_mask |= MTRR_PHYS_MASK_VALID; - - *perm_smbase = handler_base; - *perm_smsize = handler_size; - *smm_save_state_size = sizeof(em64t100_smm_state_save_area_t); -} - static int detect_num_cpus_via_cpuid(void) { register int ecx = 0; @@ -232,6 +183,7 @@ ((perf_ctl.lo >> 8) & 0xff) * CPU_BCLK); } + /* * Do essential initialization tasks before APs can be fired up * @@ -264,17 +216,18 @@ * the microcode on all cores before releasing them from reset. That means that * the BSP and all APs will come up with the same microcode revision. */ -static const struct mp_ops mp_ops = { +static struct mp_ops mp_ops = { .pre_mp_init = pre_mp_init, .get_cpu_count = get_cpu_count, - .get_smm_info = get_smm_info, .pre_mp_smm_init = southcluster_smm_clear_state, - .relocation_handler = relocation_handler, .post_mp_init = post_mp_init, }; void denverton_init_cpus(struct device *dev) { + if (CONFIG(HAVE_SMI_HANDLER)) + select_mp_ops_em64t100(&mp_ops); + /* Clear for take-off */ if (mp_init_with_smm(dev->link_list, &mp_ops) < 0) printk(BIOS_ERR, "MP initialization failure.\n"); diff --git a/src/soc/intel/denverton_ns/include/soc/smm.h b/src/soc/intel/denverton_ns/include/soc/smm.h index a020891..9de020b 100644 --- a/src/soc/intel/denverton_ns/include/soc/smm.h +++ b/src/soc/intel/denverton_ns/include/soc/smm.h @@ -18,12 +18,6 @@ #ifndef _DENVERTON_NS_SMM_H_ #define _DENVERTON_NS_SMM_H_ -struct smm_relocation_attrs { - uint32_t smbase; - uint32_t smrr_base; - uint32_t smrr_mask; -}; - #if !defined(__PRE_RAM__) && !defined(__SMM___) #include <stdint.h> void southcluster_smm_clear_state(void); diff --git a/src/soc/intel/fsp_baytrail/cpu.c b/src/soc/intel/fsp_baytrail/cpu.c index 8f925e8..8eb71c6 100644 --- a/src/soc/intel/fsp_baytrail/cpu.c +++ b/src/soc/intel/fsp_baytrail/cpu.c @@ -98,35 +98,6 @@ return pattrs->num_cpus; } -static void fill_in_relocation_params(struct smm_relocation_params *params) -{ - uintptr_t tseg_base; - size_t tseg_size; - - /* All range registers are aligned to 4KiB */ - const u32 rmask = ~(4 * KiB - 1); - - smm_region(&tseg_base, &tseg_size); - - /* SMRR has 32-bits of valid address aligned to 4KiB. */ - params->smrr_base.lo = (tseg_base & rmask) | MTRR_TYPE_WRBACK; - params->smrr_base.hi = 0; - params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID; - params->smrr_mask.hi = 0; -} - -static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, - size_t *smm_save_state_size) -{ - printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); - - fill_in_relocation_params(&smm_reloc_params); - - smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); - - *smm_save_state_size = sizeof(em64t100_smm_state_save_area_t); -} - static void get_microcode_info(const void **microcode, int *parallel) { const struct pattrs *pattrs = pattrs_get(); @@ -135,33 +106,17 @@ *parallel = 1; } -static void relocation_handler(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase) -{ - struct smm_relocation_params *relo_params = &smm_reloc_params; - em64t100_smm_state_save_area_t *smm_state; - - /* Set up SMRR. */ - wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base); - wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); - - smm_state = (void *)(SMM_EM64T100_SAVE_STATE_OFFSET + curr_smbase); - smm_state->smbase = staggered_smbase; -} - static void enable_smis(void) { if (CONFIG(HAVE_SMI_HANDLER)) southcluster_smm_enable_smi(); } -static const struct mp_ops mp_ops = { +static struct mp_ops mp_ops = { .pre_mp_init = pre_mp_init, .get_cpu_count = get_cpu_count, - .get_smm_info = get_smm_info, .get_microcode_info = get_microcode_info, .pre_mp_smm_init = southcluster_smm_clear_state, - .relocation_handler = relocation_handler, .post_mp_init = enable_smis, }; @@ -169,6 +124,9 @@ { struct bus *cpu_bus = dev->link_list; + if (CONFIG(HAVE_SMI_HANDLER)) + select_mp_ops_em64t100(&mp_ops); + if (mp_init_with_smm(cpu_bus, &mp_ops)) { printk(BIOS_ERR, "MP initialization failure.\n"); } -- To view, visit https://review.coreboot.org/c/coreboot/+/34841 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I739940f9de97ad0392f9e7765d038ef6bf97b818 Gerrit-Change-Number: 34841 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: HACK trogdor: SoC makefile BLOB support HACK

by Julius Werner (Code Review)

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35508 ) Change subject: HACK trogdor: SoC makefile BLOB support HACK ...................................................................... Patch Set 18: (1 comment) https://review.coreboot.org/c/coreboot/+/35508/15/src/soc/qualcomm/sc7180... File src/soc/qualcomm/sc7180/Makefile.inc: https://review.coreboot.org/c/coreboot/+/35508/15/src/soc/qualcomm/sc7180... PS15, Line 102: DCB_FILE := $(SC7180_BLOB)/600E_0100_1_1_dcb.bin > Julius, […] Sorry, I don't understand what you mean here? QcLib doesn't ever get to see this filename, all it gets to see is the "dcb_settings" QcLib interface table entry. In fact, not even coreboot gets to see this filename (in CBFS this is just called "fallback/dcb"). The only place where this filename currently exists is in the build file -- how the file is called in 3rdparty/blobs and the name this Makefile uses to find that. That's all I want you to change. I don't care how Qualcomm calls this internally, or even how it is called in the chipcode drops. I can rename it when I download a new version from chipcode. I just think that locally inside coreboot it doesn't need to be such a complicated name, if coreboot calls it "dcb.bin" rather than "600E_0100_1_1_dcb.bin" that makes it obvious that I need to rename something (whereas the difference between "600E_0100_1_1_dcb.bin" and 600E_0100_1_dcb.bin" was easy to overlook). -- To view, visit https://review.coreboot.org/c/coreboot/+/35508 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85a20ef31ec91c6f22221d16fd4c3097c5cb97d1 Gerrit-Change-Number: 35508 Gerrit-PatchSet: 18 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: ashk(a)codeaurora.org Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 22 Nov 2019 07:08:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: mturney mturney <mturney(a)codeaurora.org> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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