Alexander Couzens has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35438 )
Change subject: LinuxBoot: fix `make clean` for linux builds
......................................................................
LinuxBoot: fix `make clean` for linux builds
The kernel_dir variable was never correct, because targets/linux.mk
is using build directories based on the version e.g. kernel_4.19.73.
Change-Id: I749200bd32d86303ae02903afd96f730ac36b307
Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu>
---
M payloads/external/LinuxBoot/Makefile
1 file changed, 1 insertion(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/35438/1
diff --git a/payloads/external/LinuxBoot/Makefile b/payloads/external/LinuxBoot/Makefile
index 5840e8e..8b81c8a 100644
--- a/payloads/external/LinuxBoot/Makefile
+++ b/payloads/external/LinuxBoot/Makefile
@@ -14,7 +14,6 @@
##
project_dir=linuxboot
-kernel_dir=$(project_dir)/kernel
unexport $(COREBOOT_EXPORTS)
@@ -65,7 +64,7 @@
linuxboot: kernel initramfs_compressed
clean:
- if [ -d "$(kernel_dir)" ]; then rm -rf $(kernel_dir); fi
+ rm -rf $(project_dir)/kernel*
rm -f $(project_dir)/u-root
rm -f $(project_dir)/initramfs*
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I749200bd32d86303ae02903afd96f730ac36b307
Gerrit-Change-Number: 35438
Gerrit-PatchSet: 1
Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu>
Gerrit-MessageType: newchange
Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35739 )
Change subject: soc/intel/common/block: Update microcode for each core
......................................................................
soc/intel/common/block: Update microcode for each core
On Hyper-Threading enabled platform update the microcde only once
for each core, not for each thread.
Follow Intel Software Developer Guidelines as the added comment
also states.
Change-Id: I72804753e567a137a5648ca6950009fed332531b
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/soc/intel/common/block/cpu/mp_init.c
1 file changed, 20 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/35739/1
diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c
index 2c5061f..e7689cf 100644
--- a/src/soc/intel/common/block/cpu/mp_init.c
+++ b/src/soc/intel/common/block/cpu/mp_init.c
@@ -26,6 +26,7 @@
#include <intelblocks/fast_spi.h>
#include <intelblocks/mp_init.h>
#include <intelblocks/msr.h>
+#include <cpu/intel/common/common.h>
#include <soc/cpu.h>
static const void *microcode_patch;
@@ -44,7 +45,24 @@
static void init_one_cpu(struct device *dev)
{
soc_core_init(dev);
- intel_microcode_load_unlocked(microcode_patch);
+
+ /*
+ * Update just on the first CPU in the core. Other siblings
+ * get the update automatically according to Document: 253668-060US
+ * Intel SDM Chapter 9.11.6.3
+ * "Update in a System Supporting Intel Hyper-Threading Technology"
+ * Intel Hyper-Threading Technology has implications on the loading of the
+ * microcode update. The update must be loaded for each core in a physical
+ * processor. Thus, for a processor supporting Intel Hyper-Threading
+ * Technology, only one logical processor per core is required to load the
+ * microcode update. Each individual logical processor can independently
+ * load the update. However, MP initialization must provide some mechanism
+ * (e.g. a software semaphore) to force serialization of microcode update
+ * loads and to prevent simultaneous load attempts to the same core.
+ */
+ if (!intel_ht_sibling()) {
+ intel_microcode_load_unlocked(microcode_patch);
+ }
}
static struct device_operations cpu_dev_ops = {
@@ -141,6 +159,7 @@
if (CONFIG(USE_INTEL_FSP_MP_INIT))
return;
+ /* Update microcode on BSP */
microcode_patch = intel_microcode_find();
intel_microcode_load_unlocked(microcode_patch);
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I72804753e567a137a5648ca6950009fed332531b
Gerrit-Change-Number: 35739
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Gerrit-MessageType: newchange
Christoph Pomaska has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34905 )
Change subject: mb/supermicro/x10slm-f: Add new superio support to board's Kconfig
......................................................................
mb/supermicro/x10slm-f: Add new superio support to board's Kconfig
Since the superio support code didnt exist when the board was ported,
the Kconfig was not modified yet to add support for the BMC-chip.
This commit fixes the missing Kconfig entry.
Change-Id: I4f89c2ddcc00327e01d0a83fc13cfa862e6abd70
Signed-off-by: Christoph Pomaska <c.pomaska(a)hosting.de>
---
M src/mainboard/supermicro/x10slm-f/Kconfig
1 file changed, 4 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/34905/1
diff --git a/src/mainboard/supermicro/x10slm-f/Kconfig b/src/mainboard/supermicro/x10slm-f/Kconfig
index 3945c09..6effff2 100644
--- a/src/mainboard/supermicro/x10slm-f/Kconfig
+++ b/src/mainboard/supermicro/x10slm-f/Kconfig
@@ -20,15 +20,16 @@
def_bool y
select BOARD_ROMSIZE_KB_16384
select CPU_INTEL_HASWELL
- select DRIVERS_ASPEED_AST2050 # Supports AST2400 too.
+ select SOUTHBRIDGE_INTEL_LYNXPOINT
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select HAVE_OPTION_TABLE
select HAVE_CMOS_DEFAULT
select NORTHBRIDGE_INTEL_HASWELL
select SERIRQ_CONTINUOUS_MODE
- select SOUTHBRIDGE_INTEL_LYNXPOINT
- select SUPERIO_NUVOTON_NCT6776
+ select DRIVERS_ASPEED_AST2050 # Supports AST2400 too.
+ select SUPERIO_ASPEED_AST2400 # The board's BMC
+ select SUPERIO_NUVOTON_NCT6776 # the board's superio
select SUPERIO_NUVOTON_NCT6776_COM_A
config CBFS_SIZE
--
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Gerrit-Change-Id: I4f89c2ddcc00327e01d0a83fc13cfa862e6abd70
Gerrit-Change-Number: 34905
Gerrit-PatchSet: 1
Gerrit-Owner: Christoph Pomaska <github(a)aufmachen.jetzt>
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