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Change in coreboot[master]: x86: Prevent Kconfig errors resulting in a brick
by Patrick Rudolph (Code Review) 07 Aug '23

07 Aug '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34709 ) Change subject: x86: Prevent Kconfig errors resulting in a brick ...................................................................... x86: Prevent Kconfig errors resulting in a brick Always select USE_LEGACY_8254_TIMER if we know we have to. Fixes boot failure (Linux kernel/GRUB2 hangs with no console output) on X11SSH-TF using SeaBIOS as payload. Change-Id: Ica0c20255f661dd61edc3a7d15646b7447c4658e Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M payloads/external/GRUB2/Kconfig.name M payloads/external/SeaBIOS/Kconfig.name M src/device/Kconfig M src/soc/intel/common/block/timer/Kconfig 4 files changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/34709/1 diff --git a/payloads/external/GRUB2/Kconfig.name b/payloads/external/GRUB2/Kconfig.name index fe60d76..40629ad 100644 --- a/payloads/external/GRUB2/Kconfig.name +++ b/payloads/external/GRUB2/Kconfig.name @@ -1,6 +1,7 @@ config PAYLOAD_GRUB2 bool "GRUB2" depends on ARCH_X86 || ARCH_ARM + select USE_LEGACY_8254_TIMER if SOC_INTEL_COMMON_BLOCK help Select this option if you want to build a coreboot image with a GRUB2 payload. If you don't know what this is diff --git a/payloads/external/SeaBIOS/Kconfig.name b/payloads/external/SeaBIOS/Kconfig.name index bb1f30c..8f92997 100644 --- a/payloads/external/SeaBIOS/Kconfig.name +++ b/payloads/external/SeaBIOS/Kconfig.name @@ -1,6 +1,7 @@ config PAYLOAD_SEABIOS bool "SeaBIOS" depends on ARCH_X86 + select USE_LEGACY_8254_TIMER if SOC_INTEL_COMMON_BLOCK help Select this option if you want to build a coreboot image with a SeaBIOS payload. If you don't know what this is diff --git a/src/device/Kconfig b/src/device/Kconfig index e605bc2..ebf6bfb 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -86,6 +86,7 @@ bool "Run VGA Option ROMs" depends on PCI && (ARCH_X86 || ARCH_PPC64) && !MAINBOARD_FORCE_NATIVE_VGA_INIT select HAVE_VGA_TEXT_FRAMEBUFFER + select USE_LEGACY_8254_TIMER if SOC_INTEL_COMMON_BLOCK help Execute VGA Option ROMs in coreboot if found. This can be used to enable PCI/AGP/PCI-E video cards when not using a SeaBIOS diff --git a/src/soc/intel/common/block/timer/Kconfig b/src/soc/intel/common/block/timer/Kconfig index a214ef0..66bf9cf 100644 --- a/src/soc/intel/common/block/timer/Kconfig +++ b/src/soc/intel/common/block/timer/Kconfig @@ -5,7 +5,6 @@ config USE_LEGACY_8254_TIMER bool "Use Legacy 8254 Timer" - default y if PAYLOAD_SEABIOS || VGA_ROM_RUN default n help This sets the FSP UPD to enable Legacy 8254 clock gating. As per -- To view, visit https://review.coreboot.org/c/coreboot/+/34709 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica0c20255f661dd61edc3a7d15646b7447c4658e Gerrit-Change-Number: 34709 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

11 29

Change in coreboot[master]: sb/intel/common: Add AHCI code
by Patrick Rudolph (Code Review) 07 Aug '23

07 Aug '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37137 ) Change subject: sb/intel/common: Add AHCI code ...................................................................... sb/intel/common: Add AHCI code Implement a clean implementation based on AHCI spec 1.0-1.3 and the Intel ICH/PCH datasheets. The common implementation should combine all features of the duplicated code present in the various southbridge implementations. It compiles on x86_64, uses less magic values and detects the AHCI version at runtime. Change-Id: I5714788aa74b2d8bd855cbc65dd3d78c0a0101b8 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- A src/include/ahci.h M src/southbridge/intel/common/Kconfig M src/southbridge/intel/common/Makefile.inc A src/southbridge/intel/common/ahci.c A src/southbridge/intel/common/ahci.h 5 files changed, 252 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/37137/1 diff --git a/src/include/ahci.h b/src/include/ahci.h new file mode 100644 index 0000000..e7818fb --- /dev/null +++ b/src/include/ahci.h @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __AHCI_H__ +#define __AHCI_H__ + +/* Serial ATA AHCI 1.3.1 Specification */ + +#define AHCI_CAP 0x00 +#define AHCI_CAP_NP 0x1f +#define AHCI_CAP_PSC (1u << 13) +#define AHCI_CAP_SSC (1u << 14) +#define AHCI_CAP_PMD (1u << 15) +#define AHCI_CAP_SPM (1u << 17) +#define AHCI_CAP_SAM (1u << 18) +#define AHCI_CAP_SNZO (1u << 19) +#define AHCI_CAP_ISS(x) ((x) << 20) +#define AHCI_CAP_SCLO (1u << 24) +#define AHCI_CAP_SAL (1u << 25) +#define AHCI_CAP_SALP (1u << 26) +#define AHCI_CAP_SSS (1u << 27) +#define AHCI_CAP_SIS (1u << 28) +#define AHCI_CAP_SNCQ (1u << 30) +#define AHCI_CAP_S64A (1u << 31) +/* Added in AHCI 1.1 */ +#define AHCI_CAP_SXS (1u << 5) +#define AHCI_CAP_EMS (1u << 6) +#define AHCI_CAP_CCCS (1u << 7) +/* Added in AHCI 1.2 */ +#define AHCI_CAP_SSNTF (1u << 29) + +#define AHCI_GHC 0x04 +#define AHCI_GHC_AE (1u << 31) +#define AHCI_PI 0x0c +#define AHCI_VS 0x10 +#define AHCI_VS_MAJOR(x) ((x >> 16) & 0xf) +#define AHCI_VS_MINOR(x) ((x >> 8) & 0xf) + +/* Added in AHCI 1.1 */ +#define AHCI_CCC_CTL 0x14 +#define AHCI_CCC_PORTS 0x18 +#define AHCI_EM_LOC 0x1c +#define AHCI_EM_CTL 0x20 +/* Added in AHCI 1.2 */ +#define AHCI_CAP2 0x24 +#define AHCI_CAP2_BOH (1u << 0) +/* Added in AHCI 1.3 */ +#define AHCI_CAP2_NVMP (1u << 1) +#define AHCI_CAP2_APST (1u << 2) +#define AHCI_CAP2_SDS (1u << 3) +#define AHCI_CAP2_SADM (1u << 4) +#define AHCI_CAP2_DESO (1u << 5) + +#define AHCI_BOHC 0x28 + +#define AHCI_VENDOR 0xa0 +#define AHCI_PORT 0x100 +#define AHCI_PORT_PxCMD 0x18 +#define AHCI_PORT_LEN 0x80 + + +#endif diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig index 18bcd2e..376f077 100644 --- a/src/southbridge/intel/common/Kconfig +++ b/src/southbridge/intel/common/Kconfig @@ -2,6 +2,10 @@ def_bool n select HAVE_CF9_RESET +config SOUTHBRIDGE_INTEL_COMMON_AHCI + def_bool n + depends on PCI + config SOUTHBRIDGE_INTEL_COMMON_RTC def_bool n diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index c8521e1..e87ae82 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -18,6 +18,8 @@ all-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c +ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_AHCI) += ahci.c + romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c diff --git a/src/southbridge/intel/common/ahci.c b/src/southbridge/intel/common/ahci.c new file mode 100644 index 0000000..ca20d30 --- /dev/null +++ b/src/southbridge/intel/common/ahci.c @@ -0,0 +1,142 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <ahci.h> +#include <arch/io.h> +#include <device/device.h> +#include <device/pci.h> +#include <console/console.h> + +#include "ahci.h" + +/** + * Initialize the AHCI config space. + * @param port_map The ports to enable + * @param sam Set SAM bit (no legacy device support) + * @param cccs Set CCCS bit + * @param iss Limit the controller to sata gen x + * @param devslp Enable DEVSLP feature if supported + * @param clear_vnd Clear bits in vendor config space + */ +void sb_ahci_init(struct device *const dev, + const u32 port_map, + const bool sam, + const bool cccs, + const u8 iss, + const bool devslp, + const u32 clear_vnd) +{ + u32 reg32; + u8 major, minor; + struct resource *res; + u8 *abar; + unsigned int ports; + + /* Initialize AHCI memory-mapped space */ + res = find_resource(dev, PCI_BASE_ADDRESS_5); + if (!res) + return; + + abar = res2mmio(res, 0, 0); + /* + * Set AHCI access mode. + * Spec: "No other ABAR registers should be accessed before this." + */ + reg32 = read32(abar + AHCI_GHC); + if (!(reg32 & AHCI_GHC_AE)) { + reg32 |= AHCI_GHC_AE; + write32(abar + AHCI_GHC, reg32); + } + + /* Get AHCI version */ + reg32 = read32(abar + AHCI_VS); + major = AHCI_VS_MAJOR(reg32); + minor = AHCI_VS_MINOR(reg32); + printk(BIOS_DEBUG, "AHCI: implements AHCI %d.%d\n", major, minor); + + reg32 = read32(abar + AHCI_CAP); + printk(BIOS_DEBUG, "AHCI: supports SATA Gen%d\n", (reg32 >> 20) & 0xf); + + ports = reg32 & AHCI_CAP_NP; + printk(BIOS_DEBUG, "AHCI: supports up to %d ports\n", ports); + + /* CAP (HBA Capabilities) : enable power management */ + /* Program Write-Once bits (this isn't part of the AHCI spec, but PCH). */ + if (sam) + reg32 |= AHCI_CAP_SAM; + if (cccs && major >= 1 && minor >= 1) + reg32 |= AHCI_CAP_CCCS; + if (iss) { + u8 max_iss; + if (major >= 1 && minor >= 2) + max_iss = MIN(iss, 3); + else + max_iss = MIN(iss, 2); + reg32 &= ~AHCI_CAP_ISS(0xf); + reg32 |= AHCI_CAP_ISS(max_iss); + printk(BIOS_DEBUG, "AHCI: limited to Gen%d\n", max_iss); + } + reg32 |= AHCI_CAP_PSC; + reg32 |= AHCI_CAP_SSC; + reg32 |= AHCI_CAP_SALP; + reg32 |= AHCI_CAP_SSS; + if (major >= 1 && minor >= 1) { + reg32 &= ~AHCI_CAP_SXS; + reg32 &= ~AHCI_CAP_EMS; + reg32 &= ~AHCI_CAP_SPM; + } + write32(abar + AHCI_CAP, reg32); + + if (major >= 1 && minor >= 2) { + reg32 = read32(abar + AHCI_CAP2); + /* Clear BIOS handoff support */ + reg32 &= ~AHCI_CAP2_BOH; + if (major >= 1 && minor >= 3) { + /* Configure DEVSLP support */ + if (devslp) { + reg32 |= AHCI_CAP2_APST; + reg32 |= AHCI_CAP2_SDS; + reg32 |= AHCI_CAP2_SADM; + reg32 |= AHCI_CAP2_DESO; + } else { + reg32 &= ~AHCI_CAP2_SDS; + } + /* Disable NVMHCI */ + reg32 &= ~AHCI_CAP2_NVMP; + } + write32(abar + AHCI_CAP2, reg32); + } + + if (port_map & ~((1 << ports) - 1)) + printk(BIOS_ERR, "AHCI: Invalid port map given!\n"); + + write32(abar + AHCI_PI, port_map & ((1 << ports) - 1)); + /* PCH code reads back twice, do we need it, too? */ + (void) read32(abar + AHCI_PI); /* Read back 1 */ + (void) read32(abar + AHCI_PI); /* Read back 2 */ + + /* Clear vendor specific bits */ + reg32 = read32(abar + AHCI_VENDOR); + reg32 &= ~clear_vnd; + write32(abar + AHCI_VENDOR, reg32); + + /* Lock R/WO bits in Port command registers. */ + for (size_t i = 0; i < ports; ++i) { + if (!((1 << i) & port_map)) + continue; + u8 *addr = abar + AHCI_PORT + (i * AHCI_PORT_LEN); + write32(addr, read32(addr + AHCI_PORT_PxCMD)); + } +} diff --git a/src/southbridge/intel/common/ahci.h b/src/southbridge/intel/common/ahci.h new file mode 100644 index 0000000..9d4a025 --- /dev/null +++ b/src/southbridge/intel/common/ahci.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOUTHBRIDGE_INTEL_COMMON_AHCI_H +#define SOUTHBRIDGE_INTEL_COMMON_AHCI_H + +#include <device/device.h> + +void sb_ahci_init(struct device *const dev, + const u32 port_map, + const bool sam, + const bool cccs, + const u8 iss, + const bool devslp, + const u32 clear_vnd); + +#endif /* SOUTHBRIDGE_INTEL_COMMON_AHCI_H */ + -- To view, visit https://review.coreboot.org/c/coreboot/+/37137 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5714788aa74b2d8bd855cbc65dd3d78c0a0101b8 Gerrit-Change-Number: 37137 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

8 13

Change in coreboot[master]: src/superio: Add it8987e
by Sergey Larin (Code Review) 07 Aug '23

07 Aug '23

Sergey Larin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38253 ) Change subject: src/superio: Add it8987e ...................................................................... src/superio: Add it8987e Add support for IT8987E SuperIO. Based on it8528e. Currently untested. Signed-off-by: cerg2010cerg2010 <cerg2010cerg2010(a)mail.ru> Change-Id: I3e39be986ffbdebe873ff9b9dbc6902ed1ceaf6f --- A src/superio/ite/it8987e/Kconfig A src/superio/ite/it8987e/Makefile.inc A src/superio/ite/it8987e/it8987e.h A src/superio/ite/it8987e/superio.c 4 files changed, 135 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/38253/1 diff --git a/src/superio/ite/it8987e/Kconfig b/src/superio/ite/it8987e/Kconfig new file mode 100644 index 0000000..b8e3258 --- /dev/null +++ b/src/superio/ite/it8987e/Kconfig @@ -0,0 +1,18 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 Sergey Larin <cerg2010cerg2010(a)mail.ru> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config SUPERIO_ITE_IT8987E + bool + select SUPERIO_ITE_COMMON_PRE_RAM diff --git a/src/superio/ite/it8987e/Makefile.inc b/src/superio/ite/it8987e/Makefile.inc new file mode 100644 index 0000000..01e4d3e --- /dev/null +++ b/src/superio/ite/it8987e/Makefile.inc @@ -0,0 +1,17 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 Sergey Larin <cerg2010cerg2010(a)mail.ru> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-$(CONFIG_SUPERIO_ITE_IT8987E) += superio.c diff --git a/src/superio/ite/it8987e/it8987e.h b/src/superio/ite/it8987e/it8987e.h new file mode 100644 index 0000000..4e265df --- /dev/null +++ b/src/superio/ite/it8987e/it8987e.h @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Sergey Larin <cerg2010cerg2010(a)mail.ru> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SUPERIO_ITE_IT8987E_H +#define SUPERIO_ITE_IT8987E_H + +#define IT8987E_SWUC 0x04 /* System Wake-Up */ +#define IT8987E_KBCM 0x05 /* PS/2 mouse */ +#define IT8987E_KBCK 0x06 /* PS/2 keyboard */ +#define IT8987E_IR 0x0a /* Consumer IR */ +#define IT8987E_SMFI 0x0f /* Shared Memory/Flash Interface */ +#define IT8987E_RTCT 0x10 /* RTC-like Timer */ +#define IT8987E_PMC1 0x11 /* Power Management Channel 1 */ +#define IT8987E_PMC2 0x12 /* Power Management Channel 2 */ +#define IT8987E_SSPI 0x13 /* Serial Peripheral Interface */ +#define IT8987E_PECI 0x14 /* Platform EC Interface */ +#define IT8987E_PMC3 0x17 /* Power Management Channel 3 */ +#define IT8987E_PMC4 0x18 /* Power Management Channel 4 */ +#define IT8987E_PMC5 0x19 /* Power Management Channel 5 */ + + +#endif /* SUPERIO_ITE_IT8987E_H */ diff --git a/src/superio/ite/it8987e/superio.c b/src/superio/ite/it8987e/superio.c new file mode 100644 index 0000000..dce7a6f --- /dev/null +++ b/src/superio/ite/it8987e/superio.c @@ -0,0 +1,65 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Sergey Larin <cerg2010cerg2010(a)mail.ru> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <device/pnp.h> +#include <superio/conf_mode.h> + +#include "it8987e.h" + +static void it8987e_init(struct device *dev) +{ +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = it8987e_init, + .ops_pnp_mode = &pnp_conf_mode_870155_aa, +}; + +static struct pnp_info pnp_dev_info[] = { + { NULL, IT8987E_SWUC, PNP_IO0 | PNP_IRQ0, 0xfff0, }, + { NULL, IT8987E_KBCM, PNP_IRQ0, }, + { NULL, IT8987E_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07ff, }, + { NULL, IT8987E_IR, PNP_IO0 | PNP_IRQ0, 0xfff8, }, + { NULL, IT8987E_SMFI, PNP_IO0 | PNP_IRQ0 | PNP_MSC4, 0xfff0, }, + { NULL, IT8987E_RTCT, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IO3 | PNP_IRQ0 + | PNP_MSC0 | PNP_MSC1 | PNP_MSC2, + 0xfffe, 0xfffe, 0xfffe, 0xfffe}, + { NULL, IT8987E_PMC1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07ff }, + { NULL, IT8987E_PMC2, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IRQ0 | PNP_MSC0, + 0x07fc, 0x07fc, 0xfff0 }, + { NULL, IT8987E_SSPI, PNP_IO0 | PNP_IRQ0, 0xfff8 }, + { NULL, IT8987E_PECI, PNP_IO0, 0xfff8 }, + { NULL, IT8987E_PMC3, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07ff }, + { NULL, IT8987E_PMC4, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC0, + 0x07ff, 0x07ff }, + { NULL, IT8987E_PMC5, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC0, + 0x07ff, 0x07ff }, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_ite_it8987e_ops = { + CHIP_NAME("ITE IT8987E Super I/O") + .enable_dev = enable_dev, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/38253 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e39be986ffbdebe873ff9b9dbc6902ed1ceaf6f Gerrit-Change-Number: 38253 Gerrit-PatchSet: 1 Gerrit-Owner: Sergey Larin <cerg2010cerg2010(a)mail.ru> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: soc/intel/baytrail: Start VBOOT in bootblock
by Arthur Heymans (Code Review) 07 Aug '23

07 Aug '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36874 ) Change subject: soc/intel/baytrail: Start VBOOT in bootblock ...................................................................... soc/intel/baytrail: Start VBOOT in bootblock The earlier the more that can be updated via RW fmap regions. Change-Id: Ifcaf6ad8e27c09fee99cf6a8b12f9fadcb0cef2c Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/google/rambi/Makefile.inc M src/soc/intel/baytrail/Kconfig M src/soc/intel/baytrail/Makefile.inc M src/soc/intel/baytrail/pmutil.c 4 files changed, 9 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/36874/1 diff --git a/src/mainboard/google/rambi/Makefile.inc b/src/mainboard/google/rambi/Makefile.inc index 0e80b64..6660d23 100644 --- a/src/mainboard/google/rambi/Makefile.inc +++ b/src/mainboard/google/rambi/Makefile.inc @@ -13,6 +13,7 @@ ## GNU General Public License for more details. ## +verstage-$(CONFIG_CHROMEOS) += chromeos.c romstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index cfea93a..e4e8c30 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -41,11 +41,8 @@ config VBOOT select VBOOT_MUST_REQUEST_DISPLAY - select VBOOT_STARTS_IN_ROMSTAGE - -config BOOTBLOCK_CPU_INIT - string - default "soc/intel/baytrail/bootblock/bootblock.c" + select VBOOT_STARTS_IN_BOOTBLOCK + select VBOOT_SEPARATE_VERSTAGE config MMCONF_BASE_ADDRESS hex diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index eda3e25..d21f744 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -16,6 +16,8 @@ bootblock-y += ../../../cpu/x86/early_reset.S bootblock-y += bootblock/bootblock.c +verstage-y += pmutil.c + romstage-y += iosf.c romstage-y += memmap.c romstage-y += pmutil.c diff --git a/src/soc/intel/baytrail/pmutil.c b/src/soc/intel/baytrail/pmutil.c index 51174fc..2d14d84 100644 --- a/src/soc/intel/baytrail/pmutil.c +++ b/src/soc/intel/baytrail/pmutil.c @@ -368,7 +368,10 @@ { uint32_t gen_pmcon1; int rtc_fail; - struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); + struct chipset_power_state *ps = NULL; + + if (ENV_RAMSTAGE) + ps = cbmem_find(CBMEM_ID_POWER_STATE); if (ps != NULL) gen_pmcon1 = ps->gen_pmcon1; -- To view, visit https://review.coreboot.org/c/coreboot/+/36874 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifcaf6ad8e27c09fee99cf6a8b12f9fadcb0cef2c Gerrit-Change-Number: 36874 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 6

Change in ...coreboot[master]: nb/intel/sandybridge: Introduce soc/iomap.h
by Patrick Rudolph (Code Review) 07 Aug '23

07 Aug '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32075 Change subject: nb/intel/sandybridge: Introduce soc/iomap.h ...................................................................... nb/intel/sandybridge: Introduce soc/iomap.h Defines the memory ranges used by the northbridge in a separate header. Include the new header and rename the defines to match the one found in soc/intel/common. Change-Id: I93aa0e78ff52e46256debd26601600a96404509f Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/northbridge/intel/sandybridge/Makefile.inc M src/northbridge/intel/sandybridge/acpi.c M src/northbridge/intel/sandybridge/early_init.c A src/northbridge/intel/sandybridge/include/soc/iomap.h M src/northbridge/intel/sandybridge/northbridge.c M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/raminit_mrc.c M src/northbridge/intel/sandybridge/sandybridge.h 8 files changed, 92 insertions(+), 54 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/32075/1 diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index 54a4057..c3d9079 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -15,6 +15,8 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE)$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE),y) +CFLAGS_common += -Isrc/northbridge/intel/sandybridge/include + ramstage-y += ram_calc.c ramstage-y += northbridge.c ramstage-y += pcie.c diff --git a/src/northbridge/intel/sandybridge/acpi.c b/src/northbridge/intel/sandybridge/acpi.c index 4afb546..af2f37b 100644 --- a/src/northbridge/intel/sandybridge/acpi.c +++ b/src/northbridge/intel/sandybridge/acpi.c @@ -92,7 +92,8 @@ unsigned long tmp; tmp = current; - current += acpi_create_dmar_drhd(current, 0, 0, IOMMU_BASE1); + current += acpi_create_dmar_drhd(current, 0, 0, + GFXVT_BASE_ADDRESS); current += acpi_create_dmar_ds_pci(current, 0, 2, 0); current += acpi_create_dmar_ds_pci(current, 0, 2, 1); acpi_dmar_drhd_fixup(tmp, current); @@ -107,8 +108,8 @@ } const unsigned long tmp = current; - current += acpi_create_dmar_drhd(current, - DRHD_INCLUDE_PCI_ALL, 0, IOMMU_BASE2); + current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, + VTVC0_BASE_ADDRESS); current += acpi_create_dmar_ds_ioapic(current, 2, PCH_IOAPIC_PCI_BUS, PCH_IOAPIC_PCI_SLOT, 0); size_t i; diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index 5307a2c..2e0f087 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -35,20 +35,20 @@ return; /* setup BARs */ - MCHBAR32(0x5404) = IOMMU_BASE1 >> 32; - MCHBAR32(0x5400) = IOMMU_BASE1 | 1; - MCHBAR32(0x5414) = IOMMU_BASE2 >> 32; - MCHBAR32(0x5410) = IOMMU_BASE2 | 1; + MCHBAR32(0x5404) = GFXVT_BASE_ADDRESS >> 32; + MCHBAR32(0x5400) = GFXVT_BASE_ADDRESS | 1; + MCHBAR32(0x5414) = VTVC0_BASE_ADDRESS >> 32; + MCHBAR32(0x5410) = VTVC0_BASE_ADDRESS | 1; /* lock policies */ - write32((void *)(IOMMU_BASE1 + 0xff0), 0x80000000); + write32((void *)(GFXVT_BASE_ADDRESS + 0xff0), 0x80000000); const struct device *const azalia = pcidev_on_root(0x1b, 0); if (azalia && azalia->enabled) { - write32((void *)(IOMMU_BASE2 + 0xff0), 0x20000000); - write32((void *)(IOMMU_BASE2 + 0xff0), 0xa0000000); + write32((void *)(VTVC0_BASE_ADDRESS + 0xff0), 0x20000000); + write32((void *)(VTVC0_BASE_ADDRESS + 0xff0), 0xa0000000); } else { - write32((void *)(IOMMU_BASE2 + 0xff0), 0x80000000); + write32((void *)(VTVC0_BASE_ADDRESS + 0xff0), 0x80000000); } } @@ -67,12 +67,12 @@ { printk(BIOS_DEBUG, "Setting up static northbridge registers..."); /* Set up all hardcoded northbridge BARs */ - pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1); - pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR + 4, (0LL+DEFAULT_EPBAR) >> 32); - pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1); - pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4, (0LL+(uintptr_t)DEFAULT_MCHBAR) >> 32); - pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1); - pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, (0LL+(uintptr_t)DEFAULT_DMIBAR) >> 32); + pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, EP_BASE_ADDRESS | 1); + pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR + 4, EP_BASE_ADDRESS >> 32); + pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, MCH_BASE_ADDRESS | 1); + pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4, MCH_BASE_ADDRESS >> 32); + pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, DMI_BASE_ADDRESS | 1); + pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, DMI_BASE_ADDRESS >> 32); printk(BIOS_DEBUG, " done\n"); } diff --git a/src/northbridge/intel/sandybridge/include/soc/iomap.h b/src/northbridge/intel/sandybridge/include/soc/iomap.h new file mode 100644 index 0000000..75fd9d9 --- /dev/null +++ b/src/northbridge/intel/sandybridge/include/soc/iomap.h @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_SANDYBRIDGE_IOMAP_H_ +#define _SOC_SANDYBRIDGE_IOMAP_H_ + +/* + * Memory-mapped I/O registers. + */ +#define MCFG_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS +#define MCFG_BASE_SIZE 0x4000000 + +/* Intel Enhanced Debug region must be 4MB */ + +#define IED_SIZE CONFIG_IED_REGION_SIZE + +#define ILB_BASE_ADDRESS 0xfed08000ULL +#define ILB_BASE_SIZE 0x400 + +#define DMI_BASE_ADDRESS 0xfed18000ULL +#define DMI_BASE_SIZE 0x1000 + +#define MCH_BASE_ADDRESS 0xfed10000ULL +#define MCH_BASE_SIZE 0x4000 + +#define EP_BASE_ADDRESS 0xfed19000ULL +#define EP_BASE_SIZE 0x1000 + +#define GFXVT_BASE_ADDRESS 0xfed90000ULL +#define GFXVT_BASE_SIZE 0x1000 + +#define VTVC0_BASE_ADDRESS 0xfed91000ULL +#define VTVC0_BASE_SIZE 0x1000 + +#define TPM_BASE_ADDRESS 0xfed40000ULL +#define TPM_BASE_SIZE 0x5000 + + +#endif diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 5aa06c8..71dea62 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -112,8 +112,8 @@ /* Reserve IOMMU BARs */ const u32 capid0_a = pci_read_config32(dev, 0xe4); if (!(capid0_a & (1 << 23))) { - mmio_resource(dev, index++, IOMMU_BASE1 >> 10, 4); - mmio_resource(dev, index++, IOMMU_BASE2 >> 10, 4); + mmio_resource(dev, index++, GFXVT_BASE_ADDRESS / KiB, 4); + mmio_resource(dev, index++, VTVC0_BASE_ADDRESS / KiB, 4); } } diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 55df03b..72ae5b0 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -41,23 +41,23 @@ * Channel X = [0, 1] * Command queue index Y = [0, 1, 2, 3] * - * DEFAULT_MCHBAR + 0x4220 + 0x400 * X + 4 * Y: command io register + * MCH_BASE_ADDRESS + 0x4220 + 0x400 * X + 4 * Y: command io register * Controls the DRAM command signals * Bit 0: !RAS * Bit 1: !CAS * Bit 2: !WE * - * DEFAULT_MCHBAR + 0x4200 + 0x400 * X + 4 * Y: addr bankslot io register + * MCH_BASE_ADDRESS + 0x4200 + 0x400 * X + 4 * Y: addr bankslot io register * Controls the address, bank address and slotrank signals * Bit 0-15 : Address * Bit 20-22: Bank Address * Bit 24-25: slotrank * - * DEFAULT_MCHBAR + 0x4230 + 0x400 * X + 4 * Y: idle register + * MCH_BASE_ADDRESS + 0x4230 + 0x400 * X + 4 * Y: idle register * Controls the idle time after issuing this DRAM command * Bit 16-32: number of clock-cylces to idle * - * DEFAULT_MCHBAR + 0x4284 + 0x400 * channel: execute command queue + * MCH_BASE_ADDRESS + 0x4284 + 0x400 * channel: execute command queue * Starts to execute all queued commands * Bit 0 : start DRAM command execution * Bit 18-19 : number of queued commands - 1 diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index c544a74..2382084 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -277,10 +277,10 @@ static void northbridge_fill_pei_data(struct pei_data *pei_data) { - pei_data->mchbar = (uintptr_t)DEFAULT_MCHBAR; - pei_data->dmibar = (uintptr_t)DEFAULT_DMIBAR; - pei_data->epbar = DEFAULT_EPBAR; - pei_data->pciexbar = CONFIG_MMCONF_BASE_ADDRESS; + pei_data->mchbar = MCH_BASE_ADDRESS; + pei_data->dmibar = DMI_BASE_ADDRESS; + pei_data->epbar = EP_BASE_ADDRESS; + pei_data->pciexbar = MCFG_BASE_ADDRESS; pei_data->smbusbar = SMBUS_IO_BASE; pei_data->wdbbar = 0x4000000; pei_data->wdbsize = 0x1000; diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index d7de843..dc9f889 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -17,6 +17,8 @@ #ifndef __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__ #define __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__ +#include <northbridge/intel/sandybridge/include/soc/iomap.h> + /* Device ID for SandyBridge and IvyBridge */ #define BASE_REV_SNB 0x00 #define BASE_REV_IVB 0x50 @@ -34,24 +36,6 @@ #define IVB_STEP_K0 (BASE_REV_IVB + 5) #define IVB_STEP_D0 (BASE_REV_IVB + 6) -/* Intel Enhanced Debug region must be 4MB */ - -#define IED_SIZE CONFIG_IED_REGION_SIZE - -/* Northbridge BARs */ -#ifndef __ACPI__ -#define DEFAULT_MCHBAR ((u8 *)0xfed10000) /* 16 KB */ -#define DEFAULT_DMIBAR ((u8 *)0xfed18000) /* 4 KB */ -#else -#define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */ -#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ -#endif -#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ -#define DEFAULT_RCBABASE ((u8 *)0xfed1c000) - -#define IOMMU_BASE1 0xfed90000ULL -#define IOMMU_BASE2 0xfed91000ULL - /* Everything below this line is ignored in the DSDT */ #ifndef __ACPI__ #include <cpu/intel/model_206ax/model_206ax.h> @@ -118,9 +102,9 @@ * MCHBAR */ -#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x)))) +#define MCHBAR8(x) (*((volatile u8 *)((uintptr_t)MCH_BASE_ADDRESS + (x)))) +#define MCHBAR16(x) (*((volatile u16 *)((uintptr_t)MCH_BASE_ADDRESS + (x)))) +#define MCHBAR32(x) (*((volatile u32 *)((uintptr_t)MCH_BASE_ADDRESS + (x)))) #define MCHBAR32_OR(x, or) (MCHBAR32(x) = (MCHBAR32(x) | (or))) #define MCHBAR32_AND(x, and) (MCHBAR32(x) = (MCHBAR32(x) & (and))) #define MCHBAR32_AND_OR(x, and, or) \ @@ -133,9 +117,9 @@ * EPBAR - Egress Port Root Complex Register Block */ -#define EPBAR8(x) (*((volatile u8 *)(DEFAULT_EPBAR + (x)))) -#define EPBAR16(x) (*((volatile u16 *)(DEFAULT_EPBAR + (x)))) -#define EPBAR32(x) (*((volatile u32 *)(DEFAULT_EPBAR + (x)))) +#define EPBAR8(x) (*((volatile u8 *)((uintptr_t)EP_BASE_ADDRESS + (x)))) +#define EPBAR16(x) (*((volatile u16 *)((uintptr_t)EP_BASE_ADDRESS + (x)))) +#define EPBAR32(x) (*((volatile u32 *)((uintptr_t)EP_BASE_ADDRESS + (x)))) #define EPPVCCAP1 0x004 /* 32bit */ #define EPPVCCAP2 0x008 /* 32bit */ @@ -164,9 +148,9 @@ * DMIBAR */ -#define DMIBAR8(x) (*((volatile u8 *)(DEFAULT_DMIBAR + (x)))) -#define DMIBAR16(x) (*((volatile u16 *)(DEFAULT_DMIBAR + (x)))) -#define DMIBAR32(x) (*((volatile u32 *)(DEFAULT_DMIBAR + (x)))) +#define DMIBAR8(x) (*((volatile u8 *)((uintptr_t)DMI_BASE_ADDRESS + (x)))) +#define DMIBAR16(x) (*((volatile u16 *)((uintptr_t)DMI_BASE_ADDRESS + (x)))) +#define DMIBAR32(x) (*((volatile u32 *)((uintptr_t)DMI_BASE_ADDRESS + (x)))) #define DMIVCECH 0x000 /* 32bit */ #define DMIPVCCAP1 0x004 /* 32bit */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32075 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93aa0e78ff52e46256debd26601600a96404509f Gerrit-Change-Number: 32075 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

6 9

Change in coreboot[master]: console,boot_state: Denote unit in beginning in log message
by Paul Menzel (Code Review) 07 Aug '23

07 Aug '23

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38136 ) Change subject: console,boot_state: Denote unit in beginning in log message ...................................................................... console,boot_state: Denote unit in beginning in log message Looking at the board status repository logs, lines similar to BS: postcar times (exec / console): total (unknown) / 0 ms BS: BS_DEV_ENUMERATE run times (exec / console): 6 / 0 ms are not obvious right away, as the unit visually only applies to the value after the slash. So, add the unit after `times`. BS: BS_DEV_ENUMERATE run times [ms] (exec / console): 6 / 0 Change-Id: If01a5d43a54aeefc0a6d49d4b600436c2a8328cd Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/console/printk.c M src/lib/hardwaremain.c 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/38136/1 diff --git a/src/console/printk.c b/src/console/printk.c index 3ef28f3..be7c98b 100644 --- a/src/console/printk.c +++ b/src/console/printk.c @@ -49,7 +49,7 @@ if (!TRACK_CONSOLE_TIME) return; - printk(BIOS_DEBUG, "BS: " ENV_STRING " times (exec / console): total (unknown) / %ld ms\n", + printk(BIOS_DEBUG, "BS: " ENV_STRING " times [ms] (exec / console): total (unknown) / %ld\n", DIV_ROUND_CLOSEST(console_usecs, USECS_PER_MSEC)); } diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index eba5f12..cf1e1b7 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -250,7 +250,7 @@ execution = DIV_ROUND_CLOSEST(execution, USECS_PER_MSEC); console = DIV_ROUND_CLOSEST(console, USECS_PER_MSEC); if (execution) { - printk(BIOS_DEBUG, "BS: %s %s times (exec / console): %ld / %ld ms\n", + printk(BIOS_DEBUG, "BS: %s %s times [ms] (exec / console): %ld / %ld\n", state->name, sample_id[i], execution - console, console); /* Reset again to ignore printk() time above. */ console_time_get_and_reset(); -- To view, visit https://review.coreboot.org/c/coreboot/+/38136 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If01a5d43a54aeefc0a6d49d4b600436c2a8328cd Gerrit-Change-Number: 38136 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

5 8

Change in ...coreboot[master]: [WIP]x86: Introduce the blobolator
by Patrick Rudolph (Code Review) 07 Aug '23

07 Aug '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32020 Change subject: [WIP]x86: Introduce the blobolator ...................................................................... [WIP]x86: Introduce the blobolator This is a PoC to run arbitrary code and blobs inside an emulated virtual machine using libx86emu, thus the name blobolator. The libx86emu has been patched to the following: * redirect IO to the host machine it's running on * trace IO * start in protected mode * add mechanism to drop IO access * add Kconfig to debug code it is running Implemented features: * Run ramstage in libx86emu * Run postcar in libx86emu TODO: * Add support to trace only blobs, not stages. * Improve translation of known IO to human readable format ** COM ** PCI ** APIC ** PIT ** POST Tested on qemu. Sucessfully run ramstage in blobolator. Change-Id: I13e47f45e69376d046f35c04363fe3db1cfaa610 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/Kconfig M src/arch/x86/boot.c M src/mainboard/emulation/qemu-i440fx/romstage.c M src/mainboard/emulation/qemu-q35/romstage.c M src/vendorcode/Makefile.inc A src/vendorcode/libx86emu/Makefile.inc A src/vendorcode/libx86emu/blobolator.c A src/vendorcode/libx86emu/decode.c A src/vendorcode/libx86emu/include/decode.h A src/vendorcode/libx86emu/include/mem.h A src/vendorcode/libx86emu/include/ops.h A src/vendorcode/libx86emu/include/prim_ops.h A src/vendorcode/libx86emu/include/x86emu.h A src/vendorcode/libx86emu/include/x86emu_int.h A src/vendorcode/libx86emu/mem.c A src/vendorcode/libx86emu/ops.c A src/vendorcode/libx86emu/ops2.c A src/vendorcode/libx86emu/prim_ops.c 18 files changed, 14,512 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/32020/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/32020 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I13e47f45e69376d046f35c04363fe3db1cfaa610 Gerrit-Change-Number: 32020 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

10 31

Change in coreboot[master]: Documentation: Add guidelines for new mainboard ports
by Patrick Rudolph (Code Review) 07 Aug '23

07 Aug '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34632 ) Change subject: Documentation: Add guidelines for new mainboard ports ...................................................................... Documentation: Add guidelines for new mainboard ports This is WIP and partly copied from https://www.coreboot.org/Motherboard_Porting_Guide It also list what should be documented for new mainboard ports. Change-Id: I134dbf2341696ba0dd33c3d52bf787b8eaabbdab Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M Documentation/getting_started/index.md A Documentation/getting_started/new_mainboard_ports.md M Documentation/getting_started/writing_documentation.md 3 files changed, 95 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/34632/1 diff --git a/Documentation/getting_started/index.md b/Documentation/getting_started/index.md index 52d873e..7821ee1 100644 --- a/Documentation/getting_started/index.md +++ b/Documentation/getting_started/index.md @@ -7,3 +7,4 @@ * [Gerrit Guidelines](gerrit_guidelines.md) * [Documentation License](license.md) * [Writing Documentation](writing_documentation.md) +* [Adding new mainboards](new_mainboard_ports.md) diff --git a/Documentation/getting_started/new_mainboard_ports.md b/Documentation/getting_started/new_mainboard_ports.md new file mode 100644 index 0000000..cb7cd9b --- /dev/null +++ b/Documentation/getting_started/new_mainboard_ports.md @@ -0,0 +1,91 @@ +# Adding new mainboards + +Mainboard code is placed under `src/mainboards`. It glues the HW components +together by selecting appropiate northbridge, southbridge, on-board HW and +drivers. + +It provides the devicetree.cb, configures GPIOs, audio codecs, a static ACPI +board desciption and allows the romstage code to retrieve the SPD for +DRAM training. + +## Starting a new port from scratch + +1. Identify your platform + Try to find out as much as possible about the current hardware. + Dump information with existing tools: + * lspci + * lsusb + * superiotool + * inteltool + * ectool + * dmidecode + * acpidump + + Have a look at the mainboard schematics to see how those components are + connected. +2. Find a similar existing board + It a good idea to find a similar board and use it as reference. You should + then provide a proper GPIO configuration and devicetree.cb. +3. Find a similar SuperIo or BMC + To debug coreboot you should get the serial console working first. If your + board has a SuperIO or BMC try to find a compatible one. + Some boards have UART hardware on the SoC, makeing external components + obsolete. +4. Start with a minimal bootable configuration. That is: + * serial is working + * SPD reading/DRAM is working + * A payload that is able to boot an operating system +5. Be able to recover from a bad flash. You should use external flashing as + it's likely that you will brick your platform on the first attempts. + Make sure to backup the original firmware (if any). + +## Code submission + +Here's a checklist for new mainboard ports: + +1. Try to not duplicate code, use variants scheme instead. +2. Split changes logical into top level directories: + `src/mainboard` , `src/northbridge`, `src/ec`, ... +3. Provide good documentation, see point 4 +4. In the commit message describe as much as possible or point to the + documentation, satisfying the following questions: + * Where's the flash IC located? + * Can you flash incircuit? + * Are there pinheaders for flashing? + * Is the flash hardware write-protected? + * Which flash IC is usually equipped? + * If the board features an BMC, can it be used for developing and + debugging? + * What was tested and is working? + * What was tested and isn't working? + * What wasn't tested (due to lack of testing equipment)? + * Are blobs necessary? + * How can the board be debugged? + * Are there serial, EHCI debug, xHCI debug or BMC connections? + * Does it have a SuperIO? + + In addition please descibe: + * How to retrieve blobs, like dumping them from vendor firmware + + See [Writing Documentation] for more details. + +5. What you should **not** document: + * Steps or instructions how to flash the board + * Steps or instructions how to use a specific application for flashing + * Please do not provide pictures of the whole board or it's backplate + connectors +6. Recommand a flashing method as descibed in [Flashing tutorial] +7. If you are working at/for a hardware vendor, please provide free board + schematics as well. +8. Provide a picture of the flash IC or flash connector. + * The picture should be less than 800pc in width and compressed with + 70% compression to reduce size. + * You must own the Copyright + * Try to cut of uninteresting parts of the image, like tables, cables, ... + +Once done submit your board to Gerrit. Please follow the [Gerrit Guidelines] as +well. + +[Writing Documentation]: writing_documentation.md +[Flashing tutorial]: ../flash_tutorial/index.md +[Gerrit Guidelines]: gerrit_guidelines.md diff --git a/Documentation/getting_started/writing_documentation.md b/Documentation/getting_started/writing_documentation.md index fb942a4..0b820fc 100644 --- a/Documentation/getting_started/writing_documentation.md +++ b/Documentation/getting_started/writing_documentation.md @@ -49,6 +49,8 @@ the current theme doesn't allow bigger images. 12. Shouldn't cover implementation details; for details, the code is the reference. +13. New mainboard ports should also add documentation. See + [Adding new mainboards] for more details. ## Referencing markdown documents @@ -122,3 +124,4 @@ [Markdown Guide]: https://www.markdownguide.org/ [Gerrit Guidelines]: gerrit_guidelines.md [review.coreboot.org]: https://review.coreboot.org +[Adding new mainboards]: new_mainboard_ports.md -- To view, visit https://review.coreboot.org/c/coreboot/+/34632 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I134dbf2341696ba0dd33c3d52bf787b8eaabbdab Gerrit-Change-Number: 34632 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

9 19

Change in ...coreboot[master]: WIP: google/krane: Add Panel TV101WUM-NL6 support.
by Kaka Ni (Code Review) 07 Aug '23

07 Aug '23

Kaka Ni has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32512 Change subject: WIP: google/krane: Add Panel TV101WUM-NL6 support. ...................................................................... WIP: google/krane: Add Panel TV101WUM-NL6 support. Add panel TV101WUM-NL6 for Krane. The edid info and init command are from: https://crrev.com/c/1565758 Change-Id: Ieb6b2be6c2c571c09c781f4370d8c52612421823 Signed-off-by: Kaka Ni <nigang(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/kukui/Makefile.inc M src/mainboard/google/kukui/display.c M src/mainboard/google/kukui/display.h A src/mainboard/google/kukui/panel_krane.c 4 files changed, 423 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/32512/1 diff --git a/src/mainboard/google/kukui/Makefile.inc b/src/mainboard/google/kukui/Makefile.inc index ef52031..9576b7d 100644 --- a/src/mainboard/google/kukui/Makefile.inc +++ b/src/mainboard/google/kukui/Makefile.inc @@ -24,6 +24,7 @@ ramstage-y += chromeos.c ramstage-y += display.c ramstage-y += panel_kukui.c +ramstage-y += panel_krane.c ramstage-y += mainboard.c ramstage-y += memlayout.ld ramstage-y += reset.c diff --git a/src/mainboard/google/kukui/display.c b/src/mainboard/google/kukui/display.c index 5ec6ccd..b0a5026 100644 --- a/src/mainboard/google/kukui/display.c +++ b/src/mainboard/google/kukui/display.c @@ -97,6 +97,8 @@ { if (CONFIG(BOARD_GOOGLE_KUKUI)) return &kukui_display_intf; + else if (CONFIG(BOARD_GOOGLE_KRANE)) + return &krane_display_intf; else return NULL; } diff --git a/src/mainboard/google/kukui/display.h b/src/mainboard/google/kukui/display.h index 33cc997..52420db 100644 --- a/src/mainboard/google/kukui/display.h +++ b/src/mainboard/google/kukui/display.h @@ -33,9 +33,18 @@ PANEL_KUKUI_UNINITIALIZED }; +enum krane_panel_id { + PANEL_KRANE_FIRST = 0, + PANEL_KRANE_BOE_TV101WUM_NL6, + PANEL_KRANE_UNKNOWN, + PANEL_KRANE_COUNT, + PANEL_KRANE_UNINITIALIZED +}; + union panel_id { enum kukui_panel_id kukui_panel; + enum krane_panel_id krane_panel; int value; }; @@ -90,6 +99,7 @@ * Panel Interface for boards */ extern struct board_display_intf kukui_display_intf; +extern struct board_display_intf krane_display_intf; #endif diff --git a/src/mainboard/google/kukui/panel_krane.c b/src/mainboard/google/kukui/panel_krane.c new file mode 100644 index 0000000..5c338c8 --- /dev/null +++ b/src/mainboard/google/kukui/panel_krane.c @@ -0,0 +1,410 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Huaqin Telecom Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <delay.h> +#include <device/device.h> +#include <edid.h> +#include <gpio.h> +#include <soc/auxadc.h> +#include <soc/ddp.h> +#include <soc/dsi.h> +#include <soc/gpio.h> +#include <boardid.h> + +#include "display.h" +#include "gpio.h" + +static struct edid krane_boe_tv101wum_nl6_edid = { + .panel_bits_per_color = 8, + .panel_bits_per_pixel = 24, + .mode = { + .name = "1200x1920@60Hz", + .pixel_clock = 159420, + .lvds_dual_channel = 0, + .refresh = 60, + .ha = 1200, .hbl = 164, .hso = 80, .hspw = 24, .hborder = 0, + .va = 1920, .vbl = 28, .vso = 10, .vspw = 4, .vborder = 0, + .phsync = '-', .pvsync = '-', + .x_mm = 135, .y_mm = 216, + }, +}; + +struct lcm_init_table boe_tv101wum_nl6_init_cmd[] = { + {INIT_DCS_CMD, 1, { 0x10 } }, + {DELAY_CMD, 34, {} }, + {INIT_DCS_CMD, 2, { 0xB0, 0x05 } }, + {INIT_DCS_CMD, 2, { 0xB1, 0xE5 } }, + {INIT_DCS_CMD, 2, { 0xB3, 0x52 } }, + {INIT_DCS_CMD, 2, { 0xB0, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xB3, 0x88 } }, + {INIT_DCS_CMD, 2, { 0xB0, 0x04 } }, + {INIT_DCS_CMD, 2, { 0xB8, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xB0, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xB6, 0x03 } }, + {INIT_DCS_CMD, 2, { 0xBA, 0x8B } }, + {INIT_DCS_CMD, 2, { 0xBF, 0x1A } }, + {INIT_DCS_CMD, 2, { 0xC0, 0x0F } }, + {INIT_DCS_CMD, 2, { 0xC2, 0x0C } }, + {INIT_DCS_CMD, 2, { 0xC3, 0x02 } }, + {INIT_DCS_CMD, 2, { 0xC4, 0x0C } }, + {INIT_DCS_CMD, 2, { 0xC5, 0x02 } }, + {INIT_DCS_CMD, 2, { 0xB0, 0x01 } }, + {INIT_DCS_CMD, 2, { 0xE0, 0x26 } }, + {INIT_DCS_CMD, 2, { 0xE1, 0x26 } }, + {INIT_DCS_CMD, 2, { 0xDC, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xDD, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xCC, 0x26 } }, + {INIT_DCS_CMD, 2, { 0xCD, 0x26 } }, + {INIT_DCS_CMD, 2, { 0xC8, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xC9, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xD2, 0x03 } }, + {INIT_DCS_CMD, 2, { 0xD3, 0x03 } }, + {INIT_DCS_CMD, 2, { 0xE6, 0x04 } }, + {INIT_DCS_CMD, 2, { 0xE7, 0x04 } }, + {INIT_DCS_CMD, 2, { 0xC4, 0x09 } }, + {INIT_DCS_CMD, 2, { 0xC5, 0x09 } }, + {INIT_DCS_CMD, 2, { 0xD8, 0x0A } }, + {INIT_DCS_CMD, 2, { 0xD9, 0x0A } }, + {INIT_DCS_CMD, 2, { 0xC2, 0x0B } }, + {INIT_DCS_CMD, 2, { 0xC3, 0x0B } }, + {INIT_DCS_CMD, 2, { 0xD6, 0x0C } }, + {INIT_DCS_CMD, 2, { 0xD7, 0x0C } }, + {INIT_DCS_CMD, 2, { 0xC0, 0x05 } }, + {INIT_DCS_CMD, 2, { 0xC1, 0x05 } }, + {INIT_DCS_CMD, 2, { 0xD4, 0x06 } }, + {INIT_DCS_CMD, 2, { 0xD5, 0x06 } }, + {INIT_DCS_CMD, 2, { 0xCA, 0x07 } }, + {INIT_DCS_CMD, 2, { 0xCB, 0x07 } }, + {INIT_DCS_CMD, 2, { 0xDE, 0x08 } }, + {INIT_DCS_CMD, 2, { 0xDF, 0x08 } }, + {INIT_DCS_CMD, 2, { 0xB0, 0x02 } }, + {INIT_DCS_CMD, 2, { 0xC0, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xC1, 0x0D } }, + {INIT_DCS_CMD, 2, { 0xC2, 0x17 } }, + {INIT_DCS_CMD, 2, { 0xC3, 0x26 } }, + {INIT_DCS_CMD, 2, { 0xC4, 0x31 } }, + {INIT_DCS_CMD, 2, { 0xC5, 0x1C } }, + {INIT_DCS_CMD, 2, { 0xC6, 0x2C } }, + {INIT_DCS_CMD, 2, { 0xC7, 0x33 } }, + {INIT_DCS_CMD, 2, { 0xC8, 0x31 } }, + {INIT_DCS_CMD, 2, { 0xC9, 0x37 } }, + {INIT_DCS_CMD, 2, { 0xCA, 0x37 } }, + {INIT_DCS_CMD, 2, { 0xCB, 0x37 } }, + {INIT_DCS_CMD, 2, { 0xCC, 0x39 } }, + {INIT_DCS_CMD, 2, { 0xCD, 0x2E } }, + {INIT_DCS_CMD, 2, { 0xCE, 0x2F } }, + {INIT_DCS_CMD, 2, { 0xCF, 0x2F } }, + {INIT_DCS_CMD, 2, { 0xD0, 0x07 } }, + {INIT_DCS_CMD, 2, { 0xD2, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xD3, 0x0D } }, + {INIT_DCS_CMD, 2, { 0xD4, 0x17 } }, + {INIT_DCS_CMD, 2, { 0xD5, 0x26 } }, + {INIT_DCS_CMD, 2, { 0xD6, 0x31 } }, + {INIT_DCS_CMD, 2, { 0xD7, 0x3F } }, + {INIT_DCS_CMD, 2, { 0xD8, 0x3F } }, + {INIT_DCS_CMD, 2, { 0xD9, 0x3F } }, + {INIT_DCS_CMD, 2, { 0xDA, 0x3F } }, + {INIT_DCS_CMD, 2, { 0xDB, 0x37 } }, + {INIT_DCS_CMD, 2, { 0xDC, 0x37 } }, + {INIT_DCS_CMD, 2, { 0xDD, 0x37 } }, + {INIT_DCS_CMD, 2, { 0xDE, 0x39 } }, + {INIT_DCS_CMD, 2, { 0xDF, 0x2E } }, + {INIT_DCS_CMD, 2, { 0xE0, 0x2F } }, + {INIT_DCS_CMD, 2, { 0xE1, 0x2F } }, + {INIT_DCS_CMD, 2, { 0xE2, 0x07 } }, + {INIT_DCS_CMD, 2, { 0xB0, 0x03 } }, + {INIT_DCS_CMD, 2, { 0xC8, 0x0B } }, + {INIT_DCS_CMD, 2, { 0xC9, 0x07 } }, + {INIT_DCS_CMD, 2, { 0xC3, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xE7, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xC5, 0x2A } }, + {INIT_DCS_CMD, 2, { 0xDE, 0x2A } }, + {INIT_DCS_CMD, 2, { 0xCA, 0x43 } }, + {INIT_DCS_CMD, 2, { 0xC9, 0x07 } }, + {INIT_DCS_CMD, 2, { 0xE4, 0xC0 } }, + {INIT_DCS_CMD, 2, { 0xE5, 0x0D } }, + {INIT_DCS_CMD, 2, { 0xCB, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xB0, 0x06 } }, + {INIT_DCS_CMD, 2, { 0xB8, 0xA5 } }, + {INIT_DCS_CMD, 2, { 0xC0, 0xA5 } }, + {INIT_DCS_CMD, 2, { 0xC7, 0x0F } }, + {INIT_DCS_CMD, 2, { 0xD5, 0x32 } }, + {INIT_DCS_CMD, 2, { 0xB8, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xC0, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xBC, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xB0, 0x07 } }, + {INIT_DCS_CMD, 2, { 0xB1, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xB2, 0x02 } }, + {INIT_DCS_CMD, 2, { 0xB3, 0x0F } }, + {INIT_DCS_CMD, 2, { 0xB4, 0x25 } }, + {INIT_DCS_CMD, 2, { 0xB5, 0x39 } }, + {INIT_DCS_CMD, 2, { 0xB6, 0x4E } }, + {INIT_DCS_CMD, 2, { 0xB7, 0x72 } }, + {INIT_DCS_CMD, 2, { 0xB8, 0x97 } }, + {INIT_DCS_CMD, 2, { 0xB9, 0xDC } }, + {INIT_DCS_CMD, 2, { 0xBA, 0x22 } }, + {INIT_DCS_CMD, 2, { 0xBB, 0xA4 } }, + {INIT_DCS_CMD, 2, { 0xBC, 0x2B } }, + {INIT_DCS_CMD, 2, { 0xBD, 0x2F } }, + {INIT_DCS_CMD, 2, { 0xBE, 0xA9 } }, + {INIT_DCS_CMD, 2, { 0xBF, 0x25 } }, + {INIT_DCS_CMD, 2, { 0xC0, 0x61 } }, + {INIT_DCS_CMD, 2, { 0xC1, 0x97 } }, + {INIT_DCS_CMD, 2, { 0xC2, 0xB2 } }, + {INIT_DCS_CMD, 2, { 0xC3, 0xCD } }, + {INIT_DCS_CMD, 2, { 0xC4, 0xD9 } }, + {INIT_DCS_CMD, 2, { 0xC5, 0xE7 } }, + {INIT_DCS_CMD, 2, { 0xC6, 0xF4 } }, + {INIT_DCS_CMD, 2, { 0xC7, 0xFA } }, + {INIT_DCS_CMD, 2, { 0xC8, 0xFC } }, + {INIT_DCS_CMD, 2, { 0xC9, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xCA, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xCB, 0x16 } }, + {INIT_DCS_CMD, 2, { 0xCC, 0xAF } }, + {INIT_DCS_CMD, 2, { 0xCD, 0xFF } }, + {INIT_DCS_CMD, 2, { 0xCE, 0xFF } }, + {INIT_DCS_CMD, 2, { 0xB0, 0x08 } }, + {INIT_DCS_CMD, 2, { 0xB1, 0x04 } }, + {INIT_DCS_CMD, 2, { 0xB2, 0x05 } }, + {INIT_DCS_CMD, 2, { 0xB3, 0x11 } }, + {INIT_DCS_CMD, 2, { 0xB4, 0x24 } }, + {INIT_DCS_CMD, 2, { 0xB5, 0x39 } }, + {INIT_DCS_CMD, 2, { 0xB6, 0x4F } }, + {INIT_DCS_CMD, 2, { 0xB7, 0x72 } }, + {INIT_DCS_CMD, 2, { 0xB8, 0x98 } }, + {INIT_DCS_CMD, 2, { 0xB9, 0xDC } }, + {INIT_DCS_CMD, 2, { 0xBA, 0x23 } }, + {INIT_DCS_CMD, 2, { 0xBB, 0xA6 } }, + {INIT_DCS_CMD, 2, { 0xBC, 0x2C } }, + {INIT_DCS_CMD, 2, { 0xBD, 0x30 } }, + {INIT_DCS_CMD, 2, { 0xBE, 0xAA } }, + {INIT_DCS_CMD, 2, { 0xBF, 0x26 } }, + {INIT_DCS_CMD, 2, { 0xC0, 0x62 } }, + {INIT_DCS_CMD, 2, { 0xC1, 0x9B } }, + {INIT_DCS_CMD, 2, { 0xC2, 0xB5 } }, + {INIT_DCS_CMD, 2, { 0xC3, 0xCF } }, + {INIT_DCS_CMD, 2, { 0xC4, 0xDB } }, + {INIT_DCS_CMD, 2, { 0xC5, 0xE8 } }, + {INIT_DCS_CMD, 2, { 0xC6, 0xF5 } }, + {INIT_DCS_CMD, 2, { 0xC7, 0xFA } }, + {INIT_DCS_CMD, 2, { 0xC8, 0xFC } }, + {INIT_DCS_CMD, 2, { 0xC9, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xCA, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xCB, 0x16 } }, + {INIT_DCS_CMD, 2, { 0xCC, 0xAF } }, + {INIT_DCS_CMD, 2, { 0xCD, 0xFF } }, + {INIT_DCS_CMD, 2, { 0xCE, 0xFF } }, + {INIT_DCS_CMD, 2, { 0xB0, 0x09 } }, + {INIT_DCS_CMD, 2, { 0xB1, 0x04 } }, + {INIT_DCS_CMD, 2, { 0xB2, 0x02 } }, + {INIT_DCS_CMD, 2, { 0xB3, 0x16 } }, + {INIT_DCS_CMD, 2, { 0xB4, 0x24 } }, + {INIT_DCS_CMD, 2, { 0xB5, 0x3B } }, + {INIT_DCS_CMD, 2, { 0xB6, 0x4F } }, + {INIT_DCS_CMD, 2, { 0xB7, 0x73 } }, + {INIT_DCS_CMD, 2, { 0xB8, 0x99 } }, + {INIT_DCS_CMD, 2, { 0xB9, 0xE0 } }, + {INIT_DCS_CMD, 2, { 0xBA, 0x26 } }, + {INIT_DCS_CMD, 2, { 0xBB, 0xAD } }, + {INIT_DCS_CMD, 2, { 0xBC, 0x36 } }, + {INIT_DCS_CMD, 2, { 0xBD, 0x3A } }, + {INIT_DCS_CMD, 2, { 0xBE, 0xAE } }, + {INIT_DCS_CMD, 2, { 0xBF, 0x2A } }, + {INIT_DCS_CMD, 2, { 0xC0, 0x66 } }, + {INIT_DCS_CMD, 2, { 0xC1, 0x9E } }, + {INIT_DCS_CMD, 2, { 0xC2, 0xB8 } }, + {INIT_DCS_CMD, 2, { 0xC3, 0xD1 } }, + {INIT_DCS_CMD, 2, { 0xC4, 0xDD } }, + {INIT_DCS_CMD, 2, { 0xC5, 0xE9 } }, + {INIT_DCS_CMD, 2, { 0xC6, 0xF6 } }, + {INIT_DCS_CMD, 2, { 0xC7, 0xFA } }, + {INIT_DCS_CMD, 2, { 0xC8, 0xFC } }, + {INIT_DCS_CMD, 2, { 0xC9, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xCA, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xCB, 0x16 } }, + {INIT_DCS_CMD, 2, { 0xCC, 0xAF } }, + {INIT_DCS_CMD, 2, { 0xCD, 0xFF } }, + {INIT_DCS_CMD, 2, { 0xCE, 0xFF } }, + {INIT_DCS_CMD, 2, { 0xB0, 0x0A } }, + {INIT_DCS_CMD, 2, { 0xB1, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xB2, 0x02 } }, + {INIT_DCS_CMD, 2, { 0xB3, 0x0F } }, + {INIT_DCS_CMD, 2, { 0xB4, 0x25 } }, + {INIT_DCS_CMD, 2, { 0xB5, 0x39 } }, + {INIT_DCS_CMD, 2, { 0xB6, 0x4E } }, + {INIT_DCS_CMD, 2, { 0xB7, 0x72 } }, + {INIT_DCS_CMD, 2, { 0xB8, 0x97 } }, + {INIT_DCS_CMD, 2, { 0xB9, 0xDC } }, + {INIT_DCS_CMD, 2, { 0xBA, 0x22 } }, + {INIT_DCS_CMD, 2, { 0xBB, 0xA4 } }, + {INIT_DCS_CMD, 2, { 0xBC, 0x2B } }, + {INIT_DCS_CMD, 2, { 0xBD, 0x2F } }, + {INIT_DCS_CMD, 2, { 0xBE, 0xA9 } }, + {INIT_DCS_CMD, 2, { 0xBF, 0x25 } }, + {INIT_DCS_CMD, 2, { 0xC0, 0x61 } }, + {INIT_DCS_CMD, 2, { 0xC1, 0x97 } }, + {INIT_DCS_CMD, 2, { 0xC2, 0xB2 } }, + {INIT_DCS_CMD, 2, { 0xC3, 0xCD } }, + {INIT_DCS_CMD, 2, { 0xC4, 0xD9 } }, + {INIT_DCS_CMD, 2, { 0xC5, 0xE7 } }, + {INIT_DCS_CMD, 2, { 0xC6, 0xF4 } }, + {INIT_DCS_CMD, 2, { 0xC7, 0xFA } }, + {INIT_DCS_CMD, 2, { 0xC8, 0xFC } }, + {INIT_DCS_CMD, 2, { 0xC9, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xCA, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xCB, 0x16 } }, + {INIT_DCS_CMD, 2, { 0xCC, 0xAF } }, + {INIT_DCS_CMD, 2, { 0xCD, 0xFF } }, + {INIT_DCS_CMD, 2, { 0xCE, 0xFF } }, + {INIT_DCS_CMD, 2, { 0xB0, 0x0B } }, + {INIT_DCS_CMD, 2, { 0xB1, 0x04 } }, + {INIT_DCS_CMD, 2, { 0xB2, 0x05 } }, + {INIT_DCS_CMD, 2, { 0xB3, 0x11 } }, + {INIT_DCS_CMD, 2, { 0xB4, 0x24 } }, + {INIT_DCS_CMD, 2, { 0xB5, 0x39 } }, + {INIT_DCS_CMD, 2, { 0xB6, 0x4F } }, + {INIT_DCS_CMD, 2, { 0xB7, 0x72 } }, + {INIT_DCS_CMD, 2, { 0xB8, 0x98 } }, + {INIT_DCS_CMD, 2, { 0xB9, 0xDC } }, + {INIT_DCS_CMD, 2, { 0xBA, 0x23 } }, + {INIT_DCS_CMD, 2, { 0xBB, 0xA6 } }, + {INIT_DCS_CMD, 2, { 0xBC, 0x2C } }, + {INIT_DCS_CMD, 2, { 0xBD, 0x30 } }, + {INIT_DCS_CMD, 2, { 0xBE, 0xAA } }, + {INIT_DCS_CMD, 2, { 0xBF, 0x26 } }, + {INIT_DCS_CMD, 2, { 0xC0, 0x62 } }, + {INIT_DCS_CMD, 2, { 0xC1, 0x9B } }, + {INIT_DCS_CMD, 2, { 0xC2, 0xB5 } }, + {INIT_DCS_CMD, 2, { 0xC3, 0xCF } }, + {INIT_DCS_CMD, 2, { 0xC4, 0xDB } }, + {INIT_DCS_CMD, 2, { 0xC5, 0xE8 } }, + {INIT_DCS_CMD, 2, { 0xC6, 0xF5 } }, + {INIT_DCS_CMD, 2, { 0xC7, 0xFA } }, + {INIT_DCS_CMD, 2, { 0xC8, 0xFC } }, + {INIT_DCS_CMD, 2, { 0xC9, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xCA, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xCB, 0x16 } }, + {INIT_DCS_CMD, 2, { 0xCC, 0xAF } }, + {INIT_DCS_CMD, 2, { 0xCD, 0xFF } }, + {INIT_DCS_CMD, 2, { 0xCE, 0xFF } }, + {INIT_DCS_CMD, 2, { 0xB0, 0x0C } }, + {INIT_DCS_CMD, 2, { 0xB1, 0x04 } }, + {INIT_DCS_CMD, 2, { 0xB2, 0x02 } }, + {INIT_DCS_CMD, 2, { 0xB3, 0x16 } }, + {INIT_DCS_CMD, 2, { 0xB4, 0x24 } }, + {INIT_DCS_CMD, 2, { 0xB5, 0x3B } }, + {INIT_DCS_CMD, 2, { 0xB6, 0x4F } }, + {INIT_DCS_CMD, 2, { 0xB7, 0x73 } }, + {INIT_DCS_CMD, 2, { 0xB8, 0x99 } }, + {INIT_DCS_CMD, 2, { 0xB9, 0xE0 } }, + {INIT_DCS_CMD, 2, { 0xBA, 0x26 } }, + {INIT_DCS_CMD, 2, { 0xBB, 0xAD } }, + {INIT_DCS_CMD, 2, { 0xBC, 0x36 } }, + {INIT_DCS_CMD, 2, { 0xBD, 0x3A } }, + {INIT_DCS_CMD, 2, { 0xBE, 0xAE } }, + {INIT_DCS_CMD, 2, { 0xBF, 0x2A } }, + {INIT_DCS_CMD, 2, { 0xC0, 0x66 } }, + {INIT_DCS_CMD, 2, { 0xC1, 0x9E } }, + {INIT_DCS_CMD, 2, { 0xC2, 0xB8 } }, + {INIT_DCS_CMD, 2, { 0xC3, 0xD1 } }, + {INIT_DCS_CMD, 2, { 0xC4, 0xDD } }, + {INIT_DCS_CMD, 2, { 0xC5, 0xE9 } }, + {INIT_DCS_CMD, 2, { 0xC6, 0xF6 } }, + {INIT_DCS_CMD, 2, { 0xC7, 0xFA } }, + {INIT_DCS_CMD, 2, { 0xC8, 0xFC } }, + {INIT_DCS_CMD, 2, { 0xC9, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xCA, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xCB, 0x16 } }, + {INIT_DCS_CMD, 2, { 0xCC, 0xAF } }, + {INIT_DCS_CMD, 2, { 0xCD, 0xFF } }, + {INIT_DCS_CMD, 2, { 0xCE, 0xFF } }, + {INIT_DCS_CMD, 2, { 0xB0, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xB3, 0x08 } }, + {INIT_DCS_CMD, 2, { 0xB0, 0x04 } }, + {INIT_DCS_CMD, 2, { 0xB8, 0x68 } }, + {DELAY_CMD, 10, {} }, + {INIT_DCS_CMD, 1, { 0x11 } }, + {DELAY_CMD, 120, {} }, + {INIT_DCS_CMD, 1, { 0x29 } }, + {DELAY_CMD, 20, {} }, + +}; + +struct panel_info krane_panel_info[] = { + PANEL(PANEL_KRANE_BOE_TV101WUM_NL6, + 74000, + krane_boe_tv101wum_nl6_edid, + boe_tv101wum_nl6_init_cmd), + {{PANEL_KRANE_UNKNOWN}, "PANEL_KRANE_UNKNOWN", + 0, NULL, NULL, 0}, +}; + + +static union panel_id krane_get_panel_id(struct board_display_intf *intf) +{ + + return (union panel_id)PANEL_KRANE_BOE_TV101WUM_NL6; +}; + +static bool krane_is_panel_id_valid(union panel_id id) +{ + if (id.value < PANEL_KRANE_UNKNOWN) + return true; + return false; +}; + +static int krane_backlight(struct board_display_intf *intf) +{ + configure_backlight(); + return 0; +}; + +static int krane_power(struct board_display_intf *intf) +{ + + if (board_id() < 2) { + /* board from p1 */ + gpio_output(GPIO(LCM_RST), 0); + udelay(100); + gpio_output(GPIO(LCM_RST), 1); + mdelay(20); + } else { + /* board from p2 */ + gpio_output(GPIO(LCM_RST), 0); + udelay(1500); + gpio_output(GPIO(SIM2_SRST), 1); + mdelay(5); + gpio_output(GPIO(PERIPHERAL_EN9), 1); + gpio_output(GPIO(MISC_BSI_CK_3), 1); + mdelay(100); + gpio_output(GPIO(LCM_RST), 1); + mdelay(10); + } + + return 0; + +}; + +struct board_display_intf krane_display_intf = { + .board = "krane", + .all_panel_info = krane_panel_info, + .all_panel_info_size = ARRAY_SIZE(krane_panel_info), + .cur_panel_info = NULL, + .get_panel_id = &krane_get_panel_id, + .is_panel_id_valid = &krane_is_panel_id_valid, + .backlight = &krane_backlight, + .power = &krane_power, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/32512 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb6b2be6c2c571c09c781f4370d8c52612421823 Gerrit-Change-Number: 32512 Gerrit-PatchSet: 1 Gerrit-Owner: Kaka Ni <nigang(a)huaqin.corp-partner.google.com> Gerrit-MessageType: newchange

6 15

Change in ...coreboot[master]: util/lint: check correctness of Change-Id line
by Idwer Vollering (Code Review) 07 Aug '23

07 Aug '23

Idwer Vollering has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33884 Change subject: util/lint: check correctness of Change-Id line ...................................................................... util/lint: check correctness of Change-Id line Change-Id: I67b9f134500bb596ae5790b68fe9f27e2fa2cfb4 Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> --- A util/lint/lint-extended-024-change-id 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/33884/1 diff --git a/util/lint/lint-extended-024-change-id b/util/lint/lint-extended-024-change-id new file mode 100755 index 0000000..1989ed4 --- /dev/null +++ b/util/lint/lint-extended-024-change-id @@ -0,0 +1,10 @@ +#!/bin/sh +if [ "$(git log -n 1 | grep -c '[[:space:]]\+Change-Id: ')" -lt 1 ] +then + echo "Change-Id line is missing"; +fi + +if [ "$(git log -n 1 | grep -c '[[:space:]]\+Change-Id: ')" -gt 1 ] +then + echo "Found more than one Change-Id line"; +fi -- To view, visit https://review.coreboot.org/c/coreboot/+/33884 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67b9f134500bb596ae5790b68fe9f27e2fa2cfb4 Gerrit-Change-Number: 33884 Gerrit-PatchSet: 1 Gerrit-Owner: Idwer Vollering <vidwer(a)gmail.com> Gerrit-MessageType: newchange

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