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Change in coreboot[master]: soc/intel/common: Make use of clflush in common platform_segment_loaded
by Subrata Banik (Code Review) 07 Aug '23

07 Aug '23

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34992 ) Change subject: soc/intel/common: Make use of clflush in common platform_segment_loaded ...................................................................... soc/intel/common: Make use of clflush in common platform_segment_loaded This patch clear cache lines based on platform_segment_loaded() supplied start and size values before loading the targeted stage. This changes is required to fix hang issues appeared due to marking DRAM ranges as WB (CONFIG_MARK_DRAM_CACHE_WB) to speed up next stage loading/ decompression/execution time. Idea is to run clflush on those ranges just before tearing down the CAR (running invd instruction) and after that postcar frame will set up new MTRR ranges. Change-Id: I591f21cb4199477af271f0dd6c073e1c11831bfd Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/common/block/cpu/Kconfig M src/soc/intel/common/block/cpu/Makefile.inc A src/soc/intel/common/block/cpu/car/car.c 3 files changed, 71 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/34992/1 diff --git a/src/soc/intel/common/block/cpu/Kconfig b/src/soc/intel/common/block/cpu/Kconfig index 8cc572d..0d1506b 100644 --- a/src/soc/intel/common/block/cpu/Kconfig +++ b/src/soc/intel/common/block/cpu/Kconfig @@ -66,3 +66,15 @@ help This option allows FSP to make use of MP services PPI published by coreboot to perform multiprocessor initialization. + +config MARK_DRAM_CACHE_WB + bool + default n + help + This option allows you to select how DRAM intermediate cache is set up. + Till discovering DRAM ranges, system will make use of CAR and CAR tear + down will handle by postcar/ramstage, that means entire postcar/ramstage + stage will execute from UC range. Intention here is to optimize the boot + flow hence enabling the caching for applicable DRAM ranges before CAR + tear down and setting up new DRAM based MTRR range. MTRR type WB + provides best optimization. diff --git a/src/soc/intel/common/block/cpu/Makefile.inc b/src/soc/intel/common/block/cpu/Makefile.inc index a6c4f37..63a2ac9 100644 --- a/src/soc/intel/common/block/cpu/Makefile.inc +++ b/src/soc/intel/common/block/cpu/Makefile.inc @@ -5,6 +5,7 @@ romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CAR) += car/exit_car.S romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += cpulib.c +romstage-$(CONFIG_MARK_DRAM_CACHE_WB) += car.c postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CAR) += car/exit_car.S postcar-$(CONFIG_FSP_CAR) += car/exit_car_fsp.S diff --git a/src/soc/intel/common/block/cpu/car/car.c b/src/soc/intel/common/block/cpu/car/car.c new file mode 100644 index 0000000..82d8e9a --- /dev/null +++ b/src/soc/intel/common/block/cpu/car/car.c @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <assert.h> +#include <cbmem.h> +#include <cpu/x86/cache.h> +#include <program_loading.h> + +static inline int is_usable_dram_addr(uintptr_t addr) +{ + return (addr < (uintptr_t) cbmem_top()); +} + +/* + * CLFLUSH the impacted WB'ed cache lines before loading postcar/ramstage + * in order to avoid getting stuck while tearing down (invd) the CAR. + */ +static void flush_cache(uintptr_t start, size_t size) +{ + uintptr_t end; + uintptr_t addr; + + end = start + (ALIGN_DOWN(size + 4096, 4096)); + for (addr = start; addr < end; addr += 64) + clflush((void *)addr); +} + +void platform_segment_loaded(uintptr_t start, size_t size, int flags) +{ + /* Bail out if this is not the final segment. */ + if (!(flags & SEG_FINAL)) + return; + + char start_dram_check = is_usable_dram_addr(start); + char end_dram_check = is_usable_dram_addr(start + size - 1); + + /* + * Bail out if loaded program segment does not lie in + * usable DRAM region. + */ + if (!start_dram_check && !end_dram_check) + return; + + flush_cache(start, size); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/34992 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I591f21cb4199477af271f0dd6c073e1c11831bfd Gerrit-Change-Number: 34992 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: mb/lenovo/{t410,x201}: Make X201 a variant board of T410
by Maccraft123 (Code Review) 07 Aug '23

07 Aug '23

Maccraft123 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36871 ) Change subject: mb/lenovo/{t410,x201}: Make X201 a variant board of T410 ...................................................................... mb/lenovo/{t410,x201}: Make X201 a variant board of T410 T410 and X201 boards are similar enough to be variants in the same mainboard tree. So I did it. Change-Id: Icfa1818812347ceb4e2de5cc4a3130537a4e13e7 Signed-off-by: Maciej Matuszczyj <maccraft123mc(a)gmail.com> --- A .tmpconfig.lintiC3nbS M src/mainboard/lenovo/t410/Kconfig M src/mainboard/lenovo/t410/Kconfig.name M src/mainboard/lenovo/t410/Makefile.inc M src/mainboard/lenovo/t410/dock.c M src/mainboard/lenovo/t410/hda_verb.c M src/mainboard/lenovo/t410/mainboard.c M src/mainboard/lenovo/t410/romstage.c C src/mainboard/lenovo/t410/variants/t410/board_info.txt R src/mainboard/lenovo/t410/variants/t410/data.vbt R src/mainboard/lenovo/t410/variants/t410/devicetree.cb R src/mainboard/lenovo/t410/variants/t410/gpio.c R src/mainboard/lenovo/t410/variants/x201/board_info.txt R src/mainboard/lenovo/t410/variants/x201/data.vbt R src/mainboard/lenovo/t410/variants/x201/devicetree.cb R src/mainboard/lenovo/t410/variants/x201/gpio.c D src/mainboard/lenovo/x201/Kconfig D src/mainboard/lenovo/x201/Kconfig.name D src/mainboard/lenovo/x201/Makefile.inc D src/mainboard/lenovo/x201/acpi/dock.asl D src/mainboard/lenovo/x201/acpi/ec.asl D src/mainboard/lenovo/x201/acpi/gpe.asl D src/mainboard/lenovo/x201/acpi/platform.asl D src/mainboard/lenovo/x201/acpi/superio.asl D src/mainboard/lenovo/x201/acpi_tables.c D src/mainboard/lenovo/x201/cmos.default D src/mainboard/lenovo/x201/cmos.layout D src/mainboard/lenovo/x201/dock.c D src/mainboard/lenovo/x201/dock.h D src/mainboard/lenovo/x201/dsdt.asl D src/mainboard/lenovo/x201/early_init.c D src/mainboard/lenovo/x201/gma-mainboard.ads D src/mainboard/lenovo/x201/hda_verb.c D src/mainboard/lenovo/x201/mainboard.c D src/mainboard/lenovo/x201/romstage.c D src/mainboard/lenovo/x201/smihandler.c D src/mainboard/lenovo/x201/thermal.h D src/mainboard/lenovo/x201/vboot-rwa.fmd 38 files changed, 106 insertions(+), 1,132 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/36871/1 diff --git a/.tmpconfig.lintiC3nbS b/.tmpconfig.lintiC3nbS new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/.tmpconfig.lintiC3nbS diff --git a/src/mainboard/lenovo/t410/Kconfig b/src/mainboard/lenovo/t410/Kconfig index 329d08d..3b21f1b 100644 --- a/src/mainboard/lenovo/t410/Kconfig +++ b/src/mainboard/lenovo/t410/Kconfig @@ -1,4 +1,4 @@ -if BOARD_LENOVO_T410 +if BOARD_LENOVO_T410 || BOARD_LENOVO_X201 config BOARD_SPECIFIC_OPTIONS def_bool y @@ -14,6 +14,7 @@ select HAVE_ACPI_TABLES select INTEL_INT15 select HAVE_ACPI_RESUME + select SUPERIO_NSC_PC87382 if BOARD_LENOVO_X201 select DRIVERS_LENOVO_WACOM select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 @@ -38,6 +39,10 @@ hex default 0x2a +config DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + config FMDFILE string default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT @@ -48,7 +53,8 @@ config MAINBOARD_PART_NUMBER string - default "ThinkPad T410" + default "ThinkPad T410" if BOARD_LENOVO_T410 + default "ThinkPad X201" if BOARD_LENOVO_X201 config USBDEBUG_HCD_INDEX int @@ -66,4 +72,10 @@ int default 10 +# Without the Intel ME's EFFS partition some PCIe devices (like the USB and SATA +# controllers) don't work as expected +config ME_CLEANER_ARGS + string + default "-S -w EFFS" + endif diff --git a/src/mainboard/lenovo/t410/Kconfig.name b/src/mainboard/lenovo/t410/Kconfig.name index d79cf39..531f21f 100644 --- a/src/mainboard/lenovo/t410/Kconfig.name +++ b/src/mainboard/lenovo/t410/Kconfig.name @@ -1,2 +1,5 @@ config BOARD_LENOVO_T410 bool "ThinkPad T410" + +config BOARD_LENOVO_X201 + bool "ThinkPad X201" diff --git a/src/mainboard/lenovo/t410/Makefile.inc b/src/mainboard/lenovo/t410/Makefile.inc index 518d91a..9ff4abe 100644 --- a/src/mainboard/lenovo/t410/Makefile.inc +++ b/src/mainboard/lenovo/t410/Makefile.inc @@ -21,4 +21,5 @@ romstage-y += dock.c ramstage-y += dock.c -romstage-y += gpio.c +romstage-$(CONFIG_MAINBOARD_LENOVO_X201) += variants/x201/gpio.c +romstage-$(CONFIG_MAINBOARD_LENOVO_T410) += variants/t410/gpio.c diff --git a/src/mainboard/lenovo/t410/dock.c b/src/mainboard/lenovo/t410/dock.c index 1575aa1..5c5f731 100644 --- a/src/mainboard/lenovo/t410/dock.c +++ b/src/mainboard/lenovo/t410/dock.c @@ -3,6 +3,7 @@ * * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> * Copyright (C) 2013 Vladimir Serbinenko <phcoder(a)gmail.com> + * Copyright (C) 2019 Maciej Matuszczyk * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -37,6 +38,9 @@ ec_set_bit(0x02, 0); ec_set_bit(0x1a, 0); ec_set_bit(0xfe, 4); + #if CONFIG(BOARD_LENOVO_X201) + set_gpio(28, GPIO_LEVEL_HICH); // Might also work ok t410, + #endif } void dock_disconnect(void) @@ -45,6 +49,9 @@ ec_clr_bit(0x02, 0); ec_clr_bit(0x1a, 0); ec_clr_bit(0xfe, 4); + #if CONFIG(BOARD_LENOVO_X201) + set_gpio(28, GPIO_LEVEL_LOW); + #endif } int dock_present(void) diff --git a/src/mainboard/lenovo/t410/hda_verb.c b/src/mainboard/lenovo/t410/hda_verb.c index 752e5da..c12e8b4 100644 --- a/src/mainboard/lenovo/t410/hda_verb.c +++ b/src/mainboard/lenovo/t410/hda_verb.c @@ -19,15 +19,27 @@ const u32 cim_verb_data[] = { /* coreboot specific header */ 0x14F15069, /* Codec Vendor / Device ID: Conexant CX20585 */ + #if CONFIG(BOARD_LENOVO_T410) 0x17AA214C, /* Subsystem ID */ + #elif CONFIG(BOARD_LENOVO_X201) + 0x17AA2155, /* Subsystem ID */ + #endif 0x0000000B, /* Number of 4 dword sets */ + #if CONFIG(BOARD_LENOVO_T410) AZALIA_SUBVENDOR(0x0, 0x17AA214C), + #elif CONFIG(BOARD_LENOVO_X201) + AZALIA_SUBVENDOR(0x0, 0x17AA2155), + #endif AZALIA_PIN_CFG(0x0, 0x19, 0x042110F0), AZALIA_PIN_CFG(0x0, 0x1A, 0x61A190F0), AZALIA_PIN_CFG(0x0, 0x1B, 0x04A110F0), AZALIA_PIN_CFG(0x0, 0x1C, 0x612140F0), + #if CONFIG(BOARD_LENOVO_T410) AZALIA_PIN_CFG(0x0, 0x1D, 0x40F001F0), + #elif CONFIG(BOARD_LENOVO_X201) + AZALIA_PIN_CFG(0x0, 0x1D, 0x601700F0), + #endif AZALIA_PIN_CFG(0x0, 0x1E, 0x40F001F0), AZALIA_PIN_CFG(0x0, 0x1F, 0x901701F0), AZALIA_PIN_CFG(0x0, 0x20, 0x40F001F0), @@ -35,7 +47,11 @@ AZALIA_PIN_CFG(0x0, 0x23, 0x90A601F0), 0x80862804, /* Codec Vendor / Device ID: Intel Ibexpeak HDMI. */ + #if CONFIG(BOARD_LENOVO_T410) 0x17AA21B5, /* Subsystem ID */ + #elif CONFIG(BOARD_LENOVO_X201) + 0x17aa21b5, /* Subsystem ID */ + #endif 0x00000004, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0x3, 0x17AA21B5), diff --git a/src/mainboard/lenovo/t410/mainboard.c b/src/mainboard/lenovo/t410/mainboard.c index 8b6a737..d961db1 100644 --- a/src/mainboard/lenovo/t410/mainboard.c +++ b/src/mainboard/lenovo/t410/mainboard.c @@ -4,6 +4,7 @@ * Copyright (C) 2007-2009 coresystems GmbH * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> * Copyright (C) 2013 Vladimir Serbinenko <phcoder(a)gmail.com> + * Copyright (C) 2019 Maciej Matuszczyk * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -17,12 +18,28 @@ */ #include <device/device.h> -#include <arch/acpi.h> -#include <drivers/intel/gma/int15.h> +#include <device/pci_ops.h> +#include <ec/acpi/ec.h> +#include <northbridge/intel/nehalem/nehalem.h> +#include <southbridge/intel/bd82x6x/pch.h> #include "dock.h" +#include <drivers/intel/gma/int15.h> +#include <cpu/x86/lapic.h> +#include <drivers/lenovo/lenovo.h> + +static void fill_ssdt(struct device *device) +{ + drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB", 0); +} static void mainboard_enable(struct device *dev) { + dev->ops->acpi_fill_ssdt_generator = fill_ssdt; + + /* If we're resuming from suspend, blink suspend LED */ + if (acpi_is_wakeup_s3()) + ec_write(0x0c, 0xc7); + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_LFP, 2); diff --git a/src/mainboard/lenovo/t410/romstage.c b/src/mainboard/lenovo/t410/romstage.c index 7c796de..df4228b 100644 --- a/src/mainboard/lenovo/t410/romstage.c +++ b/src/mainboard/lenovo/t410/romstage.c @@ -19,11 +19,11 @@ #include <stdint.h> #include <device/pci_ops.h> #include <southbridge/intel/ibexpeak/pch.h> -#include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h> #include <northbridge/intel/nehalem/nehalem.h> const struct southbridge_usb_port mainboard_usb_ports[] = { /* Enabled, Current table lookup index, OC map */ + #if CONFIG(BOARD_LENOVO_T410) { 1, IF1_557, 0 }, { 1, IF1_55F, 1 }, { 1, IF1_74B, 3 }, @@ -38,8 +38,26 @@ { 1, IF1_74B, 7 }, { 1, IF1_557, 7 }, { 1, IF1_55F, 7 }, + #elif CONFIG(BOARD_LENOVO_X201) + { 1, IF1_557, 0 }, + { 1, IF1_55F, 1 }, + { 1, IF1_74B, 3 }, + { 1, IF1_74B, 3 }, + { 1, IF1_557, 3 }, + { 1, IF1_14B, 3 }, + { 1, IF1_74B, 3 }, + { 1, IF1_74B, 3 }, + { 1, IF1_74B, 4 }, + { 1, IF1_74B, 5 }, + { 1, IF1_55F, 7 }, + { 1, IF1_55F, 7 }, + { 1, IF1_557, 7 }, + { 1, IF1_55F, 7 }, + #endif }; +#if CONFIG(BOARD_LENOVO_T410) +#include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h> static void hybrid_graphics_init(void) { bool peg, igd; @@ -62,14 +80,38 @@ pci_write_config32(PCI_DEV(0, 0, 0), D0F0_DEVEN, reg32); } +#endif + +static void set_fsb_frequency(void) +{ + u8 block[5]; + u16 fsbfreq = 62879; + smbus_block_read(0x69, 0, 5, block); + block[0] = fsbfreq; + block[1] = fsbfreq >> 8; + + smbus_block_write(0x69, 0, 5, block); +} void mainboard_pre_raminit(void) { + #if CONFIG(BOARD_LENOVO_T410) hybrid_graphics_init(); + #elif CONFIG(BOARD_LENOVO_X201) + outb((inb(DEFAULT_GPIOBASE | 0x3a) & ~0x2) | 0x20, + DEFAULT_GPIOBASE | 0x3a); + outb(0x50, 0x15ec); + outb(inb(0x15ee) & 0x70, 0x15ee); + + set_fsb_frequency(); } void mainboard_get_spd_map(u8 *spd_addrmap) { spd_addrmap[0] = 0x50; + #if CONFIG(BOARD_LENOVO_T410) spd_addrmap[2] = 0x52; + #elif CONFIG(BOARD_LENOVO_X201) + spd_addrmap[2] = 0x51; + #endif } diff --git a/src/mainboard/lenovo/x201/board_info.txt b/src/mainboard/lenovo/t410/variants/t410/board_info.txt similarity index 75% copy from src/mainboard/lenovo/x201/board_info.txt copy to src/mainboard/lenovo/t410/variants/t410/board_info.txt index b33cbaf..f27808b 100644 --- a/src/mainboard/lenovo/x201/board_info.txt +++ b/src/mainboard/lenovo/t410/variants/t410/board_info.txt @@ -1,5 +1,5 @@ Category: laptop -ROM package: SOIC-8 +ROM package: SOIC-8 / WSON-8 ROM protocol: SPI ROM socketed: n Flashrom support: n diff --git a/src/mainboard/lenovo/t410/data.vbt b/src/mainboard/lenovo/t410/variants/t410/data.vbt similarity index 100% rename from src/mainboard/lenovo/t410/data.vbt rename to src/mainboard/lenovo/t410/variants/t410/data.vbt Binary files differ diff --git a/src/mainboard/lenovo/t410/devicetree.cb b/src/mainboard/lenovo/t410/variants/t410/devicetree.cb similarity index 100% rename from src/mainboard/lenovo/t410/devicetree.cb rename to src/mainboard/lenovo/t410/variants/t410/devicetree.cb diff --git a/src/mainboard/lenovo/t410/gpio.c b/src/mainboard/lenovo/t410/variants/t410/gpio.c similarity index 100% rename from src/mainboard/lenovo/t410/gpio.c rename to src/mainboard/lenovo/t410/variants/t410/gpio.c diff --git a/src/mainboard/lenovo/x201/board_info.txt b/src/mainboard/lenovo/t410/variants/x201/board_info.txt similarity index 81% rename from src/mainboard/lenovo/x201/board_info.txt rename to src/mainboard/lenovo/t410/variants/x201/board_info.txt index b33cbaf..7eb5a66 100644 --- a/src/mainboard/lenovo/x201/board_info.txt +++ b/src/mainboard/lenovo/t410/variants/x201/board_info.txt @@ -2,5 +2,5 @@ ROM package: SOIC-8 ROM protocol: SPI ROM socketed: n -Flashrom support: n +Flashrom support: y Release year: 2010 diff --git a/src/mainboard/lenovo/x201/data.vbt b/src/mainboard/lenovo/t410/variants/x201/data.vbt similarity index 100% rename from src/mainboard/lenovo/x201/data.vbt rename to src/mainboard/lenovo/t410/variants/x201/data.vbt Binary files differ diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/t410/variants/x201/devicetree.cb similarity index 100% rename from src/mainboard/lenovo/x201/devicetree.cb rename to src/mainboard/lenovo/t410/variants/x201/devicetree.cb diff --git a/src/mainboard/lenovo/x201/gpio.c b/src/mainboard/lenovo/t410/variants/x201/gpio.c similarity index 100% rename from src/mainboard/lenovo/x201/gpio.c rename to src/mainboard/lenovo/t410/variants/x201/gpio.c diff --git a/src/mainboard/lenovo/x201/Kconfig b/src/mainboard/lenovo/x201/Kconfig deleted file mode 100644 index e40c0d3..0000000 --- a/src/mainboard/lenovo/x201/Kconfig +++ /dev/null @@ -1,71 +0,0 @@ -if BOARD_LENOVO_X201 - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select SYSTEM_TYPE_LAPTOP - select NORTHBRIDGE_INTEL_NEHALEM - select SOUTHBRIDGE_INTEL_IBEXPEAK - select EC_LENOVO_PMH7 - select EC_LENOVO_H8 - select NO_UART_ON_SUPERIO - select HAVE_OPTION_TABLE - select HAVE_CMOS_DEFAULT - select BOARD_ROMSIZE_KB_8192 - select HAVE_ACPI_TABLES - select INTEL_INT15 - select HAVE_ACPI_RESUME - select MAINBOARD_HAS_LIBGFXINIT - select SUPERIO_NSC_PC87382 - select DRIVERS_LENOVO_WACOM - select MAINBOARD_HAS_LPC_TPM - select MAINBOARD_HAS_TPM1 - select INTEL_GMA_HAVE_VBT - select MAINBOARD_USES_IFD_GBE_REGION - select H8_HAS_BAT_TRESHOLDS_IMPL - -config VBOOT - select VBOOT_VBNV_CMOS - select GBB_FLAG_DISABLE_LID_SHUTDOWN - select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC - select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC - select GBB_FLAG_DISABLE_FWMP - select HAS_RECOVERY_MRC_CACHE - -config VBOOT_SLOTS_RW_A - default y - -config VBOOT_VBNV_OFFSET - hex - default 0x2a - -config FMDFILE - string - default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT - -config MAINBOARD_DIR - string - default lenovo/x201 - -config MAINBOARD_PART_NUMBER - string - default "ThinkPad X201" - -config USBDEBUG_HCD_INDEX - int - default 2 - -config DRAM_RESET_GATE_GPIO - int - default 10 - -config MAX_CPUS - int - default 4 - -# Without the Intel ME's EFFS partition some PCIe devices (like the USB and SATA -# controllers) don't work as expected -config ME_CLEANER_ARGS - string - default "-S -w EFFS" - -endif diff --git a/src/mainboard/lenovo/x201/Kconfig.name b/src/mainboard/lenovo/x201/Kconfig.name deleted file mode 100644 index a73d224..0000000 --- a/src/mainboard/lenovo/x201/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_LENOVO_X201 - bool "ThinkPad X201 / X201i / X201s / X201t" diff --git a/src/mainboard/lenovo/x201/Makefile.inc b/src/mainboard/lenovo/x201/Makefile.inc deleted file mode 100644 index 548beff..0000000 --- a/src/mainboard/lenovo/x201/Makefile.inc +++ /dev/null @@ -1,24 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007-2008 coresystems GmbH -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -bootblock-y += early_init.c - -smm-y += dock.c -smm-y += smihandler.c -romstage-y += dock.c -ramstage-y += dock.c -romstage-y += gpio.c - -ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/lenovo/x201/acpi/dock.asl b/src/mainboard/lenovo/x201/acpi/dock.asl deleted file mode 100644 index 2bba821..0000000 --- a/src/mainboard/lenovo/x201/acpi/dock.asl +++ /dev/null @@ -1,72 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Scope (\_SB) -{ - Device(DOCK) - { - Name(_HID, "ACPI0003") - Name(_UID, 0x00) - Name(_PCL, Package() { \_SB } ) - - Method(_DCK, 1, NotSerialized) - { - if (Arg0) { - /* connect dock */ - Store (1, \GP28) - Store (1, \_SB.PCI0.LPCB.EC.DKR1) - Store (1, \_SB.PCI0.LPCB.EC.DKR2) - Store (1, \_SB.PCI0.LPCB.EC.DKR3) - } else { - /* disconnect dock */ - Store (0, \GP28) - Store (0, \_SB.PCI0.LPCB.EC.DKR1) - Store (0, \_SB.PCI0.LPCB.EC.DKR2) - Store (0, \_SB.PCI0.LPCB.EC.DKR3) - } - Xor(Arg0, \_SB.PCI0.LPCB.EC.DKR1, Local0) - Return (Local0) - } - - Method(_STA, 0, NotSerialized) - { - Return (\_SB.PCI0.LPCB.EC.DKR1) - } - } -} - -Scope(\_SB.PCI0.LPCB.EC) -{ - Method(_Q18, 0, NotSerialized) - { - Notify(\_SB.DOCK, 3) - } - - Method(_Q45, 0, NotSerialized) - { - Notify(\_SB.DOCK, 3) - } - - Method(_Q58, 0, NotSerialized) - { - Notify(\_SB.DOCK, 0) - } - - Method(_Q37, 0, NotSerialized) - { - Notify(\_SB.DOCK, 0) - } -} diff --git a/src/mainboard/lenovo/x201/acpi/ec.asl b/src/mainboard/lenovo/x201/acpi/ec.asl deleted file mode 100644 index 411a0ec..0000000 --- a/src/mainboard/lenovo/x201/acpi/ec.asl +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <ec/lenovo/h8/acpi/ec.asl> - -Scope(\_SB.PCI0.LPCB.EC) -{ -} - -#define H8_BAT_THRESHOLDS_BIT7 -#include <ec/lenovo/h8/acpi/thinkpad_bat_thresholds_24.asl> diff --git a/src/mainboard/lenovo/x201/acpi/gpe.asl b/src/mainboard/lenovo/x201/acpi/gpe.asl deleted file mode 100644 index 5c900ca..0000000 --- a/src/mainboard/lenovo/x201/acpi/gpe.asl +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Scope (\_GPE) -{ - Method(_L18, 0, NotSerialized) - { - /* Read EC register to clear wake status */ - Store(\_SB.PCI0.LPCB.EC.WAKE, Local0) - /* So that we don't get a warning that Local0 is unused. */ - Increment (Local0) - } -} diff --git a/src/mainboard/lenovo/x201/acpi/platform.asl b/src/mainboard/lenovo/x201/acpi/platform.asl deleted file mode 100644 index bcd6de6..0000000 --- a/src/mainboard/lenovo/x201/acpi/platform.asl +++ /dev/null @@ -1,132 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* The _PTS method (Prepare To Sleep) is called before the OS is - * entering a sleep state. The sleep state number is passed in Arg0 - */ - -Method(_PTS,1) -{ - \_SB.PCI0.LPCB.EC.MUTE(1) - \_SB.PCI0.LPCB.EC.USBP(0) - \_SB.PCI0.LPCB.EC.RADI(0) -} - -/* The _WAK method is called on system wakeup */ - -Method(_WAK,1) -{ - /* ME may not be up yet. */ - Store (0, \_TZ.MEB1) - Store (0, \_TZ.MEB2) - - /* Wake the HKEY to init BT/WWAN */ - \_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0) - - /* Not implemented. */ - Return(Package(){0,0}) -} - -Method(UCMS, 1, Serialized) -{ - Switch(ToInteger(Arg0)) - { - Case (0x0c) /* Turn on ThinkLight */ - { - \_SB.PCI0.LPCB.EC.LGHT(1) - } - Case (0x0d) /* Turn off ThinkLight */ - { - \_SB.PCI0.LPCB.EC.LGHT(0) - } - } -} - -/* System Bus */ - -Scope(\_SB) -{ - /* This method is placed on the top level, so we can make sure it's the - * first executed _INI method. - */ - Method(_INI, 0) - { - /* The DTS data in NVS is probably not up to date. - * Update temperature values and make sure AP thermal - * interrupts can happen - */ - - /* TRAP(71) */ /* TODO */ - - /* Determine the Operating System and save the value in OSYS. - * We have to do this in order to be able to work around - * certain windows bugs. - * - * OSYS value | Operating System - * -----------+------------------ - * 2000 | Windows 2000 - * 2001 | Windows XP(+SP1) - * 2002 | Windows XP SP2 - * 2006 | Windows Vista - * ???? | Windows 7 - */ - - /* Let's assume we're running at least Windows 2000 */ - Store (2000, OSYS) - - If (CondRefOf(_OSI)) { - If (_OSI("Windows 2001")) { - Store (2001, OSYS) - } - - If (_OSI("Windows 2001 SP1")) { - Store (2001, OSYS) - } - - If (_OSI("Windows 2001 SP2")) { - Store (2002, OSYS) - } - - If (_OSI("Windows 2001.1")) { - Store (2001, OSYS) - } - - If (_OSI("Windows 2001.1 SP1")) { - Store (2001, OSYS) - } - - If (_OSI("Windows 2006")) { - Store (2006, OSYS) - } - - If (_OSI("Windows 2006.1")) { - Store (2006, OSYS) - } - - If (_OSI("Windows 2006 SP1")) { - Store (2006, OSYS) - } - - If (_OSI("Windows 2009")) { - Store (2009, OSYS) - } - - If (_OSI("Windows 2012")) { - Store (2012, OSYS) - } - } - } -} diff --git a/src/mainboard/lenovo/x201/acpi/superio.asl b/src/mainboard/lenovo/x201/acpi/superio.asl deleted file mode 100644 index f2b35ba..0000000 --- a/src/mainboard/lenovo/x201/acpi/superio.asl +++ /dev/null @@ -1 +0,0 @@ -#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/lenovo/x201/acpi_tables.c b/src/mainboard/lenovo/x201/acpi_tables.c deleted file mode 100644 index 6fd47d7..0000000 --- a/src/mainboard/lenovo/x201/acpi_tables.c +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2013 Vladimir Serbinenko <phcoder(a)gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <southbridge/intel/ibexpeak/nvs.h> -#include "thermal.h" - -static void acpi_update_thermal_table(global_nvs_t *gnvs) -{ - gnvs->tcrt = CRITICAL_TEMPERATURE; - gnvs->tpsv = PASSIVE_TEMPERATURE; -} - -void acpi_create_gnvs(global_nvs_t * gnvs) -{ - acpi_update_thermal_table(gnvs); -} diff --git a/src/mainboard/lenovo/x201/cmos.default b/src/mainboard/lenovo/x201/cmos.default deleted file mode 100644 index 2cf484f..0000000 --- a/src/mainboard/lenovo/x201/cmos.default +++ /dev/null @@ -1,17 +0,0 @@ -boot_option=Fallback -debug_level=Debug -power_on_after_fail=Disable -nmi=Enable -volume=0x3 -first_battery=Primary -bluetooth=Enable -wwan=Enable -wlan=Enable -touchpad=Enable -trackpoint=Enable -fn_ctrl_swap=Disable -sticky_fn=Disable -power_management_beeps=Enable -low_battery_beep=Enable -sata_mode=AHCI -usb_always_on=Disable diff --git a/src/mainboard/lenovo/x201/cmos.layout b/src/mainboard/lenovo/x201/cmos.layout deleted file mode 100644 index 990db6d..0000000 --- a/src/mainboard/lenovo/x201/cmos.layout +++ /dev/null @@ -1,128 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007-2008 coresystems GmbH -## Copyright (C) 2013 Vladimir Serbinenko -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -# ----------------------------------------------------------------- -entries - -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused - -# ----------------------------------------------------------------- -# RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? - -# ----------------------------------------------------------------- -# coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused - -#400 8 r 0 reserved for century byte - -# coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail - -# coreboot config options: EC -411 1 e 8 first_battery -412 1 e 1 bluetooth -413 1 e 1 wwan -414 1 e 1 touchpad -415 1 e 1 wlan -416 1 e 1 trackpoint -417 1 e 1 fn_ctrl_swap -418 1 e 1 sticky_fn -419 1 e 1 power_management_beeps -420 1 e 1 low_battery_beep -421 1 e 9 sata_mode -422 2 e 11 usb_always_on -#423 1 r 1 unused - -# coreboot config options: northbridge -424 3 e 10 gfx_uma_size -#427 5 r 0 unused -432 8 h 0 volume - -# VBOOT -448 128 r 0 vbnv - -# coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved - -# ----------------------------------------------------------------- - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 Secondary -8 1 Primary -9 0 AHCI -9 1 Compatible -10 0 32M -10 1 48M -10 2 64M -10 3 128M -10 5 96M -10 6 160M -11 0 Disable -11 1 AC and battery -11 2 AC only - -# ----------------------------------------------------------------- -checksums - -checksum 392 415 984 diff --git a/src/mainboard/lenovo/x201/dock.c b/src/mainboard/lenovo/x201/dock.c deleted file mode 100644 index 58510ce..0000000 --- a/src/mainboard/lenovo/x201/dock.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> - * Copyright (C) 2013 Vladimir Serbinenko <phcoder(a)gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <device/device.h> -#include "dock.h" -#include <southbridge/intel/common/gpio.h> -#include <ec/lenovo/h8/h8.h> -#include <ec/acpi/ec.h> - -void init_dock(void) -{ - if (dock_present()) { - printk(BIOS_DEBUG, "dock is connected\n"); - dock_connect(); - } else - printk(BIOS_DEBUG, "dock is not connected\n"); -} - -void dock_connect(void) -{ - ec_set_bit(0x02, 0); - ec_set_bit(0x1a, 0); - ec_set_bit(0xfe, 4); - - set_gpio(28, GPIO_LEVEL_HIGH); -} - -void dock_disconnect(void) -{ - ec_clr_bit(0x02, 0); - ec_clr_bit(0x1a, 0); - ec_clr_bit(0xfe, 4); - - set_gpio(28, GPIO_LEVEL_LOW); -} - -int dock_present(void) -{ - const int dock_id_gpio[] = { 3, 4, 5, -1}; - - return get_gpios(dock_id_gpio) != 7; -} diff --git a/src/mainboard/lenovo/x201/dock.h b/src/mainboard/lenovo/x201/dock.h deleted file mode 100644 index 6a08d81..0000000 --- a/src/mainboard/lenovo/x201/dock.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef THINKPAD_X201_DOCK_H -#define THINKPAD_X201_DOCK_H -void init_dock(void); -void dock_connect(void); -void dock_disconnect(void); -int dock_present(void); -#endif diff --git a/src/mainboard/lenovo/x201/dsdt.asl b/src/mainboard/lenovo/x201/dsdt.asl deleted file mode 100644 index 9d0204e..0000000 --- a/src/mainboard/lenovo/x201/dsdt.asl +++ /dev/null @@ -1,94 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define THINKPAD_EC_GPE 17 -#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB -#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB -#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 -#define EC_LENOVO_H8_ME_WORKAROUND 1 - -#include <arch/acpi.h> -DefinitionBlock( - "dsdt.aml", - "DSDT", - 0x02, /* DSDT revision: ACPI v2.0 and up */ - OEM_ID, - ACPI_TABLE_CREATOR, - 0x20130325 /* OEM revision */ -) -{ - #include <southbridge/intel/common/acpi/platform.asl> - - /* Some generic macros */ - #include "acpi/platform.asl" - - /* global NVS and variables */ - #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> - - /* General Purpose Events */ - #include "acpi/gpe.asl" - - #include <cpu/intel/common/acpi/cpu.asl> - - Scope (\_SB) { - Device (PCI0) - { - #include <northbridge/intel/nehalem/acpi/nehalem.asl> - #include <southbridge/intel/bd82x6x/acpi/pch.asl> - - #include <drivers/intel/gma/acpi/default_brightness_levels.asl> - } - Device (UNCR) - { - Name (_BBN, 0xFF) - Name (RID, 0x00) - Name (_HID, EisaId ("PNP0A03")) - Name (_CRS, ResourceTemplate () - { - WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0x0000, /* Granularity */ - 0x00FF, /* Range Minimum */ - 0x00FF, /* Range Maximum */ - 0x0000, /* Translation Offset */ - 0x0001, /* Length */ - ,, ) - }) - Device (SAD) - { - Name (_ADR, 0x01) - Name (RID, 0x00) - OperationRegion (SADC, PCI_Config, 0x00, 0x0100) - Field (SADC, DWordAcc, NoLock, Preserve) - { - Offset (0x40), - PAM0, 8, - PAM1, 8, - PAM2, 8, - PAM3, 8, - PAM4, 8, - PAM5, 8, - PAM6, 8 - } - } - } - } - - /* Chipset specific sleep states */ - #include <southbridge/intel/common/acpi/sleepstates.asl> - - /* Dock support code */ - #include "acpi/dock.asl" -} diff --git a/src/mainboard/lenovo/x201/early_init.c b/src/mainboard/lenovo/x201/early_init.c deleted file mode 100644 index 7383381..0000000 --- a/src/mainboard/lenovo/x201/early_init.c +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> - * Copyright (C) 2013 Vladimir Serbinenko <phcoder(a)gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <bootblock_common.h> -#include <ec/acpi/ec.h> - -void bootblock_mainboard_early_init(void) -{ - /* Enable USB Power. We need to do it early for usbdebug to work. */ - ec_set_bit(0x3b, 4); -} diff --git a/src/mainboard/lenovo/x201/gma-mainboard.ads b/src/mainboard/lenovo/x201/gma-mainboard.ads deleted file mode 100644 index 9c2a3cb..0000000 --- a/src/mainboard/lenovo/x201/gma-mainboard.ads +++ /dev/null @@ -1,30 +0,0 @@ --- --- This file is part of the coreboot project. --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- - -with HW.GFX.GMA; -with HW.GFX.GMA.Display_Probing; - -use HW.GFX.GMA; -use HW.GFX.GMA.Display_Probing; - -private package GMA.Mainboard is - - ports : constant Port_List := - (DP2, -- DP++ connector on the dock - HDMI2, - Analog, - Internal, - others => Disabled); - -end GMA.Mainboard; diff --git a/src/mainboard/lenovo/x201/hda_verb.c b/src/mainboard/lenovo/x201/hda_verb.c deleted file mode 100644 index 820e2c5..0000000 --- a/src/mainboard/lenovo/x201/hda_verb.c +++ /dev/null @@ -1,77 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Vladimir Serbinenko. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License, - * or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/azalia_device.h> - -const u32 cim_verb_data[] = { - /* coreboot specific header */ - 0x14F15069, /* Codec Vendor / Device ID: Conexant CX20585 */ - 0x17AA2155, /* Subsystem ID */ - 0x0000000B, /* Number of 4 dword sets */ - - /* NID 0x01: Subsystem ID. */ - AZALIA_SUBVENDOR(0x0, 0x17AA2155), - - /* NID 0x19: Headphone jack. */ - AZALIA_PIN_CFG(0x0, 0x19, 0x042140F0), - - /* NID 0x1A: Dock mic jack. */ - AZALIA_PIN_CFG(0x0, 0x1A, 0x61A190F0), - - /* NID 0x1B: Mic jack. */ - AZALIA_PIN_CFG(0x0, 0x1B, 0x04A190F0), - - /* NID 0x1C: Dock headphone jack. */ - AZALIA_PIN_CFG(0x0, 0x1C, 0x612140F0), - - /* NID 0x1D: EAPD detect. */ - AZALIA_PIN_CFG(0x0, 0x1D, 0x601700F0), - - /* NID 0x1E */ - AZALIA_PIN_CFG(0x0, 0x1E, 0x40F001F0), - - /* NID 0x1F */ - AZALIA_PIN_CFG(0x0, 0x1F, 0x901701F0), - - /* NID 0x20 */ - AZALIA_PIN_CFG(0x0, 0x20, 0x40F001F0), - - /* NID 0x22 */ - AZALIA_PIN_CFG(0x0, 0x22, 0x40F001F0), - - /* NID 0x23: Internal mic boost volume. */ - AZALIA_PIN_CFG(0x0, 0x23, 0x90A601F0), - - 0x80862804, /* Codec Vendor / Device ID: Intel Ibexpeak HDMI. */ - 0x17aa21b5, /* Subsystem ID */ - 0x00000004, /* Number of 4 dword sets */ - - /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x17aa21b5 */ - AZALIA_SUBVENDOR(0x3, 0x17AA21B5), - - /* NID 0x04. */ - AZALIA_PIN_CFG(0x3, 0x04, 0x58560010), - - /* NID 0x05. */ - AZALIA_PIN_CFG(0x3, 0x05, 0x18560020), - - /* NID 0x06. */ - AZALIA_PIN_CFG(0x3, 0x06, 0x58560030), -}; - -const u32 pc_beep_verbs[0] = {}; - -AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c deleted file mode 100644 index a403237..0000000 --- a/src/mainboard/lenovo/x201/mainboard.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> - * Copyright (C) 2013 Vladimir Serbinenko <phcoder(a)gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/device.h> -#include <device/pci_ops.h> -#include <ec/acpi/ec.h> -#include <northbridge/intel/nehalem/nehalem.h> -#include <southbridge/intel/bd82x6x/pch.h> -#include "dock.h" -#include <drivers/intel/gma/int15.h> -#include <cpu/x86/lapic.h> -#include <drivers/lenovo/lenovo.h> - -static void fill_ssdt(struct device *device) -{ - drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB", 0); -} - -static void mainboard_enable(struct device *dev) -{ - dev->ops->acpi_fill_ssdt_generator = fill_ssdt; - - /* If we're resuming from suspend, blink suspend LED */ - if (acpi_is_wakeup_s3()) - ec_write(0x0c, 0xc7); - - install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, - GMA_INT15_PANEL_FIT_DEFAULT, - GMA_INT15_BOOT_DISPLAY_LFP, 2); - - init_dock(); -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c deleted file mode 100644 index 99875ed..0000000 --- a/src/mainboard/lenovo/x201/romstage.c +++ /dev/null @@ -1,70 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> - * Copyright (C) 2013 Vladimir Serbinenko <phcoder(a)gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <arch/io.h> -#include <device/pci_ops.h> -#include <ec/acpi/ec.h> - -#include <southbridge/intel/ibexpeak/pch.h> -#include <northbridge/intel/nehalem/nehalem.h> - -const struct southbridge_usb_port mainboard_usb_ports[] = { - /* Enabled, Current table lookup index, OC map */ - { 1, IF1_557, 0 }, - { 1, IF1_55F, 1 }, - { 1, IF1_74B, 3 }, - { 1, IF1_74B, 3 }, - { 1, IF1_557, 3 }, - { 1, IF1_14B, 3 }, - { 1, IF1_74B, 3 }, - { 1, IF1_74B, 3 }, - { 1, IF1_74B, 4 }, - { 1, IF1_74B, 5 }, - { 1, IF1_55F, 7 }, - { 1, IF1_55F, 7 }, - { 1, IF1_557, 7 }, - { 1, IF1_55F, 7 }, -}; - -static void set_fsb_frequency(void) -{ - u8 block[5]; - u16 fsbfreq = 62879; - smbus_block_read(0x69, 0, 5, block); - block[0] = fsbfreq; - block[1] = fsbfreq >> 8; - - smbus_block_write(0x69, 0, 5, block); -} - -void mainboard_pre_raminit(void) -{ - outb((inb(DEFAULT_GPIOBASE | 0x3a) & ~0x2) | 0x20, - DEFAULT_GPIOBASE | 0x3a); - outb(0x50, 0x15ec); - outb(inb(0x15ee) & 0x70, 0x15ee); - - set_fsb_frequency(); -} - -void mainboard_get_spd_map(u8 *spd_addrmap) -{ - spd_addrmap[0] = 0x50; - spd_addrmap[2] = 0x51; -} diff --git a/src/mainboard/lenovo/x201/smihandler.c b/src/mainboard/lenovo/x201/smihandler.c deleted file mode 100644 index 4ba10b4..0000000 --- a/src/mainboard/lenovo/x201/smihandler.c +++ /dev/null @@ -1,110 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <console/console.h> -#include <cpu/x86/smm.h> -#include <southbridge/intel/ibexpeak/nvs.h> -#include <southbridge/intel/common/pmutil.h> -#include <northbridge/intel/nehalem/nehalem.h> -#include <ec/acpi/ec.h> -#include <ec/lenovo/h8/h8.h> -#include <delay.h> -#include "dock.h" - -#define GPE_EC_SCI 1 -#define GPE_EC_WAKE 13 - -static void mainboard_smi_handle_ec_sci(void) -{ - u8 status = inb(EC_SC); - u8 event; - - if (!(status & EC_SCI_EVT)) - return; - - event = ec_query(); - printk(BIOS_DEBUG, "EC event %02x\n", event); - - switch (event) { - case 0x18: - /* Fn-F9 key */ - case 0x27: - /* Power loss */ - case 0x50: - /* Undock Key */ - ec_clr_bit(0x03, 2); - dock_disconnect(); - break; - case 0x37: - case 0x58: - /* Dock Event */ - ec_clr_bit(0x03, 2); - udelay(250000); - dock_connect(); - ec_set_bit(0x03, 2); - /* set dock LED to indicate status */ - ec_write(0x0c, 0x09); - ec_write(0x0c, 0x88); - break; - default: - break; - } -} - -void mainboard_smi_gpi(u32 gpi_sts) -{ - if (gpi_sts & (1 << GPE_EC_SCI)) - mainboard_smi_handle_ec_sci(); -} - -int mainboard_smi_apmc(u8 data) -{ - switch (data) { - case APM_CNT_ACPI_ENABLE: - /* use 0x1600/0x1604 to prevent races with userspace */ - ec_set_ports(0x1604, 0x1600); - /* route H8SCI to SCI */ - gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SCI); - /* discard all events, and enable attention */ - ec_write(0x80, 0x01); - break; - case APM_CNT_ACPI_DISABLE: - /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't - provide a EC query function */ - ec_set_ports(0x66, 0x62); - /* route H8SCI# to SMI */ - gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SMI); - /* discard all events, and enable attention */ - ec_write(0x80, 0x01); - break; - default: - break; - } - return 0; -} - -void mainboard_smi_sleep(u8 slp_typ) -{ - if (slp_typ == 3) { - u8 ec_wake = ec_read(0x32); - /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ - if (ec_wake & 0x14) { - /* Redirect EC WAKE GPE to SCI. */ - gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI); - } - } -} diff --git a/src/mainboard/lenovo/x201/thermal.h b/src/mainboard/lenovo/x201/thermal.h deleted file mode 100644 index 72953fd..0000000 --- a/src/mainboard/lenovo/x201/thermal.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko - * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> - * Copyright (C) 2017 James Ye <jye836(a)gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_THERMAL_H -#define MAINBOARD_THERMAL_H - -/* Temperature which OS will shutdown at */ -#define CRITICAL_TEMPERATURE 100 - -/* Temperature which OS will throttle CPU */ -#define PASSIVE_TEMPERATURE 90 - -#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/x201/vboot-rwa.fmd b/src/mainboard/lenovo/x201/vboot-rwa.fmd deleted file mode 100644 index 0d1aa5d..0000000 --- a/src/mainboard/lenovo/x201/vboot-rwa.fmd +++ /dev/null @@ -1,30 +0,0 @@ -FLASH@0xff800000 0x800000 { - SI_ALL@0x0 0x500000 { - SI_DESC@0x0 0x1000 - SI_GBE@0x1000 0x2000 - SI_ME@0x3000 0x4ed000 - } - SI_BIOS@0x500000 0x300000 { - RW_SECTION_A 0x180000 { - VBLOCK_A 0x10000 - FW_MAIN_A(CBFS) - RW_FWID_A 0x40 - } - UNIFIED_MRC_CACHE 0x20000 { - RECOVERY_MRC_CACHE 0x10000 - RW_MRC_CACHE 0x10000 - } - RW_VPD(PRESERVE) 0x1000 - SMMSTORE(PRESERVE) 0x40000 - WP_RO { - RO_VPD(PRESERVE) 0x1000 - RO_SECTION { - FMAP 0x800 - RO_FRID 0x40 - RO_PADDING 0x7c0 - GBB 0x1e000 - COREBOOT(CBFS) - } - } - } -} -- To view, visit https://review.coreboot.org/c/coreboot/+/36871 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icfa1818812347ceb4e2de5cc4a3130537a4e13e7 Gerrit-Change-Number: 36871 Gerrit-PatchSet: 1 Gerrit-Owner: Maccraft123 <maccraft123mc(a)gmail.com> Gerrit-MessageType: newchange

5 36

Change in coreboot[master]: [NOTFORMERGE]mb/*/*: Drop BINARYPI_LEGACY_WRAPPER boards
by Arthur Heymans (Code Review) 07 Aug '23

07 Aug '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37076 ) Change subject: [NOTFORMERGE]mb/*/*: Drop BINARYPI_LEGACY_WRAPPER boards ...................................................................... [NOTFORMERGE]mb/*/*: Drop BINARYPI_LEGACY_WRAPPER boards Change-Id: Ia3ffc6ef36bc42f58515dfb2674633c167c732fd Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- D src/mainboard/amd/bettong/BiosCallOuts.c D src/mainboard/amd/bettong/BiosCallOuts.h D src/mainboard/amd/bettong/Kconfig D src/mainboard/amd/bettong/Kconfig.name D src/mainboard/amd/bettong/Makefile.inc D src/mainboard/amd/bettong/OemCustomize.c D src/mainboard/amd/bettong/README D src/mainboard/amd/bettong/acpi/carrizo_fch.asl D src/mainboard/amd/bettong/acpi/gpe.asl D src/mainboard/amd/bettong/acpi/mainboard.asl D src/mainboard/amd/bettong/acpi/routing.asl D src/mainboard/amd/bettong/acpi/sleep.asl D src/mainboard/amd/bettong/acpi/usb_oc.asl D src/mainboard/amd/bettong/acpi_tables.c D src/mainboard/amd/bettong/board_info.txt D src/mainboard/amd/bettong/boardid.c D src/mainboard/amd/bettong/cmos.layout D src/mainboard/amd/bettong/devicetree.cb D src/mainboard/amd/bettong/dsdt.asl D src/mainboard/amd/bettong/fchec.c D src/mainboard/amd/bettong/irq_tables.c D src/mainboard/amd/bettong/mainboard.c D src/mainboard/amd/bettong/mptable.c D src/mainboard/amd/bettong/romstage.c D src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c D src/mainboard/amd/db-ft3b-lc/Kconfig D src/mainboard/amd/db-ft3b-lc/Kconfig.name D src/mainboard/amd/db-ft3b-lc/Makefile.inc D src/mainboard/amd/db-ft3b-lc/Memphis_MEM4G16D3EABG.spd.hex D src/mainboard/amd/db-ft3b-lc/OemCustomize.c D src/mainboard/amd/db-ft3b-lc/acpi/gpe.asl D src/mainboard/amd/db-ft3b-lc/acpi/ide.asl D src/mainboard/amd/db-ft3b-lc/acpi/mainboard.asl D src/mainboard/amd/db-ft3b-lc/acpi/routing.asl D src/mainboard/amd/db-ft3b-lc/acpi/si.asl D src/mainboard/amd/db-ft3b-lc/acpi/sleep.asl D src/mainboard/amd/db-ft3b-lc/acpi/thermal.asl D src/mainboard/amd/db-ft3b-lc/acpi/usb_oc.asl D src/mainboard/amd/db-ft3b-lc/acpi_tables.c D src/mainboard/amd/db-ft3b-lc/board_info.txt D src/mainboard/amd/db-ft3b-lc/cmos.layout D src/mainboard/amd/db-ft3b-lc/devicetree.cb D src/mainboard/amd/db-ft3b-lc/dsdt.asl D src/mainboard/amd/db-ft3b-lc/irq_tables.c D src/mainboard/amd/db-ft3b-lc/mainboard.c D src/mainboard/amd/db-ft3b-lc/mptable.c D src/mainboard/amd/db-ft3b-lc/romstage.c D src/mainboard/amd/lamar/BiosCallOuts.c D src/mainboard/amd/lamar/Kconfig D src/mainboard/amd/lamar/Kconfig.name D src/mainboard/amd/lamar/Makefile.inc D src/mainboard/amd/lamar/OemCustomize.c D src/mainboard/amd/lamar/acpi/gpe.asl D src/mainboard/amd/lamar/acpi/mainboard.asl D src/mainboard/amd/lamar/acpi/routing.asl D src/mainboard/amd/lamar/acpi/si.asl D src/mainboard/amd/lamar/acpi/sleep.asl D src/mainboard/amd/lamar/acpi/thermal.asl D src/mainboard/amd/lamar/acpi/usb_oc.asl D src/mainboard/amd/lamar/acpi_tables.c D src/mainboard/amd/lamar/board_info.txt D src/mainboard/amd/lamar/cmos.layout D src/mainboard/amd/lamar/devicetree.cb D src/mainboard/amd/lamar/dsdt.asl D src/mainboard/amd/lamar/irq_tables.c D src/mainboard/amd/lamar/mainboard.c D src/mainboard/amd/lamar/mptable.c D src/mainboard/amd/lamar/romstage.c D src/mainboard/amd/olivehillplus/BiosCallOuts.c D src/mainboard/amd/olivehillplus/Kconfig D src/mainboard/amd/olivehillplus/Kconfig.name D src/mainboard/amd/olivehillplus/Makefile.inc D src/mainboard/amd/olivehillplus/OemCustomize.c D src/mainboard/amd/olivehillplus/acpi/gpe.asl D src/mainboard/amd/olivehillplus/acpi/ide.asl D src/mainboard/amd/olivehillplus/acpi/mainboard.asl D src/mainboard/amd/olivehillplus/acpi/routing.asl D src/mainboard/amd/olivehillplus/acpi/si.asl D src/mainboard/amd/olivehillplus/acpi/sleep.asl D src/mainboard/amd/olivehillplus/acpi/thermal.asl D src/mainboard/amd/olivehillplus/acpi/usb_oc.asl D src/mainboard/amd/olivehillplus/acpi_tables.c D src/mainboard/amd/olivehillplus/board_info.txt D src/mainboard/amd/olivehillplus/cmos.layout D src/mainboard/amd/olivehillplus/devicetree.cb D src/mainboard/amd/olivehillplus/dsdt.asl D src/mainboard/amd/olivehillplus/irq_tables.c D src/mainboard/amd/olivehillplus/mainboard.c D src/mainboard/amd/olivehillplus/mptable.c D src/mainboard/amd/olivehillplus/romstage.c D src/mainboard/bap/ode_e21XX/BAP_Q7_1066.spd.hex D src/mainboard/bap/ode_e21XX/BAP_Q7_1333.spd.hex D src/mainboard/bap/ode_e21XX/BAP_Q7_800.spd.hex D src/mainboard/bap/ode_e21XX/BiosCallOuts.c D src/mainboard/bap/ode_e21XX/Kconfig D src/mainboard/bap/ode_e21XX/Kconfig.name D src/mainboard/bap/ode_e21XX/Makefile.inc D src/mainboard/bap/ode_e21XX/OemCustomize.c D src/mainboard/bap/ode_e21XX/acpi/gpe.asl D src/mainboard/bap/ode_e21XX/acpi/ide.asl D src/mainboard/bap/ode_e21XX/acpi/mainboard.asl D src/mainboard/bap/ode_e21XX/acpi/routing.asl D src/mainboard/bap/ode_e21XX/acpi/si.asl D src/mainboard/bap/ode_e21XX/acpi/sleep.asl D src/mainboard/bap/ode_e21XX/acpi/superio.asl D src/mainboard/bap/ode_e21XX/acpi/thermal.asl D src/mainboard/bap/ode_e21XX/acpi/usb_oc.asl D src/mainboard/bap/ode_e21XX/acpi_tables.c D src/mainboard/bap/ode_e21XX/board_info.txt D src/mainboard/bap/ode_e21XX/cmos.layout D src/mainboard/bap/ode_e21XX/devicetree.cb D src/mainboard/bap/ode_e21XX/dsdt.asl D src/mainboard/bap/ode_e21XX/irq_tables.c D src/mainboard/bap/ode_e21XX/mainboard.c D src/mainboard/bap/ode_e21XX/mptable.c D src/mainboard/bap/ode_e21XX/romstage.c D src/mainboard/pcengines/apu2/BiosCallOuts.c D src/mainboard/pcengines/apu2/Kconfig D src/mainboard/pcengines/apu2/Kconfig.name D src/mainboard/pcengines/apu2/Makefile.inc D src/mainboard/pcengines/apu2/OemCustomize.c D src/mainboard/pcengines/apu2/acpi/gpe.asl D src/mainboard/pcengines/apu2/acpi/mainboard.asl D src/mainboard/pcengines/apu2/acpi/routing.asl D src/mainboard/pcengines/apu2/acpi/si.asl D src/mainboard/pcengines/apu2/acpi/sleep.asl D src/mainboard/pcengines/apu2/acpi/usb_oc.asl D src/mainboard/pcengines/apu2/acpi_tables.c D src/mainboard/pcengines/apu2/board_info.txt D src/mainboard/pcengines/apu2/cmos.layout D src/mainboard/pcengines/apu2/dsdt.asl D src/mainboard/pcengines/apu2/gpio_ftns.c D src/mainboard/pcengines/apu2/gpio_ftns.h D src/mainboard/pcengines/apu2/irq_tables.c D src/mainboard/pcengines/apu2/mainboard.c D src/mainboard/pcengines/apu2/mptable.c D src/mainboard/pcengines/apu2/romstage.c D src/mainboard/pcengines/apu2/spd/HYNIX-2G-1333.spd.hex D src/mainboard/pcengines/apu2/spd/HYNIX-4G-1333-ECC.spd.hex D src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb D src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb D src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb D src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb 143 files changed, 0 insertions(+), 12,816 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/37076/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/37076 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia3ffc6ef36bc42f58515dfb2674633c167c732fd Gerrit-Change-Number: 37076 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-MessageType: newchange

2 1

Change in coreboot[master]: mb/google/octopus: test
by Regan Chang (Code Review) 07 Aug '23

07 Aug '23

Regan Chang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37268 ) Change subject: mb/google/octopus: test ...................................................................... mb/google/octopus: test Create new variant for Lick . Nothing is changed in the variant files. Signed-off-by: Regan Chang <regan.chang(a)lcfc.corp-partner.google.com> Change-Id: I6b1a79b022a0c698174dd08f3c11769a4fd6833c --- A compile.status M src/mainboard/google/octopus/Kconfig M src/mainboard/google/octopus/Kconfig.name A src/mainboard/google/octopus/variants/lick/Makefile.inc A src/mainboard/google/octopus/variants/lick/gpio.c A src/mainboard/google/octopus/variants/lick/include/variant/acpi/dptf.asl A src/mainboard/google/octopus/variants/lick/include/variant/ec.h A src/mainboard/google/octopus/variants/lick/include/variant/gpio.h A src/mainboard/google/octopus/variants/lick/mainboard.c A src/mainboard/google/octopus/variants/lick/overridetree.cb A src/mainboard/google/octopus/variants/lick/variant.c 11 files changed, 408 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/37268/1 diff --git a/compile.status b/compile.status new file mode 100644 index 0000000..74bb638 --- /dev/null +++ b/compile.status @@ -0,0 +1 @@ +failed diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig index 65a641b..f97b66d 100644 --- a/src/mainboard/google/octopus/Kconfig +++ b/src/mainboard/google/octopus/Kconfig @@ -63,6 +63,7 @@ default "octopus" if BOARD_GOOGLE_OCTOPUS default "garg" if BOARD_GOOGLE_GARG default "dood" if BOARD_GOOGLE_DOOD + default "lick" if BOARD_GOOGLE_LICK config DEVICETREE string @@ -85,6 +86,7 @@ default "Octopus" if BOARD_GOOGLE_OCTOPUS default "Garg" if BOARD_GOOGLE_GARG default "Dood" if BOARD_GOOGLE_DOOD + default "Lick" if BOARD_GOOGLE_LICK config MAINBOARD_FAMILY string @@ -119,6 +121,7 @@ default y if BOARD_GOOGLE_OCTOPUS default y if BOARD_GOOGLE_PHASER default y if BOARD_GOOGLE_YORP + default y if BOARD_GOOGLE_LICK config DRAM_PART_IN_CBI_BOARD_ID_MIN int @@ -129,5 +132,6 @@ default 3 if BOARD_GOOGLE_BOBBA default 1 if BOARD_GOOGLE_MEEP default 255 if BOARD_GOOGLE_OCTOPUS + default 2 if BOARD_GOOGLE_LICK endif # BOARD_GOOGLE_OCTOPUS diff --git a/src/mainboard/google/octopus/Kconfig.name b/src/mainboard/google/octopus/Kconfig.name index 8a8d339..b1f589d 100644 --- a/src/mainboard/google/octopus/Kconfig.name +++ b/src/mainboard/google/octopus/Kconfig.name @@ -64,3 +64,9 @@ select BASEBOARD_OCTOPUS_LAPTOP select BOARD_GOOGLE_BASEBOARD_OCTOPUS select NHLT_DA7219 if INCLUDE_NHLT_BLOBS + +config BOARD_GOOGLE_LICK + bool "-> Lick" + select BASEBOARD_OCTOPUS_LAPTOP + select BOARD_GOOGLE_BASEBOARD_OCTOPUS + select NHLT_DA7219 if INCLUDE_NHLT_BLOBS diff --git a/src/mainboard/google/octopus/variants/lick/Makefile.inc b/src/mainboard/google/octopus/variants/lick/Makefile.inc new file mode 100644 index 0000000..37270eb --- /dev/null +++ b/src/mainboard/google/octopus/variants/lick/Makefile.inc @@ -0,0 +1,5 @@ +bootblock-y += gpio.c + +ramstage-y += variant.c +ramstage-y += gpio.c +ramstage-y += mainboard.c diff --git a/src/mainboard/google/octopus/variants/lick/gpio.c b/src/mainboard/google/octopus/variants/lick/gpio.c new file mode 100644 index 0000000..281bde0 --- /dev/null +++ b/src/mainboard/google/octopus/variants/lick/gpio.c @@ -0,0 +1,90 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <boardid.h> +#include <gpio.h> +#include <soc/gpio.h> +#include <ec/google/chromeec/ec.h> + +#define SKU_UNKNOWN 0xFFFFFFFF + +static const struct pad_config default_override_table[] = { + PAD_NC(GPIO_52, UP_20K), + PAD_NC(GPIO_53, UP_20K), + PAD_NC(GPIO_67, UP_20K), + PAD_NC(GPIO_117, UP_20K), + PAD_NC(GPIO_143, UP_20K), + + /* EN_PP3300_TOUCHSCREEN */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0, + DISPUPD), + + PAD_NC(GPIO_161, DN_20K), + + PAD_NC(GPIO_213, DN_20K), + PAD_NC(GPIO_214, DN_20K), +}; + +static const struct pad_config sku1_default_override_table[] = { + /* disable I2C7 SCL and SDA */ + PAD_NC(GPIO_114, UP_20K), /* LPSS_I2C7_SDA */ + PAD_NC(GPIO_115, UP_20K), /* LPSS_I2C7_SCL */ + + PAD_NC(GPIO_52, UP_20K), + PAD_NC(GPIO_53, UP_20K), + PAD_NC(GPIO_67, UP_20K), + PAD_NC(GPIO_117, UP_20K), + PAD_NC(GPIO_143, UP_20K), + + /* EN_PP3300_TOUCHSCREEN */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0, + DISPUPD), + + PAD_NC(GPIO_161, DN_20K), + + /* EN_PP3300_WLAN_L */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_178, 0, DEEP, NONE, Tx0RxDCRx0, + DISPUPD), + + PAD_NC(GPIO_213, DN_20K), + PAD_NC(GPIO_214, DN_20K), +}; + +bool no_touchscreen_sku(uint32_t sku_id) +{ + if ((sku_id == 1) || (sku_id == 6)) + return true; + else + return false; +} + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + const struct pad_config *c; + uint32_t sku_id = SKU_UNKNOWN; + + google_chromeec_cbi_get_sku_id(&sku_id); + if (no_touchscreen_sku(sku_id)) { + c = sku1_default_override_table; + *num = ARRAY_SIZE(sku1_default_override_table); + } else { + c = default_override_table; + *num = ARRAY_SIZE(default_override_table); + } + + return c; +} diff --git a/src/mainboard/google/octopus/variants/lick/include/variant/acpi/dptf.asl b/src/mainboard/google/octopus/variants/lick/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..cc17d56 --- /dev/null +++ b/src/mainboard/google/octopus/variants/lick/include/variant/acpi/dptf.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/acpi/dptf.asl> diff --git a/src/mainboard/google/octopus/variants/lick/include/variant/ec.h b/src/mainboard/google/octopus/variants/lick/include/variant/ec.h new file mode 100644 index 0000000..16f931b --- /dev/null +++ b/src/mainboard/google/octopus/variants/lick/include/variant/ec.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/octopus/variants/lick/include/variant/gpio.h b/src/mainboard/google/octopus/variants/lick/include/variant/gpio.h new file mode 100644 index 0000000..1fd1e11 --- /dev/null +++ b/src/mainboard/google/octopus/variants/lick/include/variant/gpio.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <baseboard/gpio.h> + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/octopus/variants/lick/mainboard.c b/src/mainboard/google/octopus/variants/lick/mainboard.c new file mode 100644 index 0000000..2d44830 --- /dev/null +++ b/src/mainboard/google/octopus/variants/lick/mainboard.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <boardid.h> +#include <ec/google/chromeec/ec.h> +#include <sar.h> + +const char *get_wifi_sar_cbfs_filename(void) +{ + const char *filename = NULL; + uint32_t sku_id; + + if (google_chromeec_cbi_get_sku_id(&sku_id)) + return NULL; + + if (sku_id == 5) + filename = "wifi_sar-laser.hex"; + + return filename; +} diff --git a/src/mainboard/google/octopus/variants/lick/overridetree.cb b/src/mainboard/google/octopus/variants/lick/overridetree.cb new file mode 100644 index 0000000..625c2a6 --- /dev/null +++ b/src/mainboard/google/octopus/variants/lick/overridetree.cb @@ -0,0 +1,176 @@ +chip soc/intel/apollolake + + # EMMC Tx CMD Delay + # Refer to EDS-Vol2-16.32. + # [14:8] steps of delay for DDR mode, each 125ps. + # [6:0] steps of delay for SDR mode, each 125ps. + register "emmc_tx_cmd_cntl" = "0x505" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-16.33. + # [14:8] steps of delay for HS400, each 125ps. + # [6:0] steps of delay for SDR104/HS200, each 125ps. + register "emmc_tx_data_cntl1" = "0x0b0c" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-16.34. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_tx_data_cntl2" = "0x1c282929" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-16.35. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_rx_cmd_data_cntl1" = "0x00181b1b" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-16.37. + # [17:16] stands for Rx Clock before Output Buffer + # [14:8] steps of delay for Auto Tuning Mode, each 125ps. + # [6:0] steps of delay for HS200, each 125ps. + register "emmc_rx_cmd_data_cntl2" = "0x10028" + + # EMMC Rx Strobe Delay + # Refer to EDS-Vol2-16.36. + # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps. + # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps. + register "emmc_rx_strobe_cntl" = "0x0b0b" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | Digitizer | + #| I2C5 | Audio | + #| I2C6 | Trackpad | + #| I2C7 | Touchscreen | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 66, + .fall_time_ns = 90, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 104, + .fall_time_ns = 52, + }, + .i2c[6] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 66, + .fall_time_ns = 90, + .data_hold_time_ns = 350, + }, + .i2c[7] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 76, + .fall_time_ns = 164, + }, + }" + + device domain 0 on + device pci 16.0 on + chip drivers/i2c/hid + register "generic.hid" = ""WCOM50C1"" + register "generic.desc" = ""WCOM Digitizer"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_139_IRQ)" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" + register "generic.reset_delay_ms" = "20" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x1" + device i2c 0x9 on end + end + end # - I2C 0 + device pci 17.1 on + chip drivers/i2c/da7219 + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_137_IRQ)" + register "btn_cfg" = "50" + register "mic_det_thr" = "500" + register "jack_ins_deb" = "20" + register "jack_det_rate" = ""32ms_64ms"" + register "jack_rem_deb" = "1" + register "a_d_btn_thr" = "0xa" + register "d_b_btn_thr" = "0x16" + register "b_c_btn_thr" = "0x21" + register "c_mic_btn_thr" = "0x3e" + register "btn_avg" = "4" + register "adc_1bit_rpt" = "1" + register "micbias_lvl" = "2600" + register "mic_amp_in_sel" = ""diff"" + device i2c 1a on end + end + end # - I2C 5 + device pci 17.2 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPIO_135_IRQ)" + register "wake" = "GPE0_DW3_27" + register "probed" = "1" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPIO_135_IRQ)" + register "generic.wake" = "GPE0_DW3_27" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 0x2c on end + end + end # - I2C 6 + device pci 17.3 on + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" + register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" + register "reset_delay_ms" = "20" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" + register "enable_delay_ms" = "1" + register "has_power_resource" = "1" + device i2c 10 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""SYTS7817"" + register "generic.desc" = ""Synaptics Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" + register "generic.reset_delay_ms" = "45" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 20 on end + end + chip drivers/i2c/generic + register "hid" = ""RAYD0001"" + register "desc" = ""Raydium Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" + register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" + register "reset_delay_ms" = "1" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" + register "enable_delay_ms" = "50" + register "has_power_resource" = "1" + device i2c 39 on end + end + end # - I2C 7 + end +end diff --git a/src/mainboard/google/octopus/variants/lick/variant.c b/src/mainboard/google/octopus/variants/lick/variant.c new file mode 100644 index 0000000..aeefda5 --- /dev/null +++ b/src/mainboard/google/octopus/variants/lick/variant.c @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/variants.h> +#include <soc/pci_devs.h> +#include <ec/google/chromeec/ec.h> + +#define SKU_UNKNOWN 0xFFFFFFFF + +void variant_update_devtree(struct device *dev) +{ + uint32_t sku_id = SKU_UNKNOWN; + struct device *touchscreen_i2c_host; + + touchscreen_i2c_host = pcidev_path_on_root(PCH_DEVFN_I2C7); + + if (touchscreen_i2c_host == NULL) + return; + + /* SKU ID 1, 6 does not have a touchscreen device, hence disable it. */ + google_chromeec_cbi_get_sku_id(&sku_id); + if (no_touchscreen_sku(sku_id)) + touchscreen_i2c_host->enabled = 0; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/37268 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b1a79b022a0c698174dd08f3c11769a4fd6833c Gerrit-Change-Number: 37268 Gerrit-PatchSet: 1 Gerrit-Owner: Regan Chang <regan.chang(a)lcfc.corp-partner.google.com> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: arch/x86: Move generic functions from postcar_loader.c to stage_loader.c
by Subrata Banik (Code Review) 07 Aug '23

07 Aug '23

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34751 ) Change subject: arch/x86: Move generic functions from postcar_loader.c to stage_loader.c ...................................................................... arch/x86: Move generic functions from postcar_loader.c to stage_loader.c This patch moves few generic functions (finalize_load and stack_push) from postcar_loader.c to stage_loader.c file so that other callers can also use these functions. Change-Id: I4d2200d95e68c0eb01681b8f9b71b3d30d122c43 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/arch/x86/Makefile.inc A src/arch/x86/include/arch/stage_loader.h M src/arch/x86/postcar_loader.c A src/arch/x86/stage_loader.c 4 files changed, 62 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/34751/1 diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 32e0173..2fad75e 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -239,6 +239,7 @@ romstage-y += memset.c romstage-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c romstage-y += postcar_loader.c +romstage-y += stage_loader.c romstage-$(CONFIG_COLLECT_TIMESTAMPS_TSC) += timestamp.c romstage-$(CONFIG_ARCH_ROMSTAGE_X86_32) += walkcbfs.S diff --git a/src/arch/x86/include/arch/stage_loader.h b/src/arch/x86/include/arch/stage_loader.h new file mode 100644 index 0000000..23ac6e9 --- /dev/null +++ b/src/arch/x86/include/arch/stage_loader.h @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef STAGE_LOADER_H +#define STAGE_LOADER_H + +#include <arch/cpu.h> + +static inline void stack_push(struct postcar_frame *pcf, uint32_t val) +{ + uint32_t *ptr; + + pcf->stack -= sizeof(val); + ptr = (void *)pcf->stack; + *ptr = val; +} + +void finalize_load(uintptr_t *stack_top_ptr, uintptr_t stack_top); + +#endif /* STAGE_LOADER_H */ diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c index 35e139f..3f42298 100644 --- a/src/arch/x86/postcar_loader.c +++ b/src/arch/x86/postcar_loader.c @@ -13,7 +13,7 @@ * GNU General Public License for more details. */ -#include <arch/cpu.h> +#include <arch/stage_loader.h> #include <cbmem.h> #include <console/console.h> #include <cpu/cpu.h> @@ -25,15 +25,6 @@ #include <stage_cache.h> #include <timestamp.h> -static inline void stack_push(struct postcar_frame *pcf, uint32_t val) -{ - uint32_t *ptr; - - pcf->stack -= sizeof(val); - ptr = (void *)pcf->stack; - *ptr = val; -} - static void postcar_frame_prepare(struct postcar_frame *pcf) { msr_t msr; @@ -131,17 +122,6 @@ return (void *) pcf->stack; } -static void finalize_load(uintptr_t *stack_top_ptr, uintptr_t stack_top) -{ - *stack_top_ptr = stack_top; - /* - * Signal to rest of system that another update was made to the - * postcar program prior to running it. - */ - prog_segment_loaded((uintptr_t)stack_top_ptr, sizeof(uintptr_t), - SEG_FINAL); -} - static void load_postcar_cbfs(struct prog *prog, struct postcar_frame *pcf) { struct rmod_stage_load rsl = { diff --git a/src/arch/x86/stage_loader.c b/src/arch/x86/stage_loader.c new file mode 100644 index 0000000..ca6a987 --- /dev/null +++ b/src/arch/x86/stage_loader.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/stage_loader.h> +#include <stage_cache.h> + +void finalize_load(uintptr_t *stack_top_ptr, uintptr_t stack_top) +{ + *stack_top_ptr = stack_top; + /* + * Signal to rest of system that another update was made to the + * postcar program prior to running it. + */ + prog_segment_loaded((uintptr_t)stack_top_ptr, sizeof(uintptr_t), + SEG_FINAL); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/34751 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d2200d95e68c0eb01681b8f9b71b3d30d122c43 Gerrit-Change-Number: 34751 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

3 21

Change in coreboot[4.8_branch]: cpu/allwinner: Prepend the BOOT0 header to the bootblock.bin
by Arthur Heymans (Code Review) 07 Aug '23

07 Aug '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35401 ) Change subject: cpu/allwinner: Prepend the BOOT0 header to the bootblock.bin ...................................................................... cpu/allwinner: Prepend the BOOT0 header to the bootblock.bin Instead of prepending the BOOT0 header to the full coreboot.rom to create a new file called BOOT0, prepend to the bootblock.bin that gets included in BOOTBLOCK FMAP region. Change-Id: I974a6aaa1a340c6b26f78b9d038be0f580331831 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/allwinner/a10/Makefile.inc 1 file changed, 3 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/35401/1 diff --git a/src/cpu/allwinner/a10/Makefile.inc b/src/cpu/allwinner/a10/Makefile.inc index a6cd4b4..9f5f6ac 100644 --- a/src/cpu/allwinner/a10/Makefile.inc +++ b/src/cpu/allwinner/a10/Makefile.inc @@ -25,8 +25,6 @@ romstage-y += uart.c uart_console.c ramstage-y += uart.c uart_console.c -real-target: $(obj)/BOOT0 - get_bootblock_size= \ $(eval bb_s=$(shell $(CBFSTOOL) $(1) print | grep bootblocksize | \ sed 's/[^0-9 ]//g')) \ @@ -46,11 +44,11 @@ # under util/arm_boot_tools/mksunxiboot. The boot ROM will load at most 24KiB of # data to SRAM. The BOOT0 header takes 32 bytes, so bootblock is limited to # 24KiB - 32 bytes. -# TODO: make mksunxiboot take the bootblock size as a parameter # TODO: print an error if bootblock is too large (maybe place ROMSTAGE at the # exact offset needed to collide with the bootblock) # FIXME: A10 loads 24KiB. According to Oliver other chips load a little more # -$(obj)/BOOT0: $(obj)/coreboot.rom $(MKSUNXIBOOT) - @printf " BOOT0 $(subst $(obj)/,,$(^))\n" + +$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin $(MKSUNXIBOOT) + @printf " Prepending BOOT0 header $(subst $(obj)/,,$(^))\n" $(MKSUNXIBOOT) $(word 1, $^) $@ -- To view, visit https://review.coreboot.org/c/coreboot/+/35401 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.8_branch Gerrit-Change-Id: I974a6aaa1a340c6b26f78b9d038be0f580331831 Gerrit-Change-Number: 35401 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: configs: Build config to run nvramcui with seabios on qemu
by Name of user not set (Code Review) 07 Aug '23

07 Aug '23

Name of user not set #1002476 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35850 ) Change subject: configs: Build config to run nvramcui with seabios on qemu ...................................................................... configs: Build config to run nvramcui with seabios on qemu Provide additional build config to run nvramcui as a secondary payload with seabios on qemu. It resolves `Could not find Coreboot Option Table`. Fixes: https://ticket.coreboot.org/issues/97 Change-Id: Ifae854bdc0092276c85ca198a33f0003cc3c1d0b Signed-off-by: Himanshu Sahdev <himanshusah(a)hcl.com> --- A configs/config.emulation_qemu_x86_i440fx_nvramcui 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/35850/1 diff --git a/configs/config.emulation_qemu_x86_i440fx_nvramcui b/configs/config.emulation_qemu_x86_i440fx_nvramcui new file mode 100644 index 0000000..bccef90 --- /dev/null +++ b/configs/config.emulation_qemu_x86_i440fx_nvramcui @@ -0,0 +1,2 @@ +CONFIG_USE_OPTION_TABLE=y +CONFIG_NVRAMCUI_SECONDARY_PAYLOAD=y -- To view, visit https://review.coreboot.org/c/coreboot/+/35850 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifae854bdc0092276c85ca198a33f0003cc3c1d0b Gerrit-Change-Number: 35850 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1002476 Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: mainboard/google: Shim out Puff board
by Edward O'Callaghan (Code Review) 07 Aug '23

07 Aug '23

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36065 ) Change subject: mainboard/google: Shim out Puff board ...................................................................... mainboard/google: Shim out Puff board TODO: devicetree. Workout a way to fold this back into Hatch. Change-Id: Icc8b13471e6e0b8cf540c35c712089c3205a3497 Signed-off-by: Edward O'Callaghan <quasisec(a)chromium.org> --- A src/mainboard/google/puff/Kconfig A src/mainboard/google/puff/Kconfig.name A src/mainboard/google/puff/Makefile.inc A src/mainboard/google/puff/acpi_tables.c A src/mainboard/google/puff/board_info.txt A src/mainboard/google/puff/bootblock.c A src/mainboard/google/puff/chromeos-16MiB.fmd A src/mainboard/google/puff/chromeos.c A src/mainboard/google/puff/chromeos.fmd A src/mainboard/google/puff/dsdt.asl A src/mainboard/google/puff/ec.c A src/mainboard/google/puff/mainboard.asl A src/mainboard/google/puff/mainboard.c A src/mainboard/google/puff/ramstage.c A src/mainboard/google/puff/romstage.c A src/mainboard/google/puff/smihandler.c A src/mainboard/google/puff/variants/baseboard/Makefile.inc A src/mainboard/google/puff/variants/baseboard/devicetree.cb A src/mainboard/google/puff/variants/baseboard/gpio.c A src/mainboard/google/puff/variants/baseboard/include/baseboard/acpi/dptf.asl A src/mainboard/google/puff/variants/baseboard/include/baseboard/ec.h A src/mainboard/google/puff/variants/baseboard/include/baseboard/gpio.h A src/mainboard/google/puff/variants/baseboard/include/baseboard/variants.h A src/mainboard/google/puff/variants/baseboard/memory.c A src/mainboard/google/puff/variants/puff/Makefile.inc A src/mainboard/google/puff/variants/puff/gpio.c A src/mainboard/google/puff/variants/puff/include/variant/acpi/dptf.asl A src/mainboard/google/puff/variants/puff/include/variant/ec.h A src/mainboard/google/puff/variants/puff/include/variant/gpio.h A src/mainboard/google/puff/variants/puff/overridetree.cb 30 files changed, 2,186 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/36065/1 diff --git a/src/mainboard/google/puff/Kconfig b/src/mainboard/google/puff/Kconfig new file mode 100644 index 0000000..0c49d6a --- /dev/null +++ b/src/mainboard/google/puff/Kconfig @@ -0,0 +1,109 @@ + +config BOARD_GOOGLE_BASEBOARD_PUFF + def_bool n + select DRIVERS_GENERIC_GPIO_KEYS + select DRIVERS_GENERIC_MAX98357A + select DRIVERS_I2C_DA7219 + select DRIVERS_I2C_GENERIC + select DRIVERS_I2C_HID + select DRIVERS_I2C_SX9310 + select DRIVERS_SPI_ACPI + select DRIVERS_USB_ACPI + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_BOARDID + select EC_GOOGLE_CHROMEEC_ESPI + select GOOGLE_SMBIOS_MAINBOARD_VERSION + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_LPSS_UART_FOR_CONSOLE + select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_SPI_TPM_CR50 + select MAINBOARD_HAS_TPM2 + select MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE + select SOC_INTEL_COMETLAKE + select SYSTEM_TYPE_LAPTOP + +if BOARD_GOOGLE_BASEBOARD_PUFF + +config CHROMEOS + bool + default y + select EC_GOOGLE_CHROMEEC_SWITCHES + select GBB_FLAG_FORCE_DEV_SWITCH_ON + select GBB_FLAG_FORCE_DEV_BOOT_USB + select GBB_FLAG_FORCE_DEV_BOOT_LEGACY + select GBB_FLAG_FORCE_MANUAL_RECOVERY + select HAS_RECOVERY_MRC_CACHE + select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN + select VBOOT_LID_SWITCH + +config CHROMEOS_WIFI_SAR + bool "Enable SAR options for Chrome OS build" + depends on CHROMEOS + select DSAR_ENABLE + select GEO_SAR_ENABLE + select SAR_ENABLE + select USE_SAR + select WIFI_SAR_CBFS + +config DEVICETREE + string + default "variants/baseboard/devicetree.cb" + +config DIMM_MAX + int + default 2 + +config DIMM_SPD_SIZE + int + default 512 + +config DRIVER_TPM_SPI_BUS + default 0x1 + +config UART_FOR_CONSOLE + default 0 + +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos-16MiB.fmd" if BOARD_ROMSIZE_KB_16384 + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if BOARD_ROMSIZE_KB_32768 + +config MAINBOARD_DIR + string + default "google/puff" + +config MAINBOARD_FAMILY + string + default "Google_Puff" + +config MAINBOARD_PART_NUMBER + string + default "Puff" if BOARD_GOOGLE_PUFF + +config MAINBOARD_VENDOR + string + default "Google" + +config MAX_CPUS + int + default 8 + +config OVERRIDE_DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" + +config TPM_TIS_ACPI_INTERRUPT + int + default 53 # GPE0_DW1_21 (GPP_C21) + +config VARIANT_DIR + string + default "puff" if BOARD_GOOGLE_PUFF + +config VBOOT + select HAS_RECOVERY_MRC_CACHE + select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN + select VBOOT_LID_SWITCH + +endif # BOARD_GOOGLE_BASEBOARD_PUFF diff --git a/src/mainboard/google/puff/Kconfig.name b/src/mainboard/google/puff/Kconfig.name new file mode 100644 index 0000000..61c4e0f --- /dev/null +++ b/src/mainboard/google/puff/Kconfig.name @@ -0,0 +1,6 @@ +comment "Puff" + +config BOARD_GOOGLE_PUFF + bool "-> Puff" + select BOARD_GOOGLE_BASEBOARD_PUFF + select BOARD_ROMSIZE_KB_32768 diff --git a/src/mainboard/google/puff/Makefile.inc b/src/mainboard/google/puff/Makefile.inc new file mode 100644 index 0000000..adab446 --- /dev/null +++ b/src/mainboard/google/puff/Makefile.inc @@ -0,0 +1,34 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2018 Google LLC +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +bootblock-y += bootblock.c +bootblock-$(CONFIG_CHROMEOS) += chromeos.c + +ramstage-y += ramstage.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c +ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c + +romstage-y += romstage.c +romstage-$(CONFIG_CHROMEOS) += chromeos.c + +verstage-$(CONFIG_CHROMEOS) += chromeos.c +smm-y += smihandler.c + +subdirs-y += variants/baseboard +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include + +VARIANT_DIR:=$(call strip_quotes,$(CONFIG_VARIANT_DIR)) +subdirs-y += variants/$(VARIANT_DIR) +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/google/puff/acpi_tables.c b/src/mainboard/google/puff/acpi_tables.c new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/google/puff/acpi_tables.c diff --git a/src/mainboard/google/puff/board_info.txt b/src/mainboard/google/puff/board_info.txt new file mode 100644 index 0000000..1168548 --- /dev/null +++ b/src/mainboard/google/puff/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Puff +Category: desktop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/puff/bootblock.c b/src/mainboard/google/puff/bootblock.c new file mode 100644 index 0000000..15dfe93 --- /dev/null +++ b/src/mainboard/google/puff/bootblock.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/variants.h> +#include <bootblock_common.h> +#include <soc/gpio.h> + +static void early_config_gpio(void) +{ + const struct pad_config *variant_early_table; + size_t variant_gpios; + + variant_early_table = variant_early_gpio_table(&variant_gpios); + gpio_configure_pads(variant_early_table, variant_gpios); +} + +void bootblock_mainboard_init(void) +{ + early_config_gpio(); +} diff --git a/src/mainboard/google/puff/chromeos-16MiB.fmd b/src/mainboard/google/puff/chromeos-16MiB.fmd new file mode 100644 index 0000000..eb92bb0 --- /dev/null +++ b/src/mainboard/google/puff/chromeos-16MiB.fmd @@ -0,0 +1,43 @@ +FLASH@0xff000000 0x1000000 { + SI_ALL@0x0 0x400000 { + SI_DESC@0x0 0x1000 + SI_ME@0x1000 0x3ff000 + } + SI_BIOS@0x400000 0xc00000 { + RW_SECTION_A@0x0 0x368000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x357fc0 + RW_FWID_A@0x367fc0 0x40 + } + RW_SECTION_B@0x368000 0x368000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0x357fc0 + RW_FWID_B@0x367fc0 0x40 + } + RW_MISC@0x6D0000 0x30000 { + UNIFIED_MRC_CACHE@0x0 0x20000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + } + RW_ELOG(PRESERVE)@0x20000 0x4000 + RW_SHARED@0x24000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD(PRESERVE)@0x28000 0x2000 + RW_NVRAM(PRESERVE)@0x2a000 0x6000 + } + # RW_LEGACY needs to be minimum of 1MB + RW_LEGACY(CBFS)@0x700000 0x100000 + WP_RO@0x800000 0x400000 { + RO_VPD(PRESERVE)@0x0 0x4000 + RO_SECTION@0x4000 0x3fc000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0xef000 + COREBOOT(CBFS)@0xf0000 0x30c000 + } + } + } +} diff --git a/src/mainboard/google/puff/chromeos.c b/src/mainboard/google/puff/chromeos.c new file mode 100644 index 0000000..4119670 --- /dev/null +++ b/src/mainboard/google/puff/chromeos.c @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <baseboard/variants.h> +#include <boot/coreboot_tables.h> +#include <ec/google/chromeec/ec.h> +#include <gpio.h> +#include <variant/gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio chromeos_gpios[] = { + {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, + {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, + {-1, ACTIVE_HIGH, 0, "power"}, + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + {GPIO_EC_IN_RW, ACTIVE_HIGH, gpio_get(GPIO_EC_IN_RW), + "EC in RW"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); +} + +int get_write_protect_state(void) +{ + return gpio_get(GPIO_PCH_WP); +} + +void mainboard_chromeos_acpi_generate(void) +{ + const struct cros_gpio *cros_gpios; + size_t num_gpios = 0; + + cros_gpios = variant_cros_gpios(&num_gpios); + + chromeos_acpi_gpio_generate(cros_gpios, num_gpios); +} diff --git a/src/mainboard/google/puff/chromeos.fmd b/src/mainboard/google/puff/chromeos.fmd new file mode 100644 index 0000000..45dbc81 --- /dev/null +++ b/src/mainboard/google/puff/chromeos.fmd @@ -0,0 +1,47 @@ +FLASH@0xfe000000 0x2000000 { + SI_ALL@0x0 0x400000 { + SI_DESC@0x0 0x1000 + SI_ME@0x1000 0x3ff000 + } + SI_BIOS@0x400000 0x1c00000 { + # Place RW_LEGACY at the start of BIOS region such that the rest + # of BIOS regions start at 16MiB boundary. Since this is a 32MiB + # SPI flash only the top 16MiB actually gets memory mapped. + RW_LEGACY(CBFS)@0x0 0x1000000 + RW_SECTION_A@0x1000000 0x3e0000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x3cffc0 + RW_FWID_A@0x3dffc0 0x40 + } + RW_SECTION_B@0x13e0000 0x3e0000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0x3cffc0 + RW_FWID_B@0x3dffc0 0x40 + } + RW_MISC@0x17c0000 0x40000 { + UNIFIED_MRC_CACHE(PRESERVE)@0x0 0x30000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x20000 + } + RW_ELOG(PRESERVE)@0x30000 0x4000 + RW_SHARED@0x34000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD(PRESERVE)@0x38000 0x2000 + RW_NVRAM(PRESERVE)@0x3a000 0x6000 + } + # Make WP_RO region align with SPI vendor + # memory protected range specification. + WP_RO@0x1800000 0x400000 { + RO_VPD(PRESERVE)@0x0 0x4000 + RO_SECTION@0x4000 0x3fc000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0xef000 + COREBOOT(CBFS)@0xf0000 0x30c000 + } + } + } +} diff --git a/src/mainboard/google/puff/dsdt.asl b/src/mainboard/google/puff/dsdt.asl new file mode 100644 index 0000000..e2959a7 --- /dev/null +++ b/src/mainboard/google/puff/dsdt.asl @@ -0,0 +1,79 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <variant/ec.h> +#include <variant/gpio.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI v2.0 and up */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 /* OEM revision */ +) +{ + /* Some generic macros */ + #include <soc/intel/cannonlake/acpi/platform.asl> + + /* global NVS and variables */ + #include <soc/intel/cannonlake/acpi/globalnvs.asl> + + /* CPU */ + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/cannonlake/acpi/northbridge.asl> + #include <soc/intel/cannonlake/acpi/southbridge.asl> + } + + /* Mainboard hooks */ + #include "mainboard.asl" + } + +#if CONFIG(CHROMEOS) + /* Chrome OS specific */ + #include <vendorcode/google/chromeos/acpi/chromeos.asl> +#endif + + /* Chipset specific sleep states */ + #include <soc/intel/cannonlake/acpi/sleepstates.asl> + + /* Low power idle table */ + #include <soc/intel/cannonlake/acpi/lpit.asl> + + /* Chrome OS Embedded Controller */ + Scope (\_SB.PCI0.LPCB) + { + /* ACPI code for EC SuperIO functions */ + #include <ec/google/chromeec/acpi/superio.asl> + /* ACPI code for EC functions */ + #include <ec/google/chromeec/acpi/ec.asl> + } + + /* Dynamic Platform Thermal Framework */ + Scope (\_SB) + { + /* Per board variant specific definitions. */ + #include <variant/acpi/dptf.asl> + /* Include soc specific DPTF changes */ + #include <soc/intel/cannonlake/acpi/dptf.asl> + /* Include common dptf ASL files */ + #include <soc/intel/common/acpi/dptf/dptf.asl> + } +} diff --git a/src/mainboard/google/puff/ec.c b/src/mainboard/google/puff/ec.c new file mode 100644 index 0000000..9fb3d80 --- /dev/null +++ b/src/mainboard/google/puff/ec.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <ec/ec.h> +#include <ec/google/chromeec/ec.h> +#include <variant/ec.h> + +void mainboard_ec_init(void) +{ + const struct google_chromeec_event_info info = { + .log_events = MAINBOARD_EC_LOG_EVENTS, + .sci_events = MAINBOARD_EC_SCI_EVENTS, + .s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS, + .s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS, + .s0ix_wake_events = MAINBOARD_EC_S0IX_WAKE_EVENTS, + }; + + google_chromeec_events_init(&info, acpi_is_wakeup_s3()); +} diff --git a/src/mainboard/google/puff/mainboard.asl b/src/mainboard/google/puff/mainboard.asl new file mode 100644 index 0000000..dff1a75 --- /dev/null +++ b/src/mainboard/google/puff/mainboard.asl @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <intelblocks/gpio.h> + +Method (LOCL, 1, Serialized) +{ + For (Local0 = 0, Local0 < 5, Local0++) + { + \_SB.PCI0.CGPM (Local0, Arg0) + } +} + +/* + * Method called from _PTS prior to system sleep state entry + * Enables dynamic clock gating for all 5 GPIO communities + */ +Method (MPTS, 1, Serialized) +{ + LOCL (MISCCFG_ENABLE_GPIO_PM_CONFIG) +} + +/* + * Method called from _WAK prior to system sleep state wakeup + * Disables dynamic clock gating for all 5 GPIO communities + */ +Method (MWAK, 1, Serialized) +{ + LOCL (0) +} + +/* + * S0ix Entry/Exit Notifications + * Called from \_SB.LPID._DSM + */ +Method (MS0X, 1, Serialized) +{ + If (Arg0 == 1) { + /* S0ix Entry */ + LOCL (MISCCFG_ENABLE_GPIO_PM_CONFIG) + } Else { + /* S0ix Exit */ + LOCL (0) + } +} diff --git a/src/mainboard/google/puff/mainboard.c b/src/mainboard/google/puff/mainboard.c new file mode 100644 index 0000000..5761b08 --- /dev/null +++ b/src/mainboard/google/puff/mainboard.c @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/variants.h> +#include <boardid.h> +#include <console/console.h> +#include <ec/google/chromeec/ec.h> +#include <smbios.h> +#include <string.h> +#include <stdint.h> + +#define SKU_UNKNOWN 0xFFFFFFFF +#define SKU_MAX 255 + +uint32_t get_board_sku(void) +{ + static uint32_t sku_id = SKU_UNKNOWN; + + if (sku_id != SKU_UNKNOWN) + return sku_id; + + if (google_chromeec_cbi_get_sku_id(&sku_id)) + sku_id = SKU_UNKNOWN; + + return sku_id; +} + +const char *smbios_system_sku(void) +{ + static char sku_str[7]; /* sku{0..255} */ + uint32_t sku_id = get_board_sku(); + + if ((sku_id == SKU_UNKNOWN) || (sku_id > SKU_MAX)) { + printk(BIOS_ERR, "%s: Unexpected SKU ID %u\n", + __func__, sku_id); + return ""; + } + + snprintf(sku_str, sizeof(sku_str), "sku%u", sku_id); + + return sku_str; +} + +const char *smbios_mainboard_manufacturer(void) +{ + static char oem_name[32]; + static const char *manuf; + + if (manuf) + return manuf; + + if (google_chromeec_cbi_get_oem_name(&oem_name[0], + ARRAY_SIZE(oem_name)) < 0) { + printk(BIOS_INFO, "Couldn't obtain OEM name from CBI\n"); + manuf = CONFIG_MAINBOARD_SMBIOS_MANUFACTURER; + } else { + manuf = &oem_name[0]; + } + + return manuf; +} diff --git a/src/mainboard/google/puff/ramstage.c b/src/mainboard/google/puff/ramstage.c new file mode 100644 index 0000000..04e1bc1 --- /dev/null +++ b/src/mainboard/google/puff/ramstage.c @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <baseboard/variants.h> +#include <ec/ec.h> +#include <soc/gpio.h> +#include <soc/ramstage.h> +#include <variant/gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> + +void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ + const struct pad_config *base_table; + const struct pad_config *override_table; + size_t base_gpios; + size_t override_gpios; + + variant_devtree_update(); + base_table = base_gpio_table(&base_gpios); + override_table = override_gpio_table(&override_gpios); + + gpio_configure_pads_with_override(base_table, + base_gpios, + override_table, + override_gpios); +} + +void __weak variant_devtree_update(void) +{ + /* Override dev tree settings per board */ +} + +static void mainboard_enable(struct device *dev) +{ + mainboard_ec_init(); + + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/google/puff/romstage.c b/src/mainboard/google/puff/romstage.c new file mode 100644 index 0000000..7174a8c --- /dev/null +++ b/src/mainboard/google/puff/romstage.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/variants.h> +#include <soc/cnl_memcfg_init.h> +#include <soc/romstage.h> +#include <variant/gpio.h> +#include <spd_bin.h> + +/* + * GPIO_MEM_CH_SEL is set to 1 for single channel skus + * and 0 for dual channel skus. + */ +//#define GPIO_MEM_CH_SEL GPP_F2 + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + struct cnl_mb_cfg memcfg; + variant_memory_params(&memcfg); + + /* Read spd block to get memory config */ + struct spd_block blk = { + .addr_map = { 0x50, 0x52 }, + }; + + memcfg.dq_pins_interleaved = 1; + get_spd_smbus(&blk); + memcfg.spd[0].read_type = READ_SMBUS; + memcfg.spd[0].spd_spec.spd_smbus_address = (uintptr_t)blk.spd_array[0]; + memcfg.spd[1].read_type = READ_SMBUS; + memcfg.spd[1].spd_spec.spd_smbus_address = (uintptr_t)blk.spd_array[1]; + dump_spd_info(&blk); + + cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg); +} diff --git a/src/mainboard/google/puff/smihandler.c b/src/mainboard/google/puff/smihandler.c new file mode 100644 index 0000000..c7833e3 --- /dev/null +++ b/src/mainboard/google/puff/smihandler.c @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <baseboard/variants.h> +#include <cpu/x86/smm.h> +#include <ec/google/chromeec/ec.h> +#include <ec/google/chromeec/smm.h> +#include <elog.h> +#include <intelblocks/smihandler.h> +#include <variant/ec.h> + +void mainboard_smi_espi_handler(void) +{ + chromeec_smi_process_events(); +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + const struct pad_config *pads; + size_t num; + + pads = variant_sleep_gpio_table(slp_typ, &num); + gpio_configure_pads(pads, num); + + chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, + MAINBOARD_EC_S5_WAKE_EVENTS); +} + +int mainboard_smi_apmc(u8 apmc) +{ + chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, + MAINBOARD_EC_SMI_EVENTS); + return 0; +} + +void elog_gsmi_cb_mainboard_log_wake_source(void) +{ + google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | + MAINBOARD_EC_S0IX_WAKE_EVENTS); +} diff --git a/src/mainboard/google/puff/variants/baseboard/Makefile.inc b/src/mainboard/google/puff/variants/baseboard/Makefile.inc new file mode 100644 index 0000000..5d5695f --- /dev/null +++ b/src/mainboard/google/puff/variants/baseboard/Makefile.inc @@ -0,0 +1,25 @@ +## This file is part of the coreboot project. +## +## Copyright (C) 2018 Intel Corporation. +## Copyright 2019 Google LLC +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +bootblock-y += gpio.c + +romstage-y += gpio.c +romstage-y += memory.c + +ramstage-y += gpio.c + +verstage-y += gpio.c + +smm-y += gpio.c diff --git a/src/mainboard/google/puff/variants/baseboard/devicetree.cb b/src/mainboard/google/puff/variants/baseboard/devicetree.cb new file mode 100644 index 0000000..7382209 --- /dev/null +++ b/src/mainboard/google/puff/variants/baseboard/devicetree.cb @@ -0,0 +1,358 @@ +chip soc/intel/cannonlake + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + # DW1 is used by: + # - GPP_C1 - PCIE_14_WLAN_WAKE_ODL + # - GPP_C21 - H1_PCH_INT_ODL + register "gpe0_dw0" = "PMC_GPP_A" + register "gpe0_dw1" = "PMC_GPP_C" + register "gpe0_dw2" = "PMC_GPP_D" + + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + + # FSP configuration + register "InternalGfx" = "1" + register "SkipExtGfxScan" = "1" + register "SataSalpSupport" = "1" + register "SataMode" = "Sata_AHCI" + register "SataPortsEnable[1]" = "1" + register "SataPortsDevSlp[1]" = "1" + # Configure devslp pad reset to PLT_RST + register "SataPortsDevSlpResetConfig[1]" = "SataDevSlpPlatformReset" + register "satapwroptimize" = "1" + # Enable System Agent dynamic frequency + register "SaGv" = "SaGv_Enabled" + # Enable heci communication + register "HeciEnabled" = "0" + # Enable Speed Shift Technology support + register "speed_shift_enable" = "1" + # Enable S0ix + register "s0ix_enable" = "1" + # Enable DPTF + register "dptf_enable" = "1" + register "tdp_pl1_override" = "15" + register "tdp_pl2_override" = "64" + register "Device4Enable" = "1" + # Enable eDP device + register "DdiPortEdp" = "1" + # Enable HPD for DDI ports B/C + register "DdiPortBHpd" = "1" + register "DdiPortCHpd" = "1" + register "tcc_offset" = "10" # TCC of 90C + # Unlock GPIO pads + register "PchUnlockGpioPads" = "1" + # SD card WP pin confguration + register "ScsSdCardWpPinEnabled" = "0" + + # NOTE: if any variant wants to override this value, use the same format + # as register "common_soc_config.pch_thermal_trip" = "value", instead of + # putting it under register "common_soc_config" in overridetree.cb file. + register "common_soc_config.pch_thermal_trip" = "77" + + register "PmTimerDisabled" = "1" + + # VR Settings Configuration for 4 Domains + #+----------------+-------+-------+-------+-------+ + #| Domain/Setting | SA | IA | GTUS | GTS | + #+----------------+-------+-------+-------+-------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 5A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| IccMax | 6A | 70A | 31A | 31A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #| AcLoadline | 10.3 | 1.8 | 3.1 | 3.1 | + #| DcLoadline | 10.3 | 1.8 | 3.1 | 3.1 | + #+----------------+-------+-------+-------+-------+ + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(6), + .voltage_limit = 1520, + .ac_loadline = 1030, + .dc_loadline = 1030, + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(70), + .voltage_limit = 1520, + .ac_loadline = 180, + .dc_loadline = 180, + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(31), + .voltage_limit = 1520, + .ac_loadline = 310, + .dc_loadline = 310, + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(31), + .voltage_limit = 1520, + .ac_loadline = 310, + .dc_loadline = 310, + }" + + register "PchPmSlpS3MinAssert" = "2" # 50ms + register "PchPmSlpS4MinAssert" = "1" # 1s + register "PchPmSlpSusMinAssert" = "1" # 500ms + register "PchPmSlpAMinAssert" = "3" # 2s + + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 0 + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 1 + register "usb2_ports[2]" = "USB2_PORT_SHORT(OC3)" # Type-A Port 0 + register "usb2_ports[3]" = "USB2_PORT_LONG(OC3)" # Type-A Port 1 + register "usb2_ports[4]" = "USB2_PORT_EMPTY" + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # WWAN + register "usb2_ports[6]" = "USB2_PORT_LONG(OC_SKIP)" # Camera + register "usb2_ports[7]" = "USB2_PORT_EMPTY" + register "usb2_ports[8]" = "USB2_PORT_EMPTY" + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # BT + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 0 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 1 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port 0 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port 1 + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN + register "usb3_ports[5]" = "USB3_PORT_EMPTY" + + # Enable Root port 9(x4) for NVMe. + register "PcieRpEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + # RP 9 uses CLK SRC 1 + register "PcieClkSrcUsage[1]" = "8" + # ClkReq-to-ClkSrc mapping for CLK SRC 1 + register "PcieClkSrcClkReq[1]" = "1" + + # PCIe port 14 for M.2 E-key WLAN + register "PcieRpEnable[13]" = "1" + register "PcieRpLtrEnable[13]" = "1" + # RP 14 uses CLK SRC 3 + register "PcieClkSrcUsage[3]" = "13" + register "PcieClkSrcClkReq[3]" = "3" + + #Enable I2S Audio, SSP0, SSP1 and DMIC0, default DMIC1 N/A (by variants override) + register "PchHdaDspEnable" = "1" + register "PchHdaAudioLinkSsp0" = "1" + register "PchHdaAudioLinkSsp1" = "1" + register "PchHdaAudioLinkDmic0" = "1" + register "PchHdaAudioLinkDmic1" = "0" + + # GPIO PM programming + register "gpio_override_pm" = "1" + + # GPIO community PM configuration + # Disable dynamic clock gating; with bits 0-5 set in these registers, + # some short interrupt pulses were missed (esp. cr50 irq) + register "gpio_pm[COMM_0]" = "0" + register "gpio_pm[COMM_1]" = "0" + register "gpio_pm[COMM_2]" = "0" + register "gpio_pm[COMM_3]" = "0" + register "gpio_pm[COMM_4]" = "0" + + # chipset_lockdown configuration + # Use below format to override value in overridetree.cb if required + # format: + # register "common_soc_config.<variable_name>" = "value" + register "common_soc_config.chipset_lockdown" = CHIPSET_LOCKDOWN_COREBOOT + + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 off end # SA Thermal device + device pci 05.0 off end # SA IPU + device pci 12.0 on end # Thermal Subsystem + device pci 12.5 off end # UFS SCS + device pci 12.6 off end # GSPI #2 + device pci 14.0 on + chip drivers/usb/acpi + register "desc" = ""Root Hub"" + register "type" = "UPC_TYPE_HUB" + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""Left Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 2.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-C Port 1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 2.1 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-A Port"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 2.2 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-A Port 1"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device usb 2.3 on end + end + chip drivers/usb/acpi + register "desc" = ""WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.5 on end + end + chip drivers/usb/acpi + register "desc" = ""Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.6 on end + end + chip drivers/usb/acpi + register "desc" = ""Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C14)" + device usb 2.9 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 3.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-C Port 1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 3.1 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-A Port"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 3.2 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-A Port 1"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device usb 3.3 on end + end + chip drivers/usb/acpi + register "desc" = ""WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 3.4 on end + end + end + end + end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + chip drivers/intel/wifi + register "wake" = "GPE0_PME_B0" + device pci 14.3 on end # CNVi wifi + end + device pci 14.5 on end # SDCard + device pci 15.0 on end # I2C #0 + device pci 15.1 on end # I2C #1 + device pci 15.2 on end # I2C #2 + device pci 15.3 on end # I2C #3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 16.5 off end # Management Engine Interface 4 + device pci 17.0 on end # SATA + device pci 19.0 on end # I2C #4 + device pci 19.1 off end # I2C #5 + device pci 19.2 off end # UART #2 + device pci 1a.0 off end # eMMC + device pci 1c.0 off end # PCI Express Port 1 (USB) + device pci 1c.1 off end # PCI Express Port 2 (USB) + device pci 1c.2 off end # PCI Express Port 3 (USB) + device pci 1c.3 off end # PCI Express Port 4 (USB) + device pci 1c.4 off end # PCI Express Port 5 (USB) + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on end # PCI Express Port 9 (X4 NVME) + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1d.4 off end # PCI Express port 13 + device pci 1d.5 on + chip drivers/intel/wifi + register "wake" = "GPE0_DW1_01" + device pci 00.0 on end + end + end # PCI Express Port 14 (x4) + device pci 1e.0 on end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 on + chip drivers/spi/acpi + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "compat_string" = ""google,cr50"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C21_IRQ)" + device spi 0 on end + end + end # GSPI #0 + device pci 1e.3 on end # GSPI #1 + device pci 1f.0 on + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end # eSPI Interface + device pci 1f.1 on end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on + chip drivers/generic/max98357a + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H3)" + register "sdmode_delay" = "5" + device generic 0 on end + end + end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/google/puff/variants/baseboard/gpio.c b/src/mainboard/google/puff/variants/baseboard/gpio.c new file mode 100644 index 0000000..f8df447 --- /dev/null +++ b/src/mainboard/google/puff/variants/baseboard/gpio.c @@ -0,0 +1,445 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +static const struct pad_config gpio_table[] = { + /* A0 : SAR0_INT_ODL */ + PAD_CFG_GPI_INT(GPP_A0, NONE, PLTRST, LEVEL), + /* A1 : ESPI_IO0 */ + /* A2 : ESPI_IO1 */ + /* A3 : ESPI_IO2 */ + /* A4 : ESPI_IO3 */ + /* A5 : ESPI_CS# */ + /* A6 : SAR1_INT_ODL */ + PAD_CFG_GPI_INT(GPP_A6, NONE, PLTRST, LEVEL), + /* A7 : PP3300_SOC_A */ + PAD_NC(GPP_A7, NONE), + /* A8 : PEN_GARAGE_DET_L (wake) */ + PAD_CFG_GPI_SCI(GPP_A8, NONE, DEEP, EDGE_SINGLE, NONE), + /* A9 : ESPI_CLK */ + /* A10 : FPMCU_PCH_BOOT1 */ + PAD_CFG_GPO(GPP_A10, 0, DEEP), + /* A11 : PCH_SPI_FPMCU_CS_L */ + PAD_CFG_NF(GPP_A11, NONE, DEEP, NF2), + /* A12 : FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_A12, 1, DEEP), + /* A13 : SUSWARN_L */ + PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), + /* A14 : ESPI_RST_L */ + /* A15 : SUSACK_L */ + PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), + /* A16 : SD_1P8_SEL => NC */ + PAD_NC(GPP_A16, NONE), + /* A17 : EN_PP3300_SD_DX */ + PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), + /* A18 : EN_PP3300_WWAN */ + PAD_CFG_GPO(GPP_A18, 1, DEEP), + /* A19 : WWAN_RADIO_DISABLE_1V8_ODL */ + PAD_CFG_GPO(GPP_A19, 1, DEEP), + /* A20 : WLAN_INT_L */ + PAD_CFG_GPI_APIC(GPP_A20, NONE, PLTRST, LEVEL, INVERT), + /* A21 : TRACKPAD_INT_ODL */ + PAD_CFG_GPI_IRQ_WAKE(GPP_A21, NONE, DEEP, LEVEL, INVERT), + /* A22 : FPMCU_PCH_BOOT0 */ + PAD_CFG_GPO(GPP_A22, 0, DEEP), + /* A23 : FPMCU_PCH_INT_ODL */ + PAD_CFG_GPI_IRQ_WAKE(GPP_A23, NONE, PLTRST, LEVEL, INVERT), + + /* B0 : CORE_VID0 */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), + /* B1 : CORE_VID1 */ + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), + /* B2 : GPP_B2 ==> NC */ + PAD_NC(GPP_B2, NONE), + /* B3 : GPP_B3 ==> NC */ + PAD_NC(GPP_B3, NONE), + /* B4 : GPP_B4 ==> NC */ + PAD_NC(GPP_B4, NONE), + /* B5 : GPP_B5 ==> NC */ + PAD_NC(GPP_B5, NONE), + /* B6 : SRCCLKREQ1 */ + PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), + /* B7 : GPP_B7 ==> NC */ + PAD_NC(GPP_B7, NONE), + /* B8 : PCIE_14_WLAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), + /* B9 : GPP_B9 ==> NC */ + PAD_NC(GPP_B9, NONE), + /* B10 : GPP_B10 ==> NC */ + PAD_NC(GPP_B10, NONE), + /* B11 : EXT_PWR_GATE_L */ + PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), + /* B12 : SLP_S0_L */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + /* B13 : PLT_RST_L */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + /* B14 : GPP_B14_STRAP */ + PAD_NC(GPP_B14, NONE), + /* B15 : H1_SLAVE_SPI_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : H1_SLAVE_SPI_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : H1_SLAVE_SPI_MISO_R */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : H1_SLAVE_SPI_MOSI_R */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* B19 : Set to NF1 to match FSP setting it to NF1, i.e., GSPI1_CS0# */ + PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), + /* B20 : PCH_SPI_FPMCU_CLK_R */ + PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), + /* B21 : PCH_SPI_FPMCU_MISO */ + PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), + /* B22 : PCH_SPI_FPMCU_MOSI */ + PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1), + /* B23 : GPP_B23_STRAP */ + PAD_NC(GPP_B23, NONE), + + /* C0 : GPP_C0 => NC */ + PAD_NC(GPP_C0, NONE), + /* C1 : PCIE_14_WLAN_WAKE_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_C1, NONE, DEEP, EDGE_SINGLE), + /* C2 : GPP_C2 => NC */ + PAD_NC(GPP_C2, NONE), + /* C3 : WLAN_OFF_L */ + PAD_CFG_GPO(GPP_C3, 1, DEEP), + /* C4 : TOUCHSCREEN_DIS_L */ + PAD_CFG_GPO(GPP_C4, 1, DEEP), + /* C5 : GPP_C5 => NC */ + PAD_NC(GPP_C5, NONE), + /* C6 : PEN_PDCT_OD_L */ + PAD_NC(GPP_C6, NONE), + /* C7 : PEN_IRQ_OD_L */ + PAD_NC(GPP_C7, NONE), + /* C8 : UART_PCH_RX_DEBUG_TX */ + PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), + /* C9 : UART_PCH_TX_DEBUG_RX */ + PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), + /* C10 : GPP_10 ==> GPP_C10_TP */ + PAD_NC(GPP_C10, NONE), + /* C11 : GPP_11 ==> EN_FP_RAILS */ + PAD_CFG_GPO(GPP_C11, 1, DEEP), + /* C12 : GPP_C12 ==> NC */ + PAD_NC(GPP_C12, NONE), + /* C13 : EC_PCH_INT_L */ + PAD_CFG_GPI_APIC(GPP_C13, NONE, PLTRST, LEVEL, INVERT), + /* C14 : BT_DISABLE_L */ + PAD_CFG_GPO(GPP_C14, 1, DEEP), + /* C15 : WWAN_DPR_SAR_ODL + * + * TODO: Driver doesn't use this pin as of now. In case driver starts + * using this pin, expose this pin to driver. + */ + PAD_CFG_GPO(GPP_C15, 1, DEEP), + /* C16 : PCH_I2C_TRACKPAD_SDA */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + /* C17 : PCH_I2C_TRACKPAD_SCL */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + /* C18 : PCH_I2C_TOUCHSCREEN_SDA */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + /* C19 : PCH_I2C_TOUCHSCREEN_SCL */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + /* C20 : PCH_WP_OD */ + PAD_CFG_GPI(GPP_C20, NONE, DEEP), + /* C21 : H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C22 : EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_C22, NONE, DEEP), + /* C23 : WLAN_PE_RST# */ + PAD_CFG_GPO(GPP_C23, 1, DEEP), + + /* D0 : TP31 */ + PAD_NC(GPP_D0, NONE), + /* D1 : TP16 */ + PAD_NC(GPP_D1, NONE), + /* D2 : TP26 */ + PAD_NC(GPP_D2, NONE), + /* D3 : TP27 */ + PAD_NC(GPP_D3, NONE), + /* D4 : TP40 */ + PAD_NC(GPP_D4, NONE), + /* D5 : WWAN_CONFIG_0 */ + PAD_NC(GPP_D5, NONE), + /* D6 : WWAN_CONFIG_1 */ + PAD_NC(GPP_D6, NONE), + /* D7 : WWAN_CONFIG_2 */ + PAD_NC(GPP_D7, NONE), + /* D8 : WWAN_CONFIG_3 */ + PAD_NC(GPP_D8, NONE), + /* D9 : GPP_D9 ==> EN_PP3300_DX_TOUCHSCREEN */ + PAD_CFG_GPO(GPP_D9, 0, DEEP), + /* D10 : GPP_D10 ==> NC */ + PAD_NC(GPP_D10, NONE), + /* D11 : GPP_D11 ==> NC */ + PAD_NC(GPP_D11, NONE), + /* D12 : GPP_D12 */ + PAD_NC(GPP_D12, NONE), + /* D13 : ISH_UART_RX */ + PAD_NC(GPP_D13, NONE), + /* D14 : ISH_UART_TX */ + PAD_NC(GPP_D14, NONE), + /* D15 : TOUCHSCREEN_RST_L */ + PAD_CFG_GPO(GPP_D15, 0, DEEP), + /* D16 : USI_INT */ + PAD_CFG_GPI_APIC(GPP_D16, NONE, PLTRST, LEVEL, NONE), + /* D17 : PCH_HP_SDW_CLK */ + PAD_NC(GPP_D17, NONE), + /* D18 : PCH_HP_SDW_DAT */ + PAD_NC(GPP_D18, NONE), + /* D19 : DMIC_CLK_0_SNDW4_CLK */ + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), + /* D20 : DMIC_DATA_0_SNDW4_DATA */ + PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), + /* D21 : GPP_D21 ==> NC */ + PAD_NC(GPP_D21, NONE), + /* D22 : GPP_D22 ==> NC */ + PAD_NC(GPP_D22, NONE), + /* D23 : SPP_MCLK */ + PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), + + /* E0 : GPP_E0 ==> NC */ + PAD_NC(GPP_E0, NONE), + /* E1 : M2_SSD_PEDET */ + PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), + /* E2 : GPP_E2 ==> NC */ + PAD_NC(GPP_E2, NONE), + /* E3 : GPP_E3 ==> NC */ + PAD_NC(GPP_E3, NONE), + /* E4 : M2_SSD_PE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E4, NONE, DEEP), + /* E5 : SATA_DEVSLP1 */ + PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), + /* E6 : M2_SSD_RST_L */ + PAD_NC(GPP_E6, NONE), + /* E7 : GPP_E7 ==> NC */ + PAD_NC(GPP_E7, NONE), + /* E8 : GPP_E8 ==> NC */ + PAD_NC(GPP_E8, NONE), + /* E9 : GPP_E9 ==> NC */ + PAD_NC(GPP_E9, NONE), + /* E10 : GPP_E10 ==> NC */ + PAD_NC(GPP_E10, NONE), + /* E11 : USB_C_OC_OD USB_OC2 */ + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), + /* E12 : USB_A_OC_OD USB_OC3 */ + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), + /* E13 : USB_C0_DP_HPD */ + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), + /* E14 : DDI2_HPD_ODL */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + /* E15 : DDPD_HPD2 => NC */ + PAD_NC(GPP_E15, NONE), + /* E16 : DDPE_HPD2 => NC */ + PAD_NC(GPP_E16, NONE), + /* E17 : EDP_HPD */ + PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), + /* E18 : DDPB_CTRLCLK => NC */ + PAD_NC(GPP_E18, NONE), + /* E19 : GPP_E19_STRAP */ + PAD_CFG_GPI(GPP_E19, NONE, DEEP), + /* E20 : DDPC_CTRLCLK => NC */ + PAD_NC(GPP_E20, NONE), + /* E21 : GPP_E21_STRAP */ + PAD_CFG_GPI(GPP_E21, NONE, DEEP), + /* E22 : DDPD_CTRLCLK => NC */ + PAD_NC(GPP_E22, NONE), + /* E23 : GPP_E23_STRAP */ + PAD_NC(GPP_E23, NONE), + + /* F0 : GPIO_WWAN_WLAN_COEX3 */ + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), + /* F1 : WWAN_RESET_1V8_ODL */ + PAD_CFG_GPO(GPP_F1, 1, DEEP), + /* F2 : MEM_CH_SEL */ + PAD_CFG_GPI(GPP_F2, NONE, PLTRST), + /* F3 : GPP_F3 ==> NC */ + PAD_NC(GPP_F3, NONE), + /* F4 : CNV_BRI_DT */ + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), + /* F5 : CNV_BRI_RSP */ + PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), + /* F6 : CNV_RGI_DT */ + PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), + /* F7 : CNV_RGI_RSP */ + PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1), + /* F8 : UART_WWANTX_WLANRX_COEX1 */ + PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), + /* F9 : UART_WWANRX_WLANTX_COEX2 */ + PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), + /* F10 : GPP_F10 ==> NC */ + PAD_NC(GPP_F10, NONE), + /* F11 : PCH_MEM_STRAP2 */ + PAD_CFG_GPI(GPP_F11, NONE, PLTRST), + /* F12 : GPP_F12 ==> NC */ + PAD_NC(GPP_F12, NONE), + /* F13 : GPP_F13 ==> NC */ + PAD_NC(GPP_F13, NONE), + /* F14 : GPP_F14 ==> NC */ + PAD_NC(GPP_F14, NONE), + /* F15 : GPP_F15 ==> NC */ + PAD_NC(GPP_F15, NONE), + /* F16 : GPP_F16 ==> NC */ + PAD_NC(GPP_F16, NONE), + /* F17 : GPP_F17 ==> NC */ + PAD_NC(GPP_F17, NONE), + /* F18 : GPP_F18 ==> NC */ + PAD_NC(GPP_F18, NONE), + /* F19 : GPP_F19 ==> NC */ + PAD_NC(GPP_F19, NONE), + /* F20 : PCH_MEM_STRAP0 */ + PAD_CFG_GPI(GPP_F20, NONE, PLTRST), + /* F21 : PCH_MEM_STRAP1 */ + PAD_CFG_GPI(GPP_F21, NONE, PLTRST), + /* F22 : PCH_MEM_STRAP3 */ + PAD_CFG_GPI(GPP_F22, NONE, PLTRST), + /* F23 : GPP_F23 ==> NC */ + PAD_NC(GPP_F23, NONE), + + /* G0 : SD_CMD */ + PAD_CFG_NF(GPP_G0, NATIVE, DEEP, NF1), + /* G1 : SD_DATA0 */ + PAD_CFG_NF(GPP_G1, NATIVE, DEEP, NF1), + /* G2 : SD_DATA1 */ + PAD_CFG_NF(GPP_G2, NATIVE, DEEP, NF1), + /* G3 : SD_DATA2 */ + PAD_CFG_NF(GPP_G3, NATIVE, DEEP, NF1), + /* G4 : SD_DATA3 */ + PAD_CFG_NF(GPP_G4, NATIVE, DEEP, NF1), + /* G5 : SD_CD# */ + PAD_CFG_NF(GPP_G5, NONE, PLTRST, NF1), + /* G6 : SD_CLK */ + PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), + /* G7 : SD_WP + * As per schematics SD host controller SD_WP pin is not connected to + * uSD card connector. In order to overcome gpio default state, ensures + * to configure gpio pin as NF1 with internal 20K pull down. + */ + PAD_CFG_NF(GPP_G7, DN_20K, DEEP, NF1), + /* + * H0 : HP_INT_L + */ + PAD_CFG_GPI_INT(GPP_H0, NONE, PLTRST, EDGE_BOTH), + /* H1 : CNV_RF_RESET_L */ + PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3), + /* H2 : CNV_CLKREQ0 */ + PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3), + /* H3 : SPKR_PA_EN */ + PAD_CFG_GPO(GPP_H3, 0, DEEP), + /* H4 : PCH_I2C_PEN_SDA */ + PAD_NC(GPP_H4, NONE), + /* H5 : PCH_I2C_PEN_SCL */ + PAD_NC(GPP_H5, NONE), + /* H6 : PCH_I2C_SAR0_MST_SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* H7 : PCH_I2C_SAR0_MST_SCL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /* H8 : PCH_I2C_M2_AUDIO_SAR1_SDA */ + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), + /* H9 : PCH_I2C_M2_AUDIO_SAR1_SCL */ + PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), + /* H10 : PCH_I2C_TRACKPAD_SDA */ + PAD_NC(GPP_H10, NONE), + /* H11 : PCH_I2C_TRACKPAD_SCL */ + PAD_NC(GPP_H11, NONE), + /* H12 : GPP_H12 ==> NC */ + PAD_NC(GPP_H12, NONE), + /* H13 : GPP_H13 ==> NC */ + PAD_NC(GPP_H13, NONE), + /* H14 : GPP_H14 ==> NC */ + PAD_NC(GPP_H14, NONE), + /* H15 : GPP_H15 ==> NC */ + PAD_NC(GPP_H15, NONE), + /* H16 : GPP_H16 ==> NC */ + PAD_NC(GPP_H16, NONE), + /* H17 : TP1 */ + PAD_NC(GPP_H17, NONE), + /* H18 : CPU_C10_GATE_L */ + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), + /* H19 : GPP_H19 ==> NC */ + PAD_NC(GPP_H19, NONE), + /* H20 : TP41 */ + PAD_NC(GPP_H20, NONE), + /* H21 : XTAL_FREQ_SEL */ + PAD_NC(GPP_H21, NONE), + /* H22 : GPP_H22 ==> NC */ + PAD_NC(GPP_H22, NONE), + /* H23 : GPP_H23_STRAP */ + PAD_NC(GPP_H23, NONE), + + /* GPD2: LAN_WAKE# ==> EC_PCH_WAKE_OD */ + PAD_CFG_NF(GPD2, NONE, DEEP, NF1), + + /* SD card detect VGPIO */ + PAD_CFG_GPI_GPIO_DRIVER(vSD3_CD_B, NONE, DEEP), + + /* CNV_WCEN : Disable Wireless Charging */ + PAD_CFG_GPO(CNV_WCEN, 0, DEEP), +}; + +const struct pad_config *base_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +/* + * Default GPIO settings before entering sleep. Configure A12: FPMCU_RST_ODL + * as GPO before entering sleep. + */ +static const struct pad_config default_sleep_gpio_table[] = { + PAD_CFG_GPO(GPP_A12, 1, DEEP), /* FPMCU_RST_ODL */ +}; + +/* + * GPIO settings before entering S5, which are same as + * default_sleep_gpio_table but also, + * turn off EN_PP3300_WWAN. + */ +static const struct pad_config s5_sleep_gpio_table[] = { + PAD_CFG_GPO(GPP_A12, 1, DEEP), /* FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_A18, 0, DEEP), /* EN_PP3300_WWAN */ +}; + +const struct pad_config *__weak variant_sleep_gpio_table( + u8 slp_typ, size_t *num) +{ + if (slp_typ == ACPI_S5) { + *num = ARRAY_SIZE(s5_sleep_gpio_table); + return s5_sleep_gpio_table; + } + *num = ARRAY_SIZE(default_sleep_gpio_table); + return default_sleep_gpio_table; +} + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), +}; + +const struct cros_gpio *__weak variant_cros_gpios(size_t *num) +{ + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; +} + +/* Weak implementation of overrides */ +const struct pad_config *__weak override_gpio_table(size_t *num) +{ + *num = 0; + return NULL; +} diff --git a/src/mainboard/google/puff/variants/baseboard/include/baseboard/acpi/dptf.asl b/src/mainboard/google/puff/variants/baseboard/include/baseboard/acpi/dptf.asl new file mode 100644 index 0000000..b18932e --- /dev/null +++ b/src/mainboard/google/puff/variants/baseboard/include/baseboard/acpi/dptf.asl @@ -0,0 +1,126 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 95 +#define DPTF_CPU_CRITICAL 105 +#define DPTF_CPU_ACTIVE_AC0 87 +#define DPTF_CPU_ACTIVE_AC1 85 +#define DPTF_CPU_ACTIVE_AC2 83 +#define DPTF_CPU_ACTIVE_AC3 80 +#define DPTF_CPU_ACTIVE_AC4 75 + +#define DPTF_TSR0_SENSOR_ID 0 +#define DPTF_TSR0_SENSOR_NAME "Thermal Sensor 1" +#define DPTF_TSR0_PASSIVE 65 +#define DPTF_TSR0_CRITICAL 75 +#define DPTF_TSR0_ACTIVE_AC0 50 +#define DPTF_TSR0_ACTIVE_AC1 47 +#define DPTF_TSR0_ACTIVE_AC2 45 +#define DPTF_TSR0_ACTIVE_AC3 42 +#define DPTF_TSR0_ACTIVE_AC4 39 + +#define DPTF_TSR1_SENSOR_ID 1 +#define DPTF_TSR1_SENSOR_NAME "Thermal Sensor 2" +#define DPTF_TSR1_PASSIVE 65 +#define DPTF_TSR1_CRITICAL 75 +#define DPTF_TSR1_ACTIVE_AC0 50 +#define DPTF_TSR1_ACTIVE_AC1 47 +#define DPTF_TSR1_ACTIVE_AC2 45 +#define DPTF_TSR1_ACTIVE_AC3 42 +#define DPTF_TSR1_ACTIVE_AC4 39 + +#define DPTF_ENABLE_CHARGER +#define DPTF_ENABLE_FAN_CONTROL + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ +}) + +/* DFPS: Fan Performance States */ +Name (DFPS, Package () { + 0, // Revision + /* + * TODO : Need to update this Table after characterization. + * These are initial reference values. + */ + /* Control, Trip Point, Speed, NoiseLevel, Power */ + Package () {90, 0xFFFFFFFF, 6700, 220, 2200}, + Package () {80, 0xFFFFFFFF, 5800, 180, 1800}, + Package () {70, 0xFFFFFFFF, 5000, 145, 1450}, + Package () {60, 0xFFFFFFFF, 4900, 115, 1150}, + Package () {50, 0xFFFFFFFF, 3838, 90, 900}, + Package () {40, 0xFFFFFFFF, 2904, 55, 550}, + Package () {30, 0xFFFFFFFF, 2337, 30, 300}, + Package () {20, 0xFFFFFFFF, 1608, 15, 150}, + Package () {10, 0xFFFFFFFF, 800, 10, 100}, + Package () {0, 0xFFFFFFFF, 0, 0, 50} +}) + +Name (DART, Package () { + /* Fan effect on CPU */ + 0, // Revision + Package () { + /* + * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6, + * AC7, AC8, AC9 + */ + \_SB.DPTF.TFN1, \_SB.PCI0.TCPU, 100, 90, 69, 56, 46, 36, 0, 0, + 0, 0, 0 + }, + Package () { + \_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 100, 90, 69, 56, 46, 36, 0, 0, + 0, 0, 0 + }, + Package () { + \_SB.DPTF.TFN1, \_SB.DPTF.TSR1, 100, 90, 69, 56, 46, 36, 0, 0, + 0, 0, 0 + } +}) + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on Ambient (TSR0) */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 60, 0, 0, 0, 0 }, + + /* Charger Throttle Effect on Charger (TSR1) */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 100, 60, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 3000, /* PowerLimitMinimum */ + 15000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 32000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 15000, /* PowerLimitMinimum */ + 64000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 32000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) diff --git a/src/mainboard/google/puff/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/puff/variants/baseboard/include/baseboard/ec.h new file mode 100644 index 0000000..3aa9414 --- /dev/null +++ b/src/mainboard/google/puff/variants/baseboard/include/baseboard/ec.h @@ -0,0 +1,92 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __BASEBOARD_EC_H__ +#define __BASEBOARD_EC_H__ + +#include <ec/google/chromeec/ec_commands.h> +#include <variant/gpio.h> + +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP)) + +#define MAINBOARD_EC_SMI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) + +/* EC can wake from S5 with lid or power button */ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) + +/* + * EC can wake from S3 with lid or power button or key press or + * mode change event. + */ +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) + +#define MAINBOARD_EC_S0IX_WAKE_EVENTS \ + (MAINBOARD_EC_S3_WAKE_EVENTS | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT)) + +/* Log EC wake events plus EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) + +/* + * ACPI related definitions for ASL code. + */ + +/* Enable EC backed ALS device in ACPI */ +#define EC_ENABLE_ALS_DEVICE + +/* Enable EC backed PD MCU device in ACPI */ +#define EC_ENABLE_PD_MCU_DEVICE + +/* Enable LID switch and provide wake pin for EC */ +#define EC_ENABLE_LID_SWITCH +#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE + +/* Enable Tablet switch */ +#define EC_ENABLE_TBMC_DEVICE + +#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ +#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ +#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ + +/* Enable EC sync interrupt, EC_SYNC_IRQ is defined in baseboard/gpio.h */ +#define EC_ENABLE_SYNC_IRQ + +/* Enable EC backed Keyboard Backlight in ACPI */ +#define EC_ENABLE_KEYBOARD_BACKLIGHT + +#endif /* __BASEBOARD_EC_H__ */ diff --git a/src/mainboard/google/puff/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/puff/variants/baseboard/include/baseboard/gpio.h new file mode 100644 index 0000000..e83732c --- /dev/null +++ b/src/mainboard/google/puff/variants/baseboard/include/baseboard/gpio.h @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef BASEBOARD_GPIO_H +#define BASEBOARD_GPIO_H + +#include <soc/gpio.h> + +#define GPIO_EC_IN_RW GPP_C22 + +#define GPIO_PCH_WP GPP_C20 + +/* EC wake pin is LAN_WAKE# */ +#define GPE_EC_WAKE GPE0_LAN_WAK + +/* eSPI virtual wire reporting */ +#define EC_SCI_GPI GPE0_ESPI + +/* EC sync irq is GPP_C13_IRQ */ +#define EC_SYNC_IRQ GPP_C13_IRQ + +#endif /* BASEBOARD_GPIO_H */ diff --git a/src/mainboard/google/puff/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/puff/variants/baseboard/include/baseboard/variants.h new file mode 100644 index 0000000..920e428 --- /dev/null +++ b/src/mainboard/google/puff/variants/baseboard/include/baseboard/variants.h @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef BASEBOARD_VARIANTS_H +#define BASEBOARD_VARIANTS_H + +#include <soc/cnl_memcfg_init.h> +#include <soc/gpio.h> +#include <stdint.h> +#include <vendorcode/google/chromeos/chromeos.h> + +/* + * The next set of functions return the gpio table and fill in the number of + * entries for each table. The "base" GPIOs live in the "baseboard" variant, and + * the overrides live with the specific board (kohaku, kled, etc.). +*/ +const struct pad_config *base_gpio_table(size_t *num); +const struct pad_config *override_gpio_table(size_t *num); + +/* Return board specific memory configuration */ +void variant_memory_params(struct cnl_mb_cfg *bcfg); + +/* Return memory SKU for the variant */ +int variant_memory_sku(void); + +/* Return variant specific gpio pads to be configured during sleep */ +const struct pad_config *variant_sleep_gpio_table(u8 slp_typ, size_t *num); + +/* Return GPIO pads that need to be configured before ramstage */ +const struct pad_config *variant_early_gpio_table(size_t *num); + +/* Return ChromeOS gpio table and fill in number of entries. */ +const struct cros_gpio *variant_cros_gpios(size_t *num); + +/* Return board SKU */ +uint32_t get_board_sku(void); + +/* Modify devictree settings during ramstage. */ +void variant_devtree_update(void); + +#endif /* BASEBOARD_VARIANTS_H */ diff --git a/src/mainboard/google/puff/variants/baseboard/memory.c b/src/mainboard/google/puff/variants/baseboard/memory.c new file mode 100644 index 0000000..bcfc49f --- /dev/null +++ b/src/mainboard/google/puff/variants/baseboard/memory.c @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/variants.h> +#include <baseboard/gpio.h> +#include <soc/cnl_memcfg_init.h> +#include <string.h> + +static const struct cnl_mb_cfg baseboard_memcfg = { + /* Baseboard uses 121, 81 and 100 rcomp resistors */ + .rcomp_resistor = {121, 81, 100}, + + /* Baseboard Rcomp target values */ + .rcomp_targets = {100, 40, 20, 20, 26}, + + /* Set CaVref config to 2 */ + .vref_ca_config = 2, + + /* Enable Early Command Training */ + .ect = 1, +}; + +void __weak variant_memory_params(struct cnl_mb_cfg *bcfg) +{ + memcpy(bcfg, &baseboard_memcfg, sizeof(baseboard_memcfg)); +} diff --git a/src/mainboard/google/puff/variants/puff/Makefile.inc b/src/mainboard/google/puff/variants/puff/Makefile.inc new file mode 100644 index 0000000..30daaf7 --- /dev/null +++ b/src/mainboard/google/puff/variants/puff/Makefile.inc @@ -0,0 +1,16 @@ +## This file is part of the coreboot project. +## +## Copyright 2019 Google LLC +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-y += gpio.c +bootblock-y += gpio.c diff --git a/src/mainboard/google/puff/variants/puff/gpio.c b/src/mainboard/google/puff/variants/puff/gpio.c new file mode 100644 index 0000000..f3efae5 --- /dev/null +++ b/src/mainboard/google/puff/variants/puff/gpio.c @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +/* Pad configuration in ramstage */ +static const struct pad_config gpio_table[] = { +}; + +const struct pad_config *override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/google/puff/variants/puff/include/variant/acpi/dptf.asl b/src/mainboard/google/puff/variants/puff/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..31f72b3 --- /dev/null +++ b/src/mainboard/google/puff/variants/puff/include/variant/acpi/dptf.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/acpi/dptf.asl> diff --git a/src/mainboard/google/puff/variants/puff/include/variant/ec.h b/src/mainboard/google/puff/variants/puff/include/variant/ec.h new file mode 100644 index 0000000..c36f957 --- /dev/null +++ b/src/mainboard/google/puff/variants/puff/include/variant/ec.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_EC_H +#define VARIANT_EC_H + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/puff/variants/puff/include/variant/gpio.h b/src/mainboard/google/puff/variants/puff/include/variant/gpio.h new file mode 100644 index 0000000..5d69eed --- /dev/null +++ b/src/mainboard/google/puff/variants/puff/include/variant/gpio.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +#endif diff --git a/src/mainboard/google/puff/variants/puff/overridetree.cb b/src/mainboard/google/puff/variants/puff/overridetree.cb new file mode 100644 index 0000000..bc6aa11 --- /dev/null +++ b/src/mainboard/google/puff/variants/puff/overridetree.cb @@ -0,0 +1,181 @@ +chip soc/intel/cannonlake + + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + [PchSerialIoIndexSPI0] = PchSerialIoPci, + [PchSerialIoIndexSPI1] = PchSerialIoPci, + [PchSerialIoIndexSPI2] = PchSerialIoDisabled, + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + # VR Slew rate setting + register "AcousticNoiseMitigation" = "1" + register "SlowSlewRateForIa" = "2" + register "SlowSlewRateForGt" = "2" + register "SlowSlewRateForSa" = "2" + register "FastPkgCRampDisableIa" = "1" + register "FastPkgCRampDisableGt" = "1" + register "FastPkgCRampDisableSa" = "1" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| GSPI1 | FP MCU | + #| I2C0 | Touchpad | + #| I2C1 | Touch screen | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 50, + .fall_time_ns = 15, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 60, + .fall_time_ns = 25, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 150, + .fall_time_ns = 150, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 120, + .fall_time_ns = 120, + }, + }" + + # GPIO for SD card detect + register "sdcard_cd_gpio" = "vSD3_CD_B" + + device domain 0 on + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_A21_IRQ)" + register "wake" = "GPE0_DW0_21" + device i2c 15 on end + end + end # I2C #0 + device pci 15.1 on + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "reset_delay_ms" = "100" + register "reset_off_delay_ms" = "5" + register "has_power_resource" = "1" + register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)" + register "stop_off_delay_ms" = "5" + device i2c 49 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "generic.reset_delay_ms" = "500" + register "generic.reset_off_delay_ms" = "3" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)" + register "generic.enable_delay_ms" = "12" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 5d on end + end + chip drivers/generic/gpio_keys + register "name" = ""PENH"" + register "gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A8)" + register "key.wake" = "GPE0_DW0_08" + register "key.wakeup_event_action" = "EV_ACT_DEASSERTED" + register "key.dev_name" = ""EJCT"" + register "key.linux_code" = "SW_PEN_INSERTED" + register "key.linux_input_type" = "EV_SW" + register "key.label" = ""pen_eject"" + device generic 0 on end + end + end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 on + chip drivers/i2c/sx9310 + register "desc" = ""SAR Proximity Sensor"" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A0)" + register "speed" = "I2C_SPEED_FAST" + register "uid" = "1" + register "reg_prox_ctrl0" = "0x10" + register "reg_prox_ctrl1" = "0x00" + register "reg_prox_ctrl2" = "0x84" + register "reg_prox_ctrl3" = "0x0e" + register "reg_prox_ctrl4" = "0x07" + register "reg_prox_ctrl5" = "0xc6" + register "reg_prox_ctrl6" = "0x20" + register "reg_prox_ctrl7" = "0x0d" + register "reg_prox_ctrl8" = "0x8d" + register "reg_prox_ctrl9" = "0x43" + register "reg_prox_ctrl10" = "0x1f" + register "reg_prox_ctrl11" = "0x00" + register "reg_prox_ctrl12" = "0x00" + register "reg_prox_ctrl13" = "0x00" + register "reg_prox_ctrl14" = "0x00" + register "reg_prox_ctrl15" = "0x00" + register "reg_prox_ctrl16" = "0x00" + register "reg_prox_ctrl17" = "0x00" + register "reg_prox_ctrl18" = "0x00" + register "reg_prox_ctrl19" = "0x00" + register "reg_sar_ctrl0" = "0x50" + register "reg_sar_ctrl1" = "0x8a" + register "reg_sar_ctrl2" = "0x3c" + device i2c 28 on end + end + end # I2C #3 + device pci 19.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)" + register "property_count" = "1" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end #I2C #4 + device pci 1e.3 on + chip drivers/spi/acpi + register "name" = ""CRFP"" + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "uid" = "1" + register "compat_string" = ""google,cros-ec-spi"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A23_IRQ)" + register "wake" = "GPE0_DW0_23" + device spi 1 on end + end # FPMCU + end # GSPI #1 + end + +end -- To view, visit https://review.coreboot.org/c/coreboot/+/36065 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc8b13471e6e0b8cf540c35c712089c3205a3497 Gerrit-Change-Number: 36065 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

4 8

Change in ...coreboot[master]: [NOTFORMERGE] intel/d945gclf board fork attempt
by junaid (Code Review) 07 Aug '23

07 Aug '23

junaid has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30977 Change subject: [NOTFORMERGE] intel/d945gclf board fork attempt ...................................................................... [NOTFORMERGE] intel/d945gclf board fork attempt port coreboot for som4461. 1.make a folder advantech in mainboard . 2.change vendor name in Kconfig.name files accordingly. 3.copy folder intle/d945gclf in advantech folder. rename folder with som4461 4.In som4461/kconfig.name change board name to som4461 5.In som4461/kconfig , change existing superio to select SUPERIO_WINBOND_W83627DHG 6.In som4461/devicetree.cb change existing chip to chip superio/winbond/w83627dhg 7.Change gpio.c as per inteltool.log of som4461 8.Change romstage.c , include winbond.h and w83627dhg.h 9.make menuconfig, slect vendor--> advantech , model--> som4461, chipset-->donot include microcode, select coreinfo as payload 10. coreboot.Rom file made 11. when dump in 4461 board , nothing appeares on serial console. Change-Id: I7ea260021dc8033c58f134a5c60cdcae12b44d88 Signed-off-by: junaid <junaidimpex(a)gmail.com> --- A src/mainboard/advantech/Kconfig A src/mainboard/advantech/Kconfig.name A src/mainboard/advantech/som4461/Kconfig A src/mainboard/advantech/som4461/Kconfig.name A src/mainboard/advantech/som4461/Makefile.inc A src/mainboard/advantech/som4461/acpi/ec.asl A src/mainboard/advantech/som4461/acpi/ich7_pci_irqs.asl A src/mainboard/advantech/som4461/acpi/mainboard.asl A src/mainboard/advantech/som4461/acpi/platform.asl A src/mainboard/advantech/som4461/acpi/superio.asl A src/mainboard/advantech/som4461/acpi/thermal.asl A src/mainboard/advantech/som4461/acpi_tables.c A src/mainboard/advantech/som4461/board_info.txt A src/mainboard/advantech/som4461/cmos.default A src/mainboard/advantech/som4461/cmos.layout A src/mainboard/advantech/som4461/cstates.c A src/mainboard/advantech/som4461/data.vbt A src/mainboard/advantech/som4461/devicetree.cb A src/mainboard/advantech/som4461/dsdt.asl A src/mainboard/advantech/som4461/gpio.c A src/mainboard/advantech/som4461/hda_verb.c A src/mainboard/advantech/som4461/irq_tables.c A src/mainboard/advantech/som4461/mptable.c A src/mainboard/advantech/som4461/romstage.c 24 files changed, 1,209 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/30977/1 diff --git a/src/mainboard/advantech/Kconfig b/src/mainboard/advantech/Kconfig new file mode 100644 index 0000000..b464c1a --- /dev/null +++ b/src/mainboard/advantech/Kconfig @@ -0,0 +1,30 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 Advanced Micro Devices, Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +if VENDOR_ADVANTECH + +choice + prompt "Mainboard model" + +source "src/mainboard/advantech/*/Kconfig.name" + +endchoice + +source "src/mainboard/advantech/*/Kconfig" + +config MAINBOARD_VENDOR + string + default "Advantech" + +endif # VENDOR_ADVANTECH diff --git a/src/mainboard/advantech/Kconfig.name b/src/mainboard/advantech/Kconfig.name new file mode 100644 index 0000000..8862ffc --- /dev/null +++ b/src/mainboard/advantech/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_ADVANTECH + bool "Advantech" diff --git a/src/mainboard/advantech/som4461/Kconfig b/src/mainboard/advantech/som4461/Kconfig new file mode 100644 index 0000000..24dc984 --- /dev/null +++ b/src/mainboard/advantech/som4461/Kconfig @@ -0,0 +1,51 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +if BOARD_ADVANTECH_SOM4461 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select CPU_INTEL_SOCKET_441 + select NORTHBRIDGE_INTEL_I945 + select NORTHBRIDGE_INTEL_SUBTYPE_I945GC + select SOUTHBRIDGE_INTEL_I82801GX + select SUPERIO_WINBOND_W83627DHG + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select HAVE_PIRQ_TABLE + select HAVE_MP_TABLE + select HAVE_ACPI_TABLES + select HAVE_ACPI_RESUME + select BOARD_ROMSIZE_KB_512 + select CHANNEL_XOR_RANDOMIZATION + select MAINBOARD_HAS_NATIVE_VGA_INIT + select INTEL_GMA_HAVE_VBT + +config MAINBOARD_DIR + string + default advantech/som4461 + +config MAINBOARD_PART_NUMBER + string + default "SOM4461" + +config IRQ_SLOT_COUNT + int + default 18 + +config MAX_CPUS + int + default 4 + +endif # BOARD_ADVANTECH_SOM4461 diff --git a/src/mainboard/advantech/som4461/Kconfig.name b/src/mainboard/advantech/som4461/Kconfig.name new file mode 100644 index 0000000..1ff7de8 --- /dev/null +++ b/src/mainboard/advantech/som4461/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ADVANTECH_SOM4461 + bool "SOM4461" diff --git a/src/mainboard/advantech/som4461/Makefile.inc b/src/mainboard/advantech/som4461/Makefile.inc new file mode 100644 index 0000000..f3d7e76 --- /dev/null +++ b/src/mainboard/advantech/som4461/Makefile.inc @@ -0,0 +1,2 @@ +ramstage-y += cstates.c +romstage-y += gpio.c diff --git a/src/mainboard/advantech/som4461/acpi/ec.asl b/src/mainboard/advantech/som4461/acpi/ec.asl new file mode 100644 index 0000000..5362bb2 --- /dev/null +++ b/src/mainboard/advantech/som4461/acpi/ec.asl @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device(EC0) +{ + Name (_HID, EISAID("PNP0C09")) + Name (_UID, 1) + + // _REG method requires that an operation region be defined. + OperationRegion (ERAM, EmbeddedControl, 0x00, 0xff) + Field (ERAM, ByteAcc, Lock, Preserve) + { + } + + Method (_CRS, 0, Serialized) + { + Name (ECMD, ResourceTemplate() + { + IO (Decode16, 0x62, 0x62, 0, 1) + IO (Decode16, 0x66, 0x66, 0, 1) + }) + + Return (ECMD) + } + + Method (_REG, 2) + { + // This method is needed by Windows XP/2000 + // for EC initialization before a driver + // is loaded + } + + Name (_GPE, 23) // GPI07 / GPE23 -> Runtime SCI + + // TODO EC Query methods + + // TODO Scope _SB devices for AC power, LID, Power button + +} diff --git a/src/mainboard/advantech/som4461/acpi/ich7_pci_irqs.asl b/src/mainboard/advantech/som4461/acpi/ich7_pci_irqs.asl new file mode 100644 index 0000000..0da7e70 --- /dev/null +++ b/src/mainboard/advantech/som4461/acpi/ich7_pci_irqs.asl @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* This is board specific information: IRQ routing for the + * 0:1e.0 PCI bridge of the ICH7 + */ + +If (PICM) { + Return (Package() { + Package() { 0x0000ffff, 0, 0, 21}, + Package() { 0x0000ffff, 1, 0, 22}, + Package() { 0x0000ffff, 2, 0, 23}, + Package() { 0x0000ffff, 3, 0, 20}, + + Package() { 0x0001ffff, 0, 0, 22}, + Package() { 0x0001ffff, 1, 0, 21}, + Package() { 0x0001ffff, 2, 0, 20}, + Package() { 0x0001ffff, 3, 0, 23}, + + Package() { 0x0002ffff, 0, 0, 18}, + Package() { 0x0002ffff, 1, 0, 19}, + Package() { 0x0002ffff, 2, 0, 17}, + Package() { 0x0002ffff, 3, 0, 16}, + + Package() { 0x0003ffff, 0, 0, 19}, + Package() { 0x0003ffff, 1, 0, 18}, + Package() { 0x0003ffff, 2, 0, 21}, + Package() { 0x0003ffff, 3, 0, 22}, + + Package() { 0x0005ffff, 0, 0, 17}, + Package() { 0x0005ffff, 1, 0, 20}, + Package() { 0x0005ffff, 2, 0, 22}, + Package() { 0x0005ffff, 3, 0, 21}, + + Package() { 0x0008ffff, 0, 0, 20}, + }) +} Else { + Return (Package() { + Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKF, 0}, + Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKG, 0}, + Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKH, 0}, + Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKE, 0}, + + Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKG, 0}, + Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKF, 0}, + Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKE, 0}, + Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKH, 0}, + + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKC, 0}, + Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKD, 0}, + Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKB, 0}, + Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKA, 0}, + + Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKD, 0}, + Package() { 0x0003ffff, 1, \_SB.PCI0.LPCB.LNKC, 0}, + Package() { 0x0003ffff, 2, \_SB.PCI0.LPCB.LNKF, 0}, + Package() { 0x0003ffff, 3, \_SB.PCI0.LPCB.LNKG, 0}, + + Package() { 0x0005ffff, 0, \_SB.PCI0.LPCB.LNKB, 0}, + Package() { 0x0005ffff, 1, \_SB.PCI0.LPCB.LNKE, 0}, + Package() { 0x0005ffff, 2, \_SB.PCI0.LPCB.LNKG, 0}, + Package() { 0x0005ffff, 3, \_SB.PCI0.LPCB.LNKF, 0}, + + Package() { 0x0008ffff, 0, \_SB.PCI0.LPCB.LNKE, 0}, + }) +} diff --git a/src/mainboard/advantech/som4461/acpi/mainboard.asl b/src/mainboard/advantech/som4461/acpi/mainboard.asl new file mode 100644 index 0000000..0454c3f --- /dev/null +++ b/src/mainboard/advantech/som4461/acpi/mainboard.asl @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (SLPB) +{ + Name(_HID, EisaId("PNP0C0E")) + + // Wake + Name(_PRW, Package(){0x1d, 0x04}) +} + +Device (PWRB) +{ + Name(_HID, EisaId("PNP0C0C")) + + // Wake + Name(_PRW, Package(){0x1d, 0x04}) +} diff --git a/src/mainboard/advantech/som4461/acpi/platform.asl b/src/mainboard/advantech/som4461/acpi/platform.asl new file mode 100644 index 0000000..21eb3df --- /dev/null +++ b/src/mainboard/advantech/som4461/acpi/platform.asl @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ + // Call a trap so SMI can prepare for Sleep as well. + // TRAP(0x55) +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + // CPU specific part + + // Notify PCI Express slots in case a card + // was inserted while a sleep state was active. + + // Are we going to S3? + If (LEqual(Arg0, 3)) { + // .. + } + + // Are we going to S4? + If (LEqual(Arg0, 4)) { + // .. + } + + // TODO: Windows XP SP2 P-State restore + + Return(Package(){0,0}) +} diff --git a/src/mainboard/advantech/som4461/acpi/superio.asl b/src/mainboard/advantech/som4461/acpi/superio.asl new file mode 100644 index 0000000..152302e --- /dev/null +++ b/src/mainboard/advantech/som4461/acpi/superio.asl @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +Device (SIO1) +{ + Name (_HID, EISAID("PNP0A05")) + Name (_UID, 1) + + Device (UAR1) + { + Name(_HID, EISAID("PNP0501")) + Name(_UID, 1) + + // Some methods need an implementation here: + // missing: _STA, _DIS, _CRS, _PRS, + // missing: _SRS, _PS0, _PS3 + } + + Device (UAR2) + { + Name(_HID, EISAID("PNP0501")) + Name(_UID, 2) + + // Some methods need an implementation here: + // missing: _STA, _DIS, _CRS, _PRS, + // missing: _SRS, _PS0, _PS3 + } +} diff --git a/src/mainboard/advantech/som4461/acpi/thermal.asl b/src/mainboard/advantech/som4461/acpi/thermal.asl new file mode 100644 index 0000000..27337d4 --- /dev/null +++ b/src/mainboard/advantech/som4461/acpi/thermal.asl @@ -0,0 +1,89 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// Thermal Zone + +Scope (\_TZ) +{ + ThermalZone (THRM) + { + + // FIXME these could/should be read from the + // GNVS area, so they can be controlled by + // coreboot + Name(TC1V, 0x04) + Name(TC2V, 0x03) + Name(TSPV, 0x64) + + // At which temperature should the OS start + // active cooling? + Method (_AC0, 0, Serialized) + { + Return (0xf5c) // Value for Rocky + } + + // Method (_AC1, 0, Serialized) + // { + // Return (0xf5c) + // } + + // Critical shutdown temperature + Method (_CRT, 0, Serialized) + { + Return (Add (0x0aac, 0x50)) // FIXME + } + + // CPU throttling start temperature + Method (_PSV, 0, Serialized) + { + Return (0xaaf) // FIXME + } + + // Get DTS Temperature + Method (_TMP, 0, Serialized) + { + Return (0xaac) // FIXME + } + + // Processors used for active cooling + Method (_PSL, 0, Serialized) + { + If (MPEN) { + Return (Package() {\_PR.CP01, \_PR.CP02}) + } + Return (Package() {\_PR.CP01}) + } + + // TC1 value for passive cooling + Method (_TC1, 0, Serialized) + { + Return (TC1V) + } + + // TC2 value for passive cooling + Method (_TC2, 0, Serialized) + { + Return (TC2V) + } + + // Sampling period for passive cooling + Method (_TSP, 0, Serialized) + { + Return (TSPV) + } + + + } +} diff --git a/src/mainboard/advantech/som4461/acpi_tables.c b/src/mainboard/advantech/som4461/acpi_tables.c new file mode 100644 index 0000000..ba3995e --- /dev/null +++ b/src/mainboard/advantech/som4461/acpi_tables.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <southbridge/intel/i82801gx/nvs.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ +} diff --git a/src/mainboard/advantech/som4461/board_info.txt b/src/mainboard/advantech/som4461/board_info.txt new file mode 100644 index 0000000..d2bead1 --- /dev/null +++ b/src/mainboard/advantech/som4461/board_info.txt @@ -0,0 +1,3 @@ +Category: mini +Board URL: http://www.http://origindownload.advantech.com/ProductFile/PIS/SOM-4461/Pro… +Release year: 2011 diff --git a/src/mainboard/advantech/som4461/cmos.default b/src/mainboard/advantech/som4461/cmos.default new file mode 100644 index 0000000..2cb37df --- /dev/null +++ b/src/mainboard/advantech/som4461/cmos.default @@ -0,0 +1,6 @@ +boot_option=Fallback +debug_level=Debug +hyper_threading=Enable +nmi=Enable +boot_devices='' +gfx_uma_size=8M diff --git a/src/mainboard/advantech/som4461/cmos.layout b/src/mainboard/advantech/som4461/cmos.layout new file mode 100644 index 0000000..bdc264b --- /dev/null +++ b/src/mainboard/advantech/som4461/cmos.layout @@ -0,0 +1,114 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2007-2008 coresystems GmbH +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +# Status Register A +# ----------------------------------------------------------------- +# Status Register B +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +#392 3 r 0 unused +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail + +# coreboot config options: northbridge +411 3 e 11 gfx_uma_size + +# coreboot config options: bootloader +416 512 s 0 boot_devices +#928 80 r 0 unused + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +# RAM initialization internal data +1024 8 r 0 C0WL0REOST +1032 8 r 0 C1WL0REOST +1040 8 r 0 RCVENMT +1048 4 r 0 C0DRT1 +1052 4 r 0 C1DRT1 + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +11 0 1M +11 1 4M +11 2 8M +11 3 16M +11 4 32M +11 5 48M +11 6 64M + +# ----------------------------------------------------------------- +checksums + +checksum 392 983 984 diff --git a/src/mainboard/advantech/som4461/cstates.c b/src/mainboard/advantech/som4461/cstates.c new file mode 100644 index 0000000..f683756 --- /dev/null +++ b/src/mainboard/advantech/som4461/cstates.c @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <arch/x86/include/arch/acpigen.h> + +int get_cst_entries(acpi_cstate_t **entries) +{ + return 0; +} diff --git a/src/mainboard/advantech/som4461/data.vbt b/src/mainboard/advantech/som4461/data.vbt new file mode 100644 index 0000000..326eab7 --- /dev/null +++ b/src/mainboard/advantech/som4461/data.vbt Binary files differ diff --git a/src/mainboard/advantech/som4461/devicetree.cb b/src/mainboard/advantech/som4461/devicetree.cb new file mode 100644 index 0000000..864775a --- /dev/null +++ b/src/mainboard/advantech/som4461/devicetree.cb @@ -0,0 +1,106 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip northbridge/intel/i945 + + device cpu_cluster 0 on + chip cpu/intel/socket_441 + device lapic 0 on end + end + end + + register "pci_mmio_size" = "768" + + device domain 0 on + subsystemid 0x8086 0x464c inherit + device pci 00.0 on end # host bridge + device pci 01.0 off end # i945 PCIe root port + device pci 02.0 on end # vga controller + device pci 02.1 on end # display controller + + chip southbridge/intel/i82801gx + register "pirqa_routing" = "0x05" + register "pirqb_routing" = "0x07" + register "pirqc_routing" = "0x05" + register "pirqd_routing" = "0x07" + register "pirqe_routing" = "0x80" + register "pirqf_routing" = "0x80" + register "pirqg_routing" = "0x80" + register "pirqh_routing" = "0x06" + + # GPI routing + # 0 No effect (default) + # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) + # 2 SCI (if corresponding GPIO_EN bit is also set) + register "gpi13_routing" = "1" + register "gpe0_en" = "0x20000601" + + register "ide_legacy_combined" = "0x0" + register "ide_enable_primary" = "0x1" + register "ide_enable_secondary" = "0x0" + register "sata_ahci" = "0x0" + register "c3_latency" = "85" + register "p_cnt_throttling_supported" = "0" + + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe port 1 + device pci 1c.1 off end # PCIe port 2 + device pci 1c.2 on end # PCIe port 3 + device pci 1c.3 on end # PCIe port 4 + device pci 1c.4 off end # PCIe port 5 + device pci 1c.5 off end # PCIe port 6 + device pci 1d.0 on end # USB UHCI + device pci 1d.1 on end # USB UHCI + device pci 1d.2 on end # USB UHCI + device pci 1d.3 off end # USB UHCI + device pci 1d.7 on end # USB2 EHCI + device pci 1e.0 on end # PCI bridge + device pci 1e.2 off end # AC'97 Audio + device pci 1e.3 off end # AC'97 Modem + device pci 1f.0 on # LPC bridge + chip superio/winbond/w83627dhg + device pnp 2e.0 off end # Floppy + device pnp 2e.1 off end # Parallel Port + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard,Mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + #device pnp 2e.6 off end # SPI + device pnp 2e.307 off end # GPIO6 + device pnp 2e.8 off end # WDTO, PLED + device pnp 2e.009 off end # GPIO2 + device pnp 2e.109 off end # GPIO3 + device pnp 2e.209 off end # GPIO4 + device pnp 2e.309 off end # GPIO5 + device pnp 2e.A off end # ACPI + device pnp 2e.B off end # HW Monitor + end # w83627dhg + end + device pci 1f.1 off end # IDE + device pci 1f.2 on end # SATA + device pci 1f.3 on end # SMBus + end + end +end diff --git a/src/mainboard/advantech/som4461/dsdt.asl b/src/mainboard/advantech/som4461/dsdt.asl new file mode 100644 index 0000000..95ed8d9 --- /dev/null +++ b/src/mainboard/advantech/som4461/dsdt.asl @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20090419 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" + + // global NVS and variables + #include <southbridge/intel/i82801gx/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/platform.asl> + + // General Purpose Events + //#include "acpi/gpe.asl" + + // mainboard specific devices + #include "acpi/mainboard.asl" + + // Thermal Zone + //#include "acpi/thermal.asl" + + #include <cpu/intel/speedstep/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/i945/acpi/i945.asl> + #include <southbridge/intel/i82801gx/acpi/ich7.asl> + } + } + + /* Chipset specific sleep states */ + #include <southbridge/intel/i82801gx/acpi/sleepstates.asl> +} diff --git a/src/mainboard/advantech/som4461/gpio.c b/src/mainboard/advantech/som4461/gpio.c new file mode 100644 index 0000000..cd5a1fc --- /dev/null +++ b/src/mainboard/advantech/som4461/gpio.c @@ -0,0 +1,127 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Arthur Heymans <arthur(a)aheymans.xyz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_GPIO, + .gpio10 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio19 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_GPIO, + .gpio26 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_OUTPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + + .gpio12 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + + .gpio19 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + + .gpio23 = GPIO_DIR_OUTPUT, + + .gpio24 = GPIO_DIR_OUTPUT, + .gpio25 = GPIO_DIR_OUTPUT, + .gpio26 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, + +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + + .gpio7 = GPIO_LEVEL_HIGH, + .gpio23 = GPIO_LEVEL_HIGH, + + .gpio24 = GPIO_LEVEL_HIGH, + .gpio25 = GPIO_LEVEL_HIGH, + + .gpio26 = GPIO_LEVEL_LOW, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, + .gpio15 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_OUTPUT, + + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio33 = GPIO_LEVEL_HIGH, + .gpio34 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, +}; diff --git a/src/mainboard/advantech/som4461/hda_verb.c b/src/mainboard/advantech/som4461/hda_verb.c new file mode 100644 index 0000000..5d08879 --- /dev/null +++ b/src/mainboard/advantech/som4461/hda_verb.c @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[0] = {}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/advantech/som4461/irq_tables.c b/src/mainboard/advantech/som4461/irq_tables.c new file mode 100644 index 0000000..1a7e85b --- /dev/null +++ b/src/mainboard/advantech/som4461/irq_tables.c @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/pirq_routing.h> + +static const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32+16*18, /* There can be total 18 devices on the bus */ + 0x00, /* Where the interrupt router lies (bus) */ + (0x1f << 3)|0x0, /* Where the interrupt router lies (dev) */ + 0, /* IRQs devoted exclusively to PCI usage */ + 0x8086, /* Vendor */ + 0x27b0, /* Device */ + 0, /* miniport */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0xf, /* u8 checksum. */ + { + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00,(0x01 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe? + {0x00,(0x02 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA + {0x00,(0x1e << 3)|0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // PCI bridge + {0x00,(0x1f << 3)|0x0, {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC + {0x00,(0x1d << 3)|0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, // USB#1 + {0x00,(0x1b << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Audio device + {0x00,(0x1c << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, // PCIe bridge + {0x04,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Firewire + {0x04,(0x01 << 3)|0x0, {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, // PCI Bridge + {0x04,(0x02 << 3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0}, + {0x04,(0x03 << 3)|0x0, {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0}, + {0x04,(0x04 << 3)|0x0, {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0}, + {0x04,(0x05 << 3)|0x0, {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0}, + {0x04,(0x06 << 3)|0x0, {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0}, + {0x04,(0x09 << 3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0}, + {0x01,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // Ethernet 8168 + {0x02,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0}, + {0x03,(0x00 << 3)|0x0, {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0}, + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr, &intel_irq_routing_table); +} diff --git a/src/mainboard/advantech/som4461/mptable.c b/src/mainboard/advantech/som4461/mptable.c new file mode 100644 index 0000000..d9aa098 --- /dev/null +++ b/src/mainboard/advantech/som4461/mptable.c @@ -0,0 +1,85 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <device/pci.h> +#include <arch/smp/mpspec.h> +#include <arch/ioapic.h> +#include <string.h> +#include <stdint.h> + +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + int isa_bus; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + + mptable_init(mc, LOCAL_APIC_ADDR); + + smp_write_processors(mc); + + mptable_write_buses(mc, NULL, &isa_bus); + + /* I/O APICs: APIC ID Version State Address */ + smp_write_ioapic(mc, 2, 0x20, VIO_APIC_VADDR); + + /* Legacy Interrupts */ + + mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0); + + /* Builtin devices on Bus 0 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x8, 0x2, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x7d, 0x2, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x74, 0x2, 0x17); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x75, 0x2, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x76, 0x2, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x77, 0x2, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x6c, 0x2, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x70, 0x2, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x71, 0x2, 0x11); + + /* Firewire 4:0.0 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x0, 0x2, 0x10); + + /* Old riser card */ + // riser slot top 5:8.0 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x20, 0x2, 0x14); + // riser slot middle 5:9.0 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x24, 0x2, 0x15); + // riser slot bottom 5:a.0 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x28, 0x2, 0x16); + + /* New Riser Card */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x30, 0x2, 0x14); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x34, 0x2, 0x15); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x38, 0x2, 0x16); + + /* Onboard Ethernet */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, 0x2, 0x10); + + /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + mptable_lintsrc(mc, isa_bus); + + /* Compute the checksums */ + return mptable_finalize(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr, 0); + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/advantech/som4461/romstage.c b/src/mainboard/advantech/som4461/romstage.c new file mode 100644 index 0000000..7671f9f --- /dev/null +++ b/src/mainboard/advantech/som4461/romstage.c @@ -0,0 +1,173 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// __PRE_RAM__ means: use "unsigned" for device, not a struct. +#include <stdint.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627dhg/w83627dhg.h> +#include <console/console.h> +#include <cpu/x86/bist.h> +#include <cpu/intel/romstage.h> +#include <northbridge/intel/i945/i945.h> +#include <northbridge/intel/i945/raminit.h> +#include <southbridge/intel/i82801gx/i82801gx.h> +#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) +#define GPIO_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345_V) +static void ich7_enable_lpc(void) +{ + // Enable Serial IRQ + pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0); + // Set COM1/COM2 decode range + pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0010); + // Enable COM1 + pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN | KBC_LPC_EN + | FDD_LPC_EN | LPT_LPC_EN | COMA_LPC_EN); + // Enable SuperIO Power Management Events + pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x007c0681); +} + +static void rcba_config(void) +{ + /* Set up virtual channel 0 */ + //RCBA32(0x0014) = 0x80000001; + //RCBA32(0x001c) = 0x03128010; + + /* dev irq route register */ + RCBA16(D31IR) = 0x0132; + RCBA16(D30IR) = 0x0146; + RCBA16(D29IR) = 0x0237; + RCBA16(D28IR) = 0x3201; + RCBA16(D27IR) = 0x0146; + + /* Enable IOAPIC */ + RCBA8(OIC) = 0x03; + + /* Disable unused devices */ + RCBA32(FD) |= FD_INTLAN; + + /* Enable PCIe Root Port Clock Gate */ + // RCBA32(0x341c) = 0x00000001; +} + +static void early_ich7_init(void) +{ + uint8_t reg8; + uint32_t reg32; + + // program secondary mlt XXX byte? + pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); + + // reset rtc power status + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); + reg8 &= ~(1 << 2); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); + + // usb transient disconnect + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); + reg8 |= (3 << 0); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); + reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); + reg32 |= (1 << 29) | (1 << 17); + pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); + reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); + reg32 |= (1 << 31) | (1 << 27); + pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); + RCBA32(0x0088) = 0x0011d000; + RCBA16(0x01fc) = 0x060f; + RCBA32(0x01f4) = 0x86000040; + RCBA32(0x0214) = 0x10030549; + RCBA32(0x0218) = 0x00020504; + RCBA8(0x0220) = 0xc5; + reg32 = RCBA32(0x3410); + reg32 |= (1 << 6); + RCBA32(0x3410) = reg32; + reg32 = RCBA32(0x3430); + reg32 &= ~(3 << 0); + reg32 |= (1 << 0); + RCBA32(0x3430) = reg32; + RCBA16(0x0200) = 0x2008; + RCBA8(0x2027) = 0x0d; + RCBA16(0x3e08) |= (1 << 7); + RCBA16(0x3e48) |= (1 << 7); + RCBA32(0x3e0e) |= (1 << 7); + RCBA32(0x3e4e) |= (1 << 7); + + // next step only on ich7m b0 and later: + reg32 = RCBA32(0x2034); + reg32 &= ~(0x0f << 16); + reg32 |= (5 << 16); + RCBA32(0x2034) = reg32; +} + +void mainboard_romstage_entry(unsigned long bist) +{ + int s3resume = 0, boot_mode = 0; + + if (bist == 0) + enable_lapic(); + + ich7_enable_lpc(); + /* Enable SuperIO PM */ + //lpc47m15x_enable_serial(PME_DEV, 0x680); + + //lpc47m15x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); /* 0x3f8 */ + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + + /* Set up the console */ + console_init(); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + if (MCHBAR16(SSKPD) == 0xCAFE) +{ + printk(BIOS_DEBUG, "soft reset detected.\n"); + boot_mode = 1; +} + + /* Perform some early chipset initialization required + * before RAM initialization can work + */ + i945_early_initialization(); + + s3resume = southbridge_detect_s3_resume(); + + /* Enable SPD ROMs and DDR-II DRAM */ + enable_smbus(); + +#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 + dump_spd_registers(); +#endif + + sdram_initialize(s3resume ? 2 : boot_mode, NULL); + + /* Perform some initialization that must run before stage2 */ + early_ich7_init(); + + /* This should probably go away. Until now it is required + * and mainboard specific + */ + rcba_config(); + + /* Chipset Errata! */ + fixup_i945_errata(); + + /* Initialize the internal PCIe links before we go into stage2 */ + i945_late_initialization(s3resume); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/30977 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ea260021dc8033c58f134a5c60cdcae12b44d88 Gerrit-Change-Number: 30977 Gerrit-PatchSet: 1 Gerrit-Owner: junaid <junaidimpex(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/intel/icelake_rvp: Add SMI handlers
by Aamir Bohra (Code Review) 07 Aug '23

07 Aug '23

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32252 Change subject: mb/intel/icelake_rvp: Add SMI handlers ...................................................................... mb/intel/icelake_rvp: Add SMI handlers Add SMI handlers for below SMI events: 1. eSPI SMI event. 2. ACPI enable/disable SMI event -> Add support for EC to configure SMI mask on ACPI disable. -> Add support for EC to configure SCI mask on ACPI enable. 3. Sleep(S3/S5) SMI event -> Add support for EC to configure wake mask for S3/S5 event Change-Id: Ibc0284b99bb2f4807ff2c0ec90b316730b251ddb Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/mainboard/intel/icelake_rvp/Makefile.inc A src/mainboard/intel/icelake_rvp/smihandler.c 2 files changed, 45 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/32252/1 diff --git a/src/mainboard/intel/icelake_rvp/Makefile.inc b/src/mainboard/intel/icelake_rvp/Makefile.inc index 7e74f09..ad9100f 100644 --- a/src/mainboard/intel/icelake_rvp/Makefile.inc +++ b/src/mainboard/intel/icelake_rvp/Makefile.inc @@ -29,6 +29,8 @@ ramstage-y += mainboard.c ramstage-y += board_id.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c + subdirs-y += variants/baseboard CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include diff --git a/src/mainboard/intel/icelake_rvp/smihandler.c b/src/mainboard/intel/icelake_rvp/smihandler.c new file mode 100644 index 0000000..1ba7dee --- /dev/null +++ b/src/mainboard/intel/icelake_rvp/smihandler.c @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/x86/smm.h> +#include <ec/google/chromeec/smm.h> +#include <gpio.h> +#include <soc/gpio.h> +#include <soc/smm.h> +#include <variant/ec.h> + +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + +void mainboard_smi_espi_handler(void) +{ + chromeec_smi_process_events(); +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, + MAINBOARD_EC_S5_WAKE_EVENTS); +} + +int mainboard_smi_apmc(u8 apmc) +{ + chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, + MAINBOARD_EC_SMI_EVENTS); + return 0; +} + +#endif \ No newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/32252 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibc0284b99bb2f4807ff2c0ec90b316730b251ddb Gerrit-Change-Number: 32252 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newchange

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