July 2020 - coreboot-gerrit - mail.coreboot.org

Change in coreboot[master]: [WIP] soc/amd/common: Use configure_scimap()

by Kyösti Mälkki (Code Review)

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43012 ) Change subject: [WIP] soc/amd/common: Use configure_scimap() ...................................................................... [WIP] soc/amd/common: Use configure_scimap() There is little point stashing the SCI trigger register configuration. Remove it to mase SCI and SMI programming more symmetrical. Change-Id: Ie23da79546858282910db65182a6315ade506279 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/common/block/gpio_banks/gpio.c 1 file changed, 12 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/43012/1 diff --git a/src/soc/amd/common/block/gpio_banks/gpio.c b/src/soc/amd/common/block/gpio_banks/gpio.c index 1bcfc8b..141d04f 100644 --- a/src/soc/amd/common/block/gpio_banks/gpio.c +++ b/src/soc/amd/common/block/gpio_banks/gpio.c @@ -40,12 +40,6 @@ configure_gevent_smi(gevent_num, SMI_MODE_SMI, level); } -struct sci_trigger_regs { - uint32_t mask; - uint32_t polarity; - uint32_t level; -}; - /* * For each general purpose event, GPE, the choice of edge/level triggered * event is represented as a single bit in SMI_SCI_LEVEL register. @@ -53,37 +47,24 @@ * In a similar fashion, polarity (rising/falling, hi/lo) of each GPE is * represented as a single bit in SMI_SCI_TRIG register. */ -static void fill_sci_trigger(uint32_t flags, int gpe, struct sci_trigger_regs *regs) +static void program_sci(uint32_t flags, int gevent_num) { - uint32_t mask = 1 << gpe; + struct sci_source sci; - regs->mask |= mask; + sci.scimap = gevent_num; + sci.gpe = gevent_num; if (is_gpio_event_level_triggered(flags)) - regs->level |= mask; + sci.level = SMI_SCI_LVL; else - regs->level &= ~mask; + sci.level = SMI_SCI_EDG; if (is_gpio_event_active_high(flags)) - regs->polarity |= mask; + sci.direction = SMI_SCI_LVL_HIGH; else - regs->polarity &= ~mask; -} + sci.direction = SMI_SCI_LVL_LOW; -/* TODO: See configure_scimap() implementations. */ -static void set_sci_trigger(const struct sci_trigger_regs *regs) -{ - uint32_t value; - - value = smi_read32(SMI_SCI_TRIG); - value &= ~regs->mask; - value |= regs->polarity; - smi_write32(SMI_SCI_TRIG, value); - - value = smi_read32(SMI_SCI_LEVEL); - value &= ~regs->mask; - value |= regs->level; - smi_write32(SMI_SCI_LEVEL, value); + configure_scimap(&sci); } uintptr_t gpio_get_address(gpio_t gpio_num) @@ -175,7 +156,7 @@ __weak void soc_gpio_hook(uint8_t gpio, uint8_t mux) {} -static void set_single_gpio(const struct soc_amd_gpio *g, struct sci_trigger_regs *sci_cfg) +static void set_single_gpio(const struct soc_amd_gpio *g) { static const struct soc_amd_event *gev_tbl; static size_t gev_items; @@ -206,14 +187,12 @@ if (g->flags & GPIO_FLAG_SMI) { program_smi(g->flags, gevent_num); } else if (g->flags & GPIO_FLAG_SCI) { - fill_sci_trigger(g->flags, gevent_num, sci_cfg); - soc_route_sci(gevent_num); + program_sci(g->flags, gevent_num); } } void program_gpios(const struct soc_amd_gpio *gpio_list_ptr, size_t size) { - struct sci_trigger_regs sci_trigger_cfg = { 0 }; size_t i; /* @@ -229,7 +208,7 @@ master_switch_clr(GPIO_MASK_STS_EN | GPIO_INTERRUPT_EN); for (i = 0; i < size; i++) - set_single_gpio(&gpio_list_ptr[i], &sci_trigger_cfg); + set_single_gpio(&gpio_list_ptr[i]); /* * Re-enable interrupt status generation. @@ -239,9 +218,6 @@ * to be missed during boot. */ master_switch_set(GPIO_INTERRUPT_EN); - - /* Set all SCI trigger polarity (high/low) and level (edge/level). */ - set_sci_trigger(&sci_trigger_cfg); } int gpio_interrupt_status(gpio_t gpio) -- To view, visit https://review.coreboot.org/c/coreboot/+/43012 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie23da79546858282910db65182a6315ade506279 Gerrit-Change-Number: 43012 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

14 hours, 19 minutes

3
9
0 0

Change in coreboot[master]: drivers/i2c/tas5825m: Add driver for TI TAS5825M amplifier

by Jeremy Soller (Code Review)

Jeremy Soller has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43614 ) Change subject: drivers/i2c/tas5825m: Add driver for TI TAS5825M amplifier ...................................................................... drivers/i2c/tas5825m: Add driver for TI TAS5825M amplifier This adds a driver for the TI TAS5825M, documentation can be found here: https://www.ti.com/product/TAS5825M This driver expects the mainboard using it to define tas5825m_setup, which uses the tas5825m_* functions to set configuration data. Each mainboard may have very different configuration data, depending on its audio hardware. Tested on system76/addw2 and system76/oryp6, which will be added in a future patch. Signed-off-by: Jeremy Soller <jeremy(a)system76.com> Change-Id: I896e8f272f18e64bfc90f406e7d4163010800aaf --- A src/drivers/i2c/tas5825m/Kconfig A src/drivers/i2c/tas5825m/Makefile.inc A src/drivers/i2c/tas5825m/tas5825m.c A src/drivers/i2c/tas5825m/tas5825m.h 4 files changed, 81 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/43614/1 diff --git a/src/drivers/i2c/tas5825m/Kconfig b/src/drivers/i2c/tas5825m/Kconfig new file mode 100644 index 0000000..0deca17 --- /dev/null +++ b/src/drivers/i2c/tas5825m/Kconfig @@ -0,0 +1,5 @@ +config DRIVERS_I2C_TAS5825M + bool + default n + help + Enable support for TI TAS5825M Amplifier. diff --git a/src/drivers/i2c/tas5825m/Makefile.inc b/src/drivers/i2c/tas5825m/Makefile.inc new file mode 100644 index 0000000..909ffdb --- /dev/null +++ b/src/drivers/i2c/tas5825m/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_I2C_TAS5825M) += tas5825m.c diff --git a/src/drivers/i2c/tas5825m/tas5825m.c b/src/drivers/i2c/tas5825m/tas5825m.c new file mode 100644 index 0000000..2970a8ee --- /dev/null +++ b/src/drivers/i2c/tas5825m/tas5825m.c @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <device/smbus.h> +#include <device/pci.h> +#include "tas5825m.h" + +int tas5825m_write_at(struct device *dev, uint8_t addr, uint8_t value) { + return smbus_write_byte(dev, addr, value); +} + +//TODO: use I2C block write for better performance +int tas5825m_write_block_at(struct device *dev, uint8_t addr, const uint8_t * values, uint8_t length) { + int res = 0; + for (uint8_t i = 0; i < length; i++) { + res = smbus_write_byte(dev, addr + i, values[i]); + if (res < 0) return res; + } + return (int)length; +} + +int tas5825m_set_page(struct device *dev, uint8_t page) { + return tas5825m_write_at(dev, 0x00, page); +} + +int tas5825m_set_book(struct device *dev, uint8_t book) { + int res = tas5825m_set_page(dev, 0x00); + if (res < 0) return res; + return tas5825m_write_at(dev, 0x7F, book); +} + +__weak int tas5825m_setup(struct device *dev) { + printk(BIOS_ERR, "tas5825m: setup not implemented\n"); + return -1; +} + +static void tas5825m_init(struct device *dev) { + if (dev->enabled && dev->path.type == DEVICE_PATH_I2C && + ops_smbus_bus(get_pbus_smbus(dev))) { + printk(BIOS_DEBUG, "tas5825m at %s\n", dev_path(dev)); + int res = tas5825m_setup(dev); + if (res) { + printk(BIOS_ERR, "tas5825m init failed: %d\n", res); + } else { + printk(BIOS_DEBUG, "tas5825m init successful\n"); + } + } +} + +static struct device_operations tas5825m_operations = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .init = tas5825m_init, +}; + +static void tas5825m_enable_dev(struct device *dev) { + dev->ops = &tas5825m_operations; +} + +struct chip_operations drivers_i2c_tas5825m_ops = { + CHIP_NAME("TI TAS5825M Amplifier") + .enable_dev = tas5825m_enable_dev, +}; diff --git a/src/drivers/i2c/tas5825m/tas5825m.h b/src/drivers/i2c/tas5825m/tas5825m.h new file mode 100644 index 0000000..c58f86a --- /dev/null +++ b/src/drivers/i2c/tas5825m/tas5825m.h @@ -0,0 +1,12 @@ +#ifndef TAS5825M_H +#define TAS5825M_H + +#include <device/device.h> + +int tas5825m_write_at(struct device *dev, uint8_t addr, uint8_t value); +int tas5825m_write_block_at(struct device *dev, uint8_t addr, const uint8_t * values, uint8_t length); +int tas5825m_set_page(struct device *dev, uint8_t page); +int tas5825m_set_book(struct device *dev, uint8_t book); +int tas5825m_setup(struct device *dev); + +#endif // TAS5825M_H -- To view, visit https://review.coreboot.org/c/coreboot/+/43614 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I896e8f272f18e64bfc90f406e7d4163010800aaf Gerrit-Change-Number: 43614 Gerrit-PatchSet: 1 Gerrit-Owner: Jeremy Soller <jeremy(a)system76.com> Gerrit-MessageType: newchange

1 day, 6 hours

5
12
0 0

Change in coreboot[master]: soc/intel/cannonlake: Add debugging of a number of FSPM parameters

by Jeremy Soller (Code Review)

Jeremy Soller has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35802 ) Change subject: soc/intel/cannonlake: Add debugging of a number of FSPM parameters ...................................................................... soc/intel/cannonlake: Add debugging of a number of FSPM parameters This implements soc_display_fspm_upd_params for soc/intel/cannonlake Some parameters are available only on Coffee Lake FSP or Comet Lake FSP Tested on System76 galp3-c (Coffee Lake FSP) and System76 galp4 (Comet Lake FSP) Change-Id: I01c7a07ce7446ff762849c64600e728339a4974f Signed-Of-By: Jeremy Soller <jeremy(a)system76.com> --- M src/soc/intel/cannonlake/romstage/romstage.c 1 file changed, 313 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/35802/1 diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index f782f63..af278cf 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -141,3 +141,316 @@ if (!s3wake) save_dimm_info(); } + +void soc_display_fspm_upd_params(const FSPM_UPD *fspm_old_upd, + const FSPM_UPD *fspm_new_upd) +{ + const FSP_M_CONFIG *new; + const FSP_M_CONFIG *old; + + old = &fspm_old_upd->FspmConfig; + new = &fspm_new_upd->FspmConfig; + + /* Display the parameters for MemoryInit */ + printk(BIOS_SPEW, "UPD values for MemoryInit:\n"); + + //TODO: Add more Comet Lake values + fsp_display_upd_value("PlatformMemorySize", 8, + old->PlatformMemorySize, new->PlatformMemorySize); + fsp_display_upd_value("MemorySpdPtr00", 4, old->MemorySpdPtr00, + new->MemorySpdPtr00); + fsp_display_upd_value("MemorySpdPtr01", 4, old->MemorySpdPtr01, + new->MemorySpdPtr01); + fsp_display_upd_value("MemorySpdPtr10", 4, old->MemorySpdPtr10, + new->MemorySpdPtr10); + fsp_display_upd_value("MemorySpdPtr11", 4, old->MemorySpdPtr11, + new->MemorySpdPtr11); + fsp_display_upd_value("MemorySpdDataLen", 2, old->MemorySpdDataLen, + new->MemorySpdDataLen); + fsp_display_upd_value("DqByteMapCh0[0]", 1, old->DqByteMapCh0[0], + new->DqByteMapCh0[0]); + fsp_display_upd_value("DqByteMapCh0[1]", 1, old->DqByteMapCh0[1], + new->DqByteMapCh0[1]); + fsp_display_upd_value("DqByteMapCh0[2]", 1, old->DqByteMapCh0[2], + new->DqByteMapCh0[2]); + fsp_display_upd_value("DqByteMapCh0[3]", 1, old->DqByteMapCh0[3], + new->DqByteMapCh0[3]); + fsp_display_upd_value("DqByteMapCh0[4]", 1, old->DqByteMapCh0[4], + new->DqByteMapCh0[4]); + fsp_display_upd_value("DqByteMapCh0[5]", 1, old->DqByteMapCh0[5], + new->DqByteMapCh0[5]); + fsp_display_upd_value("DqByteMapCh0[6]", 1, old->DqByteMapCh0[6], + new->DqByteMapCh0[6]); + fsp_display_upd_value("DqByteMapCh0[7]", 1, old->DqByteMapCh0[7], + new->DqByteMapCh0[7]); + fsp_display_upd_value("DqByteMapCh0[8]", 1, old->DqByteMapCh0[8], + new->DqByteMapCh0[8]); + fsp_display_upd_value("DqByteMapCh0[9]", 1, old->DqByteMapCh0[9], + new->DqByteMapCh0[9]); + fsp_display_upd_value("DqByteMapCh0[10]", 1, old->DqByteMapCh0[10], + new->DqByteMapCh0[10]); + fsp_display_upd_value("DqByteMapCh0[11]", 1, old->DqByteMapCh0[11], + new->DqByteMapCh0[11]); + fsp_display_upd_value("DqByteMapCh1[0]", 1, old->DqByteMapCh1[0], + new->DqByteMapCh1[0]); + fsp_display_upd_value("DqByteMapCh1[1]", 1, old->DqByteMapCh1[1], + new->DqByteMapCh1[1]); + fsp_display_upd_value("DqByteMapCh1[2]", 1, old->DqByteMapCh1[2], + new->DqByteMapCh1[2]); + fsp_display_upd_value("DqByteMapCh1[3]", 1, old->DqByteMapCh1[3], + new->DqByteMapCh1[3]); + fsp_display_upd_value("DqByteMapCh1[4]", 1, old->DqByteMapCh1[4], + new->DqByteMapCh1[4]); + fsp_display_upd_value("DqByteMapCh1[5]", 1, old->DqByteMapCh1[5], + new->DqByteMapCh1[5]); + fsp_display_upd_value("DqByteMapCh1[6]", 1, old->DqByteMapCh1[6], + new->DqByteMapCh1[6]); + fsp_display_upd_value("DqByteMapCh1[7]", 1, old->DqByteMapCh1[7], + new->DqByteMapCh1[7]); + fsp_display_upd_value("DqByteMapCh1[8]", 1, old->DqByteMapCh1[8], + new->DqByteMapCh1[8]); + fsp_display_upd_value("DqByteMapCh1[9]", 1, old->DqByteMapCh1[9], + new->DqByteMapCh1[9]); + fsp_display_upd_value("DqByteMapCh1[10]", 1, old->DqByteMapCh1[10], + new->DqByteMapCh1[10]); + fsp_display_upd_value("DqByteMapCh1[11]", 1, old->DqByteMapCh1[11], + new->DqByteMapCh1[11]); + fsp_display_upd_value("DqsMapCpu2DramCh0[0]", 1, + old->DqsMapCpu2DramCh0[0], new->DqsMapCpu2DramCh0[0]); + fsp_display_upd_value("DqsMapCpu2DramCh0[1]", 1, + old->DqsMapCpu2DramCh0[1], new->DqsMapCpu2DramCh0[1]); + fsp_display_upd_value("DqsMapCpu2DramCh0[2]", 1, + old->DqsMapCpu2DramCh0[2], new->DqsMapCpu2DramCh0[2]); + fsp_display_upd_value("DqsMapCpu2DramCh0[3]", 1, + old->DqsMapCpu2DramCh0[3], new->DqsMapCpu2DramCh0[3]); + fsp_display_upd_value("DqsMapCpu2DramCh0[4]", 1, + old->DqsMapCpu2DramCh0[4], new->DqsMapCpu2DramCh0[4]); + fsp_display_upd_value("DqsMapCpu2DramCh0[5]", 1, + old->DqsMapCpu2DramCh0[5], new->DqsMapCpu2DramCh0[5]); + fsp_display_upd_value("DqsMapCpu2DramCh0[6]", 1, + old->DqsMapCpu2DramCh0[6], new->DqsMapCpu2DramCh0[6]); + fsp_display_upd_value("DqsMapCpu2DramCh0[7]", 1, + old->DqsMapCpu2DramCh0[7], new->DqsMapCpu2DramCh0[7]); + fsp_display_upd_value("DqsMapCpu2DramCh1[0]", 1, + old->DqsMapCpu2DramCh1[0], new->DqsMapCpu2DramCh1[0]); + fsp_display_upd_value("DqsMapCpu2DramCh1[1]", 1, + old->DqsMapCpu2DramCh1[1], new->DqsMapCpu2DramCh1[1]); + fsp_display_upd_value("DqsMapCpu2DramCh1[2]", 1, + old->DqsMapCpu2DramCh1[2], new->DqsMapCpu2DramCh1[2]); + fsp_display_upd_value("DqsMapCpu2DramCh1[3]", 1, + old->DqsMapCpu2DramCh1[3], new->DqsMapCpu2DramCh1[3]); + fsp_display_upd_value("DqsMapCpu2DramCh1[4]", 1, + old->DqsMapCpu2DramCh1[4], new->DqsMapCpu2DramCh1[4]); + fsp_display_upd_value("DqsMapCpu2DramCh1[5]", 1, + old->DqsMapCpu2DramCh1[5], new->DqsMapCpu2DramCh1[5]); + fsp_display_upd_value("DqsMapCpu2DramCh1[6]", 1, + old->DqsMapCpu2DramCh1[6], new->DqsMapCpu2DramCh1[6]); + fsp_display_upd_value("DqsMapCpu2DramCh1[7]", 1, + old->DqsMapCpu2DramCh1[7], new->DqsMapCpu2DramCh1[7]); + fsp_display_upd_value("RcompResistor[0]", 2, old->RcompResistor[0], + new->RcompResistor[0]); + fsp_display_upd_value("RcompResistor[1]", 2, old->RcompResistor[1], + new->RcompResistor[1]); + fsp_display_upd_value("RcompResistor[2]", 2, old->RcompResistor[2], + new->RcompResistor[2]); + fsp_display_upd_value("RcompTarget[0]", 2, old->RcompTarget[0], + new->RcompTarget[0]); + fsp_display_upd_value("RcompTarget[1]", 2, old->RcompTarget[1], + new->RcompTarget[1]); + fsp_display_upd_value("RcompTarget[2]", 2, old->RcompTarget[2], + new->RcompTarget[2]); + fsp_display_upd_value("RcompTarget[3]", 2, old->RcompTarget[3], + new->RcompTarget[3]); + fsp_display_upd_value("RcompTarget[4]", 2, old->RcompTarget[4], + new->RcompTarget[4]); + fsp_display_upd_value("DqPinsInterleaved", 1, old->DqPinsInterleaved, + new->DqPinsInterleaved); + fsp_display_upd_value("CaVrefConfig", 1, old->CaVrefConfig, + new->CaVrefConfig); + fsp_display_upd_value("SmramMask", 1, old->SmramMask, new->SmramMask); +#if CONFIG(SOC_INTEL_COMETLAKE) + // Value only exists on Comet Lake + fsp_display_upd_value("MrcTimeMeasure", 1, old->MrcTimeMeasure, + new->MrcTimeMeasure); +#endif + fsp_display_upd_value("MrcFastBoot", 1, old->MrcFastBoot, + new->MrcFastBoot); + fsp_display_upd_value("RmtPerTask", 1, old->RmtPerTask, + new->RmtPerTask); + fsp_display_upd_value("TrainTrace", 1, old->TrainTrace, + new->TrainTrace); + fsp_display_upd_value("IedSize", 4, old->IedSize, new->IedSize); + fsp_display_upd_value("TsegSize", 4, old->TsegSize, new->TsegSize); + fsp_display_upd_value("MmioSize", 2, old->MmioSize, new->MmioSize); + fsp_display_upd_value("ProbelessTrace", 1, old->ProbelessTrace, + new->ProbelessTrace); + fsp_display_upd_value("GdxcIotSize", 1, old->GdxcIotSize, + new->GdxcIotSize); + fsp_display_upd_value("GdxcMotSize", 1, old->GdxcMotSize, + new->GdxcMotSize); + fsp_display_upd_value("SmbusEnable", 1, old->SmbusEnable, + new->SmbusEnable); + fsp_display_upd_value("SpdAddressTable[0]", 1, old->SpdAddressTable[0], + new->SpdAddressTable[0]); + fsp_display_upd_value("SpdAddressTable[1]", 1, old->SpdAddressTable[1], + new->SpdAddressTable[1]); + fsp_display_upd_value("SpdAddressTable[2]", 1, old->SpdAddressTable[2], + new->SpdAddressTable[2]); + fsp_display_upd_value("SpdAddressTable[3]", 1, old->SpdAddressTable[3], + new->SpdAddressTable[3]); + fsp_display_upd_value("PlatformDebugConsent", 1, + old->PlatformDebugConsent, new->PlatformDebugConsent); + fsp_display_upd_value("DciUsb3TypecUfpDbg", 1, old->DciUsb3TypecUfpDbg, + new->DciUsb3TypecUfpDbg); + fsp_display_upd_value("PchTraceHubMode", 1, old->PchTraceHubMode, + new->PchTraceHubMode); + fsp_display_upd_value("PchTraceHubMemReg0Size", 1, + old->PchTraceHubMemReg0Size, new->PchTraceHubMemReg0Size); + fsp_display_upd_value("PchTraceHubMemReg1Size", 1, + old->PchTraceHubMemReg1Size, new->PchTraceHubMemReg1Size); + // Skip PchPreMemRsvd[9] + fsp_display_upd_value("IgdDvmt50PreAlloc", 1, old->IgdDvmt50PreAlloc, + new->IgdDvmt50PreAlloc); + fsp_display_upd_value("InternalGfx", 1, old->InternalGfx, + new->InternalGfx); + fsp_display_upd_value("ApertureSize", 1, old->ApertureSize, + new->ApertureSize); + fsp_display_upd_value("UserBd", 1, old->UserBd, + new->UserBd); + fsp_display_upd_value("SaGv", 1, old->SaGv, + new->SaGv); + // Skip UnusedUpdSpace0 + fsp_display_upd_value("DdrFreqLimit", 2, old->DdrFreqLimit, + new->DdrFreqLimit); + fsp_display_upd_value("FreqSaGvLow", 2, old->FreqSaGvLow, + new->FreqSaGvLow); +#if ! CONFIG(SOC_INTEL_COMETLAKE) + // Value does not exist on Comet Lake + fsp_display_upd_value("FreqSaGvMid", 2, old->FreqSaGvMid, + new->FreqSaGvMid); +#endif + fsp_display_upd_value("RMT", 1, old->RMT, + new->RMT); + fsp_display_upd_value("DisableDimmChannel0", 1, + old->DisableDimmChannel0, new->DisableDimmChannel0); + fsp_display_upd_value("DisableDimmChannel1", 1, + old->DisableDimmChannel1, new->DisableDimmChannel1); + fsp_display_upd_value("ScramblerSupport", 1, old->ScramblerSupport, + new->ScramblerSupport); + fsp_display_upd_value("SkipMpInit", 1, old->SkipMpInit, + new->SkipMpInit); + // Skip UnusedUpdSpace1[15] + fsp_display_upd_value("SpdProfileSelected", 1, + old->SpdProfileSelected, new->SpdProfileSelected); + fsp_display_upd_value("RefClk", 1, old->RefClk, + new->RefClk); + fsp_display_upd_value("VddVoltage", 2, old->VddVoltage, + new->VddVoltage); + fsp_display_upd_value("Ratio", 1, old->Ratio, + new->Ratio); + fsp_display_upd_value("OddRatioMode", 1, old->OddRatioMode, + new->OddRatioMode); + fsp_display_upd_value("tCL", 1, old->tCL, + new->tCL); + fsp_display_upd_value("tCWL", 1, old->tCWL, + new->tCWL); + fsp_display_upd_value("tRCDtRP", 1, old->tRCDtRP, + new->tRCDtRP); + fsp_display_upd_value("tRRD", 1, old->tRRD, + new->tRRD); + fsp_display_upd_value("tFAW", 2, old->tFAW, + new->tFAW); + fsp_display_upd_value("tRAS", 2, old->tRAS, + new->tRAS); + fsp_display_upd_value("tREFI", 2, old->tREFI, + new->tREFI); + fsp_display_upd_value("tRFC", 2, old->tRFC, + new->tRFC); + fsp_display_upd_value("tRTP", 1, old->tRTP, + new->tRTP); + fsp_display_upd_value("tWR", 1, old->tWR, + new->tWR); + fsp_display_upd_value("NModeSupport", 1, old->NModeSupport, + new->NModeSupport); + fsp_display_upd_value("DllBwEn0", 1, old->DllBwEn0, + new->DllBwEn0); + fsp_display_upd_value("DllBwEn1", 1, old->DllBwEn1, + new->DllBwEn1); + fsp_display_upd_value("DllBwEn2", 1, old->DllBwEn2, + new->DllBwEn2); + fsp_display_upd_value("DllBwEn3", 1, old->DllBwEn3, + new->DllBwEn3); + fsp_display_upd_value("IsvtIoPort", 1, old->IsvtIoPort, + new->IsvtIoPort); + fsp_display_upd_value("CpuTraceHubMode", 1, old->CpuTraceHubMode, + new->CpuTraceHubMode); + fsp_display_upd_value("CpuTraceHubMemReg0Size", 1, + old->CpuTraceHubMemReg0Size, new->CpuTraceHubMemReg0Size); + fsp_display_upd_value("CpuTraceHubMemReg1Size", 1, + old->CpuTraceHubMemReg1Size, new->CpuTraceHubMemReg1Size); + fsp_display_upd_value("PeciC10Reset", 1, old->PeciC10Reset, + new->PeciC10Reset); + fsp_display_upd_value("PeciSxReset", 1, old->PeciSxReset, + new->PeciSxReset); + // Skip UnusedUpdSpace2[4] + fsp_display_upd_value("PchHdaEnable", 1, old->PchHdaEnable, + new->PchHdaEnable); + fsp_display_upd_value("PchIshEnable", 1, old->PchIshEnable, + new->PchIshEnable); + fsp_display_upd_value("HeciTimeouts", 1, old->HeciTimeouts, + new->HeciTimeouts); + // Skip UnusedUpdSpace3 + fsp_display_upd_value("Heci1BarAddress", 4, old->Heci1BarAddress, + new->Heci1BarAddress); + fsp_display_upd_value("Heci2BarAddress", 4, old->Heci2BarAddress, + new->Heci2BarAddress); + fsp_display_upd_value("Heci3BarAddress", 4, old->Heci3BarAddress, + new->Heci3BarAddress); + fsp_display_upd_value("SgDelayAfterPwrEn", 2, old->SgDelayAfterPwrEn, + new->SgDelayAfterPwrEn); + fsp_display_upd_value("SgDelayAfterHoldReset", 2, old->SgDelayAfterHoldReset, + new->SgDelayAfterHoldReset); + fsp_display_upd_value("MmioSizeAdjustment", 2, old->MmioSizeAdjustment, + new->MmioSizeAdjustment); + fsp_display_upd_value("DmiGen3ProgramStaticEq", 1, + old->DmiGen3ProgramStaticEq, new->DmiGen3ProgramStaticEq); + fsp_display_upd_value("Peg0Enable", 1, old->Peg0Enable, + new->Peg0Enable); + fsp_display_upd_value("Peg1Enable", 1, old->Peg1Enable, + new->Peg1Enable); + fsp_display_upd_value("Peg2Enable", 1, old->Peg2Enable, + new->Peg2Enable); + fsp_display_upd_value("Peg3Enable", 1, old->Peg3Enable, + new->Peg3Enable); + fsp_display_upd_value("Peg0MaxLinkSpeed", 1, old->Peg0MaxLinkSpeed, + new->Peg0MaxLinkSpeed); + fsp_display_upd_value("Peg1MaxLinkSpeed", 1, old->Peg1MaxLinkSpeed, + new->Peg1MaxLinkSpeed); + fsp_display_upd_value("Peg2MaxLinkSpeed", 1, old->Peg2MaxLinkSpeed, + new->Peg2MaxLinkSpeed); + fsp_display_upd_value("Peg3MaxLinkSpeed", 1, old->Peg3MaxLinkSpeed, + new->Peg3MaxLinkSpeed); + fsp_display_upd_value("Peg0MaxLinkWidth", 1, old->Peg0MaxLinkWidth, + new->Peg0MaxLinkWidth); + fsp_display_upd_value("Peg1MaxLinkWidth", 1, old->Peg1MaxLinkWidth, + new->Peg1MaxLinkWidth); + fsp_display_upd_value("Peg2MaxLinkWidth", 1, old->Peg2MaxLinkWidth, + new->Peg2MaxLinkWidth); + fsp_display_upd_value("Peg3MaxLinkWidth", 1, old->Peg3MaxLinkWidth, + new->Peg3MaxLinkWidth); + fsp_display_upd_value("Peg0PowerDownUnusedLanes", 1, + old->Peg0PowerDownUnusedLanes, new->Peg0PowerDownUnusedLanes); + fsp_display_upd_value("Peg1PowerDownUnusedLanes", 1, + old->Peg1PowerDownUnusedLanes, new->Peg1PowerDownUnusedLanes); + fsp_display_upd_value("Peg2PowerDownUnusedLanes", 1, + old->Peg2PowerDownUnusedLanes, new->Peg2PowerDownUnusedLanes); + fsp_display_upd_value("Peg3PowerDownUnusedLanes", 1, + old->Peg3PowerDownUnusedLanes, new->Peg3PowerDownUnusedLanes); + fsp_display_upd_value("InitPcieAspmAfterOprom", 1, + old->InitPcieAspmAfterOprom, new->InitPcieAspmAfterOprom); + fsp_display_upd_value("PegDisableSpreadSpectrumClocking", 1, + old->PegDisableSpreadSpectrumClocking, + new->PegDisableSpreadSpectrumClocking); + // Skip UnusedUpdSpace4[3] + //TODO: Offset 0x128 and up +} -- To view, visit https://review.coreboot.org/c/coreboot/+/35802 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I01c7a07ce7446ff762849c64600e728339a4974f Gerrit-Change-Number: 35802 Gerrit-PatchSet: 1 Gerrit-Owner: Jeremy Soller <jackpot51(a)gmail.com> Gerrit-MessageType: newchange

2 days, 20 hours

4
8
0 0

Change in coreboot[master]: tests: Add lib/bootmem-test test case

by Jan Dabros (Code Review)

Jan Dabros has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43510 ) Change subject: tests: Add lib/bootmem-test test case ...................................................................... tests: Add lib/bootmem-test test case Signed-off-by: Jan Dabros <jsd(a)semihalf.com> Change-Id: Ic1e539061ee5051d4158712a8a981a475ea7458a --- M tests/lib/Makefile.inc A tests/lib/bootmem-test.c A tests/lib/bootmem-test.ld 3 files changed, 296 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/43510/1 diff --git a/tests/lib/Makefile.inc b/tests/lib/Makefile.inc index dae406a..69e3fd4 100644 --- a/tests/lib/Makefile.inc +++ b/tests/lib/Makefile.inc @@ -4,6 +4,7 @@ tests-y += b64_decode-test tests-y += hexstrtobin-test tests-y += memrange-test +tests-y += bootmem-test string-test-srcs += tests/lib/string-test.c string-test-srcs += src/lib/string.c @@ -19,3 +20,10 @@ memrange-test-srcs += src/lib/memrange.c memrange-test-srcs += tests/stubs/console.c memrange-test-srcs += tests/mocks/device/device_util.c + +bootmem-test-srcs += tests/lib/bootmem-test.c +bootmem-test-srcs += src/lib/bootmem.c +bootmem-test-srcs += src/lib/memrange.c +bootmem-test-srcs += tests/stubs/console.c +bootmem-test-srcs += tests/mocks/device/device_util.c +bootmem-test-cflags += -Wl,--script=tests/lib/bootmem-test.ld diff --git a/tests/lib/bootmem-test.c b/tests/lib/bootmem-test.c new file mode 100644 index 0000000..8082720 --- /dev/null +++ b/tests/lib/bootmem-test.c @@ -0,0 +1,272 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <tests/test.h> +#include <stdlib.h> + +#include <bootmem.h> +#include <commonlib/coreboot_tables.h> +#include <device/device.h> +#include <device/resource.h> +#include <memrange.h> +#include <symbols.h> + +/* Stubs defined to satisfy linker dependencies */ +void cbmem_add_bootmem(void) +{ +} + +void bootmem_arch_add_ranges(void) +{ +} + +struct bootmem_ranges_t { + uint64_t start; + uint64_t size; + uint32_t type; +}; + +struct bootmem_ranges_t *os_ranges; +struct bootmem_ranges_t *ranges; + +/* See tests/lib/bootmem-test.ld for boundaries definitions */ +extern u8 _ramstage_size[]; +#define PROGRAM_START ((uintptr_t)_program) +#define RAMSTAGE_SIZE ((uintptr_t)_ramstage_size) +#define CACHEABLE_START PROGRAM_START +#define CACHEABLE_SIZE (1ULL << 32) +#define CACHEABLE_END (CACHEABLE_START + CACHEABLE_SIZE) +#define RESERVED_START (1ULL << 32) +#define RESERVED_SIZE 0x100000 +#define RESERVED_END (RESERVED_START + RESERVED_SIZE) +#define FIRST (RESERVED_END - CACHEABLE_START) + +/* Note that second region overlaps first */ +struct resource res_mock[] = { + { .base = CACHEABLE_START, .size = CACHEABLE_SIZE, .next = &res_mock[1], + .flags = IORESOURCE_CACHEABLE | IORESOURCE_MEM }, + { .base = RESERVED_START, .size = RESERVED_SIZE, .next = NULL, + .flags = IORESOURCE_RESERVE | IORESOURCE_MEM } +}; + +/* Device simulating RAM */ +struct device mem_device_mock = { + .enabled = 1, + .resource_list = res_mock, + .next = NULL +}; + +/* Simplified version for the purpose of tests */ +static uint32_t bootmem_to_lb_tag(const enum bootmem_type tag) +{ + switch (tag) { + case BM_MEM_RAM: + return LB_MEM_RAM; + case BM_MEM_RESERVED: + return LB_MEM_RESERVED; + default: + return LB_MEM_RESERVED; + } +} + +/* Bootmem layout for bootmem tests + * + * Regions marked with asteriks (***) are not visible for OS + * + * +-------+----CACHEABLE_MEMORY---------+-+ <-0x10000000 + * | | ***PROGRAM*** | | + * | +-----------------------------+ | <-0x10040000 + * | | ***STACK*** | | + * | +-----------------------------+ | <-0x10041000 + * | | + * | | + * | | + * | +-------RESERVED_MEMORY-------+ | <-0x100000000 + * | | | | + * | | | | + * | | | | + * | +-----------------------------+ | <-0x100100000 + * | | + * | | + * +---------------------------------------+ <-0x110000000 + * + */ +static int test_basic_setup(void **state) +{ + os_ranges = (struct bootmem_ranges_t *)malloc(3 * sizeof(*os_ranges)); + + if (!os_ranges) + return -1; + + os_ranges[0].start = CACHEABLE_START; + os_ranges[0].size = RESERVED_START - CACHEABLE_START; + os_ranges[0].type = BM_MEM_RAM; + + os_ranges[1].start = RESERVED_START; + os_ranges[1].size = RESERVED_SIZE; + os_ranges[1].type = BM_MEM_RESERVED; + + os_ranges[2].start = RESERVED_END; + os_ranges[2].size = CACHEABLE_END - RESERVED_END; + os_ranges[2].type = BM_MEM_RAM; + + return 0; +} + +static int test_basic_teardown(void **state) +{ + free(os_ranges); + + return 0; +} + +/* This test need to be run first, in order to use bootmem library API */ +static void test_bootmem_write_mem_table(void **state) +{ + int i; + struct lb_memory *lb_mem; + + will_return_always(search_global_resources, &mem_device_mock); + + /* Allocate space for 5 lb_mem entries to be safe */ + lb_mem = malloc(sizeof(*lb_mem) + 5 * sizeof(struct lb_memory_range)); + + bootmem_write_memory_table(lb_mem); + + /* There should be only three entries visible in coreboot table */ + assert_int_equal(lb_mem->size, 3 * sizeof(struct lb_memory_range)); + + for (i = 0; i < lb_mem->size / sizeof(struct lb_memory_range); i++) { + assert_int_equal(unpack_lb64(lb_mem->map[i].start), os_ranges[i].start); + assert_int_equal(unpack_lb64(lb_mem->map[i].size), os_ranges[i].size); + assert_int_equal(lb_mem->map[i].type, bootmem_to_lb_tag(os_ranges[i].type)); + } + + free(lb_mem); +} + +int os_bootmem_walk_cnt; +int bootmem_walk_cnt; + +static bool verify_os_bootmem_walk(const struct range_entry *r, void *arg) +{ + assert_int_equal(range_entry_base(r), os_ranges[os_bootmem_walk_cnt].start); + assert_int_equal(range_entry_size(r), os_ranges[os_bootmem_walk_cnt].size); + assert_int_equal(range_entry_tag(r), os_ranges[os_bootmem_walk_cnt].type); + + os_bootmem_walk_cnt++; + + return true; +} + +static bool verify_bootmem_walk(const struct range_entry *r, void *arg) +{ + assert_int_equal(range_entry_base(r), ranges[bootmem_walk_cnt].start); + assert_int_equal(range_entry_size(r), ranges[bootmem_walk_cnt].size); + assert_int_equal(range_entry_tag(r), ranges[bootmem_walk_cnt].type); + + bootmem_walk_cnt++; + + return true; +} + +static int test_bootmem_walk_setup(void **state) +{ + if (test_basic_setup(state) < 0) + return -1; + + /* program and stack regions should be merged since they are neighbors */ + ranges = (struct bootmem_ranges_t *)malloc(4 * sizeof(*os_ranges)); + + ranges[0].start = PROGRAM_START; + ranges[0].size = RAMSTAGE_SIZE; + ranges[0].type = BM_MEM_RAMSTAGE; + + ranges[1].start = CACHEABLE_START + RAMSTAGE_SIZE; + ranges[1].size = RESERVED_START - ranges[1].start; + ranges[1].type = BM_MEM_RAM; + + ranges[2].start = RESERVED_START; + ranges[2].size = RESERVED_SIZE; + ranges[2].type = BM_MEM_RESERVED; + + ranges[3].start = RESERVED_END; + ranges[3].size = CACHEABLE_END - RESERVED_END; + ranges[3].type = BM_MEM_RAM; + + os_bootmem_walk_cnt = 0; + bootmem_walk_cnt = 0; + + return 0; +} + +static int test_bootmem_walk_teardown(void **state) +{ + test_basic_teardown(state); + + free(ranges); + + return 0; +} + +static void test_bootmem_walk(void **state) +{ + bootmem_walk_os_mem(verify_os_bootmem_walk, NULL); + bootmem_walk(verify_bootmem_walk, NULL); + + assert_int_equal(os_bootmem_walk_cnt, 3); + assert_int_equal(bootmem_walk_cnt, 4); +} + +static void test_bootmem_region_targets_type(void **state) +{ + int ret; + + ret = bootmem_region_targets_type(PROGRAM_START, RAMSTAGE_SIZE, BM_MEM_RAMSTAGE); + assert_int_equal(ret, 1); + + /* Below range covers two differently tagged regions */ + ret = bootmem_region_targets_type(PROGRAM_START, RAMSTAGE_SIZE, BM_MEM_RAMSTAGE + 1); + assert_int_equal(ret, 0); +} + +static void test_bootmem_allocate_buffer(void **state) +{ + void *buf; + + /* All allocated buffers should be below 32bit boundary */ + buf = bootmem_allocate_buffer((1ULL << 32)); + assert_null(buf); + + /* Try too big size for our BM_MEM_RAM range below 32bit boundary */ + buf = bootmem_allocate_buffer(RESERVED_START - PROGRAM_START); + assert_null(buf); + + /* Two working cases */ + buf = bootmem_allocate_buffer(0xE0000000); + assert_non_null(buf); + assert_in_range((uintptr_t)buf, CACHEABLE_START + RAMSTAGE_SIZE, RESERVED_START); + + buf = bootmem_allocate_buffer(0xF000000); + assert_non_null(buf); + assert_in_range((uintptr_t)buf, CACHEABLE_START + RAMSTAGE_SIZE, RESERVED_START); + + /* Run out of memory for new allocations */ + buf = bootmem_allocate_buffer(0x1000000); + assert_null(buf); +} + +int main(void) +{ + const struct CMUnitTest tests[] = { + cmocka_unit_test_setup_teardown(test_bootmem_write_mem_table, + test_basic_setup, + test_basic_teardown), + cmocka_unit_test_setup_teardown(test_bootmem_walk, + test_bootmem_walk_setup, + test_bootmem_walk_teardown), + cmocka_unit_test(test_bootmem_allocate_buffer), + cmocka_unit_test(test_bootmem_region_targets_type) + }; + + return cmocka_run_group_tests(tests, NULL, NULL); +} diff --git a/tests/lib/bootmem-test.ld b/tests/lib/bootmem-test.ld new file mode 100644 index 0000000..eefef63 --- /dev/null +++ b/tests/lib/bootmem-test.ld @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * Below values needs to be in sync with tests/lib/bootmem-test.c code, + * since there are some assumptions about overlapping regions, neighboring + * ones etc. + */ +SECTIONS { + _program = 0x10000000; + _eprogram = _program + 0x40000; + _stack = _eprogram; + _estack = _stack + 0x1000; + _ramstage_size = _estack - _program; +} +/* Below instruction is just for the default script not being overwritten by this helper */ +INSERT AFTER .rodata; -- To view, visit https://review.coreboot.org/c/coreboot/+/43510 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1e539061ee5051d4158712a8a981a475ea7458a Gerrit-Change-Number: 43510 Gerrit-PatchSet: 1 Gerrit-Owner: Jan Dabros <jsd(a)semihalf.com> Gerrit-MessageType: newchange

4 days, 4 hours

5
31
0 0

Change in coreboot[master]: mb/ocp/tiogapass: Add UART init in bootblock

by David Hendricks (Code Review)

Hello Andrey Petrov, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/39270 to review the following change. Change subject: mb/ocp/tiogapass: Add UART init in bootblock ...................................................................... mb/ocp/tiogapass: Add UART init in bootblock Based off code from CB:38840 Signed-off-by: Andrey Petrov <anpetrov(a)fb.com> Signed-off-by: David Hendricks <dhendrix(a)fb.com> Change-Id: I9a5c17e29173110429d66ec551be5a77b1c15538 --- M src/mainboard/ocp/tiogapass/Kconfig M src/mainboard/ocp/tiogapass/Makefile.inc A src/mainboard/ocp/tiogapass/bootblock.c M src/soc/intel/xeon_sp/bootblock/bootblock.c 4 files changed, 49 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/39270/1 diff --git a/src/mainboard/ocp/tiogapass/Kconfig b/src/mainboard/ocp/tiogapass/Kconfig index dfa8f54..0a35697 100644 --- a/src/mainboard/ocp/tiogapass/Kconfig +++ b/src/mainboard/ocp/tiogapass/Kconfig @@ -25,6 +25,7 @@ select SOC_INTEL_XEON_SP select MAINBOARD_USES_FSP2_0 select FSP_CAR + select SUPERIO_ASPEED_AST2400 config MAINBOARD_DIR string diff --git a/src/mainboard/ocp/tiogapass/Makefile.inc b/src/mainboard/ocp/tiogapass/Makefile.inc index f5ea591..ae5fb70 100644 --- a/src/mainboard/ocp/tiogapass/Makefile.inc +++ b/src/mainboard/ocp/tiogapass/Makefile.inc @@ -15,6 +15,8 @@ ## GNU General Public License for more details. ## +bootblock-y += bootblock.c + ramstage-y += ramstage.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c diff --git a/src/mainboard/ocp/tiogapass/bootblock.c b/src/mainboard/ocp/tiogapass/bootblock.c new file mode 100644 index 0000000..bed8b1a --- /dev/null +++ b/src/mainboard/ocp/tiogapass/bootblock.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include <bootblock_common.h> +#include <console/console.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <intelblocks/lpc_lib.h> +#include <intelblocks/pcr.h> +#include <intelblocks/uart.h> +#include <soc/pci_devs.h> +#include <superio/aspeed/ast2400/ast2400.h> +#include <superio/aspeed/common/aspeed.h> + +#define PID_DMI 0xef + +void bootblock_mainboard_init(void) +{ + /* + * Set up decoding windows on PCH over PCR. The CPUs use two of AST2500 SIO ports, + * one is connected to debug header and another is used as SOL. + */ + pcr_write32(PID_DMI, PCR_DMI_LPCIOD, (0 << 0) | (1 << 4)); + pcr_write32(PID_DMI, PCR_DMI_LPCIOE, (1 << 0) | (1 << 1)); + /* for unidentified reason lpc_io_setup_comm_a_b() doesn't work */ + /* enable com1 and com2 and 0x3f8 and 0x2f8, and 0x2e */ + pci_mmio_write_config32(PCH_DEV_LPC, 0x80, + (1<<28) | (1<<16) | (1<<17) | (0 << 0) | (1 << 4)); + + const pnp_devfn_t serial_dev = PNP_DEV(0x2e, AST2400_SUART1); + aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE); + + if (CONFIG(BOOTBLOCK_CONSOLE)) { + console_init(); + } +} diff --git a/src/soc/intel/xeon_sp/bootblock/bootblock.c b/src/soc/intel/xeon_sp/bootblock/bootblock.c index 9eb7ff9..a3b7bce 100644 --- a/src/soc/intel/xeon_sp/bootblock/bootblock.c +++ b/src/soc/intel/xeon_sp/bootblock/bootblock.c @@ -15,11 +15,11 @@ */ #include <bootblock_common.h> +#include <console/console.h> #include <device/pci.h> #include <FsptUpd.h> #include <intelblocks/fast_spi.h> #include <soc/iomap.h> -#include <console/console.h> const FSPT_UPD temp_ram_init_params = { .FspUpdHeader = { @@ -56,6 +56,9 @@ void bootblock_soc_init(void) { - if (CONFIG(BOOTBLOCK_CONSOLE)) + bootblock_mainboard_init(); + + if (CONFIG(BOOTBLOCK_CONSOLE)) { printk(BIOS_DEBUG, "FSP TempRamInit successful...\n"); + } } -- To view, visit https://review.coreboot.org/c/coreboot/+/39270 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9a5c17e29173110429d66ec551be5a77b1c15538 Gerrit-Change-Number: 39270 Gerrit-PatchSet: 1 Gerrit-Owner: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 days, 8 hours

4
5
0 0

Change in coreboot[master]: mb/acer/aspire_vn7_572g: Adds support for an Acer laptop Adds initial...

by Benjamin Doron (Code Review)

Benjamin Doron has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35523 ) Change subject: mb/acer/aspire_vn7_572g: Adds support for an Acer laptop Adds initial, rudimentary support for Acer Aspire VN7-572G. May not boot correctly or at all. For testing purposes only. ...................................................................... mb/acer/aspire_vn7_572g: Adds support for an Acer laptop Adds initial, rudimentary support for Acer Aspire VN7-572G. May not boot correctly or at all. For testing purposes only. Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/acpi_tables.c A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/mainboard.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 18 files changed, 1,282 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/1 diff --git a/src/mainboard/acer/Kconfig b/src/mainboard/acer/Kconfig new file mode 100644 index 0000000..f56a2a2 --- /dev/null +++ b/src/mainboard/acer/Kconfig @@ -0,0 +1,16 @@ +if VENDOR_ACER + +choice + prompt "Mainboard model" + +source "src/mainboard/acer/*/Kconfig.name" + +endchoice + +source "src/mainboard/acer/*/Kconfig" + +config MAINBOARD_VENDOR + string "Mainboard Vendor" + default "Acer" + +endif # VENDOR_ACER diff --git a/src/mainboard/acer/Kconfig.name b/src/mainboard/acer/Kconfig.name new file mode 100644 index 0000000..bb177f9 --- /dev/null +++ b/src/mainboard/acer/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_ACER + bool "Acer" diff --git a/src/mainboard/acer/aspire_vn7_572g/Kconfig b/src/mainboard/acer/aspire_vn7_572g/Kconfig new file mode 100644 index 0000000..4b3c127 --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/Kconfig @@ -0,0 +1,68 @@ +if BOARD_ACER_VN7_572G + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SYSTEM_TYPE_LAPTOP + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SOC_INTEL_SKYLAKE + select MAINBOARD_USES_FSP2_0 + select SPD_READ_BY_WORD + select MAINBOARD_HAS_LPC_TPM + select NO_POST # This platform has no way to see POST codes so disable them by default. + +config IRQ_SLOT_COUNT + int + default 18 + +config MAINBOARD_VENDOR + string + default "Acer" + +config MAINBOARD_FAMILY + string + default "Aspire V Nitro" + +config MAINBOARD_PART_NUMBER + string + default "Aspire VN7-572G" + +config MAINBOARD_DIR + string + default "acer/aspire_vn7_572g" + +config DEVICETREE + string + default "devicetree.cb" + +config MAX_CPUS + int + default 4 + +config VGA_BIOS_ID + string + default "8086,1916" + +config DIMM_MAX + int + default 2 + +config DIMM_SPD_SIZE + int + default 512 + +config CPU_MICROCODE_CBFS_LEN + hex + default 0x18000 + +config CPU_MICROCODE_CBFS_LOC + hex + default 0xFFE115A0 + +config CBFS_SIZE + hex + default 0x5c0000 + +endif diff --git a/src/mainboard/acer/aspire_vn7_572g/Kconfig.name b/src/mainboard/acer/aspire_vn7_572g/Kconfig.name new file mode 100644 index 0000000..b881680 --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ACER_VN7_572G + bool "Aspire VN7-572G" diff --git a/src/mainboard/acer/aspire_vn7_572g/Makefile.inc b/src/mainboard/acer/aspire_vn7_572g/Makefile.inc new file mode 100644 index 0000000..35f0f6c --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/Makefile.inc @@ -0,0 +1,17 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2015 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-y += ramstage.c +ramstage-y += hda_verb.c diff --git a/src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl b/src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl new file mode 100644 index 0000000..2eed489 --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl @@ -0,0 +1,328 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Name (EMBA, 0xFE800000) + +Device (EC0) +{ + Name (_HID, EisaId ("PNP0C09")) /* Embedded Controller Device */ // _HID: Hardware ID + + Name (_GPE, 0x50) // _GPE: General Purpose Events + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings + IO (Decode16, 0x62, 0x62, 0, 1) // Range Minimum, Range Maximum, Alignment, Length + IO (Decode16, 0x66, 0x66, 0, 1) // Range Minimum, Range Maximum, Alignment, Length + }) + OperationRegion (ECO1, SystemIO, 0x62, One) + Field (ECO1, ByteAcc, Lock, Preserve) + { + PX62, 8 + } + + OperationRegion (ECO2, SystemIO, 0x66, One) + Field (ECO2, ByteAcc, Lock, Preserve) + { + PX66, 8 + } + + OperationRegion (ECMB, SystemMemory, EMBA, 0x0200) + OperationRegion (RAM, EmbeddedControl, Zero, 0xFF) + Field (RAM, ByteAcc, Lock, Preserve) + { + CMDB, 8, + Offset (0x06), + CMD2, 8, + CMD1, 8, + CMD0, 8, + Offset (0x0A), + , 1, /* Reserved */ + , 1, /* Reserved */ + Offset (0x10), + EQEN, 1, + , 1, /* Reserved */ + Offset (0x4E), + ISEN, 1, /* Sense? (0=Not Exist, 1=Exist) */ + Offset (0x51), + , 3, /* Reserved */ + TPEN, 1, + Offset (0x52), + WLEX, 1, /* Wireless LAN (0=Not Exist, 1=Exist) */ + BTEX, 1, /* Bluetooth? (0=Not Exist, 1=Exist) */ + EX3G, 1, /* 3G (0=Not Exist, 1=Exist) */ + , 3, /* Reserved */ + RFEX, 1, + Offset (0x57), + , 7, /* Reserved */ + AHKB, 1, + AHKE, 8, + Offset (0x5C), + Offset (0x5D), + Offset (0x70), + , 1, /* Reserved */ + KLID, 1, /* LID? */ + , 3, /* Reserved */ + KACS, 1, /* AC power? */ + Offset (0x71), + WLEN, 1, /* Wireless LAN (0=Not Enabled, 1=Enabled) */ + BTEN, 1, /* Bluetooth (0=Not Enabled, 1=Enabled) */ + , 3, /* Reserved */ + ISS3, 1, + ISS4, 1, + ISS5, 1, + Offset (0x74), + , 2, /* Reserved */ + , 1, /* Reserved */ + TPEX, 1, + Offset (0x75), + BLST, 1, + LMIB, 1, + Offset (0x76), + ECSS, 4, + EOSS, 4 + } + + Method (_REG, 2, NotSerialized) // _REG: Region Availability + { + /* Initialize AC power state */ + Store (KACS, \PWRS) + + /* Initialize LID switch state */ + Store (KLID, \LIDS) + } + + /* KEY_BRIGHTNESSUP */ + Method (_Q1C, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Notify (^^^GFX0.DD1F, 0x86) // Device-Specific + } + + /* KEY_BRIGHTNESSDOWN */ + Method (_Q1D, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Notify (^^^GFX0.DD1F, 0x87) // Device-Specific + } + + /* Battery Information Event */ + Method (_Q40, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Notify (BAT0, 0x81) // Information Change + } + + /* AC event */ + Method (_Q50, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Notify (ADP1, 0x80) // Status Change + } + + /* Lid event */ + Method (_Q52, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Notify (LID0, 0x80) // Status Change + } + + /* Battery Information Event */ + Method (_Q41, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Notify (BAT0, 0x81) // Information Change + } + + /* Battery Status Event */ + Method (_Q48, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Notify (BAT0, 0x80) // Status Change + } + + Method (ECWK, 1, NotSerialized) + { + EQEN = One + Notify (BAT0, 0x81) // Information Change + If (((Arg0 == 0x03) || (Arg0 == 0x04))) + { + Notify (SLPB, 0x02) // Device Wake + } + } + + Name (B0ST, Zero) + Field (ECMB, ByteAcc, Lock, Preserve) + { + Offset (0x08), + MB0S, 8 + } + + OperationRegion (MBB0, SystemMemory, (EMBA + 0x80), 0xFF) + Field (MBB0, ByteAcc, Lock, Preserve) + { + MBRC, 16, + MBFC, 16, + MBPE, 16, + MBAC, 16, + MBVO, 16, + , 15, + MBCM, 1, + MBCU, 16, + MBTV, 16 + } + + Method (GBIF, 3, NotSerialized) + { + If (Arg2) + { + Arg1 [One] = 0xFFFFFFFF + Arg1 [0x02] = 0xFFFFFFFF + Arg1 [0x04] = 0xFFFFFFFF + Arg1 [0x05] = Zero + Arg1 [0x06] = Zero + } + + Return (Arg1) + } + + Method (GBST, 4, NotSerialized) + { + Local0 = Zero + + If ((Arg1 & One)) + { + Local1 = MBAC /* \_SB_.PCI0.LPCB.EC0_.MBAC */ + Local2 = MBRC /* \_SB_.PCI0.LPCB.EC0_.MBRC */ + If (ACST) + { + If ((Arg1 & 0x20)) + { + Local2 = MBFC /* \_SB_.PCI0.LPCB.EC0_.MBFC */ + } + } + + Local3 = MBVO /* \_SB_.PCI0.LPCB.EC0_.MBVO */ + If ((Local1 >= 0x8000)) + { + If ((Local0 & One)) + { + Local1 = (0x00010000 - Local1) + } + Else + { + Local1 = Zero + } + } + + If (Arg2) + { + Local1 *= Local3 + Divide (Local1, 0x03E8, Local1) + } + } + Else + { + Local0 = Zero + Local1 = 0xFFFFFFFF + Local2 = 0xFFFFFFFF + Local3 = 0xFFFFFFFF + } + + Arg3 [Zero] = Local0 + Arg3 [One] = Local1 + Arg3 [0x02] = Local2 + Arg3 [0x03] = Local3 + Return (Arg3) + } + + Name (ACST, One) + Device (ADP1) + { + Name (_HID, "ACPI0003") /* Power Source Device */ // _HID: Hardware ID + Name (_PCL, Package () { \_SB }) // _PCL: Power Consumer List + Method (_PSR) // _PSR: Power Source + { + Return (\PWRS) + } + Method (_STA) // _STA: Status + { + Return (0x0F) + } + } + + Device (BAT0) + { + Name (_HID, EisaId ("PNP0C0A")) /* Control Method Battery */ // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Method (_PCL, 0, NotSerialized) // _PCL: Power Consumer List + { + Return (_SB) /* \_SB_ */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + If (B0ST) + { + Return (0x1F) + } + Else + { + Return (0x0F) + } + } + + Name (B0IP, Package (0x0D) + { + 0x00000001, /* 0x00: Power Unit: mAH */ + 0xFFFFFFFF, /* 0x01: Design Capacity */ + 0xFFFFFFFF, /* 0x02: Last Full Charge Capacity */ + 0x00000001, /* 0x03: Battery Technology: Rechargeable */ + 0xFFFFFFFF, /* 0x04: Design Voltage */ + 0x00000000, /* 0x05: Design Capacity of Warning */ + 0x00000000, /* 0x06: Design Capacity of Low */ + 0x00000001, /* 0x07: Capacity Granularity 1 */ + 0x00000001, /* 0x08: Capacity Granularity 2 */ + "", /* 0x09: Model Number */ + "100", /* 0x0a: Serial Number */ + "Lion", /* 0x0b: Battery Type */ + 0x00000000 /* 0x0c: OEM Information */ + }) + + Method (_BIF, 0, NotSerialized) // _BIF: Battery Information + { + Local6 = B0ST /* \_SB_.PCI0.LPCB.EC0_.B0ST */ + While ((Local6)) + { + Local1 = MB0S /* \_SB_.PCI0.LPCB.EC0_.MB0S */ + If ((Local1 & 0x08)) + { + Local6 = Zero + } + } + + Return (GBIF (Zero, B0IP, Local6)) + } + + Name (B0SP, Package (0x04) + { + 0x00000000, /* 0x00: Battery State */ + 0xFFFFFFFF, /* 0x01: Battery Present Rate */ + 0xFFFFFFFF, /* 0x02: Battery Remaining Capacity */ + 0xFFFFFFFF /* 0x03: Battery Present Voltage */ + }) + + Method (_BST, 0, NotSerialized) // _BST: Battery Status + { + Local0 = (DerefOf (B0IP [Zero]) ^ One) + Return (GBST (Zero, MB0S, Local0, B0SP)) + } + } +} diff --git a/src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl b/src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl new file mode 100644 index 0000000..e145a2b --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +OperationRegion (SANV, SystemMemory, 0x7CE5FD98, Zero) +Field (SANV, AnyAcc, Lock, Preserve) +{ + BRTL, 8 +} + +Scope (\_SB.PCI0) +{ + Device (GFX0) + { + Name (_ADR, 0x00020000) // _ADR: Address + + Device (DD1F) + { + Method (_ADR, 0, Serialized) // _ADR: Address + { + Return (0x1F) + } + + Method (_BCL, 0, NotSerialized) // _BCL: Brightness Control Levels + { + Return (Package (0x0C) + { + 0x50, + 0x32, + 0x0A, + 0x14, + 0x1E, + 0x28, + 0x32, + 0x3C, + 0x46, + 0x50, + 0x5A, + 0x64 + }) + } + + Method (_BCM, 1, NotSerialized) // _BCM: Brightness Control Method + { + If (((Arg0 >= Zero) && (Arg0 <= 0x64))) + { + BRTL = Arg0 + } + } + + Method (_BQC, 0, NotSerialized) // _BQC: Brightness Query Current + { + Return (BRTL) /* \BRTL */ + } + } + } +} diff --git a/src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl b/src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl new file mode 100644 index 0000000..90e75f2 --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB) +{ + Device (LID0) /* Lid Device */ + { + Name (_HID, EisaId ("PNP0C0D")) + + Method (_STA) // _STA: Status + { + Return (0xF) + } + + Method (_LID) // _LID: Lid Status + { + Return (\LIDS) + } + } + + Device (PWRB) + { + Name (_HID, EisaId ("PNP0C0C")) + + Method (_STA) + { + Return (0xF) + } + + Name (_PRW, Package () { 27, 4 }) + } + + Device (SLPB) /* Sleep Button Device */ // _HID: Hardware ID + { + Name (_HID, EisaId ("PNP0C0E")) + + Method (_STA) // _STA: Status + { + Return (0xF) + } + } +} diff --git a/src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl b/src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl new file mode 100644 index 0000000..92c272e --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/acer/aspire_vn7_572g/acpi_tables.c b/src/mainboard/acer/aspire_vn7_572g/acpi_tables.c new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/acpi_tables.c diff --git a/src/mainboard/acer/aspire_vn7_572g/board_info.txt b/src/mainboard/acer/aspire_vn7_572g/board_info.txt new file mode 100644 index 0000000..f16707e --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/board_info.txt @@ -0,0 +1,8 @@ +Vendor name: Acer +Board name: Aspire VN7-572G +Category: laptop +ROM package: SOIC8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2015 diff --git a/src/mainboard/acer/aspire_vn7_572g/devicetree.cb b/src/mainboard/acer/aspire_vn7_572g/devicetree.cb new file mode 100644 index 0000000..f38b0b8 --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/devicetree.cb @@ -0,0 +1,218 @@ +chip soc/intel/skylake + + # Disable deep Sx states + register "deep_s3_enable_ac" = "0" + register "deep_s3_enable_dc" = "0" + register "deep_s5_enable_ac" = "0" + register "deep_s5_enable_dc" = "0" + register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" + + register "eist_enable" = "1" + + # Set the Thermal Control Circuit (TCC) activaction value to 95C + # even though FSP integration guide says to set it to 100C for SKL-U + # (offset at 0), because when the TCC activates at 100C, the CPU + # will have already shut itself down from overheating protection. + register "tcc_offset" = "5" # TCC of 95C + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_C" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + # EC host command ranges are in 0x60-0x66 + register "gen1_dec" = "0x00000061" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # Disable DPTF + register "dptf_enable" = "0" + + # FSP Configuration + register "ProbelessTrace" = "0" + register "EnableLan" = "0" + register "EnableSata" = "1" + register "SataSalpSupport" = "1" + register "SataMode" = "0" + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + register "SataPortsEnable[2]" = "1" + register "SataPortsDevSlp[0]" = "0" + register "SataPortsDevSlp[1]" = "0" + register "SataPortsDevSlp[2]" = "0" + register "EnableAzalia" = "1" + register "DspEnable" = "1" + register "IoBufferOwnership" = "0" + register "EnableTraceHub" = "0" + register "SsicPortEnable" = "0" + register "SmbusEnable" = "1" + register "Cio2Enable" = "0" + register "ScsEmmcEnabled" = "0" + register "ScsEmmcHs400Enabled" = "0" + register "ScsSdCardEnabled" = "0" + register "PttSwitch" = "0" + register "SkipExtGfxScan" = "0" + register "Device4Enable" = "0" + register "HeciEnabled" = "1" + register "SaGv" = "0" + register "PmConfigSlpS3MinAssert" = "2" # 50ms + register "PmConfigSlpS4MinAssert" = "1" # 1s + register "PmConfigSlpSusMinAssert" = "3" # 500ms + register "PmConfigSlpAMinAssert" = "3" # 2s + register "PmTimerDisabled" = "0" + + # EC/KBC requires continuous mode + register "serirq_mode" = "SERIRQ_CONTINUOUS" + + register "pirqa_routing" = "PCH_IRQ11" + register "pirqb_routing" = "PCH_IRQ10" + register "pirqc_routing" = "PCH_IRQ11" + register "pirqd_routing" = "PCH_IRQ11" + register "pirqe_routing" = "PCH_IRQ11" + register "pirqf_routing" = "PCH_IRQ11" + register "pirqg_routing" = "PCH_IRQ11" + register "pirqh_routing" = "PCH_IRQ11" + + # VR Settings Configuration for 4 Domains + #+----------------+-----------+-----------+-------------+----------+ + #| Domain/Setting | SA | IA | GT Unsliced | GT | + #+----------------+-----------+-----------+-------------+----------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| IccMax | 7A | 34A | 35A | 35A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #+----------------+-----------+-----------+-------------+----------+ + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(4), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(7), + .voltage_limit = 1520, + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(34), + .voltage_limit = 1520, + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(35), + .voltage_limit = 1520, + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(35), + .voltage_limit = 1520, + }" + + # Enable Root Ports 1, 9 and 10 + register "PcieRpEnable[2]" = "1" + register "PcieRpLtrEnable[2]" = "1" + register "PcieRpEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + register "PcieRpEnable[9]" = "1" + register "PcieRpLtrEnable[9]" = "1" + +# register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port + register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # Type-A Port (right) + register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # Type-A Port (right) + register "usb2_ports[3]" = "USB2_PORT_MID(OC1)" # Type-A Port (left) + register "usb2_ports[4]" = "USB2_PORT_FLEX(OC2)" # Bluetooth + register "usb2_ports[6]" = "USB2_PORT_FLEX(OC2)" # Webcam + register "usb2_ports[7]" = "USB2_PORT_FLEX(OC2)" # SD + + # OC0 should be for Type-C but it seems to not have been wired, according to + # the available schematics, even though it is labeled as USB_OC_TYPEC. +# register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (right) + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (right) + + # PL2 override 25W + register "tdp_pl2_override" = "25" + + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" + + # Lock Down + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 14.0 on end # USB xHCI + device pci 14.1 on end # USB xDCI (OTG) + device pci 14.2 on end # Thermal Subsystem + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 17.0 on end # SATA + device pci 1c.0 on end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 off end # PCI Express Port 5 + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on end # PCI Express Port 9 + device pci 1d.1 on end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end # LPC Interface + device pci 1f.1 off end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/acer/aspire_vn7_572g/dsdt.asl b/src/mainboard/acer/aspire_vn7_572g/dsdt.asl new file mode 100644 index 0000000..c9bcb7d --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/dsdt.asl @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2016 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 // OEM revision +) +{ + // Some generic macros + #include <soc/intel/skylake/acpi/platform.asl> + + // global NVS and variables + #include <soc/intel/skylake/acpi/globalnvs.asl> + + // CPU + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/skylake/acpi/systemagent.asl> + #include <soc/intel/skylake/acpi/pch.asl> + } + } + + // Chipset specific sleep states + #include <soc/intel/skylake/acpi/sleepstates.asl> + + // Mainboard specific + #include "acpi/mainboard.asl" + + // Graphics display + #include "acpi/graphics.asl" +} diff --git a/src/mainboard/acer/aspire_vn7_572g/gpio.h b/src/mainboard/acer/aspire_vn7_572g/gpio.h new file mode 100644 index 0000000..4d98da1 --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/gpio.h @@ -0,0 +1,201 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <soc/gpe.h> +#include <soc/gpio.h> + +#ifndef __ACPI__ + +/* Pad configuration in ramstage. */ +static const struct pad_config gpio_table[] = { +_PAD_CFG_STRUCT(GPP_A0, 0x44000703, 0x0), /* RCIN# */ +_PAD_CFG_STRUCT(GPP_A1, 0x44000702, 0x3c00), /* LAD0 */ +_PAD_CFG_STRUCT(GPP_A2, 0x44000702, 0x3c00), /* LAD1 */ +_PAD_CFG_STRUCT(GPP_A3, 0x44000702, 0x3c00), /* LAD2 */ +_PAD_CFG_STRUCT(GPP_A4, 0x44000702, 0x3c00), /* LAD3 */ +_PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x0), /* LFRAME# */ +_PAD_CFG_STRUCT(GPP_A6, 0x44000702, 0x0), /* SERIRQ */ +_PAD_CFG_STRUCT(GPP_A7, 0x44000702, 0x0), /* PIRQA# */ +_PAD_CFG_STRUCT(GPP_A8, 0x44000700, 0x0), /* CLKRUN# */ +_PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x1000), /* CLKOUT_LPC0 */ +_PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x1000), /* CLKOUT_LPC1 */ +_PAD_CFG_STRUCT(GPP_A11, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_A12, 0x44000100, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_A13, 0x44000700, 0x0), /* SUSWARN#/SUSPWRDNACK */ +_PAD_CFG_STRUCT(GPP_A14, 0x44000700, 0x0), /* SUS_STAT# */ +_PAD_CFG_STRUCT(GPP_A15, 0x44000700, 0x1000), /* SUS_ACK# */ +_PAD_CFG_STRUCT(GPP_A16, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_A17, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_A18, 0x44000102, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_A19, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_A20, 0x44000100, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_A21, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_A22, 0x44000201, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_A23, 0x44000201, 0x1000), /* GPIO */ + +_PAD_CFG_STRUCT(GPP_B0, 0x44000700, 0x0), /* CORE_VID0 */ +_PAD_CFG_STRUCT(GPP_B1, 0x44000700, 0x0), /* CORE_VID1 */ +_PAD_CFG_STRUCT(GPP_B2, 0x44000100, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_B3, 0x80100102, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_B4, 0x44000200, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_B5, 0x44000702, 0x0), /* SRCCLKREQ0# */ +_PAD_CFG_STRUCT(GPP_B6, 0x44000702, 0x0), /* SRCCLKREQ1# */ +_PAD_CFG_STRUCT(GPP_B7, 0x44000700, 0x0), /* SRCCLKREQ2# */ +_PAD_CFG_STRUCT(GPP_B8, 0x44000702, 0x0), /* SRCCLKREQ3# */ +_PAD_CFG_STRUCT(GPP_B9, 0x44000702, 0x0), /* SRCCLKREQ4# */ +_PAD_CFG_STRUCT(GPP_B10, 0x44000702, 0x0), /* SRCCLKREQ5# */ +_PAD_CFG_STRUCT(GPP_B11, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_B12, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x0), /* PLTRST# */ +_PAD_CFG_STRUCT(GPP_B14, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_B15, 0x44000200, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_B16, 0x44000200, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_B17, 0x42880100, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_B18, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_B19, 0x44000100, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_B20, 0x44000102, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_B21, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_B22, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_B23, 0x44000201, 0x1000), /* GPIO */ + +_PAD_CFG_STRUCT(GPP_C0, 0x44000702, 0x0), /* SMBCLK */ +_PAD_CFG_STRUCT(GPP_C1, 0x44000702, 0x1000), /* SMBDATA */ +_PAD_CFG_STRUCT(GPP_C2, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_C3, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_C4, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_C5, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_C6, 0x44000702, 0x0), /* SML1CLK */ +_PAD_CFG_STRUCT(GPP_C7, 0x44000702, 0x1000), /* SML1DATA */ +_PAD_CFG_STRUCT(GPP_C8, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_C9, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_C10, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_C11, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_C12, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_C13, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_C14, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_C15, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_C16, 0x44000702, 0x0), /* I2C0_SDA */ +_PAD_CFG_STRUCT(GPP_C17, 0x44000702, 0x0), /* I2C0_SCL */ +_PAD_CFG_STRUCT(GPP_C18, 0x44000702, 0x0), /* I2C1_SDA */ +_PAD_CFG_STRUCT(GPP_C19, 0x44000702, 0x0), /* I2C1_SCL */ +_PAD_CFG_STRUCT(GPP_C20, 0x44000702, 0x0), /* UART2_RXD */ +_PAD_CFG_STRUCT(GPP_C21, 0x44000700, 0x0), /* UART2_TXD */ +_PAD_CFG_STRUCT(GPP_C22, 0x44000700, 0x0), /* UART2_RTS# */ +_PAD_CFG_STRUCT(GPP_C23, 0x44000702, 0x0), /* UART2_CTS# */ + +_PAD_CFG_STRUCT(GPP_D0, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D1, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D2, 0x44000700, 0x0), /* SPI1_MISO */ +_PAD_CFG_STRUCT(GPP_D3, 0x44000700, 0x0), /* SPI1_MOSI */ +_PAD_CFG_STRUCT(GPP_D4, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D5, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D6, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D7, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D8, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D9, 0x40000102, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D10, 0x40000102, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D11, 0x40000102, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D12, 0x40000102, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D13, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D14, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D15, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D16, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D17, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D18, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D19, 0x44000700, 0x0), /* DMIC_CLK0 */ +_PAD_CFG_STRUCT(GPP_D20, 0x44000700, 0x0), /* DMIC_DATA0 */ +_PAD_CFG_STRUCT(GPP_D21, 0x44000700, 0x0), /* SPI1_IO2 */ +_PAD_CFG_STRUCT(GPP_D22, 0x44000700, 0x0), /* SPI1_IO3 */ +_PAD_CFG_STRUCT(GPP_D23, 0x44000201, 0x1000), /* GPIO */ + +_PAD_CFG_STRUCT(GPP_E0, 0x44000700, 0x0), /* SATAXPCIE0 */ +_PAD_CFG_STRUCT(GPP_E1, 0x44000700, 0x0), /* SATAXPCIE1 */ +_PAD_CFG_STRUCT(GPP_E2, 0x44000702, 0x0), /* SATAXPCIE2 */ +_PAD_CFG_STRUCT(GPP_E3, 0x44000201, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_E4, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_E5, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_E6, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_E7, 0x40900100, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_E8, 0xffffffff, 0xffffff00),/* RESERVED */ +_PAD_CFG_STRUCT(GPP_E9, 0x44000702, 0x0), /* USB2_OC0# */ +_PAD_CFG_STRUCT(GPP_E10, 0x44000702, 0x0), /* USB2_OC1# */ +_PAD_CFG_STRUCT(GPP_E11, 0x44000702, 0x0), /* USB2_OC2# */ +_PAD_CFG_STRUCT(GPP_E12, 0x44000702, 0x0), /* USB2_OC3# */ +_PAD_CFG_STRUCT(GPP_E13, 0x44000700, 0x0), /* DDPB_HPD0 */ +_PAD_CFG_STRUCT(GPP_E14, 0x44000700, 0x0), /* DDPC_HPD1 */ +_PAD_CFG_STRUCT(GPP_E15, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_E16, 0x80880102, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_E17, 0x44000702, 0x0), /* EDP_HPD */ +_PAD_CFG_STRUCT(GPP_E18, 0x44000702, 0x0), /* DDPB_CTRLCLK */ +_PAD_CFG_STRUCT(GPP_E19, 0x44000702, 0x1000), /* DDPB_CTRLDATA */ +_PAD_CFG_STRUCT(GPP_E20, 0x44000700, 0x0), /* DDPC_CTRLCLK */ +_PAD_CFG_STRUCT(GPP_E21, 0x44000702, 0x1000), /* DDPC_CTRLDATA */ +_PAD_CFG_STRUCT(GPP_E22, 0x40100000, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_E23, 0x44000201, 0x1000), /* GPIO */ + +_PAD_CFG_STRUCT(GPD0, 0x4000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPD1, 0x4000702, 0x0), /* ACPRESENT */ +_PAD_CFG_STRUCT(GPD2, 0x4000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPD3, 0x4000702, 0x3000), /* PWRBTN# */ +_PAD_CFG_STRUCT(GPD4, 0x4000700, 0x0), /* SLP_S3# */ +_PAD_CFG_STRUCT(GPD5, 0x4000700, 0x0), /* SLP_S4# */ +_PAD_CFG_STRUCT(GPD6, 0x4000601, 0x1000), /* SLP_A# */ +_PAD_CFG_STRUCT(GPD7, 0x4000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPD8, 0x4000700, 0x0), /* SUSCLK */ +_PAD_CFG_STRUCT(GPD9, 0x4000601, 0x1000), /* SLP_WLAN# */ +_PAD_CFG_STRUCT(GPD10, 0x4000601, 0x1000), /* SLP_S5# */ +_PAD_CFG_STRUCT(GPD11, 0x4000201, 0x1000), /* GPIO */ + +_PAD_CFG_STRUCT(GPP_F0, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F1, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F2, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F3, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F4, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F5, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F6, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F7, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F8, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F9, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F10, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F11, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F12, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F13, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F14, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F15, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F16, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F17, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F18, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F19, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F20, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F21, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F22, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F23, 0x40100100, 0x0), /* GPIO */ + +_PAD_CFG_STRUCT(GPP_G0, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_G1, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_G2, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_G3, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_G4, 0x44000200, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_G5, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_G6, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_G7, 0x44000201, 0x1000), /* GPIO */ +}; + +#endif + +#endif diff --git a/src/mainboard/acer/aspire_vn7_572g/hda_verb.c b/src/mainboard/acer/aspire_vn7_572g/hda_verb.c new file mode 100644 index 0000000..8cd5f97 --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/hda_verb.c @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Purism SPC. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0255, /* Codec Vendor / Device ID: Realtek ALC255 */ + 0x10251037, /* Subsystem ID */ + 0x0000000c, /* Number of jacks (NID entries) */ + + 0x0017ff00, /* Function Reset */ + 0x0017ff00, /* Double Function Reset */ + 0x0017ff00, + 0x0017ff00, + + /* Bits 31:28 - Codec Address */ + /* Bits 27:20 - NID */ + /* Bits 19:8 - Verb ID */ + /* Bits 7:0 - Payload */ + + /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x10251037 */ + AZALIA_SUBVENDOR(0x0, 0x10251037), + + /* Pin Widget Verb Table */ + + /* Pin Complex (NID 0x12) */ + AZALIA_PIN_CFG(0x0, 0x12, 0x411111c0), + + /* Pin Complex (NID 0x14) */ + AZALIA_PIN_CFG(0x0, 0x14, 0x90172120), + + /* Pin Complex (NID 0x17) */ + AZALIA_PIN_CFG(0x0, 0x17, 0x40000000), + + /* Pin Complex (NID 0x18) */ + AZALIA_PIN_CFG(0x0, 0x18, 0x411111f0), + + /* Pin Complex (NID 0x19) */ + AZALIA_PIN_CFG(0x0, 0x19, 0x411111f0), + + /* Pin Complex (NID 0x1A) */ + AZALIA_PIN_CFG(0x0, 0x1A, 0x411111f0), + + /* Pin Complex (NID 0x1B) */ + AZALIA_PIN_CFG(0x0, 0x1B, 0x411111f0), + + /* Pin Complex (NID 0x1D) */ + AZALIA_PIN_CFG(0x0, 0x1D, 0x40700001), + + /* Pin Complex (NID 0x1E) */ + AZALIA_PIN_CFG(0x0, 0x1E, 0x411111f0), + + /* Pin Complex (NID 0x21) */ + AZALIA_PIN_CFG(0x0, 0x21, 0x02211030), +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/acer/aspire_vn7_572g/mainboard.c b/src/mainboard/acer/aspire_vn7_572g/mainboard.c new file mode 100644 index 0000000..462b995 --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/mainboard.c @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Purism SPC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <smbios.h> +#include <string.h> +#include <cbfs.h> + +#define MAX_SERIAL_LENGTH 0x100 + +const char *smbios_mainboard_serial_number(void) +{ + static char serial_number[MAX_SERIAL_LENGTH + 1] = {0}; + struct cbfsf file; + + if (serial_number[0] != 0) + return serial_number; + + if (cbfs_boot_locate(&file, "serial_number", NULL) == 0) { + struct region_device cbfs_region; + size_t serial_len; + + cbfs_file_data(&cbfs_region, &file); + + serial_len = region_device_sz(&cbfs_region); + if (serial_len <= MAX_SERIAL_LENGTH) { + if (rdev_readat(&cbfs_region, serial_number, 0, + serial_len) == serial_len) { + serial_number[serial_len] = 0; + return serial_number; + } + } + } + + strncpy(serial_number, CONFIG_MAINBOARD_SERIAL_NUMBER, + MAX_SERIAL_LENGTH); + + return serial_number; +} diff --git a/src/mainboard/acer/aspire_vn7_572g/ramstage.c b/src/mainboard/acer/aspire_vn7_572g/ramstage.c new file mode 100644 index 0000000..94f8071 --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/ramstage.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corporation + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/ramstage.h> +#include "gpio.h" + +void mainboard_silicon_init_params(FSP_SIL_UPD *params) +{ + /* Configure pads prior to SiliconInit() in case there's any + * dependencies during hardware initialization. */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/acer/aspire_vn7_572g/romstage.c b/src/mainboard/acer/aspire_vn7_572g/romstage.c new file mode 100644 index 0000000..86ef5af --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/romstage.c @@ -0,0 +1,84 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation + * Copyright (C) 2017 Purism SPC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <assert.h> +#include <soc/romstage.h> +#include <spd_bin.h> +#include <string.h> + +static void mainboard_fill_dq_map_data(void *dq_map_ch0, void *dq_map_ch1) +{ + /* DQ byte map */ + const u8 dq_map[2][12] = { + { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, + { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, + 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; + memcpy(dq_map_ch0, dq_map[0], sizeof(dq_map[0])); + memcpy(dq_map_ch1, dq_map[1], sizeof(dq_map[1])); +} + +static void mainboard_fill_dqs_map_data(void *dqs_map_ch0, void *dqs_map_ch1) +{ + /* DQS CPU<>DRAM map */ + const u8 dqs_map[2][8] = { + { 0, 1, 3, 2, 4, 5, 6, 7 }, + { 1, 0, 4, 5, 2, 3, 6, 7 } }; + memcpy(dqs_map_ch0, dqs_map[0], sizeof(dqs_map[0])); + memcpy(dqs_map_ch1, dqs_map[1], sizeof(dqs_map[1])); +} + +static void mainboard_fill_rcomp_res_data(void *rcomp_ptr) +{ + /* Rcomp resistor */ + const u16 RcompResistor[3] = { 121, 81, 100 }; + memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor)); +} + +static void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) +{ + /* Rcomp target */ + const u16 RcompTarget[5] = { 100, 40, 20, 20, 26 }; + memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); +} + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *mem_cfg; + struct spd_block blk = { + .addr_map = { 0x50, 0x52 }, + }; + + mem_cfg = &mupd->FspmConfig; + + get_spd_smbus(&blk); + dump_spd_info(&blk); + assert(blk.spd_array[0][0] != 0); + + mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0, + &mem_cfg->DqByteMapCh1); + mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0, + &mem_cfg->DqsMapCpu2DramCh1); + mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); + mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); + + mem_cfg->DqPinsInterleaved = TRUE; + mem_cfg->MemorySpdDataLen = blk.len; + mem_cfg->MemorySpdPtr00 = (uintptr_t) blk.spd_array[0]; + mem_cfg->MemorySpdPtr10 = (uintptr_t) blk.spd_array[1]; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/35523 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Gerrit-Change-Number: 35523 Gerrit-PatchSet: 1 Gerrit-Owner: Benjamin Doron Gerrit-MessageType: newchange

4 days, 16 hours

8
300
0 0

Change in coreboot[master]: libgfxinit: Allow to configure screen rotation

by Nico Huber (Code Review)

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38922 ) Change subject: libgfxinit: Allow to configure screen rotation ...................................................................... libgfxinit: Allow to configure screen rotation This allows us to configure a default screen rotation in 90 degree steps. The framebuffer contents will then be displayed by the same amount in the other direction. The 90 and 270 degree settings are only supported by newer display engines, from Skylake / Apollo Lake on. Change-Id: Iac75cefbd34f28c55ec20ee152fe67351cc48653 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/device/Kconfig M src/drivers/intel/gma/hires_fb/gma-gfx_init.adb 2 files changed, 47 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/38922/1 diff --git a/src/device/Kconfig b/src/device/Kconfig index a25bb91..6859c24 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -478,6 +478,27 @@ Set the maximum height of the framebuffer. This may help with default fonts too tiny for high-resolution displays. +choice DEFAULT_SCREEN_ROTATION + prompt "Default screen rotation" + depends on LINEAR_FRAMEBUFFER && MAINBOARD_USE_LIBGFXINIT + default DEFAULT_SCREEN_ROTATION_NONE + +config DEFAULT_SCREEN_ROTATION_NONE + bool "None" + +config DEFAULT_SCREEN_ROTATION_90 + bool "90 degrees CCW" + depends on GFX_GMA_GENERATION = "Broxton" || GFX_GMA_GENERATION = "Skylake" + +config DEFAULT_SCREEN_ROTATION_180 + bool "180 degrees" + +config DEFAULT_SCREEN_ROTATION_270 + bool "90 degrees CW" + depends on GFX_GMA_GENERATION = "Broxton" || GFX_GMA_GENERATION = "Skylake" + +endchoice + endmenu # "Display" config PCI diff --git a/src/drivers/intel/gma/hires_fb/gma-gfx_init.adb b/src/drivers/intel/gma/hires_fb/gma-gfx_init.adb index 1393784..014e92b 100644 --- a/src/drivers/intel/gma/hires_fb/gma-gfx_init.adb +++ b/src/drivers/intel/gma/hires_fb/gma-gfx_init.adb @@ -54,9 +54,20 @@ ---------------------------------------------------------------------------- + procedure Screen_Rotation (rotation : out Rotation_Type) + is + begin + rotation := + (if Config.DEFAULT_SCREEN_ROTATION_90 then Rotated_90 + elsif Config.DEFAULT_SCREEN_ROTATION_180 then Rotated_180 + elsif Config.DEFAULT_SCREEN_ROTATION_270 then Rotated_270 + else No_Rotation); + end Screen_Rotation; + procedure gfxinit (lightup_ok : out Interfaces.C.int) is use type pos32; + use type word32; use type word64; ports : Port_List; @@ -84,10 +95,21 @@ end loop; fb := configs (Primary).Framebuffer; - fb.Width := Width_Type (min_h); - fb.Height := Height_Type (min_v); - fb.Stride := Div_Round_Up (fb.Width, 16) * 16; - fb.V_Stride := fb.Height; + Screen_Rotation (fb.Rotation); + + if fb.Rotation = Rotated_90 or fb.Rotation = Rotated_270 then + fb.Width := Width_Type (min_v); + fb.Height := Height_Type (min_h); + fb.Stride := Div_Round_Up (fb.Width, 32) * 32; + fb.V_Stride := Div_Round_Up (fb.Height, 32) * 32; + fb.Tiling := Y_Tiled; + fb.Offset := word32 (GTT_Rotation_Offset) * GTT_Page_Size; + else + fb.Width := Width_Type (min_h); + fb.Height := Height_Type (min_v); + fb.Stride := Div_Round_Up (fb.Width, 16) * 16; + fb.V_Stride := fb.Height; + end if; for i in Pipe_Index loop exit when configs (i).Port = Disabled; -- To view, visit https://review.coreboot.org/c/coreboot/+/38922 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iac75cefbd34f28c55ec20ee152fe67351cc48653 Gerrit-Change-Number: 38922 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

5 days, 1 hour

3
11
0 0

Change in coreboot[master]: payloads/LinuxBoot: make linux kernel build reproducible

by Alexander Couzens (Code Review)

Alexander Couzens has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35393 ) Change subject: payloads/LinuxBoot: make linux kernel build reproducible ...................................................................... payloads/LinuxBoot: make linux kernel build reproducible Reproducible builds have to be independent from user, host, domain, time. Taken from OpenWrt (GPL2). Change-Id: I420588acc66647051c08e4da6fbedc205cd62877 --- M payloads/external/LinuxBoot/targets/linux.mk 1 file changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/35393/1 diff --git a/payloads/external/LinuxBoot/targets/linux.mk b/payloads/external/LinuxBoot/targets/linux.mk index 8be0926..c676f68 100644 --- a/payloads/external/LinuxBoot/targets/linux.mk +++ b/payloads/external/LinuxBoot/targets/linux.mk @@ -30,7 +30,11 @@ OBJCOPY:=$(LINUXBOOT_CROSS_COMPILE)objcopy KERNEL_MAKE_FLAGS = \ - ARCH=$(ARCH-y) + ARCH=$(ARCH-y) \ + KBUILD_BUILD_USER="coreboot" \ + KBUILD_BUILD_HOST="reproducible" \ + KBUILD_BUILD_TIMESTAMP="$(shell perl -e 'print scalar gmtime($(SOURCE_DATE_EPOCH))')" \ + KBUILD_BUILD_VERSION="0" ifeq ($(CONFIG_LINUXBOOT_KERNEL_CUSTOM),y) kernel_version:=$(CONFIG_LINUXBOOT_KERNEL_CUSTOM_VERSION) -- To view, visit https://review.coreboot.org/c/coreboot/+/35393 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I420588acc66647051c08e4da6fbedc205cd62877 Gerrit-Change-Number: 35393 Gerrit-PatchSet: 1 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-MessageType: newchange

1 week

2
7
0 0

Change in coreboot[master]: cpu/smm/ssm_stub: Add x86_64 support

by Patrick Rudolph (Code Review)

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37392 ) Change subject: cpu/smm/ssm_stub: Add x86_64 support ...................................................................... cpu/smm/ssm_stub: Add x86_64 support Enable long mode in SMM handler. x86_32 isn't affected from this change. * Enter long mode * Add 64bit entry to GDT * Use x86_64 SysV ABI calling conventions for C code entry * Change smm_module_params' cpu to size_t as 'push' is native integer Tested on Lenovo T410 with additional x86_64 patches. Change-Id: I26300492e4be62ddd5d80525022c758a019d63a1 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/x86/smm/smm_stub.S M src/include/cpu/x86/smm.h 2 files changed, 25 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/37392/1 diff --git a/src/cpu/x86/smm/smm_stub.S b/src/cpu/x86/smm/smm_stub.S index f0e55f9..3feee9b 100644 --- a/src/cpu/x86/smm/smm_stub.S +++ b/src/cpu/x86/smm/smm_stub.S @@ -90,6 +90,10 @@ /* gdt selector 0x10, flat data segment */ .word 0xffff, 0x0000 .byte 0x00, 0x93, 0xcf, 0x00 + + /* gdt selector 0x18, flat code segment (64-bit) */ + .word 0xffff, 0x0000 + .byte 0x00, 0x9b, 0xaf, 0x00 smm_relocate_gdt_end: .align 4 @@ -172,11 +176,30 @@ /* Align stack to 16 bytes. Another 32 bytes are pushed below. */ andl $0xfffffff0, %esp +#ifdef __x86_64__ + /* entry64.inc preserves ebx, esi, edi */ + mov %ecx, %edi +#include <cpu/x86/64bit/entry64.inc> + mov %edi, %ecx + +#endif + /* Call into the c-based SMM relocation function with the platform * parameters. Equivalent to: * struct arg = { c_handler_params, cpu_num, smm_runtime, canary }; * c_handler(&arg) */ +#ifdef __x86_64__ + push %rbx /* uintptr_t *canary */ + push $(smm_runtime) + push %rcx /* int cpu */ + push c_handler_arg /* void *arg */ + + mov %rsp, %rdi /* *arg */ + + movl c_handler, %eax + call *%rax +#else push $0x0 /* Padding */ push $0x0 /* Padding */ push $0x0 /* Padding */ @@ -187,7 +210,7 @@ push %esp /* smm_module_params *arg (allocated on stack). */ mov c_handler, %eax call *%eax - +#endif /* Retrieve fxsave location. */ mov -4(%ebp), %edi test %edi, %edi diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index cf107b1..0de08b6 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -75,7 +75,7 @@ struct smm_module_params { void *arg; - int cpu; + size_t cpu; const struct smm_runtime *runtime; /* A canary value that has been placed at the end of the stack. * If (uintptr_t)canary != *canary then a stack overflow has occurred. -- To view, visit https://review.coreboot.org/c/coreboot/+/37392 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I26300492e4be62ddd5d80525022c758a019d63a1 Gerrit-Change-Number: 37392 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

1 week

9
36
0 0

Change in coreboot[master]: [WIP] mb/google/kahlee,zork: Remove special GPIO_2 override

by Kyösti Mälkki (Code Review)

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43049 ) Change subject: [WIP] mb/google/kahlee,zork: Remove special GPIO_2 override ...................................................................... [WIP] mb/google/kahlee,zork: Remove special GPIO_2 override Change-Id: I44661f05c8f517ece88714c625603579731d174b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/amd/padmelon/gpio.c M src/mainboard/google/kahlee/variants/baseboard/gpio.c M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c M src/soc/amd/common/block/gpio_banks/gpio.c M src/soc/amd/common/block/include/amdblocks/gpio_banks.h M src/soc/amd/picasso/gpio.c M src/soc/amd/stoneyridge/gpio.c 7 files changed, 3 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/43049/1 diff --git a/src/mainboard/amd/padmelon/gpio.c b/src/mainboard/amd/padmelon/gpio.c index 7897d7b..966c69c 100644 --- a/src/mainboard/amd/padmelon/gpio.c +++ b/src/mainboard/amd/padmelon/gpio.c @@ -28,7 +28,7 @@ /* WLAND */ PAD_WAKE(GPIO_137, PULL_UP, LEVEL_LOW, S3), #else - /* PCIE_WAKE */ + /* PCIE_WAKE, SCI */ PAD_GPI(GPIO_2, PULL_DOWN), /* DEVSLP1 - default as GPIO, do not program */ diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c index 59d7631..27db3fb 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c +++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c @@ -81,7 +81,7 @@ /* GPIO_1 - SYS_RST_ODL */ PAD_NF(GPIO_1, SYS_RESET_L, PULL_UP), - /* GPIO_2 - WLAN_PCIE_WAKE_3V3_ODL */ + /* GPIO_2 - WLAN_PCIE_WAKE_3V3_ODL, SCI*/ PAD_NF(GPIO_2, WAKE_L, PULL_UP), /* GPIO_3 - MEM_VOLT_SEL */ diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c index 2191793..5d5dd11 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c @@ -73,7 +73,7 @@ PAD_NF(GPIO_0, PWR_BTN_L, PULL_UP), /* SYS_RESET_L */ PAD_NF(GPIO_1, SYS_RESET_L, PULL_NONE), - /* PCIE_WAKE_L */ + /* PCIE_WAKE_L, SCI */ PAD_NF(GPIO_2, WAKE_L, PULL_UP), /* PEN_DETECT_ODL */ PAD_GPI(GPIO_4, PULL_UP), diff --git a/src/soc/amd/common/block/gpio_banks/gpio.c b/src/soc/amd/common/block/gpio_banks/gpio.c index 1bcfc8b..f66921d 100644 --- a/src/soc/amd/common/block/gpio_banks/gpio.c +++ b/src/soc/amd/common/block/gpio_banks/gpio.c @@ -173,8 +173,6 @@ return gpio; } -__weak void soc_gpio_hook(uint8_t gpio, uint8_t mux) {} - static void set_single_gpio(const struct soc_amd_gpio *g, struct sci_trigger_regs *sci_cfg) { static const struct soc_amd_event *gev_tbl; @@ -184,8 +182,6 @@ iomux_write8(g->gpio, g->function & AMD_GPIO_MUX_MASK); iomux_read8(g->gpio); /* Flush posted write */ - soc_gpio_hook(g->gpio, g->function); - /* Clear interrupt and wake status (write 1-to-clear bits) */ uint32_t control = g->control | GPIO_INT_STATUS | GPIO_WAKE_STATUS; __gpio_setbits32(g->gpio, PAD_CFG_MASK, control); diff --git a/src/soc/amd/common/block/include/amdblocks/gpio_banks.h b/src/soc/amd/common/block/include/amdblocks/gpio_banks.h index 92eae73..4143e81 100644 --- a/src/soc/amd/common/block/include/amdblocks/gpio_banks.h +++ b/src/soc/amd/common/block/include/amdblocks/gpio_banks.h @@ -340,7 +340,5 @@ int gpio_interrupt_status(gpio_t gpio); /* Implemented by soc, provides table of available GPIO mapping to Gevents */ void soc_get_gpio_event_table(const struct soc_amd_event **table, size_t *items); -/* May be implemented by soc to handle special cases */ -void soc_gpio_hook(uint8_t gpio, uint8_t mux); #endif /* __AMDBLOCK_GPIO_BANKS_H__ */ diff --git a/src/soc/amd/picasso/gpio.c b/src/soc/amd/picasso/gpio.c index 47c005e..78c15fe 100644 --- a/src/soc/amd/picasso/gpio.c +++ b/src/soc/amd/picasso/gpio.c @@ -38,10 +38,3 @@ *table = gpio_event_table; *items = ARRAY_SIZE(gpio_event_table); } - -void soc_gpio_hook(uint8_t gpio, uint8_t mux) -{ - /* Always program Gevent when WAKE_L_AGPIO2 is configured as WAKE_L */ - if ((gpio == 2) && !(mux & AMD_GPIO_MUX_MASK)) - soc_route_sci(GPIO_2_EVENT); -} diff --git a/src/soc/amd/stoneyridge/gpio.c b/src/soc/amd/stoneyridge/gpio.c index bd9d1b1..26dec3f 100644 --- a/src/soc/amd/stoneyridge/gpio.c +++ b/src/soc/amd/stoneyridge/gpio.c @@ -38,10 +38,3 @@ *table = gpio_event_table; *items = ARRAY_SIZE(gpio_event_table); } - -void soc_gpio_hook(uint8_t gpio, uint8_t mux) -{ - /* Always program Gevent when WAKE_L_AGPIO2 is configured as WAKE_L */ - if ((gpio == 2) && !(mux & AMD_GPIO_MUX_MASK)) - soc_route_sci(GPIO_2_EVENT); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/43049 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44661f05c8f517ece88714c625603579731d174b Gerrit-Change-Number: 43049 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

1 week

3
17
0 0

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit July 2020