Change in coreboot[master]: [WIP]lib/edid_fill_fb: Support multiple framebuffers
by Patrick Rudolph (Code Review)
Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39002 )
Change subject: [WIP]lib/edid_fill_fb: Support multiple framebuffers
......................................................................
[WIP]lib/edid_fill_fb: Support multiple framebuffers
Add an implementation that supports multiple framebuffers.
This will allow to compile in multiple graphic drivers and select
at runtime which one to choose.
Change-Id: I7264c2ea2f72f36adfd26f26b00e3ce172133621
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/include/edid.h
A src/include/framebuffer_info.h
M src/lib/edid_fill_fb.c
M src/mainboard/google/kukui/mainboard.c
4 files changed, 174 insertions(+), 64 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/39002/1
diff --git a/src/include/edid.h b/src/include/edid.h
index a97b99b..7c3e9c8 100644
--- a/src/include/edid.h
+++ b/src/include/edid.h
@@ -104,11 +104,12 @@
EDID_ABSENT,
};
+struct edid_fb_info;
/* Defined in src/lib/edid.c */
int decode_edid(unsigned char *edid, int size, struct edid *out);
void edid_set_framebuffer_bits_per_pixel(struct edid *edid, int fb_bpp,
int row_byte_alignment);
-void set_vbe_mode_info_valid(const struct edid *edid, uintptr_t fb_addr);
+struct edid_fb_info *set_vbe_mode_info_valid(const struct edid *edid, uintptr_t fb_addr);
void set_vbe_framebuffer_orientation(enum lb_fb_orientation orientation);
int set_display_mode(struct edid *edid, enum edid_modes mode);
diff --git a/src/include/framebuffer_info.h b/src/include/framebuffer_info.h
new file mode 100644
index 0000000..6d2f9a6
--- /dev/null
+++ b/src/include/framebuffer_info.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright 2013 Google Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but without any warranty; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __FRAMEBUFFER_INFO_H_
+#define __FRAMEBUFFER_INFO_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <commonlib/coreboot_tables.h>
+
+struct edid_fb_info;
+struct edid_fb_info *fb_new_framebuffer_info(void);
+
+bool fb_fill_framebuffer_info_ex(struct edid_fb_info *info,
+ uintptr_t fb_addr, uint32_t x_resolution,
+ uint32_t y_resolution, uint32_t bytes_per_line,
+ uint8_t bits_per_pixel, uint8_t reserved_mask_pos,
+ uint8_t reserved_mask_size, uint8_t red_mask_pos,
+ uint8_t red_mask_size, uint8_t green_mask_pos,
+ uint8_t green_mask_size, uint8_t blue_mask_pos,
+ uint8_t blue_mask_size);
+
+bool fb_fill_framebuffer_info(struct edid_fb_info *info,
+ uintptr_t fb_addr, uint32_t x_resolution,
+ uint32_t y_resolution, uint32_t bytes_per_line,
+ uint8_t bits_per_pixel);
+
+void fb_fill_framebuffer_set_orientation(struct edid_fb_info *info,
+ enum lb_fb_orientation orientation);
+
+#endif /* __FRAMEBUFFER_INFO_H_ */
diff --git a/src/lib/edid_fill_fb.c b/src/lib/edid_fill_fb.c
index 1b38ead..3abcdd0 100644
--- a/src/lib/edid_fill_fb.c
+++ b/src/lib/edid_fill_fb.c
@@ -23,75 +23,137 @@
#include <console/console.h>
#include <edid.h>
#include <boot/coreboot_tables.h>
+#include <framebuffer_info.h>
+#include <string.h>
+#include <stdlib.h>
-static int fb_valid;
-static struct lb_framebuffer edid_fb;
+struct edid_fb_info {
+ bool valid;
+ struct lb_framebuffer edid_fb;
+ struct edid_fb_info *next;
+};
+static struct edid_fb_info *list;
+
+/*
+ * Allocate a new framebuffer info struct on heap.
+ * Returns NULL on error.
+ */
+struct edid_fb_info *fb_new_framebuffer_info(void)
+{
+ struct edid_fb_info *ret;
+ ret = malloc(sizeof(struct edid_fb_info));
+ if (ret) {
+ memset(ret, 0, sizeof(struct edid_fb_info));
+ ret->next = list;
+ list = ret;
+ }
+ return ret;
+}
+
+/*
+ * Fills a provided framebuffer info struct and sets the valid bit to true.
+ * Returns false on error.
+ */
+bool fb_fill_framebuffer_info_ex(struct edid_fb_info *info,
+ uintptr_t fb_addr, uint32_t x_resolution,
+ uint32_t y_resolution, uint32_t bytes_per_line,
+ uint8_t bits_per_pixel, uint8_t reserved_mask_pos,
+ uint8_t reserved_mask_size, uint8_t red_mask_pos,
+ uint8_t red_mask_size, uint8_t green_mask_pos,
+ uint8_t green_mask_size, uint8_t blue_mask_pos,
+ uint8_t blue_mask_size)
+{
+ /* Validate */
+ if (!info)
+ return false;
+
+ if (!x_resolution || !y_resolution || !bytes_per_line || !bits_per_pixel) {
+ printk(BIOS_ERR, "%s: Invalid framebuffer data provided\n", __func__);
+ return false;
+ }
+
+ printk(BIOS_INFO, "framebuffer_info: bytes_per_line: %d, bits_per_pixel: %d\n "
+ " x_res x y_res: %d x %d, size: %d at %p\n",
+ bytes_per_line, bits_per_pixel, x_resolution,
+ y_resolution, (bytes_per_line * y_resolution),
+ (void *)fb_addr);
+
+ /* Update */
+ info->edid_fb.physical_address = fb_addr;
+ info->edid_fb.x_resolution = x_resolution;
+ info->edid_fb.y_resolution = y_resolution;
+ info->edid_fb.bytes_per_line = bytes_per_line;
+ info->edid_fb.bits_per_pixel = bits_per_pixel;
+ info->edid_fb.reserved_mask_pos = reserved_mask_pos;
+ info->edid_fb.reserved_mask_size = reserved_mask_size;
+ info->edid_fb.red_mask_pos = red_mask_pos;
+ info->edid_fb.red_mask_size = red_mask_size;
+ info->edid_fb.green_mask_pos = green_mask_pos;
+ info->edid_fb.green_mask_size = green_mask_size;
+ info->edid_fb.blue_mask_pos = blue_mask_pos;
+ info->edid_fb.blue_mask_size = blue_mask_size;
+ info->valid = true;
+
+ return true;
+}
+
+/* Fills a framebuffer into struct with common values for 32/24/16bpp framebuffers */
+bool fb_fill_framebuffer_info(struct edid_fb_info *info,
+ uintptr_t fb_addr, uint32_t x_resolution,
+ uint32_t y_resolution, uint32_t bytes_per_line,
+ uint8_t bits_per_pixel)
+{
+ if (!info)
+ return false;
+
+ switch (bits_per_pixel) {
+ case 32:
+ case 24:
+ /* packed into 4-byte words */
+ return fb_fill_framebuffer_info_ex(info, fb_addr, x_resolution, y_resolution,
+ bytes_per_line, bits_per_pixel, 24, 8, 16, 8, 8, 8, 0, 8);
+ break;
+ case 16:
+ /* packed into 2-byte words */
+ return fb_fill_framebuffer_info_ex(info, fb_addr, x_resolution, y_resolution,
+ bytes_per_line, bits_per_pixel, 0, 0, 11, 5, 5, 6, 0, 5);
+ break;
+ default:
+ printk(BIOS_SPEW, "%s: unsupported BPP %d\n", __func__, bits_per_pixel);
+ return false;
+ }
+ return true;
+}
+
+void fb_fill_framebuffer_set_orientation(struct edid_fb_info *info,
+ enum lb_fb_orientation orientation)
+{
+ if (!info)
+ return;
+
+ info->edid_fb.orientation = orientation;
+}
/*
* Take an edid, and create a framebuffer. Set fb_valid to 1.
*/
-void set_vbe_mode_info_valid(const struct edid *edid, uintptr_t fb_addr)
+struct edid_fb_info *set_vbe_mode_info_valid(const struct edid *edid, uintptr_t fb_addr)
{
- edid_fb.physical_address = fb_addr;
- edid_fb.x_resolution = edid->x_resolution;
- edid_fb.y_resolution = edid->y_resolution;
- edid_fb.bytes_per_line = edid->bytes_per_line;
- /* In the case of (e.g.) 24 framebuffer bits per pixel, the convention
- * nowadays seems to be to round it up to the nearest reasonable
- * boundary, because otherwise the byte-packing is hideous.
- * So, for example, in RGB with no alpha, the bytes are still
- * packed into 32-bit words, the so-called 32bpp-no-alpha mode.
- * Or, in 5:6:5 mode, the bytes are also packed into 32-bit words,
- * and in 4:4:4 mode, they are packed into 16-bit words.
- * Good call on the hardware guys part.
- * It's not clear we're covering all cases here, but
- * I'm not sure with grahpics you ever can.
- */
- edid_fb.bits_per_pixel = edid->framebuffer_bits_per_pixel;
- edid_fb.reserved_mask_pos = 0;
- edid_fb.reserved_mask_size = 0;
- switch (edid->framebuffer_bits_per_pixel) {
- case 32:
- case 24:
- /* packed into 4-byte words */
- edid_fb.reserved_mask_pos = 24;
- edid_fb.reserved_mask_size = 8;
- edid_fb.red_mask_pos = 16;
- edid_fb.red_mask_size = 8;
- edid_fb.green_mask_pos = 8;
- edid_fb.green_mask_size = 8;
- edid_fb.blue_mask_pos = 0;
- edid_fb.blue_mask_size = 8;
- break;
- case 16:
- /* packed into 2-byte words */
- edid_fb.red_mask_pos = 11;
- edid_fb.red_mask_size = 5;
- edid_fb.green_mask_pos = 5;
- edid_fb.green_mask_size = 6;
- edid_fb.blue_mask_pos = 0;
- edid_fb.blue_mask_size = 5;
- break;
- default:
- printk(BIOS_SPEW, "%s: unsupported BPP %d\n", __func__,
- edid->framebuffer_bits_per_pixel);
- return;
- }
-
- fb_valid = 1;
-}
-
-void set_vbe_framebuffer_orientation(enum lb_fb_orientation orientation)
-{
- edid_fb.orientation = orientation;
+ struct edid_fb_info *info = fb_new_framebuffer_info();
+ if (!info)
+ return NULL;
+ fb_fill_framebuffer_info(info, fb_addr, edid->x_resolution, edid->y_resolution,
+ edid->bytes_per_line, edid->framebuffer_bits_per_pixel);
+ return info;
}
int fill_lb_framebuffer(struct lb_framebuffer *framebuffer)
{
- if (!fb_valid)
- return -1;
-
- *framebuffer = edid_fb;
-
- return 0;
+ for (struct edid_fb_info *i = list; i != NULL; i = i->next) {
+ if (i->valid) {
+ *framebuffer = i->edid_fb;
+ return 0;
+ }
+ }
+ return -1;
}
diff --git a/src/mainboard/google/kukui/mainboard.c b/src/mainboard/google/kukui/mainboard.c
index 844496d..4033d51 100644
--- a/src/mainboard/google/kukui/mainboard.c
+++ b/src/mainboard/google/kukui/mainboard.c
@@ -172,8 +172,10 @@
return false;
}
mtk_ddp_mode_set(edid);
- set_vbe_mode_info_valid(edid, 0);
- set_vbe_framebuffer_orientation(panel->s->orientation);
+ struct edid_fb_info *info = set_vbe_mode_info_valid(edid, 0);
+ if (info)
+ fb_fill_framebuffer_set_orientation(info, panel->s->orientation);
+
return true;
}
--
To view, visit https://review.coreboot.org/c/coreboot/+/39002
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I7264c2ea2f72f36adfd26f26b00e3ce172133621
Gerrit-Change-Number: 39002
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Gerrit-MessageType: newchange
21 minutes
- 9
- 59
Change in ...coreboot[master]: Adding Asus A88XM-E FM2+ motherboard with documentation
by Balázs Vinarz (Code Review)
Balázs Vinarz has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30987
Change subject: Adding Asus A88XM-E FM2+ motherboard with documentation
......................................................................
Adding Asus A88XM-E FM2+ motherboard with documentation
Signed-off-by: Balazs Vinarz <vinibali1(a)gmail.com>
Change-Id: I60fa0636ba41f5f1a6a3faa2764bf2f0a968cf90
---
A Documentation/mainboard/asus/a88xm-e.md
A src/mainboard/asus/a88xm-e/BiosCallOuts.c
A src/mainboard/asus/a88xm-e/Kconfig
A src/mainboard/asus/a88xm-e/Kconfig.name
A src/mainboard/asus/a88xm-e/Makefile.inc
A src/mainboard/asus/a88xm-e/OemCustomize.c
A src/mainboard/asus/a88xm-e/OptionsIds.h
A src/mainboard/asus/a88xm-e/acpi/cpstate.asl
A src/mainboard/asus/a88xm-e/acpi/gpe.asl
A src/mainboard/asus/a88xm-e/acpi/mainboard.asl
A src/mainboard/asus/a88xm-e/acpi/routing.asl
A src/mainboard/asus/a88xm-e/acpi/sata.asl
A src/mainboard/asus/a88xm-e/acpi/si.asl
A src/mainboard/asus/a88xm-e/acpi/sleep.asl
A src/mainboard/asus/a88xm-e/acpi/superio.asl
A src/mainboard/asus/a88xm-e/acpi/thermal.asl
A src/mainboard/asus/a88xm-e/acpi/usb_oc.asl
A src/mainboard/asus/a88xm-e/acpi_tables.c
A src/mainboard/asus/a88xm-e/board_info.txt
A src/mainboard/asus/a88xm-e/buildOpts.c
A src/mainboard/asus/a88xm-e/cmos.layout
A src/mainboard/asus/a88xm-e/devicetree_a88xm-e.cb
A src/mainboard/asus/a88xm-e/dsdt.asl
A src/mainboard/asus/a88xm-e/irq_tables.c
A src/mainboard/asus/a88xm-e/mainboard.c
A src/mainboard/asus/a88xm-e/mptable.c
A src/mainboard/asus/a88xm-e/romstage.c
27 files changed, 2,371 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/30987/1
diff --git a/Documentation/mainboard/asus/a88xm-e.md b/Documentation/mainboard/asus/a88xm-e.md
new file mode 100644
index 0000000..5f50c5a
--- /dev/null
+++ b/Documentation/mainboard/asus/a88xm-e.md
@@ -0,0 +1,131 @@
+# ASUS A88XM-E
+
+This page describes how to run coreboot on the [ASUS A88XM-E].
+
+## Technology
+
+Both "Trinity" and "Richland" FM2 desktop processing units are working,
+the CPU architecture in these CPUs/APUs are [Piledriver],
+and their GPU is [TeraScale 3] (VLIW4-based).
+
+Kaveri is non-working at the moment (FM2+),
+the CPU architecture in these CPUs/APUs are [Steamroller],
+and their GPU is [Sea Islands] (GCN2-based).
+
+```eval_rst
++------------------+--------------------------------------------------+
+| A88XM-E | |
++------------------+--------------------------------------------------+
+| DDR voltage IC | Nuvoton 3101S |
++------------------+--------------------------------------------------+
+| Network | Realtek RTL8111G - Not working |
++------------------+--------------------------------------------------+
+| Northbridge | Integrated into CPU with IMC and GPU (APUs only) |
++------------------+--------------------------------------------------+
+| Southbridge | Bolton-D4 |
++------------------+--------------------------------------------------+
+| Sound IC | Realtek ALC887 |
++------------------+--------------------------------------------------+
+| Super I/O | ITE 8603E |
++------------------+--------------------------------------------------+
+| VRM controller | DIGI VRM ASP1206 |
++------------------+--------------------------------------------------+
+```
+
+## Flashing coreboot
+
+```eval_rst
++---------------------+------------+
+| Type | Value |
++=====================+============+
+| Socketed flash | yes |
++---------------------+------------+
+| Model | [GD25Q64] |
++---------------------+------------+
+| Size | 8 MiB |
++---------------------+------------+
+| Package | DIP-8 |
++---------------------+------------+
+| Write protection | yes |
++---------------------+------------+
+| Dual BIOS feature | no |
++---------------------+------------+
+| Internal flashing | yes |
++---------------------+------------+
+```
+
+### Internal programming
+
+The main SPI flash can be accessed using [flashrom], if the
+AmdSpiRomProtect modules have been deleted in the factory image previously.
+
+## Integrated graphics
+
+### Retrieve the VGA optionrom from the vendor EFI binary by running:
+
+ # dd if=/dev/mem of=vgabios.bin bs=1k count=64 skip=768
+
+This version is usable for all the GPUs.
+1002,9901 Trinity (Radeon HD 7660D)
+1002,9904 Trinity (Radeon HD 7560D)
+1002,990c Richland (Radeon HD 8670D)
+1002,990e Richland (Radeon HD 8570D)
+1002,9991 Trinity (Radeon HD 7540D)
+1002,9993 Trinity (Radeon HD 7480D)
+1002,9996 Richland (Radeon HD 8470D)
+1002,9998 Richland (Radeon HD 8370D)
+1002,999d Richland (Radeon HD 8550D)
+1002,130f Kaveri (Radeon R7)
+
+## Known issues
+
+- AHCI hot-plug
+- Integrated ethernet
+- S3 resume
+- XHCI
+
+### XHCI ports can broke after using any of the blobs, restarting the
+board with factory image makes it work again as fallback.
+Tested even with/without the Bolton and Hudson blobs.
+
+## Untested
+
+- audio over HDMI
+- IOMMU
+- PS/2 mouse
+
+## TODOs
+
+- one ATOMBIOS module for all the integrated GPUs
+- manage to work with Kaveri/Godavary (missing PSP firmware?)
+
+## Working
+
+- ACPI
+- CPU frequency scaling
+- flashrom under coreboot
+- Hardware monitoring
+- Integrated graphics
+- Keyboard
+- KVM virtualization
+- Onboard audio
+- PCI
+- PCIe
+- PS/2 keyboard (during payload, bootloader)
+- SATA
+- Serial port
+- SuperIO based fan control
+- USB (disabling XHCI controller makes to work as fallback USB2.0 ports)
+
+## Extra resources
+
+- [Board manual]
+
+[ASUS A88XM-E]: https://www.asus.com/Motherboards/A88XME/
+[Board manual]: https://dlcdnets.asus.com/pub/ASUS/mb/SocketFM2/A88XM-E/E9125_A88XM-E.pdf
+[flashrom]: https://flashrom.org/Flashrom
+[GD25Q64]: http://www.elm-tech.com/ja/products/spi-flash-memory/gd25q64/gd25q64.pdf
+[Piledriver]: https://en.wikipedia.org/wiki/Piledriver_%28microarchitecture%29#APU_lines
+[Sea Islands]: https://en.wikipedia.org/wiki/Graphics_Core_Next#GCN_2nd_generation
+[Steamroller]: https://en.wikipedia.org/wiki/Steamroller_(microarchitecture)
+[TeraScale 3]: https://en.wikipedia.org/wiki/TeraScale_%28microarchitecture%29#TeraScale_3
diff --git a/src/mainboard/asus/a88xm-e/BiosCallOuts.c b/src/mainboard/asus/a88xm-e/BiosCallOuts.c
new file mode 100644
index 0000000..56c1753
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/BiosCallOuts.c
@@ -0,0 +1,98 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <AGESA.h>
+#include <northbridge/amd/agesa/BiosCallOuts.h>
+#include <northbridge/amd/agesa/state_machine.h>
+
+#include <vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h>
+#include <stdlib.h>
+
+const BIOS_CALLOUT_STRUCT BiosCallouts[] =
+{
+ {AGESA_DO_RESET, agesa_Reset },
+ {AGESA_READ_SPD, agesa_ReadSpd },
+ {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported },
+ {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp },
+ {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData },
+ {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess },
+ {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess },
+ {AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage }
+};
+const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
+
+/**
+ * ASUS A88XM-E board ALC887-VD Verb Table
+ *
+ * Copied from `/sys/class/sound/hwC1D0/init_pin_configs` when running
+ * the vendor BIOS.
+ */
+#if !IS_ENABLED(CONFIG_BOARD_ASUS_A88XM_E)
+const CODEC_ENTRY a88xm_e_alc887_VerbTbl[] = {
+ {0x11, 0x90460130},
+ {0x12, 0x40330000},
+ {0x14, 0x01014010},
+ {0x15, 0x411111f0},
+ {0x16, 0x411111f0},
+ {0x17, 0x411111f0},
+ {0x18, 0x01a19040},
+ {0x19, 0x02a19050},
+ {0x1a, 0x0181304f},
+ {0x1b, 0x02214020},
+ {0x1c, 0x411111f0},
+ {0x1d, 0x4044c601},
+ {0x1e, 0x411111f0},
+ {0x1f, 0x411111f0}
+ };
+#else
+const CODEC_ENTRY a88xm_e_alc887_VerbTbl[] = {
+ {0x11, 0x90460130},
+ {0x12, 0x40330000},
+ {0x14, 0x01014010},
+ {0x15, 0x411111f0},
+ {0x16, 0x411111f0},
+ {0x17, 0x411111f0},
+ {0x18, 0x01a19040},
+ {0x19, 0x02a19050},
+ {0x1a, 0x0181304f},
+ {0x1b, 0x02214020},
+ {0x1c, 0x411111f0},
+ {0x1d, 0x4044c601},
+ {0x1e, 0x411111f0},
+ {0x1f, 0x411111f0}
+};
+#endif
+
+static const CODEC_TBL_LIST CodecTableList[] =
+{
+ {0x10ec0887, (CODEC_ENTRY*)&a88xm_e_alc887_VerbTbl[0]},
+ {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL}
+};
+
+void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset)
+{
+ FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE);
+}
+
+void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams_env)
+{
+ /* Azalia Controller OEM Codec Table Pointer */
+ FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&CodecTableList[0]);
+
+ /* Fan Control */
+ FchParams_env->Imc.ImcEnable = FALSE;
+ FchParams_env->Hwm.HwMonitorEnable = FALSE;
+ FchParams_env->Hwm.HwmFchtsiAutoPoll = FALSE;/* 1 enable, 0 disable TSI Auto Polling */
+}
diff --git a/src/mainboard/asus/a88xm-e/Kconfig b/src/mainboard/asus/a88xm-e/Kconfig
new file mode 100644
index 0000000..70be2f1
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/Kconfig
@@ -0,0 +1,117 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+# Copyright (C) 2012 Rudolf Marek <r.marek(a)assembler.cz>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+if BOARD_ASUS_A88XM_E
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select CPU_AMD_AGESA_FAMILY15_TN
+ select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN
+ select SOUTHBRIDGE_AMD_AGESA_HUDSON
+ select HAVE_OPTION_TABLE
+ select HAVE_PIRQ_TABLE
+ select HAVE_MP_TABLE
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select SUPERIO_ITE_IT8728F
+ select BOARD_ROMSIZE_KB_8192
+ select GFXUMA
+
+choice
+ prompt "DDR3 memory voltage"
+ default BOARD_ASUS_A88XM_E_DDR3_VOLT_150
+
+config BOARD_ASUS_A88XM_E_DDR3_VOLT_135
+ bool "1.35V"
+ help
+ Set DRR3 memory voltage to 1.35V
+config BOARD_ASUS_A88XM_E_DDR3_VOLT_150
+ bool "1.50V"
+ help
+ Set DRR3 memory voltage to 1.50V
+config BOARD_ASUS_A88XM_E_DDR3_VOLT_165
+ bool "1.65V"
+ help
+ Set DRR3 memory voltage to 1.65V
+endchoice
+
+config BOARD_ASUS_A88XM_E_DDR3_VOLT_VAL
+ hex
+ default 0x9e if BOARD_ASUS_A88XM_E_DDR3_VOLT_135
+ default 0x0 if BOARD_ASUS_A88XM_E_DDR3_VOLT_150
+ default 0x1e if BOARD_ASUS_A88XM_E_DDR3_VOLT_165
+
+config MAINBOARD_DIR
+ string
+ default asus/a88xm-e
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "A88XM-E" if BOARD_ASUS_A88XM_E
+
+config HW_MEM_HOLE_SIZEK
+ hex
+ default 0x200000
+
+config MAX_CPUS
+ int
+ default 4
+
+config HUDSON_XHCI_FWM
+ bool
+ default n
+
+config HUDSON_IMC_FWM
+ bool
+ default n
+
+config IRQ_SLOT_COUNT
+ int
+ default 11
+
+config ONBOARD_VGA_IS_PRIMARY
+ bool
+ default y
+
+config VGA_BIOS_ID
+ string
+ default "1002,990e"
+
+config CONFIG_DRIVERS_PS2_KEYBOARD
+ bool
+ default y
+
+config CONFIG_HUDSON_XHCI_ENABLE
+ bool
+ default n
+
+config HUDSON_LEGACY_FREE
+ bool
+ default n
+
+config POST_IO
+ bool
+ default n
+
+config CONFIG_POST_DEVICE_PCI_PCIE
+ bool
+ default y
+
+config DEVICETREE
+ string
+ default "devicetree_a88xm-e.cb"
+
+endif # BOARD_ASUS_A88XM_E
diff --git a/src/mainboard/asus/a88xm-e/Kconfig.name b/src/mainboard/asus/a88xm-e/Kconfig.name
new file mode 100644
index 0000000..492d610
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_ASUS_A88XM_E
+ bool "A88XM-E"
diff --git a/src/mainboard/asus/a88xm-e/Makefile.inc b/src/mainboard/asus/a88xm-e/Makefile.inc
new file mode 100644
index 0000000..f8895fa
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/Makefile.inc
@@ -0,0 +1,22 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+romstage-y += buildOpts.c
+romstage-y += BiosCallOuts.c
+romstage-y += OemCustomize.c
+
+ramstage-y += buildOpts.c
+ramstage-y += BiosCallOuts.c
+ramstage-y += OemCustomize.c
diff --git a/src/mainboard/asus/a88xm-e/OemCustomize.c b/src/mainboard/asus/a88xm-e/OemCustomize.c
new file mode 100644
index 0000000..4c4c5bf
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/OemCustomize.c
@@ -0,0 +1,177 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <Porting.h>
+#include <AGESA.h>
+
+#include <northbridge/amd/agesa/state_machine.h>
+#include <PlatformMemoryConfiguration.h>
+
+/*
+ * Lane ID Mapping (from Fam15h BKDG: Table 45: Lane Id Mapping)
+ *
+ * Lane Id
+ * 0 P_UMI_[T,R]X[P,N]0 - southbridge link, connect via dev 8
+ * 1 P_UMI_[T,R]X[P,N]1 - southbridge link, connect via dev 8
+ * 2 P_UMI_[T,R]X[P,N]2 - southbridge link, connect via dev 8
+ * 3 P_UMI_[T,R]X[P,N]3 - southbridge link, connect via dev 8
+ * 4 P_GPP_[T,R]X[P,N]0 - may connect to PCI dev 4 - 7
+ * 5 P_GPP_[T,R]X[P,N]1 - may connect to PCI dev 4 - 7
+ * 6 P_GPP_[T,R]X[P,N]2 - may connect to PCI dev 4 - 7
+ * 7 P_GPP_[T,R]X[P,N]3 - may connect to PCI dev 4 - 7
+ * 8 P_GFX_[T,R]X[P,N]0 - may be used to form GFX slot or DDI
+ * 9 P_GFX_[T,R]X[P,N]1 - may be used to form GFX slot or DDI
+ * 10 P_GFX_[T,R]X[P,N]2 - may be used to form GFX slot or DDI
+ * 11 P_GFX_[T,R]X[P,N]3 - may be used to form GFX slot or DDI
+ * 12 P_GFX_[T,R]X[P,N]4 - may be used to form GFX slot or DDI
+ * 13 P_GFX_[T,R]X[P,N]5 - may be used to form GFX slot or DDI
+ * 14 P_GFX_[T,R]X[P,N]6 - may be used to form GFX slot or DDI
+ * 15 P_GFX_[T,R]X[P,N]7 - may be used to form GFX slot or DDI
+ * 16 P_GFX_[T,R]X[P,N]8 - may be used to form GFX slot or DDI
+ * 17 P_GFX_[T,R]X[P,N]9 - may be used to form GFX slot or DDI
+ * 18 P_GFX_[T,R]X[P,N]10 - may be used to form GFX slot or DDI
+ * 19 P_GFX_[T,R]X[P,N]11 - may be used to form GFX slot or DDI
+ * 20 P_GFX_[T,R]X[P,N]12 - may be used to form GFX slot or DDI
+ * 21 P_GFX_[T,R]X[P,N]13 - may be used to form GFX slot or DDI
+ * 22 P_GFX_[T,R]X[P,N]14 - may be used to form GFX slot or DDI
+ * 23 P_GFX_[T,R]X[P,N]15 - may be used to form GFX slot or DDI
+ * 24 DP0_TX[P,N]0 - rest is just for DDI (graphics outputs)
+ * 25 DP0_TX[P,N]1
+ * 26 DP0_TX[P,N]2
+ * 27 DP0_TX[P,N]3
+ * 28 DP1_TX[P,N]0
+ * 29 DP1_TX[P,N]1
+ * 30 DP1_TX[P,N]2
+ * 31 DP1_TX[P,N]3
+ * 32 DP2_TX[P,N]0
+ * 33 DP2_TX[P,N]1
+ * 34 DP2_TX[P,N]2
+ * 35 DP2_TX[P,N]3
+ * 36 DP2_TX[P,N]4
+ * 37 DP2_TX[P,N]5
+ * 38 DP2_TX[P,N]6
+ */
+
+static const PCIe_PORT_DESCRIPTOR PortList[] = {
+ /* PCIe port, Lanes 8:23, PCI Device Number 2, blue x16 slot */
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 8, 23),
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 1)
+ },
+ /* PCIe port, Lanes 4:7, PCI Device Number 4, black x16 slot (in fact x4) */
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7),
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 1)
+ },
+ /* PCIe port, Lanes 0:3, UMI link to SB, PCI Device Number 8 */
+ {
+ DESCRIPTOR_TERMINATE_LIST,
+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 0)
+ },
+};
+
+/*
+ * It is not known, if the setup is complete.
+ *
+ * Tested and works: VGA/DVI
+ * Untested: HDMI
+ */
+static const PCIe_DDI_DESCRIPTOR DdiList[] = {
+ // DP0 to HDMI0/DP
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 24, 27),
+ PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux1, Hdp1)
+ },
+ // DP1 to FCH
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 28, 31),
+ PCIE_DDI_DATA_INITIALIZER(ConnectorTypeNutmegDpToVga, Aux2, Hdp2)
+ },
+ // DP2 to HDMI1/DP
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 32, 35),
+ PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux3, Hdp3)
+ },
+};
+
+static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
+ .Flags = DESCRIPTOR_TERMINATE_LIST,
+ .SocketId = 0,
+ .PciePortList = PortList,
+ .DdiLinkList = DdiList,
+};
+
+void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
+{
+ FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface;
+ FchReset->Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
+ FchReset->Xhci1Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
+}
+
+void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
+{
+ InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
+ InitEarly->GnbConfig.PsppPolicy = 0;
+}
+
+/*----------------------------------------------------------------------------------------
+ * CUSTOMER OVERIDES MEMORY TABLE
+ *----------------------------------------------------------------------------------------
+ */
+
+/*
+ * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
+ * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
+ * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
+ * use its default conservative settings.
+ */
+
+static CONST PSO_ENTRY ROMDATA MemoryTable_XM_E[] = {
+
+ NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 1),
+ NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2),
+
+ PSO_END
+};
+
+void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
+{
+ if (IS_ENABLED(CONFIG_BOARD_ASUS_A88XM_E))
+ InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *) MemoryTable_XM_E;
+}
+
+void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid)
+{
+ /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
+ InitMid->GnbMidConfiguration.iGpuVgaMode = 0;
+}
diff --git a/src/mainboard/asus/a88xm-e/OptionsIds.h b/src/mainboard/asus/a88xm-e/OptionsIds.h
new file mode 100644
index 0000000..b45f5a8
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/OptionsIds.h
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/**
+ * @file
+ *
+ * IDS Option File
+ *
+ * This file is used to switch on/off IDS features.
+ *
+ */
+#ifndef _OPTION_IDS_H_
+#define _OPTION_IDS_H_
+
+/**
+ *
+ * This file generates the defaults tables for the Integrated Debug Support
+ * Module. The documented build options are imported from a user controlled
+ * file for processing. The build options for the Integrated Debug Support
+ * Module are listed below:
+ *
+ * IDSOPT_IDS_ENABLED
+ * IDSOPT_ERROR_TRAP_ENABLED
+ * IDSOPT_CONTROL_ENABLED
+ * IDSOPT_TRACING_ENABLED
+ * IDSOPT_PERF_ANALYSIS
+ * IDSOPT_ASSERT_ENABLED
+ * IDS_DEBUG_PORT
+ * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
+ *
+ **/
+
+//#define IDSOPT_IDS_ENABLED TRUE
+//#define IDSOPT_CONTROL_ENABLED TRUE
+#define IDSOPT_TRACING_ENABLED TRUE
+#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE
+//#define IDSOPT_PERF_ANALYSIS TRUE
+#define IDSOPT_ASSERT_ENABLED TRUE
+//#undef IDSOPT_DEBUG_ENABLED
+//#define IDSOPT_DEBUG_ENABLED FALSE
+//#undef IDSOPT_HOST_SIMNOW
+//#define IDSOPT_HOST_SIMNOW FALSE
+//#undef IDSOPT_HOST_HDT
+//#define IDSOPT_HOST_HDT FALSE
+//#define IDS_DEBUG_PORT 0x80
+
+#endif
diff --git a/src/mainboard/asus/a88xm-e/acpi/cpstate.asl b/src/mainboard/asus/a88xm-e/acpi/cpstate.asl
new file mode 100644
index 0000000..69de2d8
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/cpstate.asl
@@ -0,0 +1,112 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* This file defines the processor and performance state capability
+ * for each core in the system. It is included into the DSDT for each
+ * core. It assumes that each core of the system has the same performance
+ * characteristics.
+*/
+/*
+#include <arch/acpi.h>
+DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001)
+ {
+ Scope (\_PR) {
+ Processor(CPU0,0,0x808,0x06) {
+ #include "cpstate.asl"
+ }
+ Processor(CPU1,1,0x0,0x0) {
+ #include "cpstate.asl"
+ }
+ Processor(CPU2,2,0x0,0x0) {
+ #include "cpstate.asl"
+ }
+ Processor(CPU3,3,0x0,0x0) {
+ #include "cpstate.asl"
+ }
+ }
+*/
+ /* P-state support: The maximum number of P-states supported by the */
+ /* CPUs we'll use is 6. */
+ /* Get from AMI BIOS. */
+ Name(_PSS, Package(){
+ Package()
+ {
+ 0x00000D48,
+ 0x00011170,
+ 0x00000004,
+ 0x00000004,
+ 0x00000000,
+ 0x00000000
+ },
+
+ Package()
+ {
+ 0x00000AF0,
+ 0x0000C544,
+ 0x00000004,
+ 0x00000004,
+ 0x00000001,
+ 0x00000001
+ },
+
+ Package()
+ {
+ 0x000009C4,
+ 0x0000B3B0,
+ 0x00000004,
+ 0x00000004,
+ 0x00000002,
+ 0x00000002
+ },
+
+ Package()
+ {
+ 0x00000898,
+ 0x0000ABE0,
+ 0x00000004,
+ 0x00000004,
+ 0x00000003,
+ 0x00000003
+ },
+
+ Package()
+ {
+ 0x00000708,
+ 0x0000A410,
+ 0x00000004,
+ 0x00000004,
+ 0x00000004,
+ 0x00000004
+ },
+
+ Package()
+ {
+ 0x00000578,
+ 0x00006F54,
+ 0x00000004,
+ 0x00000004,
+ 0x00000005,
+ 0x00000005
+ }
+ })
+
+ Name(_PCT, Package(){
+ ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},
+ ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}
+ })
+
+ Method(_PPC, 0){
+ Return(0)
+ }
diff --git a/src/mainboard/asus/a88xm-e/acpi/gpe.asl b/src/mainboard/asus/a88xm-e/acpi/gpe.asl
new file mode 100644
index 0000000..297db37
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/gpe.asl
@@ -0,0 +1,72 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Scope(\_GPE) { /* Start Scope GPE */
+
+ /* General event 3 */
+ Method(_L03) {
+ /* DBGO("\\_GPE\\_L00\n") */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* Legacy PM event */
+ Method(_L08) {
+ /* DBGO("\\_GPE\\_L08\n") */
+ }
+
+ /* Temp warning (TWarn) event */
+ Method(_L09) {
+ /* DBGO("\\_GPE\\_L09\n") */
+ /* Notify (\_TZ.TZ00, 0x80) */
+ }
+
+ /* USB controller PME# */
+ Method(_L0B) {
+ /* DBGO("\\_GPE\\_L0B\n") */
+ Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* ExtEvent0 SCI event */
+ Method(_L10) {
+ /* DBGO("\\_GPE\\_L10\n") */
+ }
+
+
+ /* ExtEvent1 SCI event */
+ Method(_L11) {
+ /* DBGO("\\_GPE\\_L11\n") */
+ }
+
+ /* GPIO0 or GEvent8 event */
+ Method(_L18) {
+ /* DBGO("\\_GPE\\_L18\n") */
+ Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* Azalia SCI event */
+ Method(_L1B) {
+ /* DBGO("\\_GPE\\_L1B\n") */
+ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+} /* End Scope GPE */
diff --git a/src/mainboard/asus/a88xm-e/acpi/mainboard.asl b/src/mainboard/asus/a88xm-e/acpi/mainboard.asl
new file mode 100644
index 0000000..8398c88
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/mainboard.asl
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+ /* Data to be patched by the BIOS during POST */
+ /* FIXME the patching is not done yet! */
+ /* Memory related values */
+ Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
+ Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
+ Name(PBLN, 0x0) /* Length of BIOS area */
+
+ Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
+ Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
+ Name(HPBA, 0xFED00000) /* Base address of HPET table */
+
+ /* Some global data */
+ Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
+ Name(OSV, Ones) /* Assume nothing */
+ Name(PMOD, One) /* Assume APIC */
diff --git a/src/mainboard/asus/a88xm-e/acpi/routing.asl b/src/mainboard/asus/a88xm-e/acpi/routing.asl
new file mode 100644
index 0000000..0af6b42
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/routing.asl
@@ -0,0 +1,258 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+ /* Routing is in System Bus scope */
+ Name(PR0, Package(){
+ /* NB devices */
+ /* Bus 0, Dev 0 - F15 Host Controller */
+ Package(){0x0000FFFF, 0, INTA, 0 },
+ Package(){0x0000FFFF, 1, INTB, 0 },
+ Package(){0x0000FFFF, 2, INTC, 0 },
+ Package(){0x0000FFFF, 3, INTD, 0 },
+
+ /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
+ Package(){0x0001FFFF, 0, INTB, 0 },
+ Package(){0x0001FFFF, 1, INTC, 0 },
+
+ /* Bus 0, Dev 2 - PCIe Bridge for x16 slot */
+ Package(){0x0002FFFF, 0, INTC, 0 },
+ Package(){0x0002FFFF, 1, INTD, 0 },
+ Package(){0x0002FFFF, 2, INTA, 0 },
+ Package(){0x0002FFFF, 3, INTB, 0 },
+
+ /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
+
+ /* Bus 0, Dev 4 - PCIe Bridge for 4x slot */
+ Package(){0x0004FFFF, 0, INTA, 0 },
+ Package(){0x0004FFFF, 1, INTB, 0 },
+ Package(){0x0004FFFF, 2, INTC, 0 },
+ Package(){0x0004FFFF, 3, INTD, 0 },
+
+ /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
+ /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
+ /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
+ /* Bus 0, Dev 8 - Southbridge port (normally hidden) */
+
+ /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */
+ Package(){0x0014FFFF, 0, INTA, 0 },
+ Package(){0x0014FFFF, 1, INTB, 0 },
+ Package(){0x0014FFFF, 2, INTC, 0 },
+ Package(){0x0014FFFF, 3, INTD, 0 },
+
+ /* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0
+ * EHCI @ func 2 */
+ Package(){0x0012FFFF, 0, INTC, 0 },
+ Package(){0x0012FFFF, 1, INTB, 0 },
+
+ Package(){0x0013FFFF, 0, INTC, 0 },
+ Package(){0x0013FFFF, 1, INTB, 0 },
+
+ Package(){0x0016FFFF, 0, INTC, 0 },
+ Package(){0x0016FFFF, 1, INTB, 0 },
+
+ /* SB devices */
+ /* Bus 0, Dev 16 - USB: XHCI func 0, 1 */
+ Package(){0x0010FFFF, 0, INTC, 0 },
+ Package(){0x0010FFFF, 1, INTB, 0 },
+
+ /* Bus 0, Dev 17 - SATA controller */
+ Package(){0x0011FFFF, 0, INTD, 0 },
+
+ /* Bus 0, Dev 21 Pcie Bridge */
+ Package(){0x0015FFFF, 0, INTA, 0 },
+ Package(){0x0015FFFF, 1, INTB, 0 },
+ Package(){0x0015FFFF, 2, INTC, 0 },
+ Package(){0x0015FFFF, 3, INTD, 0 },
+ })
+
+ Name(APR0, Package(){
+ /* NB devices in APIC mode */
+ /* Bus 0, Dev 0 - F15 Host Controller */
+ Package(){0x0000FFFF, 0, 0, 16 },
+ Package(){0x0000FFFF, 1, 0, 17 },
+ Package(){0x0000FFFF, 2, 0, 18 },
+ Package(){0x0000FFFF, 3, 0, 19 },
+
+ /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
+ Package(){0x0001FFFF, 0, 0, 17 },
+ Package(){0x0001FFFF, 1, 0, 18 },
+
+ /* Bus 0, Dev 2 - PCIe Bridge for x16 PCIe Slot */
+ Package(){0x0002FFFF, 0, 0, 18 },
+ Package(){0x0002FFFF, 1, 0, 19 },
+ Package(){0x0002FFFF, 2, 0, 16 },
+ Package(){0x0002FFFF, 3, 0, 17 },
+
+ /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
+
+ /* Bus 0, Dev 4 - PCIe Bridge for x4 PCIe Slot black */
+ Package(){0x0004FFFF, 0, 0, 16 },
+ Package(){0x0004FFFF, 1, 0, 17 },
+ Package(){0x0004FFFF, 2, 0, 18 },
+ Package(){0x0004FFFF, 3, 0, 19 },
+
+ /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
+ /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
+ /* Bus 0, Dev 7 - PCIe Bridge for network card */
+ /* Bus 0, Dev 8 - Southbridge port (normally hidden) */
+
+ /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
+ Package(){0x0014FFFF, 0, 0, 16 },
+ Package(){0x0014FFFF, 1, 0, 17 },
+ Package(){0x0014FFFF, 2, 0, 18 },
+ Package(){0x0014FFFF, 3, 0, 19 },
+
+ /* SB devices in APIC mode */
+ /* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0
+ * EHCI @ func 2 */
+ Package(){0x0012FFFF, 0, 0, 18 },
+ Package(){0x0012FFFF, 1, 0, 17 },
+
+ Package(){0x0013FFFF, 0, 0, 18 },
+ Package(){0x0013FFFF, 1, 0, 17 },
+
+ Package(){0x0016FFFF, 0, 0, 18 },
+ Package(){0x0016FFFF, 1, 0, 17 },
+
+ /* Bus 0, Dev 16 - USB: XHCI func 0, 1 */
+ Package(){0x0010FFFF, 0, 0, 0x12},
+ Package(){0x0010FFFF, 1, 0, 0x11},
+
+ /* Bus 0, Dev 17 - SATA controller */
+ Package(){0x0011FFFF, 0, 0, 19 },
+
+ /* Bus 0, Dev 21 PCIE Bridge */
+ Package(){0x0015FFFF, 0, 0, 17 },
+ Package(){0x0015FFFF, 1, 0, 18 },
+ Package(){0x0015FFFF, 2, 0, 19 },
+ Package(){0x0015FFFF, 3, 0, 16 },
+ })
+
+ Name(PS2, Package(){
+ /* The external GFX - Hooked to PCIe slot 2 */
+ Package(){0x0000FFFF, 0, INTD, 0 },
+ Package(){0x0000FFFF, 1, INTA, 0 },
+ Package(){0x0000FFFF, 2, INTB, 0 },
+ Package(){0x0000FFFF, 3, INTC, 0 },
+ })
+ Name(APS2, Package(){
+ /* The external GFX - Hooked to PCIe slot 2 */
+ Package(){0x0000FFFF, 0, 0, 18 },
+ Package(){0x0000FFFF, 1, 0, 19 },
+ Package(){0x0000FFFF, 2, 0, 16 },
+ Package(){0x0000FFFF, 3, 0, 17 },
+ })
+
+ /* black slot */
+ Name(PS4, Package(){
+ /* PCIe slot - Hooked to PCIe slot 4 */
+ Package(){0x0000FFFF, 0, INTA, 0 },
+ Package(){0x0000FFFF, 1, INTB, 0 },
+ Package(){0x0000FFFF, 2, INTC, 0 },
+ Package(){0x0000FFFF, 3, INTD, 0 },
+ })
+ Name(APS4, Package(){
+ /* PCIe slot - Hooked to PCIe slot 4 */
+ Package(){0x0000FFFF, 0, 0, 16 },
+ Package(){0x0000FFFF, 1, 0, 17 },
+ Package(){0x0000FFFF, 2, 0, 18 },
+ Package(){0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name(PS5, Package(){
+ /* PCIe slot - Hooked to PCIe slot 5 */
+ Package(){0x0000FFFF, 0, INTB, 0 },
+ Package(){0x0000FFFF, 1, INTC, 0 },
+ Package(){0x0000FFFF, 2, INTD, 0 },
+ Package(){0x0000FFFF, 3, INTA, 0 },
+ })
+ Name(APS5, Package(){
+ /* PCIe slot - Hooked to PCIe slot 5 */
+ Package(){0x0000FFFF, 0, 0, 17 },
+ Package(){0x0000FFFF, 1, 0, 18 },
+ Package(){0x0000FFFF, 2, 0, 19 },
+ Package(){0x0000FFFF, 3, 0, 16 },
+ })
+
+ Name(PS6, Package(){
+ /* PCIe slot - Hooked to PCIe slot 6 */
+ Package(){0x0000FFFF, 0, INTC, 0 },
+ Package(){0x0000FFFF, 1, INTD, 0 },
+ Package(){0x0000FFFF, 2, INTA, 0 },
+ Package(){0x0000FFFF, 3, INTB, 0 },
+ })
+ Name(APS6, Package(){
+ /* PCIe slot - Hooked to PCIe slot 6 */
+ Package(){0x0000FFFF, 0, 0, 18 },
+ Package(){0x0000FFFF, 1, 0, 19 },
+ Package(){0x0000FFFF, 2, 0, 16 },
+ Package(){0x0000FFFF, 3, 0, 17 },
+ })
+
+ Name(PS7, Package(){
+ /* The onboard Ethernet chip - Hooked to PCIe slot 7 */
+ Package(){0x0000FFFF, 0, INTD, 0 },
+ Package(){0x0000FFFF, 1, INTA, 0 },
+ Package(){0x0000FFFF, 2, INTB, 0 },
+ Package(){0x0000FFFF, 3, INTC, 0 },
+ })
+
+ Name(APS7, Package(){
+ /* The onboard Ethernet chip - Hooked to PCIe slot 7 */
+ Package(){0x0000FFFF, 0, 0, 19 },
+ Package(){0x0000FFFF, 1, 0, 16 },
+ Package(){0x0000FFFF, 2, 0, 17 },
+ Package(){0x0000FFFF, 3, 0, 18 },
+ })
+
+ Name(PBR0, Package(){
+ /* PCIx1 on SB */
+ Package(){0x0000FFFF, 0, INTA, 0 },
+ Package(){0x0000FFFF, 1, INTB, 0 },
+ Package(){0x0000FFFF, 2, INTC, 0 },
+ Package(){0x0000FFFF, 3, INTD, 0 },
+ })
+ Name(ABR0, Package(){
+ /* PCIx1 on SB */
+ Package(){0x0000FFFF, 0, 0, 0x10 },
+ Package(){0x0000FFFF, 1, 0, 0x11 },
+ Package(){0x0000FFFF, 2, 0, 0x12 },
+ Package(){0x0000FFFF, 3, 0, 0x13 },
+ })
+
+ Name(PBR1, Package(){
+ /* Onboard network */
+ Package(){0x0000FFFF, 0, INTB, 0 },
+ Package(){0x0000FFFF, 1, INTC, 0 },
+ Package(){0x0000FFFF, 2, INTD, 0 },
+ Package(){0x0000FFFF, 3, INTA, 0 },
+ })
+ Name(ABR1, Package(){
+ /* Onboard network */
+ Package(){0x0000FFFF, 0, 0, 0x11 },
+ Package(){0x0000FFFF, 1, 0, 0x12 },
+ Package(){0x0000FFFF, 2, 0, 0x13 },
+ Package(){0x0000FFFF, 3, 0, 0x10 },
+ })
+
+ /* SB PCI Bridge */
+ Name(PCIB, Package(){
+ /* PCI slots: slot 0 behind Dev14, Fun4. */
+ Package(){0x0005FFFF, 0, 0, 0x14 },
+ Package(){0x0005FFFF, 1, 0, 0x15 },
+ Package(){0x0005FFFF, 2, 0, 0x16 },
+ Package(){0x0005FFFF, 3, 0, 0x17 },
+ })
diff --git a/src/mainboard/asus/a88xm-e/acpi/sata.asl b/src/mainboard/asus/a88xm-e/acpi/sata.asl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/sata.asl
diff --git a/src/mainboard/asus/a88xm-e/acpi/si.asl b/src/mainboard/asus/a88xm-e/acpi/si.asl
new file mode 100644
index 0000000..ff0c3cf
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/si.asl
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+ Scope(\_SI) {
+ Method(_SST, 1) {
+ /* DBGO("\\_SI\\_SST\n") */
+ /* DBGO(" New Indicator state: ") */
+ /* DBGO(Arg0) */
+ /* DBGO("\n") */
+ }
+ } /* End Scope SI */
diff --git a/src/mainboard/asus/a88xm-e/acpi/sleep.asl b/src/mainboard/asus/a88xm-e/acpi/sleep.asl
new file mode 100644
index 0000000..08b7de4
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/sleep.asl
@@ -0,0 +1,96 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* Wake status package */
+Name(WKST,Package(){Zero, Zero})
+
+/*
+* \_PTS - Prepare to Sleep method
+*
+* Entry:
+* Arg0=The value of the sleeping state S1=1, S2=2, etc
+*
+* Exit:
+* -none-
+*
+* The _PTS control method is executed at the beginning of the sleep process
+* for S1-S5. The sleeping value is passed to the _PTS control method. This
+* control method may be executed a relatively long time before entering the
+* sleep state and the OS may abort the operation without notification to
+* the ACPI driver. This method cannot modify the configuration or power
+* state of any device in the system.
+*/
+Method(\_PTS, 1) {
+ /* DBGO("\\_PTS\n") */
+ /* DBGO("From S0 to S") */
+ /* DBGO(Arg0) */
+ /* DBGO("\n") */
+
+ /* Clear sleep SMI status flag and enable sleep SMI trap. */
+ /*Store(One, CSSM)
+ Store(One, SSEN)*/
+
+ /* On older chips, clear PciExpWakeDisEn */
+ /*if (LLessEqual(\_SB.SBRI, 0x13)) {
+ * Store(0,\_SB.PWDE)
+ *}
+ */
+
+ /* Clear wake status structure. */
+ Store(0, Index(WKST,0))
+ Store(0, Index(WKST,1))
+
+ Store (0x07, UPWS)
+} /* End Method(\_PTS) */
+
+/*
+* \_BFS OEM Back From Sleep method
+*
+* Entry:
+* Arg0=The value of the sleeping state S1=1, S2=2
+*
+* Exit:
+* -none-
+*/
+Method(\_BFS, 1) {
+ /* DBGO("\\_BFS\n") */
+ /* DBGO("From S") */
+ /* DBGO(Arg0) */
+ /* DBGO(" to S0\n") */
+}
+
+/*
+* \_WAK System Wake method
+*
+* Entry:
+* Arg0=The value of the sleeping state S1=1, S2=2
+*
+* Exit:
+* Return package of 2 DWords
+* Dword 1 - Status
+* 0x00000000 wake succeeded
+* 0x00000001 Wake was signaled but failed due to lack of power
+* 0x00000002 Wake was signaled but failed due to thermal condition
+* Dword 2 - Power Supply state
+* if non-zero the effective S-state the power supply entered
+*/
+Method(\_WAK, 1) {
+ /* DBGO("\\_WAK\n") */
+ /* DBGO("From S") */
+ /* DBGO(Arg0) */
+ /* DBGO(" to S0\n") */
+
+ Return(WKST)
+} /* End Method(\_WAK) */
diff --git a/src/mainboard/asus/a88xm-e/acpi/superio.asl b/src/mainboard/asus/a88xm-e/acpi/superio.asl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/superio.asl
diff --git a/src/mainboard/asus/a88xm-e/acpi/thermal.asl b/src/mainboard/asus/a88xm-e/acpi/thermal.asl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/thermal.asl
diff --git a/src/mainboard/asus/a88xm-e/acpi/usb_oc.asl b/src/mainboard/asus/a88xm-e/acpi/usb_oc.asl
new file mode 100644
index 0000000..f5d6980
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/usb_oc.asl
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* USB overcurrent mapping pins. */
+Name(UOM0, 0)
+Name(UOM1, 2)
+Name(UOM2, 0)
+Name(UOM3, 7)
+Name(UOM4, 2)
+Name(UOM5, 2)
+Name(UOM6, 6)
+Name(UOM7, 2)
+Name(UOM8, 6)
+Name(UOM9, 6)
diff --git a/src/mainboard/asus/a88xm-e/acpi_tables.c b/src/mainboard/asus/a88xm-e/acpi_tables.c
new file mode 100644
index 0000000..f94fde0
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi_tables.c
@@ -0,0 +1,46 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+
+#include <arch/acpi.h>
+#include <arch/acpigen.h>
+#include <arch/ioapic.h>
+#include <device/pci.h>
+#include <string.h>
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+ /* create all subtables for processors */
+ current = acpi_create_madt_lapics(current);
+
+ /* Write Hudson IOAPIC, only one */
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS,
+ IO_APIC_ADDR, 0);
+
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 0, 2, 0);
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 9, 9, 0xF);
+ /* 0: mean bus 0--->ISA */
+ /* 0: PIC 0 */
+ /* 2: APIC 2 */
+ /* 5 mean: 0101 --> Edge-triggered, Active high */
+
+ /* create all subtables for processors */
+ current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1);
+ /* 1: LINT1 connect to NMI */
+
+ return current;
+}
diff --git a/src/mainboard/asus/a88xm-e/board_info.txt b/src/mainboard/asus/a88xm-e/board_info.txt
new file mode 100644
index 0000000..bc090ff
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/board_info.txt
@@ -0,0 +1,7 @@
+Category: desktop
+Board URL: https://www.asus.com/Motherboards/A88XME/
+ROM package: DIP8
+ROM protocol: [http://www.winbond.com/hq/product/code-storage-flash-memory/serial-nor-flas… SPI]
+ROM socketed: y
+Flashrom support: y (without AmdSpiRomProtect modules)
+Release year: 2014
diff --git a/src/mainboard/asus/a88xm-e/buildOpts.c b/src/mainboard/asus/a88xm-e/buildOpts.c
new file mode 100644
index 0000000..c324532
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/buildOpts.c
@@ -0,0 +1,346 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/**
+ * @file
+ *
+ * AMD User options selection for a Brazos platform solution system
+ *
+ * This file is placed in the user's platform directory and contains the
+ * build option selections desired for that platform.
+ *
+ * For Information about this file, see @ref platforminstall.
+ *
+ */
+
+#include <stdlib.h>
+
+#include <vendorcode/amd/agesa/f15tn/AGESA.h>
+
+/* Include the files that instantiate the configuration definitions. */
+#include <vendorcode/amd/agesa/f15tn/Include/AdvancedApi.h>
+#include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h>
+#include <vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatures.h>
+#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h>
+/* the next two headers depend on heapManager.h */
+#include <vendorcode/amd/agesa/f15tn/Proc/Common/CreateStruct.h>
+#include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEarlyInit.h>
+/* These tables are optional and may be used to adjust memory timing settings */
+#include <vendorcode/amd/agesa/f15tn/Proc/Mem/mm.h>
+#include <vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h>
+
+
+/* Select the CPU family. */
+#define INSTALL_FAMILY_10_SUPPORT FALSE
+#define INSTALL_FAMILY_12_SUPPORT FALSE
+#define INSTALL_FAMILY_14_SUPPORT FALSE
+#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE
+
+/* Select the CPU socket type. */
+#define INSTALL_G34_SOCKET_SUPPORT FALSE
+#define INSTALL_C32_SOCKET_SUPPORT FALSE
+#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
+#define INSTALL_S1G4_SOCKET_SUPPORT FALSE
+#define INSTALL_ASB2_SOCKET_SUPPORT FALSE
+#define INSTALL_FS1_SOCKET_SUPPORT FALSE
+#define INSTALL_FM1_SOCKET_SUPPORT FALSE
+#define INSTALL_FP2_SOCKET_SUPPORT FALSE
+#define INSTALL_FT1_SOCKET_SUPPORT FALSE
+#define INSTALL_AM3_SOCKET_SUPPORT FALSE
+
+#define INSTALL_FM2_SOCKET_SUPPORT TRUE
+
+//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE
+#define BLDOPT_REMOVE_SODIMMS_SUPPORT TRUE
+#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE
+#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE
+#define BLDOPT_REMOVE_ECC_SUPPORT TRUE
+//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE
+//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE
+#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE
+#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE
+#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE
+//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE
+#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE
+//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE
+#define BLDOPT_REMOVE_SRAT FALSE //TRUE
+#define BLDOPT_REMOVE_SLIT FALSE //TRUE
+#define BLDOPT_REMOVE_WHEA FALSE //TRUE
+#define BLDOPT_REMOVE_CRAT TRUE
+#define BLDOPT_REMOVE_DMI TRUE
+//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE
+//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE
+//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE
+//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE
+//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE
+//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE
+
+//This element selects whether P-States should be forced to be independent,
+// as reported by the ACPI _PSD object. For single-link processors,
+// setting TRUE for OS to support this feature.
+
+//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE
+
+#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS
+#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER
+/* Build configuration values here.
+ */
+#define BLDCFG_VRM_CURRENT_LIMIT 90000
+#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0
+#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 0
+#define BLDCFG_PLAT_NUM_IO_APICS 3
+#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
+#define BLDCFG_MEM_INIT_PSTATE 0
+
+#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE
+
+#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY
+#define BLDCFG_MEMORY_MODE_UNGANGED TRUE
+#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE
+#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
+#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE
+#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE
+#define BLDCFG_MEMORY_SODIMM_CAPABLE FALSE
+#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE
+#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE
+#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE
+#define BLDCFG_MEMORY_POWER_DOWN TRUE
+#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT
+#define BLDCFG_ONLINE_SPARE FALSE
+#define BLDCFG_BANK_SWIZZLE TRUE
+#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO
+#define BLDCFG_MEMORY_CLOCK_SELECT DDR1600_FREQUENCY
+#define BLDCFG_DQS_TRAINING_CONTROL TRUE
+#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE
+#define BLDCFG_USE_BURST_MODE FALSE
+#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE
+#define BLDCFG_ENABLE_ECC_FEATURE FALSE
+#define BLDCFG_ECC_REDIRECTION FALSE
+#define BLDCFG_SCRUB_DRAM_RATE 0
+#define BLDCFG_SCRUB_L2_RATE 0
+#define BLDCFG_SCRUB_L3_RATE 0
+#define BLDCFG_SCRUB_IC_RATE 0
+#define BLDCFG_SCRUB_DC_RATE 0
+#define BLDCFG_ECC_SYMBOL_SIZE 4
+#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000
+#define BLDCFG_ECC_SYNC_FLOOD FALSE
+#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE
+#define BLDCFG_1GB_ALIGN FALSE
+#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE
+#define BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM 36 // PCIE Spread Spectrum default value 0.36%
+#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770
+
+#define BLDOPT_REMOVE_ALIB FALSE
+#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto
+#define BLDCFG_PROCESSOR_SCOPE_NAME0 'P'
+#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0'
+#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6
+
+#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 200
+#define BLDCFG_CFG_ABM_SUPPORT 0
+
+//#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770
+
+// Specify the default values for the VRM controlling the VDDNB plane.
+// If not specified, the values used for the core VRM will be applied
+//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 // Not currently used on Trinity
+//#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 // Zero - disable NBPSI_L, Non-zero - enable NBPSI_L
+//#define BLDCFG_VRM_NB_SLEW_RATE 5000 // Used in calculating the VSRampSlamTime
+//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 // Not currently used on Trinity
+//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE 0 // Not currently used on Trinity
+//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 // Not currently used on Trinity
+
+#define BLDCFG_VRM_NB_CURRENT_LIMIT 60000
+
+#define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3
+#define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3
+
+#if IS_ENABLED(CONFIG_GFXUMA)
+#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED
+#define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED
+//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/
+#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M
+#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE
+#endif
+
+#define BLDCFG_IOMMU_SUPPORT TRUE
+
+#define BLDCFG_CFG_GNB_HD_AUDIO TRUE
+//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID
+//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID
+//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID
+
+/* Process the options...
+ * This file include MUST occur AFTER the user option selection settings
+ */
+/*
+ * Customized OEM build configurations for FCH component
+ */
+// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00
+// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20
+// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00
+// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400
+// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404
+// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408
+// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410
+// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420
+// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000
+// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000
+// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000
+// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0
+// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00
+// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000
+// #define BLDCFG_AZALIA_SSID 0x780D1022
+// #define BLDCFG_SMBUS_SSID 0x780B1022
+// #define BLDCFG_IDE_SSID 0x780C1022
+// #define BLDCFG_SATA_AHCI_SSID 0x78011022
+// #define BLDCFG_SATA_IDE_SSID 0x78001022
+// #define BLDCFG_SATA_RAID5_SSID 0x78031022
+// #define BLDCFG_SATA_RAID_SSID 0x78021022
+// #define BLDCFG_EHCI_SSID 0x78081022
+// #define BLDCFG_OHCI_SSID 0x78071022
+// #define BLDCFG_LPC_SSID 0x780E1022
+// #define BLDCFG_SD_SSID 0x78061022
+// #define BLDCFG_XHCI_SSID 0x78121022
+// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE
+// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE
+// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4
+// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE
+// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE
+// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE
+// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE
+// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE
+// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE
+// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE
+// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE
+
+CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
+{
+ { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E },
+ { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E },
+ { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 },
+ { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 },
+ { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 },
+ { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 },
+ { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 },
+ { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 },
+ { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 },
+ { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 },
+ { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 },
+ { CPU_LIST_TERMINAL }
+};
+
+#define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList
+
+ // This is the delivery package title, "BrazosPI"
+ // This string MUST be exactly 8 characters long
+#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'}
+
+ // This is the release version number of the AGESA component
+ // This string MUST be exactly 12 characters long
+#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '}
+
+/* MEMORY_BUS_SPEED */
+#define DDR400_FREQUENCY 200 ///< DDR 400
+#define DDR533_FREQUENCY 266 ///< DDR 533
+#define DDR667_FREQUENCY 333 ///< DDR 667
+#define DDR800_FREQUENCY 400 ///< DDR 800
+#define DDR1066_FREQUENCY 533 ///< DDR 1066
+#define DDR1333_FREQUENCY 667 ///< DDR 1333
+#define DDR1600_FREQUENCY 800 ///< DDR 1600
+#define DDR1866_FREQUENCY 933 ///< DDR 1866
+#define DDR2100_FREQUENCY 1050 ///< DDR 2100
+#define DDR2133_FREQUENCY 1066 ///< DDR 2133
+#define DDR2400_FREQUENCY 1200 ///< DDR 2400
+#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency
+
+/* QUANDRANK_TYPE*/
+#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
+#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
+
+/* USER_MEMORY_TIMING_MODE */
+#define TIMING_MODE_AUTO 0 ///< Use best rate possible
+#define TIMING_MODE_LIMITED 1 ///< Set user top limit
+#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
+
+/* POWER_DOWN_MODE */
+#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
+#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
+
+/*
+ * Agesa optional capabilities selection.
+ * Uncomment and mark FALSE those features you wish to include in the build.
+ * Comment out or mark TRUE those features you want to REMOVE from the build.
+ */
+
+#define DFLT_SMBUS0_BASE_ADDRESS 0xB00
+#define DFLT_SMBUS1_BASE_ADDRESS 0xB20
+/* The AGESA likes to enable 512 bytes region on this base for LPC bus */
+#define DFLT_SIO_PME_BASE_ADDRESS 0xE00
+#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x800
+#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x804
+#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x808
+#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x810
+#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x820
+#define DFLT_SPI_BASE_ADDRESS 0xFEC10000
+#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0
+#define DFLT_HPET_BASE_ADDRESS 0xFED00000
+#define DFLT_SMI_CMD_PORT 0xB0
+#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00
+#define DFLT_GEC_BASE_ADDRESS 0xFED61000
+#define DFLT_AZALIA_SSID 0x780D1022
+#define DFLT_SMBUS_SSID 0x780B1022
+#define DFLT_IDE_SSID 0x780C1022
+#define DFLT_SATA_AHCI_SSID 0x78011022
+#define DFLT_SATA_IDE_SSID 0x78001022
+#define DFLT_SATA_RAID5_SSID 0x78031022
+#define DFLT_SATA_RAID_SSID 0x78021022
+#define DFLT_EHCI_SSID 0x78081022
+#define DFLT_OHCI_SSID 0x78071022
+#define DFLT_LPC_SSID 0x780E1022
+#define DFLT_SD_SSID 0x78061022
+#define DFLT_XHCI_SSID 0x78121022
+#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE
+#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE
+#define DFLT_FCH_GPP_LINK_CONFIG PortA1B1C1D1
+#define DFLT_FCH_GPP_PORT0_PRESENT TRUE
+#define DFLT_FCH_GPP_PORT1_PRESENT TRUE
+#define DFLT_FCH_GPP_PORT2_PRESENT FALSE
+#define DFLT_FCH_GPP_PORT3_PRESENT FALSE
+#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE
+#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE
+#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE
+#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE
+//#define BLDCFG_IR_PIN_CONTROL 0x33
+//#define FCH_NO_XHCI_SUPPORT FALSE
+GPIO_CONTROL a88xm_e_gpio[] = {
+// {183, Function1, PullUpB},
+ {-1}
+};
+#define BLDCFG_FCH_GPIO_CONTROL_LIST (&a88xm_e_gpio[0])
+
+// The following definitions specify the default values for various parameters in which there are
+// no clearly defined defaults to be used in the common file. The values below are based on product
+// and BKDG content, please consult the AGESA Memory team for consultation.
+#define DFLT_SCRUB_DRAM_RATE (0)
+#define DFLT_SCRUB_L2_RATE (0)
+#define DFLT_SCRUB_L3_RATE (0)
+#define DFLT_SCRUB_IC_RATE (0)
+#define DFLT_SCRUB_DC_RATE (0)
+#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
+#define DFLT_VRM_SLEW_RATE (5000)
+
+/* Moving this include up will break AGESA. */
+#include <PlatformInstall.h>
diff --git a/src/mainboard/asus/a88xm-e/cmos.layout b/src/mainboard/asus/a88xm-e/cmos.layout
new file mode 100644
index 0000000..e1dbd9a
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/cmos.layout
@@ -0,0 +1,66 @@
+#*****************************************************************************
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#*****************************************************************************
+
+entries
+
+0 384 r 0 reserved_memory
+384 1 e 4 boot_option
+388 4 h 0 reboot_counter
+#392 3 r 0 unused
+395 1 e 1 hw_scrubber
+396 1 e 1 interleave_chip_selects
+397 2 e 8 max_mem_clock
+399 1 e 2 multi_core
+400 1 e 1 power_on_after_fail
+412 4 e 6 debug_level
+440 4 e 9 slow_cpu
+444 1 e 1 nmi
+445 1 e 1 iommu
+456 1 e 1 ECC_memory
+728 256 h 0 user_data
+984 16 h 0 check_sum
+# Reserve the extended AMD configuration registers
+1000 24 r 0 amd_reserved
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+6 5 Notice
+6 6 Info
+6 7 Debug
+6 8 Spew
+8 0 400Mhz
+8 1 333Mhz
+8 2 266Mhz
+8 3 200Mhz
+9 0 off
+9 1 87.5%
+9 2 75.0%
+9 3 62.5%
+9 4 50.0%
+9 5 37.5%
+9 6 25.0%
+9 7 12.5%
+
+checksums
+
+checksum 392 983 984
diff --git a/src/mainboard/asus/a88xm-e/devicetree_a88xm-e.cb b/src/mainboard/asus/a88xm-e/devicetree_a88xm-e.cb
new file mode 100644
index 0000000..e2b0eea
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/devicetree_a88xm-e.cb
@@ -0,0 +1,143 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+chip northbridge/amd/agesa/family15tn/root_complex
+
+ device cpu_cluster 0 on
+ chip cpu/amd/agesa/family15tn
+ device lapic 10 on end
+ end
+ end
+
+ device domain 0 on
+ subsystemid 0x1022 0x1410 inherit
+ chip northbridge/amd/agesa/family15tn # CPU side of HT root complex
+
+ chip northbridge/amd/agesa/family15tn # PCI side of HT root complex
+ device pci 0.0 on end # Root Complex
+ device pci 0.2 on end # IOMMU
+ device pci 1.0 on end # Internal Graphics
+ device pci 1.1 on end # Internal Audio (iGPU)
+ device pci 2.0 on end # PCIE x4/x16 yellow (?)
+ device pci 3.0 on end # unused?
+ device pci 4.0 on end # PCIE x4/x16 yellow (?)
+ device pci 5.0 off end # unused
+ device pci 6.0 off end # unused?
+ device pci 7.0 off end # LAN
+ device pci 8.0 off end # NB/SB Link P2P bridge
+ end #chip northbridge/amd/agesa/family15tn # PCI side of HT root complex
+
+ chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus
+ device pci 10.0 on end # XHCI HC0
+ device pci 10.1 on end # XHCI HC1
+ device pci 11.0 on end # SATA
+ device pci 12.0 on end # USB
+ device pci 12.2 on end # USB
+ device pci 13.0 on end # USB
+ device pci 13.2 on end # USB
+ device pci 14.0 on # SMBUS
+ chip drivers/generic/generic #dimm 0
+ device i2c 50 on end # 7-bit SPD address
+ end
+ chip drivers/generic/generic #dimm 1
+ device i2c 51 on end # 7-bit SPD address
+ end
+ end # SM
+ device pci 14.1 off end # IDE 0x439c
+ device pci 14.2 on end # HDA 0x4383
+ device pci 14.3 on # LPC 0x439d
+ chip superio/ite/it8728f
+ register "TMPIN1.mode" = "THERMAL_RESISTOR"
+ register "TMPIN2.mode" = "THERMAL_RESISTOR"
+ register "TMPIN3.mode" = "THERMAL_RESISTOR"
+
+ register "FAN1.mode" = "FAN_SMART_AUTOMATIC"
+ register "FAN1.smart.tmpin" = "1"
+ register "FAN1.smart.tmp_off" = "0x80" # never
+ register "FAN1.smart.tmp_start" = "20"
+ register "FAN1.smart.tmp_full" = "70"
+ register "FAN1.smart.tmp_delta" = "0"
+ register "FAN1.smart.smoothing" = "1"
+ register "FAN1.smart.pwm_start" = "20"
+ register "FAN1.smart.slope" = "32"
+
+ # Enable tacho reading for chassis fan.
+ register "FAN2.mode" = "FAN_MODE_OFF"
+
+ device pnp 2e.0 off # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.2 off # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.3 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.4 on # Env Controller
+ io 0x60 = 0x290
+ io 0x62 = 0x220
+ irq 0x70 = 0
+ end
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ end
+ device pnp 2e.6 off # Mouse
+ irq 0x70 = 12
+ end
+ device pnp 2e.7 on # GPIO
+ io 0x60 = 0x228 #SMI
+ io 0x62 = 0x300 #Simple I/O
+ io 0x64 = 0x238 #Phony resource IT8603E does not have it
+ irq 0x70 = 0
+ end
+ device pnp 2e.a off end # CIR
+ end #superio/ite/it8728f
+ end #
+ device pci 14.3 off end # LPC
+ device pci 14.4 on end # PCI 0x4384
+ device pci 14.5 off end # USB 2
+ device pci 14.6 off end # Gec
+ device pci 14.7 off end # SD
+ device pci 15.0 on end # PCIe 0 - onboard PCIe 1x
+ device pci 15.1 off end # unused
+ device pci 15.2 on end # PCI bridge
+ device pci 15.3 off end # unused
+ end #chip southbridge/amd/agesa/hudson
+
+ device pci 18.0 on end
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ device pci 18.4 on end
+ device pci 18.5 on end
+
+ register "spdAddrLookup" = "
+ {
+ { {0xA0, 0x00}, {0xA2, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
+ { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses
+ }"
+
+ end #chip northbridge/amd/agesa/family15tn # CPU side of HT root complex
+ end #domain
+end #chip northbridge/amd/agesa/family15tn/root_complex
diff --git a/src/mainboard/asus/a88xm-e/dsdt.asl b/src/mainboard/asus/a88xm-e/dsdt.asl
new file mode 100644
index 0000000..45a2606
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/dsdt.asl
@@ -0,0 +1,110 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* DefinitionBlock Statement */
+#include <arch/acpi.h>
+DefinitionBlock (
+ "DSDT.AML", /* Output filename */
+ "DSDT", /* Signature */
+ 0x02, /* DSDT Revision, needs to be 2 for 64bit */
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x00010001 /* OEM Revision */
+ )
+{ /* Start of ASL file */
+ /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */
+
+ /* Globals for the platform */
+ #include "acpi/mainboard.asl"
+
+ /* Describe the USB Overcurrent pins */
+ #include "acpi/usb_oc.asl"
+
+ /* PCI IRQ mapping for the Southbridge */
+ #include <southbridge/amd/agesa/hudson/acpi/pcie.asl>
+
+ /* Describe the processor tree (\_PR) */
+ #include <cpu/amd/agesa/family15tn/acpi/cpu.asl>
+
+ /* Describe the supported Sleep States for this Southbridge */
+ #include <southbridge/amd/common/acpi/sleepstates.asl>
+
+ /* Describe the Sleep Methods (WAK, PTS, GTS, etc.) for this platform */
+ #include "acpi/sleep.asl"
+
+ Scope(\_SB) {
+ /* global utility methods expected within the \_SB scope */
+ #include <arch/x86/acpi/globutil.asl>
+
+ /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */
+ #include "acpi/routing.asl"
+
+ Device(PWRB) {
+ Name(_HID, EISAID("PNP0C0C"))
+ Name(_UID, 0xAA)
+ Name(_PRW, Package () {3, 0x04})
+ Name(_STA, 0x0B)
+ }
+
+ Device(PCI0) {
+ /* Describe the AMD Northbridge */
+ #include <northbridge/amd/agesa/family15tn/acpi/northbridge.asl>
+
+ /* Describe the AMD Fusion Controller Hub Southbridge */
+ #include <southbridge/amd/agesa/hudson/acpi/fch.asl>
+
+ /**
+ * TODO: The devices listed here (SBR0 and SBR1) do not appear to
+ * be referenced anywhere and could possibly be removed.
+ */
+ Device(SBR0) { /* PCIe 1x SB */
+ Name(_ADR, 0x00150000)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT,0) {
+ If(PMOD){ Return(ABR0) } /* APIC mode */
+ Return (PBR0) /* PIC mode */
+ }
+ }
+
+ Device(SBR1) { /* Onboard network */
+ Name(_ADR, 0x00150001)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT, 0) {
+ If(PMOD){ Return(ABR1) } /* APIC mode */
+ Return (PBR1) /* PIC mode */
+ }
+ }
+ }
+
+ /* Describe PCI INT[A-H] for the Southbridge */
+ #include <southbridge/amd/agesa/hudson/acpi/pci_int.asl>
+
+ } /* End Scope(_SB) */
+
+ /* Describe SMBUS for the Southbridge */
+ #include <southbridge/amd/agesa/hudson/acpi/smbus.asl>
+
+ /* Define the General Purpose Events for the platform */
+ #include "acpi/gpe.asl"
+
+ /* Define the Thermal zones and methods for the platform */
+ #include "acpi/thermal.asl"
+
+ /* Define the System Indicators for the platform */
+ #include "acpi/si.asl"
+
+}
+/* End of ASL file */
diff --git a/src/mainboard/asus/a88xm-e/irq_tables.c b/src/mainboard/asus/a88xm-e/irq_tables.c
new file mode 100644
index 0000000..88d2160
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/irq_tables.c
@@ -0,0 +1,101 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/pirq_routing.h>
+#include <console/console.h>
+#include <device/pci_def.h>
+#include <stdint.h>
+#include <string.h>
+
+static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
+ u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
+ u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
+ u8 slot, u8 rfu)
+{
+ pirq_info->bus = bus;
+ pirq_info->devfn = devfn;
+ pirq_info->irq[0].link = link0;
+ pirq_info->irq[0].bitmap = bitmap0;
+ pirq_info->irq[1].link = link1;
+ pirq_info->irq[1].bitmap = bitmap1;
+ pirq_info->irq[2].link = link2;
+ pirq_info->irq[2].bitmap = bitmap2;
+ pirq_info->irq[3].link = link3;
+ pirq_info->irq[3].bitmap = bitmap3;
+ pirq_info->slot = slot;
+ pirq_info->rfu = rfu;
+}
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+ struct irq_routing_table *pirq;
+ struct irq_info *pirq_info;
+ u32 slot_num;
+ u8 *v;
+
+ u8 sum = 0;
+ int i;
+
+ /* Align the table to be 16 byte aligned. */
+ addr += 15;
+ addr &= ~15;
+
+ /* This table must be between 0xf0000 & 0x100000 */
+ printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
+
+ pirq = (void *)(addr);
+ v = (u8 *) (addr);
+
+ pirq->signature = PIRQ_SIGNATURE;
+ pirq->version = PIRQ_VERSION;
+
+ pirq->rtr_bus = 0;
+ pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
+
+ pirq->exclusive_irqs = 0;
+
+ pirq->rtr_vendor = 0x1002;
+ pirq->rtr_device = 0x4384;
+
+ pirq->miniport_data = 0;
+
+ memset(pirq->rfu, 0, sizeof(pirq->rfu));
+
+ pirq_info = (void *)(&pirq->checksum + 1);
+ slot_num = 0;
+
+ /* pci bridge */
+ write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4),
+ 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
+ 0);
+ pirq_info++;
+
+ slot_num++;
+
+ pirq->size = 32 + 16 * slot_num;
+
+ for (i = 0; i < pirq->size; i++)
+ sum += v[i];
+
+ sum = pirq->checksum - sum;
+
+ if (sum != pirq->checksum) {
+ pirq->checksum = sum;
+ }
+
+ printk(BIOS_INFO, "write_pirq_routing_table done.\n");
+
+ return (unsigned long)pirq_info;
+}
diff --git a/src/mainboard/asus/a88xm-e/mainboard.c b/src/mainboard/asus/a88xm-e/mainboard.c
new file mode 100644
index 0000000..2a0e618
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/mainboard.c
@@ -0,0 +1,46 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/msr.h>
+#include <device/device.h>
+
+/*************************************************
+ * enable the dedicated function in thatcher board.
+ *************************************************/
+static void mainboard_enable(struct device *dev)
+{
+ msr_t msr;
+
+ printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
+
+ msr = rdmsr(LS_CFG_MSR);
+ msr.lo &= ~(1 << 28);
+ wrmsr(LS_CFG_MSR, msr);
+
+ msr = rdmsr(DC_CFG_MSR);
+ msr.lo &= ~(1 << 4);
+ msr.lo &= ~(1 << 13);
+ wrmsr(DC_CFG_MSR, msr);
+
+ msr = rdmsr(BU_CFG_MSR);
+ msr.lo &= ~(1 << 23);
+ wrmsr(BU_CFG_MSR, msr);
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/asus/a88xm-e/mptable.c b/src/mainboard/asus/a88xm-e/mptable.c
new file mode 100644
index 0000000..d97663d
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/mptable.c
@@ -0,0 +1,181 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <arch/ioapic.h>
+#include <arch/smp/mpspec.h>
+#include <cpu/x86/lapic.h>
+#include <device/pci.h>
+#include <stdint.h>
+#include <string.h>
+#include <southbridge/amd/agesa/hudson/hudson.h>
+
+u8 picr_data[] = {
+ 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
+ 0x09,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x1F,0x1F,0x1F,0x1F
+};
+u8 intr_data[0x54] = {
+ 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
+ 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x10,0x11,0x12,0x13
+};
+
+static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length)
+{
+ mc->mpc_length += length;
+ mc->mpc_entry_count++;
+}
+
+static void my_smp_write_bus(struct mp_config_table *mc,
+ unsigned char id, const char *bustype)
+{
+ struct mpc_config_bus *mpc;
+ mpc = smp_next_mpc_entry(mc);
+ memset(mpc, '\0', sizeof(*mpc));
+ mpc->mpc_type = MP_BUS;
+ mpc->mpc_busid = id;
+ memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
+ smp_add_mpc_entry(mc, sizeof(*mpc));
+}
+
+static void *smp_write_config_table(void *v)
+{
+ struct mp_config_table *mc;
+ int bus_isa;
+ u8 byte;
+
+ /*
+ * By the time this function gets called, the IOAPIC registers
+ * have been written so they can be read to get the correct
+ * APIC ID and Version
+ */
+ u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
+
+ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+
+ mptable_init(mc, LOCAL_APIC_ADDR);
+ memcpy(mc->mpc_oem, "AMD ", 8);
+
+ smp_write_processors(mc);
+
+ //mptable_write_buses(mc, NULL, &bus_isa);
+ my_smp_write_bus(mc, 0, "PCI ");
+ my_smp_write_bus(mc, 1, "PCI ");
+ bus_isa = 0x02;
+ my_smp_write_bus(mc, bus_isa, "ISA ");
+
+ /* I/O APICs: APIC ID Version State Address */
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
+
+ /* PIC IRQ routine */
+ for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
+ outb(byte, 0xC00);
+ outb(picr_data[byte], 0xC01);
+ }
+
+ /* APIC IRQ routine */
+ for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
+ outb(byte | 0x80, 0xC00);
+ outb(intr_data[byte], 0xC01);
+ }
+
+ /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
+#define IO_LOCAL_INT(type, intr, apicid, pin) \
+ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
+ mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
+
+ /* PCI interrupts are level triggered, and are
+ * associated with a specific bus/device/function tuple.
+ */
+#define PCI_INT(bus, dev, int_sign, pin) \
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
+
+ /* IOMMU */
+ PCI_INT(0x0, 0x0, 0x0, 0x10);
+ PCI_INT(0x0, 0x0, 0x1, 0x11);
+ PCI_INT(0x0, 0x0, 0x2, 0x12);
+ PCI_INT(0x0, 0x0, 0x3, 0x13);
+
+ /* Internal VGA */
+ PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
+ PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
+
+ /* SMBUS */
+ PCI_INT(0x0, 0x14, 0x0, 0x10);
+
+ /* HD Audio */
+ PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]);
+
+ /* USB */
+ PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]);
+ PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
+ PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
+ PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
+ PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
+ PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
+ PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]);
+
+ /* sata */
+ PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]);
+ PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
+
+ /* on board NIC & Slot PCIE. */
+
+ /* PCI slots */
+ struct device *dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ if (dev && dev->enabled) {
+ u8 bus_pci = dev->link_list->secondary;
+ /* PCI_SLOT 0. */
+ PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+ PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+ PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+ PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+ }
+
+ /* PCIe Lan*/
+ PCI_INT(0x0, 0x06, 0x0, 0x13);
+
+ /* FCH PCIe PortA */
+ PCI_INT(0x0, 0x15, 0x0, 0x10);
+ /* FCH PCIe PortB */
+ PCI_INT(0x0, 0x15, 0x1, 0x11);
+ /* FCH PCIe PortC */
+ PCI_INT(0x0, 0x15, 0x2, 0x12);
+ /* FCH PCIe PortD */
+ PCI_INT(0x0, 0x15, 0x3, 0x13);
+
+ /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
+ IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
+ IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
+ /* There is no extension information... */
+
+ /* Compute the checksums */
+ return mptable_finalize(mc);
+}
+
+unsigned long write_smp_table(unsigned long addr)
+{
+ void *v;
+ v = smp_write_floating_table(addr, 0);
+ return (unsigned long)smp_write_config_table(v);
+}
diff --git a/src/mainboard/asus/a88xm-e/romstage.c b/src/mainboard/asus/a88xm-e/romstage.c
new file mode 100644
index 0000000..0a85c27
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/romstage.c
@@ -0,0 +1,102 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2012 Rudolf Marek <r.marek(a)assembler.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+
+#include <northbridge/amd/agesa/state_machine.h>
+#include <southbridge/amd/common/amd_defs.h>
+#include <southbridge/amd/agesa/hudson/hudson.h>
+#include <southbridge/amd/agesa/hudson/smbus.h>
+#include <stdint.h>
+#include <string.h>
+
+#include <superio/ite/common/ite.h>
+#include <superio/ite/it8728f/it8728f.h>
+
+#define MMIO_NON_POSTED_START 0xfed00000
+#define MMIO_NON_POSTED_END 0xfedfffff
+#define SB_MMIO_MISC32(x) *(volatile u32 *)(AMD_SB_ACPI_MMIO_ADDR + 0xE00 + (x))
+
+static void sbxxx_enable_48mhzout(void)
+{
+ /* most likely programming to 48MHz out signal */
+ u32 reg32;
+ reg32 = SB_MMIO_MISC32(0x28);
+ reg32 &= 0xffc7ffff;
+ reg32 |= 0x00100000;
+ SB_MMIO_MISC32(0x28) = reg32;
+
+ reg32 = SB_MMIO_MISC32(0x40);
+ reg32 &= ~0x80u;
+ SB_MMIO_MISC32(0x40) = reg32;
+}
+
+static void superio_init_e(void)
+{
+ pnp_devfn_t uart = PNP_DEV(0x2e, IT8728F_SP1);
+ pnp_devfn_t gpio = PNP_DEV(0x2e, IT8728F_GPIO);
+
+ ite_kill_watchdog(gpio);
+ ite_enable_serial(uart, CONFIG_TTYS0_BASE);
+ ite_enable_3vsbsw(gpio);
+}
+
+void board_BeforeAgesa(struct sysinfo *cb)
+{
+ u8 byte;
+ pci_devfn_t dev;
+
+ if (IS_ENABLED(CONFIG_POST_DEVICE_PCI_PCIE))
+ hudson_pci_port80();
+ else if (IS_ENABLED(CONFIG_POST_DEVICE_LPC))
+ hudson_lpc_port80();
+
+ /* enable SIO LPC decode */
+ dev = PCI_DEV(0, 0x14, 3);
+ byte = pci_read_config8(dev, 0x48);
+ byte |= 3; /* 2e, 2f */
+ pci_write_config8(dev, 0x48, byte);
+
+ /* enable serial decode */
+ byte = pci_read_config8(dev, 0x44);
+ byte |= (1 << 6); /* 0x3f8 */
+ pci_write_config8(dev, 0x44, byte);
+
+ post_code(0x30);
+
+ /* enable SB MMIO space */
+ outb(0x24, 0xcd6);
+ outb(0x1, 0xcd7);
+
+ /* enable SIO clock */
+ sbxxx_enable_48mhzout();
+
+ if (IS_ENABLED(CONFIG_BOARD_ASUS_A88XM_E))
+ superio_init_e();
+
+ /* turn on secondary smbus at b20 */
+ outb(0x28, 0xcd6);
+ byte = inb(0xcd7);
+ byte |= 1;
+ outb(byte, 0xcd7);
+
+ /* set DDR3 voltage */
+ byte = CONFIG_BOARD_ASUS_A88XM_E_DDR3_VOLT_VAL;
+
+ /* default is byte = 0x0, so no need to set it in this case */
+ if (byte)
+ do_smbus_write_byte(0xb20, 0x15, 0x3, byte);
+}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I60fa0636ba41f5f1a6a3faa2764bf2f0a968cf90
Gerrit-Change-Number: 30987
Gerrit-PatchSet: 1
Gerrit-Owner: Balázs Vinarz <vinibali1(a)gmail.com>
Gerrit-MessageType: newchange
52 minutes
- 9
- 250
Change in coreboot[master]: [WIP]drivers: Replace set_vbe_mode_info_valid
by Patrick Rudolph (Code Review)
Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39004 )
Change subject: [WIP]drivers: Replace set_vbe_mode_info_valid
......................................................................
[WIP]drivers: Replace set_vbe_mode_info_valid
Replace set_vbe_mode_info_valid with fb_fill_framebuffer_info,
as it doesn't need a complete edid struct s paramter.
The platforms doesn't read an EDID anyway.
Change-Id: I95d1d62385a201c68c6c2527c023ad2292a235c5
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/drivers/aspeed/common/ast_mode_corebootfb.c
M src/drivers/emulation/qemu/bochs.c
M src/drivers/emulation/qemu/cirrus.c
M src/mainboard/emulation/qemu-armv7/mainboard.c
M src/soc/nvidia/tegra210/dc.c
5 files changed, 33 insertions(+), 43 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/39004/1
diff --git a/src/drivers/aspeed/common/ast_mode_corebootfb.c b/src/drivers/aspeed/common/ast_mode_corebootfb.c
index 2ec85ac..fed7754 100644
--- a/src/drivers/aspeed/common/ast_mode_corebootfb.c
+++ b/src/drivers/aspeed/common/ast_mode_corebootfb.c
@@ -30,6 +30,7 @@
*/
#include <edid.h>
+#include <framebuffer_info.h>
#include "ast_drv.h"
@@ -247,7 +248,12 @@
ast_hide_cursor(&crtc);
/* Advertise new mode */
- set_vbe_mode_info_valid(&edid, fb.mmio_addr);
+ struct edid_fb_info *info = fb_new_framebuffer_info();
+ if (info) {
+ fb_fill_framebuffer_info(info, fb.mmio_addr, edid.x_resolution,
+ edid.y_resolution, edid.bytes_per_line,
+ edid.framebuffer_bits_per_pixel);
+ }
/* Clear display */
memset((void *)fb.mmio_addr, 0, edid.bytes_per_line * edid.y_resolution);
diff --git a/src/drivers/emulation/qemu/bochs.c b/src/drivers/emulation/qemu/bochs.c
index d9e4ce1..959d431 100644
--- a/src/drivers/emulation/qemu/bochs.c
+++ b/src/drivers/emulation/qemu/bochs.c
@@ -12,7 +12,6 @@
*/
#include <stdint.h>
-#include <edid.h>
#include <arch/io.h>
#include <console/console.h>
#include <device/device.h>
@@ -20,6 +19,7 @@
#include <device/pci_ops.h>
#include <pc80/vga.h>
#include <pc80/vga_io.h>
+#include <framebuffer_info.h>
/* VGA init. We use the Bochs VESA VBE extensions */
#define VBE_DISPI_IOPORT_INDEX 0x01CE
@@ -65,7 +65,6 @@
static void bochs_init_linear_fb(struct device *dev)
{
- struct edid edid;
int id, mem, bar;
u32 addr;
@@ -112,13 +111,11 @@
outb(0x20, 0x3c0); /* disable blanking */
- /* setup coreboot framebuffer */
- edid.mode.ha = width;
- edid.mode.va = height;
- edid.panel_bits_per_color = 8;
- edid.panel_bits_per_pixel = 24;
- edid_set_framebuffer_bits_per_pixel(&edid, 32, 0);
- set_vbe_mode_info_valid(&edid, addr);
+ /* Advertise new mode */
+ struct edid_fb_info *info = fb_new_framebuffer_info();
+ if (info) {
+ fb_fill_framebuffer_info(info, addr, width, height, 4 * width, 24);
+ }
}
static void bochs_init_text_mode(struct device *dev)
diff --git a/src/drivers/emulation/qemu/cirrus.c b/src/drivers/emulation/qemu/cirrus.c
index 6b1968c..8f048f9 100644
--- a/src/drivers/emulation/qemu/cirrus.c
+++ b/src/drivers/emulation/qemu/cirrus.c
@@ -13,13 +13,13 @@
*/
#include <stdint.h>
-#include <edid.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>
#include <pc80/vga.h>
#include <pc80/vga_io.h>
+#include <framebuffer_info.h>
static int width = CONFIG_DRIVERS_EMULATION_QEMU_BOCHS_XRES;
static int height = CONFIG_DRIVERS_EMULATION_QEMU_BOCHS_YRES;
@@ -311,14 +311,10 @@
vga_sr_write (CIRRUS_SR_EXTENDED_MODE, sr_ext);
write_hidden_dac (hidden_dac);
-
- struct edid edid;
- edid.mode.ha = width;
- edid.mode.va = height;
- edid.panel_bits_per_color = 8;
- edid.panel_bits_per_pixel = 24;
- edid_set_framebuffer_bits_per_pixel(&edid, 32, 0);
- set_vbe_mode_info_valid(&edid, addr);
+ struct edid_fb_info *info = fb_new_framebuffer_info();
+ if (info) {
+ fb_fill_framebuffer_info(info, addr, width, height, 4 * width, 24);
+ }
}
static void cirrus_init_text_mode(struct device *dev)
diff --git a/src/mainboard/emulation/qemu-armv7/mainboard.c b/src/mainboard/emulation/qemu-armv7/mainboard.c
index 338cff9..22340b2 100644
--- a/src/mainboard/emulation/qemu-armv7/mainboard.c
+++ b/src/mainboard/emulation/qemu-armv7/mainboard.c
@@ -18,15 +18,14 @@
#include <device/device.h>
#include <cbmem.h>
#include <halt.h>
-#include <edid.h>
#include <device/mmio.h>
#include <ramdetect.h>
#include <symbols.h>
+#include <framebuffer_info.h>
static void init_gfx(void)
{
uint32_t *pl111;
- struct edid edid;
/* width is at most 4096 */
/* height is at most 1024 */
int width = 800, height = 600;
@@ -42,12 +41,10 @@
write32(pl111 + 10, 0xff);
write32(pl111 + 6, (5 << 1) | 0x801);
- edid.framebuffer_bits_per_pixel = 32;
- edid.bytes_per_line = width * 4;
- edid.x_resolution = width;
- edid.y_resolution = height;
-
- set_vbe_mode_info_valid(&edid, framebuffer);
+ struct edid_fb_info *info = fb_new_framebuffer_info();
+ if (info) {
+ fb_fill_framebuffer_info(info, framebuffer, width, height, 4 * width, 32);
+ }
}
static void mainboard_enable(struct device *dev)
diff --git a/src/soc/nvidia/tegra210/dc.c b/src/soc/nvidia/tegra210/dc.c
index 46443cf..b4e3378 100644
--- a/src/soc/nvidia/tegra210/dc.c
+++ b/src/soc/nvidia/tegra210/dc.c
@@ -16,10 +16,10 @@
#include <console/console.h>
#include <device/mmio.h>
#include <stdint.h>
-#include <edid.h>
#include <device/device.h>
#include <soc/nvidia/tegra/dc.h>
#include <soc/display.h>
+#include <framebuffer_info.h>
#include "chip.h"
@@ -226,19 +226,13 @@
void pass_mode_info_to_payload(
struct soc_nvidia_tegra210_config *config)
{
- struct edid edid;
-
- edid.mode.va = config->display_yres;
- edid.mode.ha = config->display_xres;
- edid_set_framebuffer_bits_per_pixel(&edid,
- config->framebuffer_bits_per_pixel, 64);
-
- printk(BIOS_INFO, "%s: bytes_per_line: %d, bits_per_pixel: %d\n "
- " x_res x y_res: %d x %d, size: %d\n",
- __func__, edid.bytes_per_line,
- edid.framebuffer_bits_per_pixel,
- edid.x_resolution, edid.y_resolution,
- (edid.bytes_per_line * edid.y_resolution));
-
- set_vbe_mode_info_valid(&edid, 0);
+ struct edid_fb_info *info = fb_new_framebuffer_info();
+ if (info) {
+ uint32_t bytes_per_line = ALIGN_UP(config->display_xres *
+ DIV_ROUND_UP(config->framebuffer_bits_per_pixel, 8), 64);
+ //FIXME: Why not config->framebuffer_base?
+ fb_fill_framebuffer_info(info, 0,
+ config->display_xres, config->display_yres,
+ bytes_per_line, config->framebuffer_bits_per_pixel);
+ }
}
--
To view, visit https://review.coreboot.org/c/coreboot/+/39004
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I95d1d62385a201c68c6c2527c023ad2292a235c5
Gerrit-Change-Number: 39004
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org>
Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Gerrit-MessageType: newchange
1 hour, 17 minutes
- 8
- 30
Change in coreboot[master]: [WIP]drivers: Replace multiple fill_fb_framebuffer with single instance
by Patrick Rudolph (Code Review)
Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39003 )
Change subject: [WIP]drivers: Replace multiple fill_fb_framebuffer with single instance
......................................................................
[WIP]drivers: Replace multiple fill_fb_framebuffer with single instance
Replace all duplications of fill_fb_framebuffer and provide a single one.
Should not change the current behaviour.
TODO: Libgfxinit seems to expose one,too
Change-Id: Ife507f7e7beaf59854e533551b4b87ea6980c1f4
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/device/oprom/realmode/x86.c
M src/device/oprom/yabel/vbe.c
M src/drivers/intel/fsp1_1/fsp_gop.c
M src/drivers/intel/fsp2_0/graphics.c
M src/drivers/intel/fsp2_0/include/fsp/util.h
M src/drivers/xgi/common/xgi_coreboot.c
M src/lib/Kconfig
M src/lib/Makefile.inc
8 files changed, 111 insertions(+), 185 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/39003/1
diff --git a/src/device/oprom/realmode/x86.c b/src/device/oprom/realmode/x86.c
index 8ba0241..4c11e6f 100644
--- a/src/device/oprom/realmode/x86.c
+++ b/src/device/oprom/realmode/x86.c
@@ -23,6 +23,7 @@
#include <pc80/i8254.h>
#include <string.h>
#include <vbe.h>
+#include <framebuffer_info.h>
/* we use x86emu's register file representation */
#include <x86emu/regs.h>
@@ -218,6 +219,7 @@
#if CONFIG(FRAMEBUFFER_SET_VESA_MODE)
static vbe_mode_info_t mode_info;
static int mode_info_valid;
+static struct edid_fb_info *fb_info;
static int vbe_mode_info_valid(void)
{
@@ -362,6 +364,28 @@
}
vbe_set_mode(&mode_info);
+
+ if (!vbe_mode_info_valid())
+ return;
+
+ if (!fb_info) {
+ fb_info = fb_new_framebuffer_info();
+ }
+ if (fb_info) {
+ fb_fill_framebuffer_info_ex(fb_info, mode_info.vesa.phys_base_ptr,
+ le16_to_cpu(mode_info.vesa.x_resolution),
+ le16_to_cpu(mode_info.vesa.y_resolution),
+ le16_to_cpu(mode_info.vesa.bytes_per_scanline),
+ mode_info.vesa.bits_per_pixel,
+ mode_info.vesa.reserved_mask_pos,
+ mode_info.vesa.reserved_mask_size,
+ mode_info.vesa.red_mask_pos,
+ mode_info.vesa.red_mask_size,
+ mode_info.vesa.green_mask_pos,
+ mode_info.vesa.green_mask_size,
+ mode_info.vesa.blue_mask_pos,
+ mode_info.vesa.blue_mask_size);
+ }
}
void vbe_textmode_console(void)
@@ -373,34 +397,6 @@
die("\nError: In %s function\n", __func__);
}
-int fill_lb_framebuffer(struct lb_framebuffer *framebuffer)
-{
- if (!vbe_mode_info_valid())
- return -1;
-
- framebuffer->physical_address = mode_info.vesa.phys_base_ptr;
-
- framebuffer->x_resolution = le16_to_cpu(mode_info.vesa.x_resolution);
- framebuffer->y_resolution = le16_to_cpu(mode_info.vesa.y_resolution);
- framebuffer->bytes_per_line =
- le16_to_cpu(mode_info.vesa.bytes_per_scanline);
- framebuffer->bits_per_pixel = mode_info.vesa.bits_per_pixel;
-
- framebuffer->red_mask_pos = mode_info.vesa.red_mask_pos;
- framebuffer->red_mask_size = mode_info.vesa.red_mask_size;
-
- framebuffer->green_mask_pos = mode_info.vesa.green_mask_pos;
- framebuffer->green_mask_size = mode_info.vesa.green_mask_size;
-
- framebuffer->blue_mask_pos = mode_info.vesa.blue_mask_pos;
- framebuffer->blue_mask_size = mode_info.vesa.blue_mask_size;
-
- framebuffer->reserved_mask_pos = mode_info.vesa.reserved_mask_pos;
- framebuffer->reserved_mask_size = mode_info.vesa.reserved_mask_size;
-
- return 0;
-}
-
#endif
void run_bios(struct device *dev, unsigned long addr)
diff --git a/src/device/oprom/yabel/vbe.c b/src/device/oprom/yabel/vbe.c
index a3d736f..2c05338 100644
--- a/src/device/oprom/yabel/vbe.c
+++ b/src/device/oprom/yabel/vbe.c
@@ -162,6 +162,7 @@
}
static int mode_info_valid;
+static struct edid_fb_info *fb_info;
static int vbe_mode_info_valid(void)
{
@@ -747,33 +748,28 @@
mode_info.video_mode = (1 << 14) | CONFIG_FRAMEBUFFER_VESA_MODE;
vbe_get_mode_info(&mode_info);
vbe_set_mode(&mode_info);
-}
-int fill_lb_framebuffer(struct lb_framebuffer *framebuffer)
-{
if (!vbe_mode_info_valid())
- return -1;
+ return;
- framebuffer->physical_address = le32_to_cpu(mode_info.vesa.phys_base_ptr);
-
- framebuffer->x_resolution = le16_to_cpu(mode_info.vesa.x_resolution);
- framebuffer->y_resolution = le16_to_cpu(mode_info.vesa.y_resolution);
- framebuffer->bytes_per_line = le16_to_cpu(mode_info.vesa.bytes_per_scanline);
- framebuffer->bits_per_pixel = mode_info.vesa.bits_per_pixel;
-
- framebuffer->red_mask_pos = mode_info.vesa.red_mask_pos;
- framebuffer->red_mask_size = mode_info.vesa.red_mask_size;
-
- framebuffer->green_mask_pos = mode_info.vesa.green_mask_pos;
- framebuffer->green_mask_size = mode_info.vesa.green_mask_size;
-
- framebuffer->blue_mask_pos = mode_info.vesa.blue_mask_pos;
- framebuffer->blue_mask_size = mode_info.vesa.blue_mask_size;
-
- framebuffer->reserved_mask_pos = mode_info.vesa.reserved_mask_pos;
- framebuffer->reserved_mask_size = mode_info.vesa.reserved_mask_size;
-
- return 0;
+ if (!fb_info) {
+ fb_info = fb_new_framebuffer_info();
+ }
+ if (fb_info) {
+ fb_fill_framebuffer_info_ex(fb_info, mode_info.vesa.phys_base_ptr,
+ le16_to_cpu(mode_info.vesa.x_resolution),
+ le16_to_cpu(mode_info.vesa.y_resolution),
+ le16_to_cpu(mode_info.vesa.bytes_per_scanline),
+ mode_info.vesa.bits_per_pixel,
+ mode_info.vesa.reserved_mask_pos,
+ mode_info.vesa.reserved_mask_size,
+ mode_info.vesa.red_mask_pos,
+ mode_info.vesa.red_mask_size,
+ mode_info.vesa.green_mask_pos,
+ mode_info.vesa.green_mask_size,
+ mode_info.vesa.blue_mask_pos,
+ mode_info.vesa.blue_mask_size);
+ }
}
void vbe_textmode_console(void)
diff --git a/src/drivers/intel/fsp1_1/fsp_gop.c b/src/drivers/intel/fsp1_1/fsp_gop.c
index eb64151..9b555e6 100644
--- a/src/drivers/intel/fsp1_1/fsp_gop.c
+++ b/src/drivers/intel/fsp1_1/fsp_gop.c
@@ -12,10 +12,12 @@
*/
#include <boot/coreboot_tables.h>
+#include <bootstate.h>
#include <console/console.h>
+#include <framebuffer_info.h>
#include <fsp/util.h>
-int fill_lb_framebuffer(struct lb_framebuffer *framebuffer)
+static void fill_framebuffer_info(void *unused)
{
VOID *hob_list_ptr;
hob_list_ptr = get_hob_list();
@@ -30,20 +32,15 @@
printk(BIOS_DEBUG, "FSP_DEBUG: Graphics Data HOB present\n");
vbt_gop = GET_GUID_HOB_DATA(vbt_hob);
- framebuffer->physical_address = vbt_gop->FrameBufferBase;
- framebuffer->x_resolution = vbt_gop->GraphicsMode.HorizontalResolution;
- framebuffer->y_resolution = vbt_gop->GraphicsMode.VerticalResolution;
- framebuffer->bytes_per_line = vbt_gop->GraphicsMode.PixelsPerScanLine
- * 4;
- framebuffer->bits_per_pixel = 32;
- framebuffer->red_mask_pos = 16;
- framebuffer->red_mask_size = 8;
- framebuffer->green_mask_pos = 8;
- framebuffer->green_mask_size = 8;
- framebuffer->blue_mask_pos = 0;
- framebuffer->blue_mask_size = 8;
- framebuffer->reserved_mask_pos = 24;
- framebuffer->reserved_mask_size = 8;
+ struct edid_fb_info *info = fb_new_framebuffer_info();
+ if (!info)
+ return;
- return 0;
+ fb_fill_framebuffer_info(info, vbt_gop->FrameBufferBase,
+ vbt_gop->GraphicsMode.HorizontalResolution,
+ vbt_gop->GraphicsMode.VerticalResolution,
+ vbt_gop->GraphicsMode.PixelsPerScanLine * 4,
+ 32);
}
+
+BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, fill_framebuffer_info, NULL);
diff --git a/src/drivers/intel/fsp2_0/graphics.c b/src/drivers/intel/fsp2_0/graphics.c
index be7afdb..f35556f 100644
--- a/src/drivers/intel/fsp2_0/graphics.c
+++ b/src/drivers/intel/fsp2_0/graphics.c
@@ -17,6 +17,7 @@
#include <fsp/util.h>
#include <soc/intel/common/vbt.h>
#include <types.h>
+#include <framebuffer_info.h>
enum pixel_format {
pixel_rgbx_8bpc = 0,
@@ -58,48 +59,18 @@
[pixel_bgrx_8bpc] = { {16, 8}, {8, 8}, {0, 8}, {24, 8} },
};
-enum cb_err fsp_fill_lb_framebuffer(struct lb_framebuffer *framebuffer)
+__weak uintptr_t fsp_soc_get_igd_bar(void)
{
- size_t size;
- const struct hob_graphics_info *ginfo;
- const struct fsp_framebuffer *fbinfo;
-
- ginfo = fsp_find_extension_hob_by_guid(fsp_graphics_info_guid, &size);
-
- if (!ginfo) {
- printk(BIOS_ALERT, "Graphics hand-off block not found\n");
- return CB_ERR;
- }
-
- if (ginfo->pixel_format >= ARRAY_SIZE(fsp_framebuffer_format_map)) {
- printk(BIOS_ALERT, "FSP set unknown framebuffer format: %d\n",
- ginfo->pixel_format);
- return CB_ERR;
- }
-
- fbinfo = fsp_framebuffer_format_map + ginfo->pixel_format;
-
- framebuffer->physical_address = ginfo->framebuffer_base;
- framebuffer->x_resolution = ginfo->horizontal_resolution;
- framebuffer->y_resolution = ginfo->vertical_resolution;
- framebuffer->bytes_per_line = ginfo->pixels_per_scanline * 4;
- framebuffer->bits_per_pixel = 32;
- framebuffer->red_mask_pos = fbinfo->red.pos;
- framebuffer->red_mask_size = fbinfo->red.size;
- framebuffer->green_mask_pos = fbinfo->green.pos;
- framebuffer->green_mask_size = fbinfo->green.size;
- framebuffer->blue_mask_pos = fbinfo->blue.pos;
- framebuffer->blue_mask_size = fbinfo->blue.size;
- framebuffer->reserved_mask_pos = fbinfo->rsvd.pos;
- framebuffer->reserved_mask_size = fbinfo->rsvd.pos;
-
- return CB_SUCCESS;
+ return 0;
}
-int fill_lb_framebuffer(struct lb_framebuffer *framebuffer)
+static void fill_framebuffer_info(void *unused)
{
+ size_t size;
enum cb_err ret;
uintptr_t framebuffer_bar;
+ const struct hob_graphics_info *ginfo;
+ const struct fsp_framebuffer *fbinfo;
/* Pci enumeration happens after silicon init.
* After enumeration graphic framebuffer base may be relocated.
@@ -109,24 +80,44 @@
if (!framebuffer_bar) {
printk(BIOS_ALERT, "Framebuffer BAR invalid\n");
- return -1;
- }
-
- ret = fsp_fill_lb_framebuffer(framebuffer);
- if (ret != CB_SUCCESS) {
- printk(BIOS_ALERT, "FSP did not return a valid framebuffer\n");
- return -1;
+ return;
}
/* Resource allocator can move the BAR around after FSP configures it */
- framebuffer->physical_address = framebuffer_bar;
- printk(BIOS_DEBUG, "Graphics framebuffer located at 0x%llx\n",
- framebuffer->physical_address);
+ printk(BIOS_DEBUG, "Graphics framebuffer located at 0x%llx\n", framebuffer_bar);
- return 0;
+ ginfo = fsp_find_extension_hob_by_guid(fsp_graphics_info_guid, &size);
+
+ if (!ginfo) {
+ printk(BIOS_ALERT, "Graphics hand-off block not found\n");
+ return;
+ }
+
+ if (ginfo->pixel_format >= ARRAY_SIZE(fsp_framebuffer_format_map)) {
+ printk(BIOS_ALERT, "FSP set unknown framebuffer format: %d\n",
+ ginfo->pixel_format);
+ return;
+ }
+
+ fbinfo = fsp_framebuffer_format_map + ginfo->pixel_format;
+
+ struct edid_fb_info *info = fb_new_framebuffer_info();
+ if (!info)
+ return;
+
+ fb_fill_framebuffer_info_ex(fb_info, ginfo->framebuffer_base,
+ ginfo->horizontal_resolution,
+ ginfo->vertical_resolution,
+ ginfo->pixels_per_scanline * 4,
+ 32,
+ fbinfo->rsvd.pos,
+ fbinfo->rsvd.size,
+ fbinfo->red.pos,
+ fbinfo->red.size,
+ fbinfo->green.pos,
+ fbinfo->green.size,
+ fbinfo->blue.pos,
+ fbinfo->blue.size);
}
-__weak uintptr_t fsp_soc_get_igd_bar(void)
-{
- return 0;
-}
+BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, fill_framebuffer_info, NULL);
diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h
index 303bafe..15e7390 100644
--- a/src/drivers/intel/fsp2_0/include/fsp/util.h
+++ b/src/drivers/intel/fsp2_0/include/fsp/util.h
@@ -76,7 +76,6 @@
void *fsp_get_hob_list_ptr(void);
const void *fsp_find_extension_hob_by_guid(const uint8_t *guid, size_t *size);
const void *fsp_find_nv_storage_data(size_t *size);
-enum cb_err fsp_fill_lb_framebuffer(struct lb_framebuffer *framebuffer);
int fsp_find_range_hob(struct range_entry *re, const uint8_t guid[16]);
void fsp_display_fvi_version_hob(void);
void fsp_find_reserved_memory(struct range_entry *re);
diff --git a/src/drivers/xgi/common/xgi_coreboot.c b/src/drivers/xgi/common/xgi_coreboot.c
index d65e007..235cbe2 100644
--- a/src/drivers/xgi/common/xgi_coreboot.c
+++ b/src/drivers/xgi/common/xgi_coreboot.c
@@ -21,6 +21,7 @@
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <pc80/vga.h>
+#include <framebuffer_info.h>
#include "xgi_coreboot.h"
#include "vstruct.h"
@@ -31,8 +32,7 @@
#include "vb_setmode.h"
#include "XGI_main.c"
-static int xgi_vbe_valid;
-static struct lb_framebuffer xgi_fb;
+static struct edid_fb_info *fb_info;
int xgifb_probe(struct pci_dev *pdev, struct xgifb_video_info *xgifb_info)
{
@@ -359,43 +359,16 @@
XGIbios_mode[xgifb_info->mode_idx].bpp,
xgifb_info->refresh_rate);
- /* Set LinuxBIOS framebuffer information */
- xgi_vbe_valid = 1;
- xgi_fb.physical_address = xgifb_info->video_base;
- xgi_fb.x_resolution = xgifb_info->video_width;
- xgi_fb.y_resolution = xgifb_info->video_height;
- xgi_fb.bytes_per_line =
- xgifb_info->video_width * xgifb_info->video_bpp;
- xgi_fb.bits_per_pixel = xgifb_info->video_bpp;
-
- xgi_fb.reserved_mask_pos = 0;
- xgi_fb.reserved_mask_size = 0;
- switch (xgifb_info->video_bpp) {
- case 32:
- case 24:
- /* packed into 4-byte words */
- xgi_fb.reserved_mask_pos = 24;
- xgi_fb.reserved_mask_size = 8;
- xgi_fb.red_mask_pos = 16;
- xgi_fb.red_mask_size = 8;
- xgi_fb.green_mask_pos = 8;
- xgi_fb.green_mask_size = 8;
- xgi_fb.blue_mask_pos = 0;
- xgi_fb.blue_mask_size = 8;
- break;
- case 16:
- /* packed into 2-byte words */
- xgi_fb.red_mask_pos = 11;
- xgi_fb.red_mask_size = 5;
- xgi_fb.green_mask_pos = 5;
- xgi_fb.green_mask_size = 6;
- xgi_fb.blue_mask_pos = 0;
- xgi_fb.blue_mask_size = 5;
- break;
- default:
- printk(BIOS_SPEW, "%s: unsupported BPP %d\n", __func__,
- xgifb_info->video_bpp);
- xgi_vbe_valid = 0;
+ /* Set framebuffer information */
+ if (!fb_info) {
+ fb_info = fb_new_framebuffer_info();
+ }
+ if (fb_info) {
+ fb_fill_framebuffer_info(fb_info, xgifb_info->video_base,
+ xgifb_info->video_width,
+ xgifb_info->video_height,
+ xgifb_info->video_width * xgifb_info->video_bpp,
+ xgifb_info->video_bpp);
}
} else {
/*
@@ -415,22 +388,6 @@
return 0;
}
-
-static int vbe_mode_info_valid(void)
-{
- return xgi_vbe_valid;
-}
-
-int fill_lb_framebuffer(struct lb_framebuffer *framebuffer)
-{
- if (!vbe_mode_info_valid())
- return -1;
-
- *framebuffer = xgi_fb;
-
- return 0;
-}
-
struct xgifb_video_info *xgifb_video_info_ptr;
struct xgifb_video_info *pci_get_drvdata(struct pci_dev *pdev) {
diff --git a/src/lib/Kconfig b/src/lib/Kconfig
index dd9974a..d831975 100644
--- a/src/lib/Kconfig
+++ b/src/lib/Kconfig
@@ -5,14 +5,6 @@
implementation. This activates a stub that logs the missing
board reset and halts execution.
-config NO_EDID_FILL_FB
- bool
- default y if !MAINBOARD_DO_NATIVE_VGA_INIT
- help
- Don't include default fill_lb_framebuffer() implementation. Select
- this if your drivers uses MAINBOARD_DO_NATIVE_VGA_INIT but provides
- its own fill_lb_framebuffer() implementation.
-
config RAMSTAGE_ADA
bool
help
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 2333f64..a1fb8c2 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -134,9 +134,7 @@
ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
ramstage-$(CONFIG_COVERAGE) += libgcov.c
ramstage-y += edid.c
-ifneq ($(CONFIG_NO_EDID_FILL_FB),y)
ramstage-y += edid_fill_fb.c
-endif
ramstage-y += memrange.c
ramstage-$(CONFIG_COOP_MULTITASKING) += thread.c
ramstage-$(CONFIG_TIMER_QUEUE) += timer_queue.c
--
To view, visit https://review.coreboot.org/c/coreboot/+/39003
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ife507f7e7beaf59854e533551b4b87ea6980c1f4
Gerrit-Change-Number: 39003
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com>
Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-MessageType: newchange
1 hour, 20 minutes
- 10
- 37
Change in coreboot[master]: mb/google/volteer: add volteer mainboard initial support
by Nick Vaccaro (Code Review)
Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38620 )
Change subject: mb/google/volteer: add volteer mainboard initial support
......................................................................
mb/google/volteer: add volteer mainboard initial support
BUG=b:142961277
BRANCH=master
TEST="emerge-volteer coreboot" compiles successfully.
Change-Id: I03a13f3df4e819ab9cf63ad69867c807d2a1b651
Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com>
---
A src/mainboard/google/volteer/Kconfig
A src/mainboard/google/volteer/Kconfig.name
A src/mainboard/google/volteer/Makefile.inc
A src/mainboard/google/volteer/acpi/mipi_camera.asl
A src/mainboard/google/volteer/acpi_tables.c
A src/mainboard/google/volteer/board_info.txt
A src/mainboard/google/volteer/bootblock.c
A src/mainboard/google/volteer/chromeos.c
A src/mainboard/google/volteer/chromeos.fmd
A src/mainboard/google/volteer/dsdt.asl
A src/mainboard/google/volteer/ec.c
A src/mainboard/google/volteer/mainboard.c
A src/mainboard/google/volteer/smihandler.c
A src/mainboard/google/volteer/spd/Makefile.inc
A src/mainboard/google/volteer/spd/samsung-K4U6E3S4AA-MGCL.spd.hex
A src/mainboard/google/volteer/variants/baseboard/Makefile.inc
A src/mainboard/google/volteer/variants/baseboard/devicetree.cb
A src/mainboard/google/volteer/variants/baseboard/gpio.c
A src/mainboard/google/volteer/variants/baseboard/include/baseboard/ec.h
A src/mainboard/google/volteer/variants/baseboard/include/baseboard/gpio.h
A src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h
A src/mainboard/google/volteer/variants/volteer/Makefile.inc
A src/mainboard/google/volteer/variants/volteer/include/variant/acpi/dptf.asl
A src/mainboard/google/volteer/variants/volteer/include/variant/ec.h
A src/mainboard/google/volteer/variants/volteer/include/variant/gpio.h
25 files changed, 2,204 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/38620/1
diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig
new file mode 100644
index 0000000..572a100
--- /dev/null
+++ b/src/mainboard/google/volteer/Kconfig
@@ -0,0 +1,71 @@
+config BOARD_GOOGLE_BASEBOARD_VOLTEER
+ def_bool n
+ select BOARD_ROMSIZE_KB_32768
+ select DRIVERS_GENERIC_MAX98357A
+ select DRIVERS_I2C_GENERIC
+ select DRIVERS_SPI_ACPI
+ select EC_GOOGLE_CHROMEEC
+ select EC_GOOGLE_CHROMEEC_BOARDID
+ select EC_GOOGLE_CHROMEEC_LPC
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select INTEL_LPSS_UART_FOR_CONSOLE
+ select MAINBOARD_HAS_CHROMEOS
+ select MAINBOARD_HAS_SPI_TPM_CR50
+ select MAINBOARD_HAS_TPM2
+ select SOC_INTEL_TIGERLAKE
+
+if BOARD_GOOGLE_BASEBOARD_VOLTEER
+
+config CHROMEOS
+ bool
+ default y
+ select EC_GOOGLE_CHROMEEC_SWITCHES
+ select GBB_FLAG_FORCE_DEV_SWITCH_ON
+ select GBB_FLAG_FORCE_DEV_BOOT_USB
+ select GBB_FLAG_FORCE_DEV_BOOT_LEGACY
+ select GBB_FLAG_FORCE_MANUAL_RECOVERY
+ select HAS_RECOVERY_MRC_CACHE
+ select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
+ select VBOOT_LID_SWITCH
+
+config DIMM_SPD_SIZE
+ int
+ default 512
+
+config DEVICETREE
+ string
+ default "variants/baseboard/devicetree.cb"
+
+config OVERRIDE_DEVICETREE
+ string
+ default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" if !BOARD_GOOGLE_VOLTEER
+
+config DRIVER_TPM_SPI_BUS
+ default 0x1
+
+config MAINBOARD_DIR
+ string
+ default "google/volteer"
+
+config MAINBOARD_FAMILY
+ string
+ default "Google_Volteer" if BOARD_GOOGLE_VOLTEER
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "Volteer" if BOARD_GOOGLE_VOLTEER
+
+config MAX_CPUS
+ int
+ default 8
+
+config TPM_TIS_ACPI_INTERRUPT
+ int
+ default 21 # GPE0_DW0_21 (GPP_C21)
+
+config VARIANT_DIR
+ string
+ default "volteer" if BOARD_GOOGLE_VOLTEER
+
+endif # BOARD_GOOGLE_BASEBOARD_VOLTEER
diff --git a/src/mainboard/google/volteer/Kconfig.name b/src/mainboard/google/volteer/Kconfig.name
new file mode 100644
index 0000000..a3fac9c
--- /dev/null
+++ b/src/mainboard/google/volteer/Kconfig.name
@@ -0,0 +1,5 @@
+comment "Volteer"
+
+config BOARD_GOOGLE_VOLTEER
+ bool "-> Volteer"
+ select BOARD_GOOGLE_BASEBOARD_VOLTEER
diff --git a/src/mainboard/google/volteer/Makefile.inc b/src/mainboard/google/volteer/Makefile.inc
new file mode 100644
index 0000000..34bb41a
--- /dev/null
+++ b/src/mainboard/google/volteer/Makefile.inc
@@ -0,0 +1,35 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright 2019 Google LLC
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+bootblock-y += bootblock.c
+
+romstage-$(CONFIG_CHROMEOS) += chromeos.c
+
+ramstage-$(CONFIG_CHROMEOS) += chromeos.c
+ramstage-y += ec.c
+ramstage-y += mainboard.c
+
+smm-y += smihandler.c
+
+verstage-$(CONFIG_CHROMEOS) += chromeos.c
+
+subdirs-y += variants/baseboard
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include
+
+VARIANT_DIR:=$(call strip_quotes,$(CONFIG_VARIANT_DIR))
+subdirs-y += variants/$(VARIANT_DIR)
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
+
+subdirs-y += spd
diff --git a/src/mainboard/google/volteer/acpi/mipi_camera.asl b/src/mainboard/google/volteer/acpi/mipi_camera.asl
new file mode 100644
index 0000000..e1ecc3a
--- /dev/null
+++ b/src/mainboard/google/volteer/acpi/mipi_camera.asl
@@ -0,0 +1,530 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Scope (\_SB.PCI0)
+{
+ Device (IPU0)
+ {
+ Name (_ADR, 0x00050000)
+ Name (_DDN, "Camera and Imaging Subsystem")
+ }
+}
+
+Scope (\_SB.PCI0.IPU0)
+{
+ Name (_DSD, Package (0x02)
+ {
+ ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
+ Package (0x02)
+ {
+ Package (0x02)
+ {
+ "port0",
+ "PRT0"
+ },
+
+ Package (0x02)
+ {
+ "port1",
+ "PRT1"
+ }
+ }
+ })
+
+ Name (PRT0, Package (0x04)
+ {
+ ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package (0x01)
+ {
+ Package (0x02)
+ {
+ "port",
+ 5
+ }
+ },
+
+ ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
+ Package (0x01)
+ {
+ Package (0x02)
+ {
+ "endpoint0",
+ "EP00"
+ }
+ }
+ })
+
+ Name (PRT1, Package (0x04)
+ {
+ ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package (0x01)
+ {
+ Package (0x02)
+ {
+ "port",
+ 1
+ }
+ },
+
+ ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
+ Package (0x01)
+ {
+ Package (0x02)
+ {
+ "endpoint0",
+ "EP10"
+ }
+ }
+ })
+}
+
+Scope (_SB.PCI0.IPU0)
+{
+ Name (EP00, Package (0x02)
+ {
+ ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package (0x04)
+ {
+ Package (0x02)
+ {
+ "endpoint",
+ Zero
+ },
+
+ Package (0x02)
+ {
+ "clock-lanes",
+ Zero
+ },
+
+ Package (0x02)
+ {
+ "data-lanes",
+ Package (0x04)
+ {
+ One,
+ 0x02,
+ 0x03,
+ 0x04
+ }
+ },
+
+ Package (0x02)
+ {
+ "remote-endpoint",
+ Package (0x03)
+ {
+ ^I2C3.CAM0,
+ Zero,
+ Zero
+ }
+ }
+ }
+ })
+ Name (EP10, Package (0x02)
+ {
+ ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package (0x04)
+ {
+ Package (0x02)
+ {
+ "endpoint",
+ Zero
+ },
+
+ Package (0x02)
+ {
+ "clock-lanes",
+ Zero
+ },
+
+ Package (0x02)
+ {
+ "data-lanes",
+ Package (0x04)
+ {
+ One,
+ 0x02
+ }
+ },
+
+ Package (0x02)
+ {
+ "remote-endpoint",
+ Package (0x03)
+ {
+ ^I2C2.CAM1,
+ Zero,
+ Zero
+ }
+ }
+ }
+ })
+}
+
+Scope (\_SB.PCI0.I2C3)
+{
+ PowerResource (RCPR, 0x00, 0x0000)
+ {
+ Name (STA, Zero)
+ Method (_ON, 0, Serialized)
+ {
+ If ((STA == Zero))
+ {
+ /* Enable CLK3:19.2MHz */
+ MCCT(3,1,1)
+ /* Pull PWREN(GPIO H20) high */
+ STXS(GPP_H20)
+ Sleep(5)
+ /* Pull RST(GPIO D4) low */
+ CTXS(GPP_D4)
+ Sleep(5)
+ /* Pull RST high */
+ STXS(GPP_D4)
+ Sleep(5)
+ Store(1,STA)
+ }
+ }
+
+ Method (_OFF, 0, Serialized)
+ {
+ If ((STA == One))
+ {
+ /* Pull RST low */
+ CTXS(GPP_D4)
+ /* Pull PWREN low */
+ CTXS(GPP_H20)
+ /* Disable CLK3 */
+ MCCT(3,0,1)
+ Store(0,STA)
+ }
+ }
+
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (STA)
+ }
+ }
+
+ Device (CAM0)
+ {
+ Name (_HID, "OVTI8856")
+ Name (_UID, Zero)
+ Name (_DDN, "Ov 8856 Camera")
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0F)
+ }
+
+ Name (_CRS, ResourceTemplate ()
+ {
+ I2cSerialBus (0x0010, ControllerInitiated, 0x00061A80,
+ AddressingMode7Bit, "\\_SB.PCI0.I2C3",
+ 0x00, ResourceConsumer, ,
+ )
+ })
+
+ Name (_PR0, Package (0x01)
+ {
+ RCPR
+ })
+
+ Name (_PR3, Package (0x01)
+ {
+ RCPR
+ })
+
+ Name (_DSD, Package (0x04)
+ {
+ ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
+ Package (0x01)
+ {
+ Package (0x02)
+ {
+ "port0",
+ "PRT0"
+ }
+ },
+
+ ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package (0x02)
+ {
+ Package (0x02)
+ {
+ "clock-frequency",
+ 0x0124F800
+ },
+ Package (0x02)
+ {
+ "lens-focus",
+ Package (0x01)
+ {
+ VCM0
+ }
+ }
+ }
+ })
+
+ Name (PRT0, Package (0x04)
+ {
+ ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package (0x01)
+ {
+ Package (0x02)
+ {
+ "port",
+ Zero
+ }
+ },
+
+ ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
+ Package (0x01)
+ {
+ Package (0x02)
+ {
+ "endpoint0",
+ "EP00"
+ }
+ }
+ })
+
+ Name (EP00, Package (0x02)
+ {
+ ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package (0x03)
+ {
+ Package (0x02)
+ {
+ "endpoint",
+ Zero
+ },
+
+ Package (0x02)
+ {
+ "link-frequencies",
+ Package (0x01)
+ {
+ 0x325AA000
+ }
+ },
+ Package (0x02)
+ {
+ "remote-endpoint",
+ Package (0x03)
+ {
+ IPU0,
+ Zero,
+ Zero
+ }
+ }
+ }
+ })
+ }
+
+ Device (VCM0)
+ {
+ Name (_HID, "PRP0001")
+ Name (_UID, 0x03)
+ Name (_DDN, "DW9714 VCM")
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0F)
+ }
+
+ Name (_CRS, ResourceTemplate ()
+ {
+ I2cSerialBus (0x000C, ControllerInitiated, 0x00061A80,
+ AddressingMode7Bit, "\\_SB.PCI0.I2C3",
+ 0x00, ResourceConsumer, ,
+ )
+ })
+ Name (_DEP, Package (0x01)
+ {
+ CAM0
+ })
+ Name (_PR0, Package (0x01)
+ {
+ RCPR
+ })
+ Name (_PR3, Package (0x01)
+ {
+ RCPR
+ })
+ Name (_DSD, Package (0x02)
+ {
+ ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package (0x01)
+ {
+ Package (0x02)
+ {
+ "compatible",
+ "dongwoon,dw9714"
+ }
+ }
+ })
+ }
+}
+
+Scope (\_SB.PCI0.I2C2)
+{
+ PowerResource (FCPR, 0x00, 0x0000)
+ {
+ Name (STA, Zero)
+ Method (_ON, 0, Serialized)
+ {
+ If ((STA == Zero))
+ {
+ /* Enable CLK2 : 19.2MHz */
+ MCCT(2,1,1)
+ /* Pull PWREN(GPIO H20) high */
+ STXS(GPP_H20)
+ Sleep(5)
+ /* Pull RST(GPIO D4) low */
+ CTXS(GPP_D4)
+ Sleep(5)
+ /* Pull RST high */
+ STXS(GPP_D4)
+ Sleep(5)
+ Store(1,STA)
+ }
+ }
+
+ Method (_OFF, 0, Serialized)
+ {
+ If ((STA == One))
+ {
+ /* Pull RST low */
+ CTXS(GPP_D4)
+ /* Pull PWREN low */
+ CTXS(GPP_H20)
+ /* Disable CLK2 */
+ MCCT(2,0,1)
+ Store(0,STA)
+ }
+ }
+
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (STA)
+ }
+ }
+
+ Device (CAM1)
+ {
+ Name (_HID, "OVTI2740")
+ Name (_UID, Zero)
+ Name (_DDN, "Ov 2740 Camera")
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0F)
+ }
+
+ Name (_CRS, ResourceTemplate ()
+ {
+ I2cSerialBus (0x0010, ControllerInitiated, 0x00061A80,
+ AddressingMode7Bit, "\\_SB.PCI0.I2C0",
+ 0x00, ResourceConsumer, ,
+ )
+ })
+
+ Name (_PR0, Package (0x01)
+ {
+ FCPR
+ })
+
+ Name (_PR3, Package (0x01)
+ {
+ FCPR
+ })
+
+ Name (_DSD, Package (0x04)
+ {
+ ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
+ Package (0x01)
+ {
+ Package (0x02)
+ {
+ "port0",
+ "PRT0"
+ }
+ },
+
+ ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package (0x01)
+ {
+ Package (0x02)
+ {
+ "clock-frequency",
+ 0x0124F800
+ }
+ }
+ })
+
+ Name (PRT0, Package (0x04)
+ {
+ ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package (0x01)
+ {
+ Package (0x02)
+ {
+ "port",
+ Zero
+ }
+ },
+
+ ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
+ Package (0x01)
+ {
+ Package (0x02)
+ {
+ "endpoint0",
+ "EP00"
+ }
+ }
+ })
+
+ Name (EP00, Package (0x02)
+ {
+ ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package (0x03)
+ {
+ Package (0x02)
+ {
+ "endpoint",
+ Zero
+ },
+
+ Package (0x02)
+ {
+ "link-frequencies",
+ Package (0x01)
+ {
+ 0x325AA000
+ }
+ },
+ Package (0x02)
+ {
+ "remote-endpoint",
+ Package (0x03)
+ {
+ IPU0,
+ One,
+ Zero
+ }
+ }
+ }
+ })
+ }
+}
diff --git a/src/mainboard/google/volteer/acpi_tables.c b/src/mainboard/google/volteer/acpi_tables.c
new file mode 100644
index 0000000..3b44754
--- /dev/null
+++ b/src/mainboard/google/volteer/acpi_tables.c
@@ -0,0 +1 @@
+/* Nothing here */
diff --git a/src/mainboard/google/volteer/board_info.txt b/src/mainboard/google/volteer/board_info.txt
new file mode 100644
index 0000000..c41a04b
--- /dev/null
+++ b/src/mainboard/google/volteer/board_info.txt
@@ -0,0 +1,6 @@
+Vendor name: Google
+Board name: Volteer Tigerlake Reference Board
+Category: laptop
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/google/volteer/bootblock.c b/src/mainboard/google/volteer/bootblock.c
new file mode 100644
index 0000000..1127d2e
--- /dev/null
+++ b/src/mainboard/google/volteer/bootblock.c
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/variants.h>
+#include <bootblock_common.h>
+
+void bootblock_mainboard_init(void)
+{
+ const struct pad_config *pads;
+ size_t num;
+
+ pads = variant_early_gpio_table(&num);
+ gpio_configure_pads(pads, num);
+}
diff --git a/src/mainboard/google/volteer/chromeos.c b/src/mainboard/google/volteer/chromeos.c
new file mode 100644
index 0000000..6cda926
--- /dev/null
+++ b/src/mainboard/google/volteer/chromeos.c
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/variants.h>
+#include <boot/coreboot_tables.h>
+#include <gpio.h>
+#include <variant/gpio.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+ struct lb_gpio chromeos_gpios[] = {
+ {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"},
+ {-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
+ {-1, ACTIVE_HIGH, 0, "power"},
+ {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
+ {GPIO_EC_IN_RW, ACTIVE_HIGH, gpio_get(GPIO_EC_IN_RW),
+ "EC in RW"},
+ };
+ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
+}
+
+int get_write_protect_state(void)
+{
+ /* Read PCH_WP GPIO. */
+ return gpio_get(GPIO_PCH_WP);
+}
+
+void mainboard_chromeos_acpi_generate(void)
+{
+ const struct cros_gpio *gpios;
+ size_t num;
+
+ gpios = variant_cros_gpios(&num);
+ chromeos_acpi_gpio_generate(gpios, num);
+}
diff --git a/src/mainboard/google/volteer/chromeos.fmd b/src/mainboard/google/volteer/chromeos.fmd
new file mode 100644
index 0000000..60ea3de
--- /dev/null
+++ b/src/mainboard/google/volteer/chromeos.fmd
@@ -0,0 +1,47 @@
+FLASH@0xfe000000 0x2000000 {
+ SI_ALL@0x0 0x500000 {
+ SI_DESC@0x0 0x1000
+ SI_ME@0x1000 0x4ff000
+ }
+ SI_BIOS@0x500000 0x1b00000 {
+ # Place RW_LEGACY at the start of BIOS region such that the rest
+ # of BIOS regions start at 16MiB boundary. Since this is a 32MiB
+ # SPI flash only the top 16MiB actually gets memory mapped.
+ RW_LEGACY(CBFS)@0x0 0xf00000
+ RW_SECTION_A@0xf00000 0x3e0000 {
+ VBLOCK_A@0x0 0x10000
+ FW_MAIN_A(CBFS)@0x10000 0x3cffc0
+ RW_FWID_A@0x3dffc0 0x40
+ }
+ RW_SECTION_B@0x12e0000 0x3e0000 {
+ VBLOCK_B@0x0 0x10000
+ FW_MAIN_B(CBFS)@0x10000 0x3cffc0
+ RW_FWID_B@0x3dffc0 0x40
+ }
+ RW_MISC@0x16c0000 0x40000 {
+ UNIFIED_MRC_CACHE(PRESERVE)@0x0 0x30000 {
+ RECOVERY_MRC_CACHE@0x0 0x10000
+ RW_MRC_CACHE@0x10000 0x20000
+ }
+ RW_ELOG(PRESERVE)@0x30000 0x4000
+ RW_SHARED@0x34000 0x4000 {
+ SHARED_DATA@0x0 0x2000
+ VBLOCK_DEV@0x2000 0x2000
+ }
+ RW_VPD(PRESERVE)@0x38000 0x2000
+ RW_NVRAM(PRESERVE)@0x3a000 0x6000
+ }
+ # Make WP_RO region align with SPI vendor
+ # memory protected range specification.
+ WP_RO@0x1700000 0x400000 {
+ RO_VPD(PRESERVE)@0x0 0x4000
+ RO_SECTION@0x4000 0x3fc000 {
+ FMAP@0x0 0x800
+ RO_FRID@0x800 0x40
+ RO_FRID_PAD@0x840 0x7c0
+ GBB@0x1000 0x3000
+ COREBOOT(CBFS)@0x4000 0x3f8000
+ }
+ }
+ }
+}
diff --git a/src/mainboard/google/volteer/dsdt.asl b/src/mainboard/google/volteer/dsdt.asl
new file mode 100644
index 0000000..a7d9e6b
--- /dev/null
+++ b/src/mainboard/google/volteer/dsdt.asl
@@ -0,0 +1,87 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+#include "variant/ec.h"
+#include "variant/gpio.h"
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, // DSDT revision: ACPI v2.0 and up
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20110725 // OEM revision
+)
+{
+ // Some generic macros
+ #include <soc/intel/tigerlake/acpi/platform.asl>
+
+ // global NVS and variables
+ #include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+
+ // CPU
+ #include <cpu/intel/common/acpi/cpu.asl>
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ #include <soc/intel/common/block/acpi/acpi/northbridge.asl>
+ #include <soc/intel/tigerlake/acpi/southbridge.asl>
+ }
+ }
+
+ Scope (\_SB) {
+ Device (PEPD)
+ {
+ Name (_HID, "INT33A1" /* Intel Power Engine */) // _HID: Hardware ID
+ Name (_CID, EisaId ("PNP0D80") /* System Power Management Controller */) // _CID: Compatible ID
+ Name (_UID, One) // _UID: Unique ID
+ Name (PPD0, Package (0x03)
+ {
+ "\\_SB.PC00.SAT0",
+ Zero,
+ Package (0x02)
+ {
+ Zero,
+ Package (0x03)
+ {
+ 0xFF,
+ Zero,
+ 0x81
+ }
+ }
+ })
+ }
+ }
+
+ // Chrome OS specific
+ #include <vendorcode/google/chromeos/acpi/chromeos.asl>
+
+ // Chrome OS Embedded Controller
+ Scope (\_SB.PCI0.LPCB)
+ {
+ // ACPI code for EC SuperIO functions
+ #include <ec/google/chromeec/acpi/superio.asl>
+ // ACPI code for EC functions
+ #include <ec/google/chromeec/acpi/ec.asl>
+ }
+
+ // Chipset specific sleep states
+ #include <southbridge/intel/common/acpi/sleepstates.asl>
+
+ /* MIPI camera */
+ #include "acpi/mipi_camera.asl"
+}
diff --git a/src/mainboard/google/volteer/ec.c b/src/mainboard/google/volteer/ec.c
new file mode 100644
index 0000000..ab5705e
--- /dev/null
+++ b/src/mainboard/google/volteer/ec.c
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Intel Corp.
+ * Copyright 2019 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+#include <ec/ec.h>
+#include <ec/google/chromeec/ec.h>
+#include <variant/ec.h>
+
+void mainboard_ec_init(void)
+{
+ static const struct google_chromeec_event_info info = {
+ .log_events = MAINBOARD_EC_LOG_EVENTS,
+ .sci_events = MAINBOARD_EC_SCI_EVENTS,
+ .s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS,
+ .s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS,
+ .s0ix_wake_events = MAINBOARD_EC_S0IX_WAKE_EVENTS,
+ };
+
+ google_chromeec_events_init(&info, acpi_is_wakeup_s3());
+}
diff --git a/src/mainboard/google/volteer/mainboard.c b/src/mainboard/google/volteer/mainboard.c
new file mode 100644
index 0000000..7f77bf5
--- /dev/null
+++ b/src/mainboard/google/volteer/mainboard.c
@@ -0,0 +1,82 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <baseboard/variants.h>
+#include <device/device.h>
+#include <ec/ec.h>
+#include <ec/google/chromeec/ec.h>
+#include <soc/gpio.h>
+#include <smbios.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+#include <variant/gpio.h>
+
+#define SKU_UNKNOWN 0xFFFFFFFF
+#define SKU_MAX 0x7FFFFFFF
+
+static uint32_t get_board_sku(void)
+{
+ static uint32_t sku_id = SKU_UNKNOWN;
+
+ if (sku_id != SKU_UNKNOWN)
+ return sku_id;
+
+ if (google_chromeec_cbi_get_sku_id(&sku_id))
+ sku_id = SKU_UNKNOWN;
+
+ return sku_id;
+}
+
+const char *smbios_system_sku(void)
+{
+ static char sku_str[14]; /* sku{0..2147483647} */
+ uint32_t sku_id = get_board_sku();
+
+ if ((sku_id == SKU_UNKNOWN) || (sku_id > SKU_MAX)) {
+ printk(BIOS_ERR, "%s: Unexpected SKU ID %u\n",
+ __func__, sku_id);
+ return "";
+ }
+
+ snprintf(sku_str, sizeof(sku_str), "sku%u", sku_id);
+
+ return sku_str;
+}
+
+static void mainboard_init(void *chip_info)
+{
+ const struct pad_config *base_pads;
+ const struct pad_config *override_pads;
+ size_t base_num, override_num;
+
+ base_pads = variant_base_gpio_table(&base_num);
+ override_pads = variant_override_gpio_table(&override_num);
+
+ gpio_configure_pads_with_override(base_pads, base_num,
+ override_pads, override_num);
+
+ mainboard_ec_init();
+}
+
+static void mainboard_enable(struct device *dev)
+{
+ dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
+}
+
+struct chip_operations mainboard_ops = {
+ .init = mainboard_init,
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/google/volteer/smihandler.c b/src/mainboard/google/volteer/smihandler.c
new file mode 100644
index 0000000..8b82de6
--- /dev/null
+++ b/src/mainboard/google/volteer/smihandler.c
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <cpu/x86/smm.h>
+#include <ec/google/chromeec/smm.h>
+#include <intelblocks/smihandler.h>
+#include <variant/ec.h>
+
+void mainboard_smi_espi_handler(void)
+{
+ chromeec_smi_process_events();
+}
+
+void mainboard_smi_sleep(u8 slp_typ)
+{
+ chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS,
+ MAINBOARD_EC_S5_WAKE_EVENTS);
+}
+
+int mainboard_smi_apmc(u8 apmc)
+{
+ chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS,
+ MAINBOARD_EC_SMI_EVENTS);
+ return 0;
+}
diff --git a/src/mainboard/google/volteer/spd/Makefile.inc b/src/mainboard/google/volteer/spd/Makefile.inc
new file mode 100644
index 0000000..93f0f60
--- /dev/null
+++ b/src/mainboard/google/volteer/spd/Makefile.inc
@@ -0,0 +1,35 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2019 Intel Corporation.
+## Copyright 2019 Google LLC
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+SPD_BIN = $(obj)/spd.bin
+
+ifeq ($(SPD_SOURCES),)
+ SPD_DEPS := $(error SPD_SOURCES is not set. Variant must provide this)
+else
+ SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
+endif
+
+# Include spd ROM data
+$(SPD_BIN): $(SPD_DEPS)
+ for f in $+; \
+ do for c in $$(cat $$f | grep -v ^#); \
+ do printf $$(printf '\%o' 0x$$c); \
+ done; \
+ done > $@
+
+cbfs-files-y += spd.bin
+spd.bin-file := $(SPD_BIN)
+spd.bin-type := spd
diff --git a/src/mainboard/google/volteer/spd/samsung-K4U6E3S4AA-MGCL.spd.hex b/src/mainboard/google/volteer/spd/samsung-K4U6E3S4AA-MGCL.spd.hex
new file mode 100644
index 0000000..e1f27fb
--- /dev/null
+++ b/src/mainboard/google/volteer/spd/samsung-K4U6E3S4AA-MGCL.spd.hex
@@ -0,0 +1,32 @@
+23 11 11 0E 15 19 95 08 00 40 00 00 02 21 00 00
+48 00 04 FF 92 55 00 00 8C 00 90 A8 90 C0 08 60
+04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 7F E1 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20
+20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/volteer/variants/baseboard/Makefile.inc b/src/mainboard/google/volteer/variants/baseboard/Makefile.inc
new file mode 100644
index 0000000..f1c6853
--- /dev/null
+++ b/src/mainboard/google/volteer/variants/baseboard/Makefile.inc
@@ -0,0 +1,21 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright 2019 Google LLC
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+bootblock-y += gpio.c
+
+ramstage-y += gpio.c
+
+smm-y += gpio.c
+
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
new file mode 100755
index 0000000..fe6ed2e
--- /dev/null
+++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
@@ -0,0 +1,391 @@
+chip soc/intel/tigerlake
+
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
+
+ # GPE configuration
+ # Note that GPE events called out in ASL code rely on this
+ # route. i.e. If this route changes then the affected GPE
+ # offset bits also need to be changed.
+ register "pmc_gpe0_dw0" = "GPP_C"
+ register "pmc_gpe0_dw1" = "GPP_D"
+ register "pmc_gpe0_dw2" = "GPP_E"
+
+ # FSP configuration
+ register "SaGv" = "SaGv_Disabled"
+ register "SmbusEnable" = "0"
+
+ register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0
+ register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A1
+ register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN
+ register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A / Type-C Cl
+ register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera
+ register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used
+ register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used
+ register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used
+ register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Type-A / Type-C Co
+ register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth
+
+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A port A0
+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # USB3/2 Type A port A1
+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN
+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 Camera
+
+ # Enable Pch iSCLK
+ register "pch_isclk" = "1"
+
+ # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
+ register "gen1_dec" = "0x00fc0801"
+ register "gen2_dec" = "0x000c0201"
+ # EC memory map range is 0x900-0x9ff
+ register "gen3_dec" = "0x00fc0901"
+
+ # Enable NVMe PCIE 9 using clk 0
+ register "PcieRpEnable[8]" = "1"
+ register "PcieClkSrcUsage[0]" = "8"
+ register "PcieClkSrcClkReq[0]" = "0"
+
+ # Enable SD Card PCIE 8 using clk 3
+ register "PcieRpEnable[7]" = "1"
+ register "PcieClkSrcUsage[3]" = "7"
+ register "PcieClkSrcClkReq[3]" = "3"
+ register "sdcard_cd_gpio" = "GPP_E11"
+
+ # Enable WLAN PCIE 7 using clk 1
+ register "PcieRpEnable[6]" = "1"
+ register "PcieClkSrcUsage[1]" = "6"
+ register "PcieClkSrcClkReq[1]" = "1"
+
+ # Enable WWAN PCIE 6 using clk 2
+ register "PcieRpEnable[5]" = "1"
+ register "PcieClkSrcUsage[2]" = "5"
+ register "PcieClkSrcClkReq[2]" = "2"
+
+ # Mark SRCCLKREQ pins as unused that are routed for a Non-Clkreq functionality
+ register "PcieClkSrcUsage[4]" = "0xFF"
+ register "PcieClkSrcUsage[5]" = "0xFF"
+ register "PcieClkSrcUsage[6]" = "0xFF"
+
+ # Enable SATA
+ register "SataEnable" = "1"
+ register "SataMode" = "0"
+ register "SataSalpSupport" = "1"
+ register "SataPortsEnable[0]" = "0"
+ register "SataPortsEnable[1]" = "1"
+ register "SataPortsDevSlp[0]" = "0"
+
+ register "SerialIoI2cMode" = "{
+ [PchSerialIoIndexI2C0] = PchSerialIoPci,
+ [PchSerialIoIndexI2C1] = PchSerialIoPci,
+ [PchSerialIoIndexI2C2] = PchSerialIoPci,
+ [PchSerialIoIndexI2C3] = PchSerialIoPci,
+ [PchSerialIoIndexI2C4] = PchSerialIoDisabled,
+ [PchSerialIoIndexI2C5] = PchSerialIoPci,
+ }"
+
+ register "SerialIoGSpiMode" = "{
+ [PchSerialIoIndexGSPI0] = PchSerialIoPci,
+ [PchSerialIoIndexGSPI1] = PchSerialIoPci,
+ [PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
+ [PchSerialIoIndexGSPI3] = PchSerialIoDisabled,
+ }"
+
+ register "SerialIoGSpiCsMode" = "{
+ [PchSerialIoIndexGSPI0] = 1,
+ [PchSerialIoIndexGSPI1] = 1,
+ [PchSerialIoIndexGSPI2] = 0,
+ [PchSerialIoIndexGSPI3] = 0,
+ }"
+
+ register "SerialIoGSpiCsState" = "{
+ [PchSerialIoIndexGSPI0] = 0,
+ [PchSerialIoIndexGSPI1] = 0,
+ [PchSerialIoIndexGSPI2] = 0,
+ [PchSerialIoIndexGSPI3] = 0,
+ }"
+
+ register "SerialIoUartMode" = "{
+ [PchSerialIoIndexUART0] = PchSerialIoPci,
+ [PchSerialIoIndexUART1] = PchSerialIoDisabled,
+ [PchSerialIoIndexUART2] = PchSerialIoDisabled,
+ }"
+
+ #HD Audio /* FIXME - TODO */
+ register "PchHdaDspEnable" = "1"
+ #register "PchHdaAudioLinkHdaEnable" = "0"
+ #register "PchHdaAudioLinkDmicEnable[0]" = "1"
+ #register "PchHdaAudioLinkDmicEnable[1]" = "1"
+ #register "PchHdaAudioLinkSspEnable[0]" = "1"
+ #register "PchHdaAudioLinkSspEnable[1]" = "1"
+ # iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T
+ #register "PchHdaIDispLinkTmode" = "2"
+ # iDisp-Link Freq 4: 96MHz, 3: 48MHz.
+ #register "PchHdaIDispLinkFrequency" = "4"
+ # Not disconnected/enumerable
+ #register "PchHdaIDispCodecDisconnect" = "0"
+
+ # ISH /* FIXME - TODO */
+ #register "PchIshSpiEnable" = "0"
+ #register "PchIshSpiCs0Enable" = "0"
+ #register "PchIshUartEnable[0]" = "0"
+ #register "PchIshUartEnable[1]" = "0"
+ #register "PchIshI2cEnable[0]" = "0"
+ #register "PchIshI2cEnable[1]" = "0"
+ #register "PchIshI2cEnable[2]" = "0"
+ #register "PchIshGpEnable[0]" = "0"
+ #register "PchIshGpEnable[1]" = "0"
+ #register "PchIshGpEnable[2]" = "0"
+ #register "PchIshGpEnable[3]" = "0"
+ #register "PchIshGpEnable[4]" = "0"
+ #register "PchIshGpEnable[5]" = "0"
+ #register "PchIshGpEnable[6]" = "0"
+ #register "PchIshGpEnable[7]" = "0"
+
+ # TCSS USB3 /* FIXME - TODO */
+ #register "TcssXhciEn" = "1"
+ #register "TcssXdciEn" = "1"
+
+ # Image clock setting
+ #register "ImguClkOutEn[0]" = "0"
+ #register "ImguClkOutEn[1]" = "0"
+ #register "ImguClkOutEn[2]" = "1"
+ #register "ImguClkOutEn[3]" = "1"
+ #register "ImguClkOutEn[4]" = "0"
+
+ # DP port
+ register "DdiPortAConfig" = "1"
+ register "DdiPortBConfig" = "0"
+
+ register "DdiPortAHpd" = "1"
+ register "DdiPortBHpd" = "1"
+ register "DdiPortCHpd" = "0"
+ register "DdiPort1Hpd" = "1"
+ register "DdiPort2Hpd" = "1"
+ register "DdiPort3Hpd" = "0"
+ register "DdiPort4Hpd" = "0"
+
+ register "DdiPortADdc" = "0"
+ register "DdiPortBDdc" = "1"
+ register "DdiPortCDdc" = "0"
+ register "DdiPort1Ddc" = "0"
+ register "DdiPort2Ddc" = "0"
+ register "DdiPort3Ddc" = "0"
+ register "DdiPort4Ddc" = "0"
+
+ # Disable PM to allow for shorter irq pulses
+ register "gpio_override_pm" = "1"
+ register "gpio_pm[0]" = "0"
+ register "gpio_pm[1]" = "0"
+ register "gpio_pm[2]" = "0"
+ register "gpio_pm[3]" = "0"
+ register "gpio_pm[4]" = "0"
+
+ # Enable "Intel Speed Shift Technology"
+ register "speed_shift_enable" = "1"
+
+ # Enable S0ix
+ register "s0ix_enable" = "1"
+
+ # Intel Common SoC Config
+ #+-------------------+---------------------------+
+ #| Field | Value |
+ #+-------------------+---------------------------+
+ #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT |
+ #| GSPI0 | cr50 TPM. Early init is |
+ #| | required to set up a BAR |
+ #| | for TPM communication |
+ #| | before memory is up |
+ #| GSPI1 | Fingerprint MCU
+ #| I2C0 | Audio |
+ #| I2C1 | Touchscreen |
+ #| I2C2 | WLAN, SAR0 |
+ #| I2C3 | Camera, SAR1 |
+ #| I2C5 | Trackpad |
+ #| pch_thermal_trip | PCH Trip Temperature |
+ #+-------------------+---------------------------+
+ register "common_soc_config" = "{
+ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+ .gspi[0] = {
+ .speed_mhz = 1,
+ .early_init = 1,
+ },
+ .i2c[0] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ .i2c[1] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ .i2c[2] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ .i2c[3] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ .i2c[5] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ .pch_thermal_trip = 75,
+ }"
+
+ device domain 0 on
+ #From EDS(575683)
+ device pci 00.0 on end # Host Bridge 0x9A14:U/0x9A12:Y
+ device pci 02.0 on end # Graphics
+ device pci 04.0 on end # DPTF 0x9A03
+ device pci 05.0 off end # IPU 0x9A19
+ device pci 06.0 off end # PEG60 0x9A09
+ device pci 07.0 on end # TBT_PCIe0 0x9A23
+ device pci 07.1 on end # TBT_PCIe1 0x9A25
+ device pci 07.2 on end # TBT_PCIe2 0x9A27
+ device pci 07.3 on end # TBT_PCIe3 0x9A29
+ device pci 08.0 on end # GNA 0x9A11
+ device pci 09.0 off end # NPK 0x9A33
+ device pci 0a.0 off end # Crash-log SRAM 0x9A0D
+ device pci 0d.0 on end # USB xHCI 0x9A13
+ device pci 0d.1 off end # USB xDCI (OTG) 0x9A15
+ device pci 0d.2 off end # TBT DMA0 0x9A1B
+ device pci 0d.3 off end # TBT DMA1 0x9A1D
+ device pci 0e.0 off end # VMD 0x9A0B
+
+ # From PCH EDS(576591)
+ device pci 10.0 on end # I2C6 0xA0D8
+ device pci 10.1 off end # I2C7 0xA0D9
+ device pci 10.2 on end # CNVi: BT 0xA0F5 - A0F7
+ device pci 10.6 off end # THC0 0xA0D0
+ device pci 10.7 off end # THC1 0xA0D1
+
+ device pci 11.0 off end # UART3 0xA0DA
+ device pci 11.1 off end # UART4 0xA0DB
+ device pci 11.2 off end # UART5 0xA0DC
+ device pci 11.3 off end # UART6 0xA0DD
+
+ device pci 12.0 off end # SensorHUB 0xA0FC
+ device pci 12.6 off end # GSPI2 0x34FB
+
+ device pci 13.0 off end # GSPI3 0xA0FD
+ device pci 13.1 off end # GSPI4 0xA0FE
+ device pci 13.2 off end # GSPI5 0xA0DE
+ device pci 13.3 off end # GSPI6 0xA0DF
+
+ device pci 14.0 on end # USB3.1 xHCI 0xA0ED
+ device pci 14.1 off end # USB3.1 xDCI 0xA0EE
+ device pci 14.2 on end # Shared RAM 0xA0EF
+ device pci 14.3 on end # CNVi: WiFi 0xA0F0 - A0F3
+
+ device pci 15.0 on
+ chip drivers/i2c/generic
+ register "hid" = ""10EC5682""
+ register "name" = ""RT58""
+ register "desc" = ""Realtek RT5682""
+ register "irq" = "ACPI_IRQ_EDGE_HIGH(GPP_F8_IRQ)"
+ # Set the jd_src to RT5668_JD1 for jack detection
+ register "property_count" = "1"
+ register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
+ register "property_list[0].name" = ""realtek,jd-src""
+ register "property_list[0].integer" = "1"
+ device i2c 1a on end
+ end
+ end # I2C #0 0xA0E8
+ device pci 15.1 on end # I2C1 0xA0E9
+ device pci 15.2 on
+ chip drivers/i2c/sx9310
+ register "desc" = ""SAR0 Proximity Sensor""
+ register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F14_IRQ)"
+ register "speed" = "I2C_SPEED_FAST"
+ register "uid" = "0"
+ register "reg_prox_ctrl0" = "0x10"
+ register "reg_prox_ctrl1" = "0x00"
+ register "reg_prox_ctrl2" = "0x84"
+ register "reg_prox_ctrl3" = "0x0e"
+ register "reg_prox_ctrl4" = "0x07"
+ register "reg_prox_ctrl5" = "0xc6"
+ register "reg_prox_ctrl6" = "0x20"
+ register "reg_prox_ctrl7" = "0x0d"
+ register "reg_prox_ctrl8" = "0x8d"
+ register "reg_prox_ctrl9" = "0x43"
+ register "reg_prox_ctrl10" = "0x1f"
+ register "reg_prox_ctrl11" = "0x00"
+ register "reg_prox_ctrl12" = "0x00"
+ register "reg_prox_ctrl13" = "0x00"
+ register "reg_prox_ctrl14" = "0x00"
+ register "reg_prox_ctrl15" = "0x00"
+ register "reg_prox_ctrl16" = "0x00"
+ register "reg_prox_ctrl17" = "0x00"
+ register "reg_prox_ctrl18" = "0x00"
+ register "reg_prox_ctrl19" = "0x00"
+ register "reg_sar_ctrl0" = "0x50"
+ register "reg_sar_ctrl1" = "0x8a"
+ register "reg_sar_ctrl2" = "0x3c"
+ device i2c 28 on end
+ end
+ end # I2C2 0xA0EA
+ device pci 15.3 on end # I2C3 0xA0EB
+
+ device pci 16.0 on end # HECI1 0xA0E0
+ device pci 16.1 off end # HECI2 0xA0E1
+ device pci 16.2 off end # CSME 0xA0E2
+ device pci 16.3 off end # CSME 0xA0E3
+ device pci 16.4 off end # HECI3 0xA0E4
+ device pci 16.5 off end # HECI4 0xA0E5
+
+ device pci 17.0 on end # SATA 0xA0D3
+
+ device pci 19.0 on end # I2C4 0xA0C5
+ device pci 19.1 on
+ chip drivers/i2c/generic
+ register "hid" = ""ELAN0000""
+ register "desc" = ""ELAN Touchpad""
+ register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E15_IRQ)"
+ register "probed" = "1"
+ device i2c 15 on end
+ end
+ end # I2C5 0xA0C6
+ device pci 19.2 off end # UART2 0xA0C7
+
+ device pci 1c.0 on end # RP1 0xA0B8
+ device pci 1c.1 off end # RP2 0xA0B9
+ device pci 1c.2 off end # RP3 0xA0BA
+ device pci 1c.3 off end # RP4 0xA0BB
+ device pci 1c.4 off end # RP5 0xA0BC
+ device pci 1c.5 on end # WWAN RP6 0xA0BD
+ device pci 1c.6 on end # RP7 0xA0BE
+ device pci 1c.7 on end # SD Card RP8 0xA0BF
+
+ device pci 1d.0 on end # RP9 0xA0B0
+ device pci 1d.1 off end # RP10 0xA0B1
+ device pci 1d.2 off end # RP11 0xA0B2
+ device pci 1d.3 off end # RP12 0xA0B3
+ device pci 1d.4 off end # RP13 0xA0B4
+ device pci 1d.5 off end # RP14 0xA0B5
+ device pci 1d.6 off end # RP15 0xA0B6
+ device pci 1d.7 off end # RP16 0xA0B7
+
+ device pci 1e.0 on end # UART0 0xA0A8
+ device pci 1e.1 off end # UART1 0xA0A9
+ device pci 1e.2 on
+ chip drivers/spi/acpi
+ register "hid" = "ACPI_DT_NAMESPACE_HID"
+ register "compat_string" = ""google,cr50""
+ register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C21_IRQ)"
+ device spi 0 on end
+ end
+ end # GSPI0 0xA0AA
+ device pci 1e.3 on end # GSPI1 0xA0AB
+
+ device pci 1f.0 on end # eSPI 0xA080 - A09F
+ device pci 1f.1 off end # P2SB 0xA0A0
+ device pci 1f.2 on end # PMC 0xA0A1
+ device pci 1f.3 on
+ chip drivers/generic/max98357a
+ register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)"
+ register "sdmode_delay" = "5"
+ device generic 0 on end
+ end
+ end # Intel HD audio 0xA0C8-A0CF
+ device pci 1f.4 off end # SMBus 0xA0A3
+ device pci 1f.5 on end # SPI 0xA0A4
+ device pci 1f.6 off end # GbE 0x15E1/0x15E2
+ device pci 1f.7 off end # TH 0xA0A6
+ end
+end
diff --git a/src/mainboard/google/volteer/variants/baseboard/gpio.c b/src/mainboard/google/volteer/variants/baseboard/gpio.c
new file mode 100644
index 0000000..7093d6a
--- /dev/null
+++ b/src/mainboard/google/volteer/variants/baseboard/gpio.c
@@ -0,0 +1,477 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <commonlib/helpers.h>
+
+/* Pad configuration in ramstage */
+/* Leave eSPI pins untouched from default settings */
+static const struct pad_config gpio_table[] = {
+ /* A0 thru A6 come configured out of reset, do not touch */
+ /* A0 : ESPI_IO0 ==> ESPI_IO_0 */
+ /* A1 : ESPI_IO1 ==> ESPI_IO_1 */
+ /* A2 : ESPI_IO2 ==> ESPI_IO_2 */
+ /* A3 : ESPI_IO3 ==> ESPI_IO_3 */
+ /* A4 : ESPI_CS# ==> ESPI_CS_L */
+ /* A5 : ESPI_CLK ==> ESPI_CLK */
+ /* A6 : ESPI_RESET# ==> NC(TP764) */
+ /* A7 : I2S2_SCLK ==> EN_PP3300_TRACKPAD */
+ PAD_CFG_GPO(GPP_A7, 1, DEEP),
+ /* A8 : I2S2_SFRM ==> EN_PP3300_TOUCHSCREEN */
+ PAD_CFG_GPO(GPP_A8, 1, DEEP),
+ /* A9 : I2S2_TXD ==> EC_IN_RW_OD */
+ PAD_CFG_GPI(GPP_A9, NONE, DEEP),
+ /* A10 : I2S2_RXD ==> EN_SPKR_PA */
+ PAD_CFG_GPO(GPP_A10, 1, DEEP),
+ /* A11 : PMC_I2C_SDA ==> SSD_PERST_ODL */
+ PAD_CFG_GPO(GPP_A11, 1, DEEP),
+ /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */
+ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
+ /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */
+ PAD_CFG_GPO(GPP_A13, 1, DEEP),
+ /* A14 : USB_OC1# ==> USB_A0_OC_ODL */
+ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
+ /* A15 : USB_OC2# ==> USB_A1_OC_ODL */
+ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
+ /* A16 : USB_OC3# ==> USB_C0_OC_ODL */
+ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
+ /* A17 : DDSP_HPDC ==> MEM_CH_SEL */
+ PAD_CFG_GPI(GPP_A17, NONE, DEEP),
+ /* A18 : DDSP_HPDB ==> HDMI_HPD */
+ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
+ /* A19 : DDSP_HPD1 ==> USB_C0_DP_HPD */
+ PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1),
+ /* A20 : DDSP_HPD2 ==> USB_C1_DP_HPD */
+ PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1),
+ /* A21 : DDPC_CTRCLK ==> EN_FP_PWR */
+ PAD_CFG_GPO(GPP_A21, 1, DEEP),
+ /* A22 : DDPC_CTRLDATA ==> EN_HDMI_PWR */
+ PAD_CFG_GPO(GPP_A22, 1, DEEP),
+ /* A23 : I2S1_SCLK ==> I2S1_SPKR_SCLK */
+ PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1),
+
+ /* B0 : CORE_VID0 */
+ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
+ /* B1 : CORE_VID1 */
+ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
+ /* B2 : VRALERT# ==> VRALERT_L */
+ PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1),
+ /* B3 : CPU_GP2 ==> PEN_DET_ODL */
+ PAD_CFG_GPI(GPP_B3, NONE, DEEP),
+ /* B4 : CPU_GP3 ==> NC */
+ PAD_NC(GPP_B4, NONE),
+ /* B5 : ISH_I2C0_CVF_SDA */
+ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
+ /* B6 : ISH_I2C0_CVF_SCL */
+ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
+ /* B7 : ISH_12C1_SDA ==> ISH_I2C0_SENSOR_SDA */
+ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
+ /* B8 : ISH_I2C1_SCL ==> ISH_I2C0_SENSOR_SCL */
+ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),
+ /* B9 : I2C5_SDA ==> PCH_I2C5_TRACKPAD_SDA */
+ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
+ /* B10 : I2C5_SCL ==> PCH_I2C5_TRACKPAD_SCL */
+ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
+ /* B11 : PMCALERT# ==> PCH_WP_OD */
+ PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP),
+ /* B12 : SLP_S0# ==> SLP_S0_L */
+ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+ /* B13 : PLTRST# ==> PLT_RST_L */
+ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+ /* B14 : SPKR ==> GPP_B14_STRAP */
+ PAD_NC(GPP_B14, NONE),
+ /* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */
+ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
+ /* B16 : GSPI0_CLK ==> PCH_GSPI0_H1_TPM_CLK */
+ PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
+ /* B17 : GSPI0_MISO ==> PCH_GSPIO_H1_TPM_MISO */
+ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
+ /* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */
+ PAD_CFG_NF(GPP_B18, DN_20K, DEEP, NF1),
+ /* B19 : GSPI1_CS0# ==> PCH_GSPI1_FPMCU_CS_L */
+ PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),
+ /* B20 : GSPI1_CLK ==> PCH_GSPI1_FPMCU_CLK */
+ PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1),
+ /* B21 : GSPI1_MISO ==> PCH_GSPI1_FPMCU_MISO */
+ PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1),
+ /* B22 : GSPI1_MOSI ==> PCH_GSPI1_GPMCU_MOSI */
+ PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1),
+ /* B23 : SML1ALERT# ==> GPP_B23_STRAP # */
+ PAD_NC(GPP_B23, DN_20K),
+
+ /* C0 : SMBCLK ==> EN_PP3300_WLAN */
+ PAD_CFG_GPO(GPP_C0, 1, DEEP),
+ /* C1 : SMBDATA ==> NOT USED */
+ PAD_NC(GPP_C1, NONE),
+ /* C2 : SMBALERT# ==> GPP_C2_STRAP */
+ PAD_NC(GPP_C2, DN_20K),
+ /* C3 : SML0CLK ==> USB4_SMB_SCL */
+ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
+ /* C4 : SML0DATA ==> USB4_SMB_SDA */
+ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
+ /* C5 : SML0ALERT# ==> USB_SMB_INT_L_BOOT_STRAP0 */
+ PAD_NC(GPP_C5, DN_20K),
+ /* C6 : SML1CLK ==> EC_PCH_INT_ODL */
+ PAD_CFG_GPI_SCI_LOW(GPP_C6, NONE, PLTRST, EDGE_SINGLE),
+ /* C7 : SML1DATA ==> EN_USI_CHARGE */
+ PAD_CFG_GPO(GPP_C7, 1, DEEP),
+ /* C8 : UART0_RXD ==> UART_PCH_RX_DEBUG_TX */
+ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
+ /* C9 : UART0_TXD ==> UART_PCH_TX_DEBUG_RX */
+ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
+ /* C10 : UART0_RTS# ==> USI_RST_L */
+ PAD_CFG_GPO(GPP_C10, 1, DEEP),
+ /* C11 : UART0_CTS# ==> CVF_LPSS_INT_L */
+ PAD_CFG_GPI(GPP_C11, NONE, DEEP),
+ /* C12 : UART1_RXD ==> MEM_STRAP_0 */
+ PAD_CFG_GPI(GPP_C12, NONE, DEEP),
+ /* C13 : UART1_TXD ==> EN_PP5000_TRACKPAD */
+ PAD_CFG_GPO(GPP_C13, 1, DEEP),
+ /* C14 : UART1_RTS# ==> MEM_STRAP_2 */
+ PAD_CFG_GPI(GPP_C14, NONE, DEEP),
+ /* C15 : UART1_CTS# ==> MEM_STRAP_1 */
+ PAD_CFG_GPI(GPP_C15, NONE, DEEP),
+ /* C16 : I2C0_SDA ==> PCH_I2C0_1V8_AUDIO_SDA */
+ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
+ /* C17 : I2C0_SCL ==> PCH_I2C0_1V8_AUDIO_SCL */
+ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
+ /* C18 : I2C1_SDA ==> PCH_I2C1_TOUCH_USI_SDA */
+ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
+ /* C19 : I2C1_SCL ==> PCH_I2C1_TOUCH_USI_SCL */
+ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
+ /* C20 : UART2_RXD ==> FPMCU_INT_L */
+ PAD_CFG_GPI_SCI_LOW(GPP_C20, NONE, PLTRST, EDGE_SINGLE),
+ /* C21 : UART2_TXD ==> H1_PCH_INT_ODL */
+ PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT),
+ /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */
+ PAD_CFG_GPO(GPP_C22, 0, DEEP),
+ /* C23 : UART2_CTS# ==> FPMCU_RST_ODL */
+ PAD_CFG_GPO(GPP_C23, 1, DEEP),
+
+ /* D0 : ISH_GP0 ==> ISH_IMU_INT_L */
+ PAD_NC(GPP_D0, UP_20K),
+ /* D1 : ISH_GP1 ==> ISH_ACCEL_INT_L */
+ PAD_CFG_GPI(GPP_D1, UP_20K, DEEP),
+ /* D2 : ISH_GP2 ==> ISH_LID_OPEN */
+ PAD_CFG_GPI(GPP_D2, UP_20K, DEEP),
+ /* D3 : ISH_GP3 ==> ISH_ALS_RGB_INT_L */
+ PAD_CFG_GPI(GPP_D3, UP_20K, DEEP),
+ /* D4 : IMGCLKOUT0 ==> FCAM_RST_L */
+ PAD_CFG_GPO(GPP_D4, 0, PLTRST),
+ /* D5 : SRCCLKREQ0$ ==> SSD_CLKREQ_ODL */
+ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
+ /* D6 : SRCCLKREQ1# ==> WLAN_CLKREQ_ODL */
+ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
+ /* D7 : SRCCLKREQ2# ==> WWAN_CLKREQ_ODL */
+ PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
+ /* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */
+ PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
+ /* D9 : ISH_SPI_CS# ==> PCH_GSPI2_CVF_CS_L */
+ PAD_CFG_NF(GPP_D9, NONE, DEEP, NF7),
+ /* D10 : ISH_SPI_CLK ==> PCH_GSPI2_CVF_CLK_STRAP */
+ PAD_CFG_NF(GPP_D10, DN_20K, DEEP, NF7),
+ /* D11 : ISH_SPI_MISO ==> PCH_GSPI2_CVF_MISO */
+ PAD_CFG_NF(GPP_D11, NONE, DEEP, NF7),
+ /* D12 : ISH_SPI_MOSI ==> PCH_GSPI2_CVF_MISO_STRAP */
+ PAD_CFG_NF(GPP_D12, DN_20K, DEEP, NF7),
+ /* D13 : ISH_UART0_RXD ==> UART_ISH_RX_DEBUG_TX */
+ PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
+ /* D14 : ISH_UART0_TXD ==> UART_ISH_TX_DEBUG_RX */
+ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1),
+ /* D15 : ISH_UART0_RTS# ==> MEM_STRAP_3 */
+ PAD_CFG_GPI(GPP_D15, NONE, DEEP),
+ /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */
+ PAD_CFG_GPO(GPP_D16, 1, DEEP),
+ /* D17 : ISH_GP4 ==> EN_FCAM_PWR */
+ PAD_CFG_GPO(GPP_D17, 1, DEEP),
+ /* D18 : ISH_GP5 ==> FCAM_SNRPWR_EN */
+ PAD_CFG_GPO(GPP_D18, 1, DEEP),
+ /* D19 : I2S_MCLK1 ==> I2S_MCLK1 */
+ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
+
+ /* E0 : SATAXPCIE0 ==> USB_A1_RT_RST_ODL */
+ PAD_CFG_GPO(GPP_E0, 1, DEEP),
+ /* E1 : SPI1_IO2 ==> PEN_DET_ODL */
+ PAD_CFG_GPI_SCI_LOW(GPP_E1, NONE, DEEP, EDGE_SINGLE),
+ /* E2 : SPI1_IO3 ==> WLAN_PCIE_WAKE_ODL */
+ PAD_CFG_GPI(GPP_E2, NONE, DEEP),
+ /* E3 : CPU_GP0 ==> USI_REPORT_EN */
+ PAD_CFG_GPO(GPP_E3, 1, DEEP),
+ /* E4 : SATA_DEVSLP0 ==> M2_SSD_PE_WAKE_ODL */
+ PAD_NC(GPP_E4, NONE),
+ /* E5 : SATA_DEVSLP1 ==> M2_SSD_DEVSLP_OD */
+ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1),
+ /* E6 : THC0_SPI1_RST# ==> GPPE6_STRAP */
+ PAD_NC(GPP_E6, NONE),
+ /* E7 : CPU_GP1 ==> USI_INT */
+ PAD_CFG_GPI(GPP_E7, NONE, DEEP),
+ /* E8 : SPI1_CS1# ==> SLP_S0IX */
+ PAD_CFG_GPO(GPP_E8, 0, DEEP),
+ /* E9 : USB2_OC0# ==> USB_C1_OC_ODL */
+ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
+ /* E10 : SPI1_CS# ==> USB_C0_AUXP_DC */
+ PAD_CFG_GPO(GPP_E10, 0, DEEP),
+ /* E11 : SPI1_CLK ==> SD_PE_WAKE_ODL */
+ PAD_CFG_GPI(GPP_E11, NONE, DEEP),
+ /* E12 : SPI1_MISO_IO1 ==> NOT USED */
+ PAD_NC(GPP_E12, NONE),
+ /* E13 : SPI1_MOSI_IO0 ==> USB_C0_AUXN_DC */
+ PAD_CFG_GPO(GPP_E13, 0, DEEP),
+ /* E14 : DDPC_HPDA ==> SOC_EDP_HPD */
+ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
+ /* E15 : ISH_GP6 ==> TRACKPAD_INT_ODL */
+ PAD_CFG_GPI_APIC(GPP_E15, NONE, PLTRST, LEVEL, INVERT),
+ /* E16 : ISH_GP7 ==> WWAN_SIM1_DET_OD */
+ PAD_CFG_GPI(GPP_E16, NONE, DEEP),
+ /* E17 : THC0_SPI1_INT# ==> WWAN_PERST_L */
+ PAD_CFG_TERM_GPO(GPP_E17, 1, DN_20K, DEEP),
+ /* E18 : DDP1_CTRLCLK ==> USB_C0_LSX_SOC_TX */
+ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF4),
+ /* E19 : DDP1_CTRLDATA ==> USB0_C0_LSX_SOC_RX_STRAP */
+ PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF4),
+ /* E20 : DDP2_CTRLCLK ==> USB_C1_LSX_SOC_TX */
+ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF4),
+ /* E21 : DDP2_CTRLDATA ==> USB_C1_LSX_SOC_RX_STRAP */
+ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF4),
+ /* E22 : DDPA_CTRLCLK ==> USB_C1_AUXP_DC: Retimer FW drives this pin */
+ PAD_NC(GPP_E22, NONE),
+ /* E23 : DDPA_CTRLDATA ==> USB_C1_AUXN_DC: Retimer FW drives this pin */
+ PAD_NC(GPP_E23, NONE),
+
+ /* F0 : CNV_BRI_DT ==> CNV_BRI_DT_STRAP */
+ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
+ /* F1 : CNV_BRI_RSP ==> NCV_BRI_RSP */
+ PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1),
+ /* F2 : I2S2_TXD ==> CNV_RGI_DT_STRAP */
+ PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
+ /* F3 : I2S2_RXD ==> CNV_RGI_RSP */
+ PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1),
+ /* F4 : CNV_RF_RESET# ==> CNV_RF_RST_L */
+ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
+ /* F5 : MODEM_CLKREQ ==> CNV_CLKREQ0 */
+ PAD_CFG_NF(GPP_F5, NONE, DEEP, NF3),
+ /* F6 : CNV_PA_BLANKING ==> WWAN_WLAN_COEX3 */
+ PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
+ /* F7 : GPPF7_STRAP */
+ PAD_NC(GPP_F7, DN_20K),
+ /* F8 : I2S_MCLK2_INOUT ==> HP_INT_L */
+ PAD_CFG_GPI_APIC(GPP_F8, UP_20K, DEEP, EDGE_BOTH, INVERT),
+ /* F9 : Reserved ==> NC */
+ /* F10 : GPPF10_STRAP */
+ PAD_NC(GPP_F10, DN_20K),
+ /* F11 : THC1_SPI2_CLK ==> EN_PP3300_WWAN */
+ PAD_CFG_GPO(GPP_F11, 1, DEEP),
+ /* F12 : GSXDOUT ==> WWAN_RST_ODL */
+ PAD_CFG_GPO(GPP_F12, 1, DEEP),
+ /* F13 : GSXDOUT ==> WiFi_DISABLE_L */
+ PAD_CFG_GPO(GPP_F13, 1, DEEP),
+ /* F14 : GSXDIN ==> SAR0_INT_L */
+ PAD_CFG_GPI_SCI_LOW(GPP_F14, NONE, PLTRST, EDGE_SINGLE),
+ /* F15 : GSXSRESET# ==> RCAM_RST_L */
+ PAD_CFG_GPO(GPP_F15, 1, DEEP),
+ /* PAD_CFG_GPI_SCI_LOW(GPP_F15, NONE, PLTRST, EDGE_SINGLE), */
+ /* F16 : GSXCLK ==> WWAN_DPR_SAR_ODL */
+ PAD_CFG_GPO(GPP_F16, 1, DEEP),
+ /* F17 : WWAN_RF_DISABLE_ODL */
+ PAD_CFG_GPO(GPP_F17, 1, DEEP),
+ /* F18 : THC1_SPI2_INT# ==> WWAN_PCIE_WAKE_ODL */
+ PAD_CFG_GPI_SCI_LOW(GPP_F18, NONE, DEEP, EDGE_SINGLE),
+ /* F19 : SRCCLKREQ6# ==> WLAN_INT_L */
+ PAD_CFG_GPI_SCI_LOW(GPP_F19, NONE, DEEP, EDGE_SINGLE),
+ /* F20 : EXT_PWR_GATE# ==> EXT_PWR_GATE_L */
+ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
+ /* F21 : EXT_PWR_GATE2# ==> EXT_PWR_GATE2_L */
+ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
+ /* F22 : VNN_CTRL */
+ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
+ /* F23 : V1P05_CTRL */
+ PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1),
+
+ /* H0 : GPPH0_BOOT_STRAP1 */
+ PAD_NC(GPP_H0, DN_20K),
+ /* H1 : GPPH1_BOOT_STRAP2 */
+ PAD_NC(GPP_H1, DN_20K),
+ /* H2 : GPPH2_BOOT_STRAP3 */
+ PAD_NC(GPP_H2, DN_20K),
+ /* H3 : SX_EXIT_HOLDOFF# ==> SD_PERST_L */
+ PAD_CFG_GPO(GPP_H3, 1, DEEP),
+ /* H4 : I2C2_SDA ==> PCH_I2C2_MISC_SDA */
+ PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
+ /* H5 : I2C2_SCL ==> PCH_I2C2_MISC_SCL */
+ PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
+ /* H6 : I2C3_SDA ==> PCH_I2C3_CAM_SDA */
+ PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
+ /* H7 : I2C3_SCL ==> PCH_I2C3_CAM_SCL */
+ PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
+ /* H8 : I2C4_SDA ==> WWAN_WLAN_COEX1 */
+ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2),
+ /* H9 : I2C4_SCL ==> WWAN_WLAN_COEX2 */
+ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2),
+ /* H10 : SRCCLKREQ4# ==> USB_C1_RT_FORCE_PWR */
+ PAD_CFG_GPO(GPP_H10, 1, DEEP),
+ /* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */
+ PAD_CFG_GPO(GPP_H11, 1, DEEP),
+ /* H12 : M2_SKT2_CFG0 ==> WWAN_CONFIG0 */
+ PAD_CFG_GPI(GPP_H12, NONE, DEEP),
+ /* H13 : M2_SKT2_CFG1 # ==> WWAN_CONFIG1 */
+ PAD_CFG_GPI(GPP_H13, NONE, DEEP),
+ /* H14 : M2_SKT2_CFG2 # ==> RCAM_SNRPWR_EN */
+ PAD_CFG_GPO(GPP_H14, 1, DEEP),
+ /* H15 : M2_SKT2_CFG3 # ==> WWAN_CONFIG3 */
+ PAD_CFG_GPI(GPP_H15, NONE, DEEP),
+ /* H16 : DDPB_CTRLCLK ==> DDPB_HDMI_CTRLCLK */
+ PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1),
+ /* H17 : DDPB_CTRLDATA ==> DDPB_HDMI_CTRLDATA */
+ PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
+ /* H18 : CPU_C10_GATE# ==> CPU_C10_GATE_L */
+ PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
+ /* H19 : TIME_SYNC0 ==> USER_PRES_FP_ODL */
+ PAD_CFG_GPI(GPP_H19, NONE, DEEP),
+ /* H20 : IMGCLKOUT1 ==> EN_MIPI_RCAM_PWR */
+ PAD_CFG_GPO(GPP_H20, 1, PLTRST),
+ /* H21 : IMGCLKOUT2 ==> CAM_MCLK1 */
+ PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
+ /* H22 : IMGCLKOUT3 ==> CAM_MCLK0 */
+ PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
+ /* H23 : IMGCLKOUT4 ==> WWAN_ESIM_SEL_ODL */
+ PAD_CFG_GPO(GPP_H23, 1, DEEP),
+
+ /* R0 : HDA_BCLK ==> I2S0_HP_SCLK */
+ PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2),
+ /* R1 : HDA_SYNC ==> I2S0_HP_SFRM */
+ PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2),
+ /* R2 : HDA_SDO ==> I2S0_PCH_TX_HP_RX_STRAP */
+ PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2),
+ /* R3 : HDA_SDIO ==> I2S0_PCH_RX_HP_TX */
+ PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2),
+ /* R4 : HDA_RST# ==> HDA_RST_L */
+ PAD_CFG_NF(GPP_R4, DN_20K, DEEP, NF1),
+ /* R5 : HDA_SDI1 ==> I2S1_PCH_RX_SPKR_TX */
+ PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2),
+ /* R6 : I2S1_TXD ==> I2S1_PCH_RX_SPKR_RX */
+ PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2),
+ /* R7 : I2S1_SFRM ==> I2S1_SPKR_SFRM */
+ PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2),
+
+ /* S0 : SNDW0_CLK ==> SNDW0_HP_CLK */
+ PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1),
+ /* S1 : SNDW0_DATA ==> SNDW0_HP_DATA */
+ PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1),
+ /* S2 : SNDW1_CLK ==> SNDW1_SPKR_CLK */
+ PAD_CFG_NF(GPP_S2, NONE, DEEP, NF1),
+ /* S3 : SNDW1_DATA ==> SNDW1_SPKR_DATA */
+ PAD_CFG_NF(GPP_S3, NONE, DEEP, NF1),
+ /* S4 : SNDW2_CLK ==> DMIC_CLK1 */
+ PAD_CFG_NF(GPP_S4, NONE, DEEP, NF2),
+ /* S5 : SNDW2_DATA ==> DMIC_DATA1 */
+ PAD_CFG_NF(GPP_S5, NONE, DEEP, NF2),
+ /* S6 : SNDW3_CLK ==> DMIC_CLK0 */
+ PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2),
+ /* S7 : SNDW3_DATA ==> DMIC_DATA0 */
+ PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2),
+
+ /* GPD0: BATLOW# ==> BATLOW_L */
+ PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
+ /* GPD1: ACPRESENT ==> PCH_ACPRESENT */
+ PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
+ /* GPD2: LAN_WAKE# ==> EC_PCH_WAKE_ODL */
+ PAD_CFG_GPI(GPD2, NONE, DEEP),
+ /* GPD3: PWRBTN# ==> EC_PCH_PWR_BTN_ODL */
+ PAD_CFG_NF(GPD3, NONE, DEEP, NF1),
+ /* GPD4: SLP_S3# ==> SLP_S3_L */
+ PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
+ /* GPD5: SLP_S4# ==> SLP_S4_L */
+ PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
+ /* GPD6: SLP_A# ==> SLP_A_L */
+ PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
+ /* GPD7: GPD7_STRAP */
+ PAD_CFG_GPI(GPD7, DN_20K, DEEP),
+ /* GPD8: SUSCLK ==> PCH_SUSCLK */
+ PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
+ /* GPD9: SLP_WLAN# ==> SLP_WLAN_L */
+ PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
+ /* GPD10: SLP_S5# ==> SLP_S5_L */
+ PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
+ /* GPD11: LANPHYC ==> NC */
+};
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+ /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */
+ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
+
+ /* A17 : DDSP_HPDC ==> MEM_CH_SEL */
+ PAD_CFG_GPI(GPP_A17, NONE, DEEP),
+
+ /* B11 : PMCALERT# ==> PCH_WP_OD */
+ PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP),
+
+ /* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */
+ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
+
+ /* B16 : GSPI0_CLK ==> PCH_GSPI0_H1_TPM_CLK */
+ PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
+
+ /* B17 : GSPI0_MISO ==> PCH_GSPIO_H1_TPM_MISO */
+ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
+
+ /* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */
+ PAD_CFG_NF(GPP_B18, DN_20K, DEEP, NF1),
+
+ /* C0 : SMBCLK ==> EN_PP3300_WLAN */
+ PAD_CFG_GPO(GPP_C0, 1, DEEP),
+
+ /* C21 : UART2_TXD ==> H1_PCH_INT_ODL */
+ PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT),
+
+ /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */
+ PAD_CFG_GPO(GPP_C22, 0, DEEP),
+
+ /* E12 : SPI1_MISO_IO1 ==> EN_PP3300_SSD */
+ PAD_CFG_GPO(GPP_E12, 1, DEEP),
+
+ /* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */
+ PAD_CFG_GPO(GPP_H11, 1, RSMRST),
+};
+
+const struct pad_config *__weak variant_base_gpio_table(size_t *num)
+{
+ *num = ARRAY_SIZE(gpio_table);
+ return gpio_table;
+}
+
+const struct pad_config *__weak variant_override_gpio_table(size_t *num)
+{
+ *num = 0;
+ return NULL;
+}
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+ *num = ARRAY_SIZE(early_gpio_table);
+ return early_gpio_table;
+}
+
+static const struct cros_gpio cros_gpios[] = {
+ CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_COMM1_NAME),
+ CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_COMM1_NAME),
+};
+
+const struct cros_gpio *__weak variant_cros_gpios(size_t *num)
+{
+ *num = ARRAY_SIZE(cros_gpios);
+ return cros_gpios;
+}
diff --git a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/ec.h
new file mode 100644
index 0000000..85d521c
--- /dev/null
+++ b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/ec.h
@@ -0,0 +1,82 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MAINBOARD_EC_H__
+#define __MAINBOARD_EC_H__
+
+#include <ec/ec.h>
+#include <ec/google/chromeec/ec_commands.h>
+#include <variant/gpio.h>
+
+#define MAINBOARD_EC_SCI_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX))
+
+#define MAINBOARD_EC_SMI_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
+
+/* EC can wake from S5 with lid or power button */
+#define MAINBOARD_EC_S5_WAKE_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
+
+/* EC can wake from S3 with lid, power button or mode change event */
+#define MAINBOARD_EC_S3_WAKE_EVENTS \
+ (MAINBOARD_EC_S5_WAKE_EVENTS |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))
+
+#define MAINBOARD_EC_S0IX_WAKE_EVENTS (MAINBOARD_EC_S3_WAKE_EVENTS)
+
+/* Log EC wake events plus EC shutdown events */
+#define MAINBOARD_EC_LOG_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
+
+/*
+ * ACPI related definitions for ASL code.
+ */
+
+/* Enable EC backed ALS device in ACPI */
+#define EC_ENABLE_ALS_DEVICE
+
+/* Enable LID switch and provide wake pin for EC */
+#define EC_ENABLE_LID_SWITCH
+#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE
+
+/* Enable Tablet switch */
+#define EC_ENABLE_TBMC_DEVICE
+
+#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */
+#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */
+#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */
+
+/* Enable EC sync interrupt, EC_SYNC_IRQ is defined in variant/gpio.h */
+#define EC_ENABLE_SYNC_IRQ
+
+#endif /* __MAINBOARD_EC_H__ */
diff --git a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/gpio.h
new file mode 100644
index 0000000..35212a3
--- /dev/null
+++ b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/gpio.h
@@ -0,0 +1,46 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2020 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __BASEBOARD_GPIO_H__
+#define __BASEBOARD_GPIO_H__
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+
+/* EC in RW */
+#define GPIO_EC_IN_RW GPP_A9
+
+/* BIOS Flash Write Protect */
+#define GPIO_PCH_WP GPP_B11
+
+/* Memory configuration board straps */
+#define GPIO_MEM_CONFIG_0 GPP_C12
+#define GPIO_MEM_CONFIG_1 GPP_C15
+#define GPIO_MEM_CONFIG_2 GPP_C14
+#define GPIO_MEM_CONFIG_3 GPP_D15
+
+/* EC wake is LAN_WAKE# */
+#define GPE_EC_WAKE GPE0_LAN_WAK
+
+/* EC sync IRQ */
+#define EC_SYNC_IRQ GPP_C6_IRQ
+
+/* eSPI virtual wire reporting */
+#define EC_SCI_GPI GPE0_ESPI
+
+/* DRAM population strap (value 0=fully-populated, 1=half-populated) */
+#define GPIO_MEM_CH_SEL GPP_A17
+
+#endif /* BASEBOARD_GPIO_H */
diff --git a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h
new file mode 100644
index 0000000..8801ecd
--- /dev/null
+++ b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2020 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __BASEBOARD_VARIANTS_H__
+#define __BASEBOARD_VARIANTS_H__
+
+#include <soc/gpio.h>
+#include <soc/meminit.h>
+#include <stdint.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+/*
+ * The next set of functions return the gpio table and fill in the number of
+ * entries for each table.
+ */
+const struct pad_config *variant_base_gpio_table(size_t *num);
+const struct pad_config *variant_early_gpio_table(size_t *num);
+const struct pad_config *variant_override_gpio_table(size_t *num);
+
+const struct cros_gpio *variant_cros_gpios(size_t *num);
+
+void variant_memory_params(struct mb_lpddr4x_cfg *bcfg);
+int variant_memory_sku(void);
+
+#endif /* __BASEBOARD_VARIANTS_H__ */
diff --git a/src/mainboard/google/volteer/variants/volteer/Makefile.inc b/src/mainboard/google/volteer/variants/volteer/Makefile.inc
new file mode 100644
index 0000000..ad968c7
--- /dev/null
+++ b/src/mainboard/google/volteer/variants/volteer/Makefile.inc
@@ -0,0 +1,17 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright 2019 Google LLC
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+## Memory Options
+SPD_SOURCES = samsung-K4U6E3S4AA-MGCL # 0b0000
diff --git a/src/mainboard/google/volteer/variants/volteer/include/variant/acpi/dptf.asl b/src/mainboard/google/volteer/variants/volteer/include/variant/acpi/dptf.asl
new file mode 100644
index 0000000..4f6497a
--- /dev/null
+++ b/src/mainboard/google/volteer/variants/volteer/include/variant/acpi/dptf.asl
@@ -0,0 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/acpi/dptf.asl>
diff --git a/src/mainboard/google/volteer/variants/volteer/include/variant/ec.h b/src/mainboard/google/volteer/variants/volteer/include/variant/ec.h
new file mode 100644
index 0000000..260d7d4
--- /dev/null
+++ b/src/mainboard/google/volteer/variants/volteer/include/variant/ec.h
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MAINBOARD_EC_H
+#define MAINBOARD_EC_H
+
+#include <baseboard/ec.h>
+
+#endif
diff --git a/src/mainboard/google/volteer/variants/volteer/include/variant/gpio.h b/src/mainboard/google/volteer/variants/volteer/include/variant/gpio.h
new file mode 100644
index 0000000..750b0d4
--- /dev/null
+++ b/src/mainboard/google/volteer/variants/volteer/include/variant/gpio.h
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+#include <baseboard/gpio.h>
+
+#endif /* MAINBOARD_GPIO_H */
--
To view, visit https://review.coreboot.org/c/coreboot/+/38620
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I03a13f3df4e819ab9cf63ad69867c807d2a1b651
Gerrit-Change-Number: 38620
Gerrit-PatchSet: 1
Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com>
Gerrit-MessageType: newchange
7 hours, 23 minutes
- 9
- 48
Change in ...coreboot[master]: csb_patcher.sh: gets,checks,installs the coreboot and SeaBIOS patches
by Mike Banon (Code Review)
Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33509
Change subject: csb_patcher.sh: gets,checks,installs the coreboot and SeaBIOS patches
......................................................................
csb_patcher.sh: gets,checks,installs the coreboot and SeaBIOS patches
Conveniently and securely gets, checks SHA256 and installs some of my
patches from this page - https://review.coreboot.org/q/status:open+banon
- and also gets a collection of useful floppy-based operating systems.
Sometimes it takes quite a long time to get a patch merged, while the
people might need it today! - and this script could be really helpful.
It asks a [Y/N] question for every addition, and since there are some
"universal" patches as well as great floppies, you may still want to
run this script - even if your board is not Lenovo G505S or not AMD.
Please share your feedback/suggestions and tell about other useful patches,
preferably the "universal" ones - i.e. SeaBIOS. Currently included:
1) "board-specific": G505S dGPU support, G505S config and AtomBIOS ROMs
2) "universal": SeaBIOS patches: advanced_bootmenu, multiple_floppies,
writeprotected_usb ; tint build system ; and also a floppies collection :
KolibriOS, FreeDOS, MichalOS, Snowdrop, Fiwix, Memtest, Tatos, Plop, FloppyBird.
Run ./csb_patcher.sh help or ./csb_patcher.sh usage for more information.
Signed-off-by: Mike Banon <mikebdp2(a)gmail.com>
Change-Id: I66f4f2865ac63ce0f2615669c7a3abd70a397e49
---
A csb_patcher.sh
1 file changed, 876 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/33509/1
diff --git a/csb_patcher.sh b/csb_patcher.sh
new file mode 100755
index 0000000..b325f71
--- /dev/null
+++ b/csb_patcher.sh
@@ -0,0 +1,876 @@
+#!/bin/sh
+#
+# csb_patcher.sh: coreboot and SeaBIOS patcher script.
+#
+# Conveniently and securely gets, checks SHA256 and installs some of my
+# patches from this page - https://review.coreboot.org/q/status:open+banon
+# and also gets a collection of useful floppy-based operating systems.
+# Please send your feedback to Mike Banon <mikebdp2(a)gmail.com>
+#
+
+# Keys
+enter=$( printf '\015' )
+ctrl_c=$( printf '\003' )
+ctrl_x=$( printf '\030' )
+ctrl_z=$( printf '\032' )
+
+# Formatting
+bold="\e[1m"
+bred="\e[1;31m"
+bgreen="\e[1;32m"
+byellow="\e[1;33m"
+bend="\e[0m"
+
+# Asks a question '$1' and waits for Y/N user input, printing a decision - with '$2' message if Y.
+yesno () {
+ printf "$1 [Y/N] "
+ yesno_old_stty_cfg=$( stty -g )
+ stty raw -echo
+ while true ; do
+ yesno_answer=$( head -c 1 )
+ case "$yesno_answer" in
+ *"$ctrl_c"*|"$ctrl_x"*|"$ctrl_z"*)
+ stty "$yesno_old_stty_cfg"
+ printf "${bred}TERMINATED${bend}\n"
+ exit 1
+ ;;
+ *"y"*|"Y"*)
+ stty "$yesno_old_stty_cfg"
+ printf "${bgreen}YES${bend}$2\n"
+ return 0
+ ;;
+ *"n"*|"N"*)
+ stty "$yesno_old_stty_cfg"
+ printf "${byellow}NO${bend}\n"
+ return 1
+ ;;
+ esac
+ done
+}
+
+# Waits until a user presses Enter.
+encontinue () {
+ printf "\npress [ENTER] to continue... "
+ encontinue_old_stty_cfg=$( stty -g )
+ stty raw -echo
+ while true ; do
+ encontinue_answer=$( head -c 1 )
+ case "$encontinue_answer" in
+ *"$ctrl_c"*|"$ctrl_x"*|"$ctrl_z"*)
+ stty "$encontinue_old_stty_cfg"
+ printf "${bred}TERMINATED${bend}\n"
+ exit 1
+ ;;
+ *"$enter"*)
+ stty "$encontinue_old_stty_cfg"
+ printf "\n"
+ return 0
+ ;;
+ esac
+ done
+}
+
+# Checks if a command '$1' exists.
+command_exists() {
+ if [ ! -x "$( command -v $1 )" ] ; then
+ printf "\n${bred}ERROR${bend}: command ${bold}$1${bend} is not found !\n"
+ encontinue
+ return 1
+ else
+ return 0
+ fi
+}
+
+# Checks if a file '$1' exists.
+file_exists () {
+ if [ ! -f "$1" ] ; then
+ printf "\n${byellow}WARNING${bend}: file ${bold}$1${bend} is not found !\n"
+ encontinue
+ return 1
+ else
+ return 0
+ fi
+}
+
+# Force removes a file '$2' and then copies a file '$1' to '$2'.
+copier () {
+ if file_exists "$1" ; then
+ rm -f "$2"
+ cp "$1" "$2"
+ return 0
+ else
+ return 1
+ fi
+}
+
+# Force removes a file '$2' and then moves a file '$1' to '$2'.
+mover () {
+ if file_exists "$1" ; then
+ rm -f "$2"
+ mv "$1" "$2"
+ return 0
+ else
+ return 1
+ fi
+}
+
+# Checks if line '$1' contains the text '$2'.
+checker () {
+ case "$1" in
+ *"$2"*)
+ return 0
+ ;;
+ *)
+ return 1
+ ;;
+ esac
+}
+
+# Prints the lines of a file '$2' which contain the text '$1'.
+grepper () {
+ if file_exists "$2" ; then
+ while IFS= read -r grepper_line
+ do
+ case "$grepper_line" in
+ *"$1"*)
+ printf '%s\n' "$grepper_line"
+ ;;
+ esac
+ done < "$2"
+ return 0
+ else
+ return 1
+ fi
+}
+
+# Checks if a file '$2' contains the text '$1'.
+grepcheck () {
+ if file_exists "$2" ; then
+ while IFS= read -r grepcheck_line
+ do
+ case "$grepcheck_line" in
+ *"$1"*)
+ return 0
+ ;;
+ esac
+ done < "$2"
+ return 1
+ else
+ return 1
+ fi
+}
+
+# Replaces the lines containing the text '$2' of a file '$1' with a line '$3'.
+sedder () {
+ if file_exists "$1" ; then
+ csb_sedder_tmp="./.csb_sedder"
+ rm -f "$csb_sedder_tmp"
+ while IFS= read -r sedder_line
+ do
+ case "$sedder_line" in
+ *"$2"*)
+ if [ ! -z "$3" ] ; then
+ printf '%s\n' "$3" >> "$csb_sedder_tmp"
+ fi
+ ;;
+ *)
+ printf '%s\n' "$sedder_line" >> "$csb_sedder_tmp"
+ ;;
+ esac
+ done < "$1"
+ mover "$csb_sedder_tmp" "$1"
+ return 0
+ else
+ return 1
+ fi
+}
+
+# Downloads a file '$1' from a link '$2' using the options '$3' and checks if this was successful.
+wgetter () {
+ rm -f "$1"
+ if [ -z "$3" ] ; then
+ wget "$2"
+ else
+ wget "$3" "$2"
+ fi
+ if [ -f "$1" ] ; then
+ wgetter_file_size=$(($( wc -c < "$1" )))
+ if [ "$wgetter_file_size" -eq "0" ] ; then
+ rm -f "$1"
+ fi
+ fi
+ if [ ! -f "$1" ] ; then
+ printf "\n${byellow}WARNING${bend}: can't download a ${bold}$1${bend} file !"
+ printf "\n Please check your Internet connection and try again.\n"
+ encontinue
+ return 1
+ else
+ return 0
+ fi
+}
+
+# Unzips the archive '$1', optional '$2' for -j path inside the archive, and then force removes it.
+unzipper () {
+ if file_exists "$1" ; then
+ if [ -z "$2" ] ; then
+ unzip "$1"
+ else
+ unzip -j "$1" "$2"
+ fi
+ rm -f "$1"
+ return 0
+ else
+ return 1
+ fi
+}
+
+# Expands a file '$1' with zeroes using a dd to '$2' size - e.g. to a standard floppy size 1474560.
+expander () {
+ if file_exists "$1" && [ ! -z "$2" ] ; then
+ expander_file_size=$(($( wc -c < "$1" )))
+ if [ "$expander_file_size" -lt "$2" ] ; then
+ dd if=/dev/zero of=$1 bs=1 count=1 seek="$(( $2 - 1 ))" conv=notrunc iflag=nocache
+ fi
+ return 0
+ else
+ return 1
+ fi
+}
+
+# Compares sha256sum of '$1.img' floppy image with '$2' and creates a hidden '.$1' file if matches.
+floppy_verifier () {
+ rm -f "./.$1"
+ cd ".."
+ if [ ! -z "$2" ] ; then
+ if file_exists "./floppies/$1.img" ; then
+ floppy_verifier_sha256sum_correct="$2 ./floppies/$1.img"
+ floppy_verifier_sha256sum_my=$( sha256sum "./floppies/$1.img" )
+ printf "\n=== sha256sum should be:\n${bold}$floppy_verifier_sha256sum_correct${bend}\n"
+ if [ "$floppy_verifier_sha256sum_my" = "$floppy_verifier_sha256sum_correct" ] ; then
+ printf "^^^ this is correct, ./floppies/${bold}$1.img${bend} is verified and could be added.\n\n"
+ cd "./floppies/"
+ touch "./.$1"
+ return 0
+ else
+ printf "${bold}^^^ ! MISMATCH for ./floppies/$1.img ! Check sha256sum manually: sha256sum ./floppies/$1.img${bend}\n"
+ encontinue
+ cd "./floppies/"
+ return 1
+ fi
+ else
+ printf "\n${byellow}WARNING${bend}: cannot find ./floppies/${bold}$1.img${bend} !\n"
+ printf "\n Please re-download a set of floppies.\n"
+ encontinue
+ return 1
+ fi
+ else
+ printf "\n${byellow}WARNING${bend}: ./floppies/${bold}$1.img${bend} - is a rolling release, its' SHA256 checksum"
+ printf "\n is changing constantly and not provided by $1 project, so not checked.\n"
+ encontinue
+ cd "./floppies/"
+ touch "./.$1"
+ return 0
+ fi
+}
+
+# Downloads a collection of floppies, for the purpose of adding them later to a coreboot ROM image.
+floppy_mass_downloader () {
+ printf "\n"
+ if [ ! -d "./floppies/" ]; then
+ mkdir "./floppies/"
+ fi
+ cd "./floppies/"
+ # KOLIBRI
+ if command_exists "7za" ; then
+ if wgetter "./latest-img.7z" "https://builds.kolibrios.org/eng/latest-img.7z" ; then
+ rm -f "./kolibri.img"
+ 7za x "./latest-img.7z"
+ rm -f "./latest-img.7z"
+ floppy_verifier "kolibri" "" # IS A ROLLING RELEASE, NO SHA256 VERIFICATION
+ fi
+ else
+ printf "\n${byellow}WARNING${bend}: cannot get ./floppies/${bold}kolibri.img${bend} without ${bold}7za${bend}\n"
+ encontinue
+ fi
+ # FREEDOS
+ if wgetter "./FD12FLOPPY.zip" "https://www.freedos.org/download/download/FD12FLOPPY.zip" ; then
+ unzipper "./FD12FLOPPY.zip" "FLOPPY.img"
+ mover "./FLOPPY.img" "./freedos.img"
+ floppy_verifier "freedos" "de2fb84dc2f132324549e89d58c6383497ec1af538c5b0ecde389fb748b9d537"
+ fi
+ # MICHALOS
+ printf "\n${byellow}WARNING${bend}: getting ./floppies/${bold}michalos.img${bend} could take a couple of minutes...\n\n"
+ if wgetter "./MichalOS 2.0 Source.zip" "https://sourceforge.net/p/michalos/tickets/_discuss/thread/69ab1508c3/39cd/…" "--content-disposition" ; then
+ unzipper "./MichalOS 2.0 Source.zip" "disk_images/michalos.img"
+ floppy_verifier "michalos" "139e9d08881f646156971a0a061972ddca77057b8acf4164e36366271ab3658c"
+ fi
+ # SNOWDROP
+ if wgetter "./snowdrop.img" "http://sebastianmihai.com/downloads/snowdrop/snowdrop.img" ; then
+ floppy_verifier "snowdrop" "" # IS A ROLLING RELEASE, NO SHA256 VERIFICATION
+ fi
+ # FIWIX
+ if wgetter "./fiwix.img" "https://www.fiwix.org/fiwix-1.0.1-i386-initrd.img" "--output-document=fiwix.img" ; then
+ floppy_verifier "fiwix" "dbec2994ec619c9954327ab0b983ab24cd362406a2e515c35c79c79bd6417cfd"
+ fi
+ # MEMTEST
+ if wgetter "./memtest86+-5.01.floppy.zip" "https://www.memtest.org/download/5.01/memtest86+-5.01.floppy.zip" ; then
+ unzipper "./memtest86+-5.01.floppy.zip" "floppy/memtestp.bin"
+ expander "./memtestp.bin" "1474560"
+ mover "./memtestp.bin" "./memtest.img"
+ floppy_verifier "memtest" "364535abd0d105da9396df6015e480c4d4c52b07dcc4e1d4756bde8ef87a30f1"
+ fi
+ # TATOS
+ if wgetter "./tatos.img" "https://github.com/tatimmer/tatOS/raw/master/tatOS.img" "--output-document=tatos.img" ; then
+ expander "./tatos.img" "1474560"
+ floppy_verifier "tatos" "2c66f884498a4fe7b469bc213aebfccd84a09fd7ace1b3b4b3e747e2392c35d1"
+ fi
+ # PLOP
+ if wgetter "./plpbt-5.0.15.zip" "https://download.plop.at/files/bootmngr/plpbt-5.0.15.zip" ; then
+ unzipper "./plpbt-5.0.15.zip" "plpbt-5.0.15/plpbt.img"
+ mover "./plpbt.img" "./plop.img"
+ floppy_verifier "plop" "f170759966ec4efe60c8531158344a234d7543c8de81e54c8c1bb9d2d69eaf27"
+ fi
+ # FLOPPYBIRD
+ if wgetter "./floppybird.img" "https://github.com/mikebdp2/floparchive/raw/master/floppies_extra/floppybir…" ; then
+ floppy_verifier "floppybird" "5db1b469e25e9eda7b8c0f666d6b655bab083c85618a9453ee72f1201cca840f"
+ fi
+ # Some floppies have the weird permissions after their extraction
+ floppy_mass_downloader_floppies=$( find . -name "*.img" )
+ if [ ! -z "$floppy_mass_downloader_floppies" ] ; then
+ chmod 755 "./"*".img"
+ fi
+ # Return back to ./coreboot/
+ cd ".."
+ return 0
+}
+
+# Adds a './pci1002,$1.rom' to coreboot '$3' ROM using '$2' cbfstool, printing '$4'/'$5'/'$6' info.
+atombios_adder () {
+ if file_exists "$2" && file_exists "$3" ; then
+ if [ -f "./pci1002,$1.rom" ] ; then
+ atombios_adder_cbfs=$( "$2" "$3" print )
+ if checker "$atombios_adder_cbfs" "pci1002,$1.rom" ; then
+ printf "\n${bgreen}NOTE${bend}: ./${bold}pci1002,$1.rom${bend} for ${bold}$5 : $6${bend} is already at your $3.\n"
+ else
+ if yesno "\nAdd a ./${bold}pci1002,$1.rom${bend} for ${bold}$5 : $6${bend} to your $3 now? ${bold}~$4${bend}" ", adding..." ; then
+ "$2" "$3" add -f "./pci1002,$1.rom" -n "pci1002,$1.rom" -t optionrom
+ else
+ printf "\n${bold}You can add it later by running:${bend}"
+ printf "\n${bold} $2 $3 add -f ./pci1002,$1.rom -n pci1002,$1.rom -t optionrom${bend}\n\n"
+ fi
+ fi
+ return 0
+ else
+ printf "\n${byellow}WARNING${bend}: cannot find ./${bold}pci1002,$1.rom${bend} ,"
+ printf "\n please re-apply ${bold}AMD atombios${bend} patch.\n"
+ encontinue
+ return 1
+ fi
+ else
+ return 1
+ fi
+}
+
+# Adds a '$1.img' floppy image to coreboot '$3' ROM using '$2' cbfstool, printing '$4' size info.
+floppy_adder () {
+ if file_exists "$2" && file_exists "$3" ; then
+ if [ -f "./floppies/$1.img" ] ; then
+ if [ -f "./floppies/.$1" ] ; then
+ floppy_adder_cbfs=$( "$2" "$3" print )
+ if checker "$floppy_adder_cbfs" "floppyimg/$1.lzma" ; then
+ printf "\n${bgreen}NOTE${bend}: ./floppies/${bold}$1.img${bend} is already at your $3.\n"
+ else
+ if checker "$1" "plop" ; then
+ printf "\n${byellow}WARNING${bend}: ./floppies/${bold}$1.img${bend} - is proprietary: all its' source code is closed !"
+ printf "\n Add it only if you really need it and trust the author of $1 project.\n"
+ encontinue
+ fi
+ if yesno "\nAdd a ./floppies/${bold}$1.img${bend} to your $3 now? ${bold}~$4${bend}" ", adding..." ; then
+ "$2" "$3" add -f "./floppies/$1.img" -n "floppyimg/$1.lzma" -t raw -c lzma
+ else
+ printf "\n${bold}You can add it later by running:${bend}"
+ printf "\n${bold} $2 $3 add -f ./floppies/$1.img -n floppyimg/$1.lzma -t raw -c lzma${bend}\n\n"
+ fi
+ fi
+ return 0
+ else
+ printf "\n${byellow}WARNING${bend}: there was a SHA256 mismatch for ./floppies/${bold}$1.img${bend} -"
+ printf "\n check sha256sum manually: sha256sum ./floppies/${bold}$1.img${bend}\n"
+ encontinue
+ return 1
+ fi
+ else
+ printf "\n${byellow}WARNING${bend}: cannot find ./floppies/${bold}$1.img${bend} !\n"
+ printf "\n Please re-download a set of floppies.\n"
+ encontinue
+ return 1
+ fi
+ else
+ return 1
+ fi
+}
+
+# Adds a set of AtomBIOS/floppies ('$1') to coreboot '$3' ROM copied to '$4', using '$2' cbfstool.
+cbfs_mass_adder () {
+ if ! grepcheck "how to submit coreboot changes" ./MAINTAINERS ; then
+ printf "\n${byellow}WARNING${bend}: not sure if I am inside the coreboot directory,"
+ printf "\n trying to add a ${bold}$1${bend} set from here - could fail.\n\n"
+ fi
+ if file_exists "$2" && file_exists "$3" ; then
+ if checker "$1" "atom" || checker "$1" "flop" ; then
+ copier "$3" "$4"
+ printf "\n${bold}=== $4 - initial memory map${bend}\n\n"
+ "$2" "$4" print
+ printf "\n"
+ if checker "$1" "atom" ; then
+###
+### https://review.coreboot.org/c/coreboot/+/31944
+### G505S AtomBIOS ROMs: known good binaries with a script to check their SHA256
+###
+ csb_patcher "atombios" "31944" "6" "78a8454" "9a8efff284bbdb81d5b912ccc8279162553e04673bde53e5288ba4bed0e4bc3d" "$1" "AMD "
+ atombios_adder "990b" "$2" "$4" "62K" "Lenovo G505S with A10-5750M" "iGPU HD-8650G"
+ atombios_adder "6663" "$2" "$4" "33K" "Lenovo G505S with A10-5750M" "dGPU HD-8570M"
+ atombios_adder "6665" "$2" "$4" "32K" "Lenovo G505S with A10-5750M" "dGPU R5-M230"
+ atombios_adder "9830" "$2" "$4" "59K" "ASUS AM1I-A with Athlon-5370" "iGPU HD-8400 / R3-Series"
+ atombios_adder "990c" "$2" "$4" "62K" "ASUS A88XM-E with A10-6700" "iGPU HD-8670D"
+ fi
+ if checker "$1" "flop" ; then
+ if [ ! -d "./floppies/" ] ; then
+ printf "\n"
+ floppy_mass_downloader
+ fi
+ # Default boot order: the last floppy added - is the first floppy to boot!
+ floppy_adder "floppybird" "$2" "$4" "2K"
+ floppy_adder "plop" "$2" "$4" "74K"
+ floppy_adder "tatos" "$2" "$4" "60K"
+ floppy_adder "memtest" "$2" "$4" "44K"
+ floppy_adder "fiwix" "$2" "$4" "458K"
+ floppy_adder "snowdrop" "$2" "$4" "126K"
+ floppy_adder "michalos" "$2" "$4" "256K"
+ floppy_adder "freedos" "$2" "$4" "698K"
+ floppy_adder "kolibri" "$2" "$4" "1264K"
+ fi
+ printf "\n${bold}=== $4 - final memory map${bend}\n\n"
+ "$2" "$4" print
+ printf "\nYou can use ./build/${bold}coreflop.rom${bend} now !\n\n"
+ return 0
+ else
+ return 1
+ fi
+ else
+ return 1
+ fi
+}
+
+# Finds the files of '$1' extension, saves the result to '$2' log and prints a message with '$3'.
+csb_finder () {
+ csb_finder_files=$( find . -name "*.$1" )
+ if [ ! -z "$csb_finder_files" ] ; then
+ printf "%25s\n" "*.$1 - YES" >> "$2"
+ printf "\n${byellow}WARNING${bend}: found ${bold}*.$1${bend} files at these locations :\n"
+ printf "$csb_finder_files"
+ printf "\n That means - Some patches $3\n"
+ encontinue
+ return 0
+ else
+ printf "%24s\n" "*.$1 - NO" >> "$2"
+ return 1
+ fi
+}
+
+# Prints a csb_patcher_log '$1' with a custom highlighting.
+csb_printer () {
+ if ! file_exists "$1" ; then
+ return 1
+ fi
+ while IFS= read -r csb_printer_line
+ do
+ case "$csb_printer_line" in
+ *"orig - YES"*)
+ printf "${csb_printer_line%???}${byellow}YES" # YELLOW
+ ;;
+ *"rej - YES"*)
+ printf "${csb_printer_line%???}${bred}YES" # RED
+ ;;
+ *"YES"*)
+ printf "${csb_printer_line%???}${bgreen}YES" # GREEN
+ ;;
+ *"orig - NO"*|*"rej - NO"*)
+ printf "${csb_printer_line%??}${bgreen}NO" # GREEN
+ ;;
+ *"NO"*)
+ printf "${csb_printer_line%??}${byellow}NO" # YELLOW
+ ;;
+ *"FAILURE_1"*)
+ printf "${csb_printer_line%?????????}${bred}FAILURE_1" # RED
+ ;;
+ *"FAILURE_2"*)
+ printf "${csb_printer_line%?????????}${bred}FAILURE_2" # RED
+ ;;
+ *"FAILURE_3"*)
+ printf "${csb_printer_line%?????????}${bred}FAILURE_3" # RED
+ ;;
+ *"\\\\"*)
+ printf "${bold}${csb_printer_line%?????}\\\\\!//" # ALIEN HAIR
+ ;;
+ *)
+ printf "${bold}$csb_printer_line"
+ ;;
+ esac
+ printf "${bend}\n"
+ done < "$1"
+ return 0
+}
+
+# Configure some popular options of a config file '$1'.
+csb_configurer () {
+ if file_exists "$1" ; then
+ csb_configurer_tmp="./.csb_configurer"
+ rm -f "$csb_configurer_tmp"
+ grepper "CONFIG_BOARD_" "$1" > "$csb_configurer_tmp"
+ if grepcheck "_LENOVO_G505S=y" "$csb_configurer_tmp" ; then
+ printf "\n\n${bgreen}[CONFIG]${bend} Questions about your Lenovo G505S\n\n"
+ sedder "$1" "### CSB_CONFIGURER OPTIONS" ""
+ printf "### CSB_CONFIGURER OPTIONS\n" >> "$1"
+ sedder "$1" "# CONFIG_DRIVERS_INTEL_WIFI is not set" ""
+ if ! yesno "Do you have an Intel WiFi adapter?" "" ; then
+ printf "# CONFIG_DRIVERS_INTEL_WIFI is not set\n" >> "$1"
+ fi
+ sedder "$1" "CONFIG_MULTIPLE_VGA_ADAPTERS=y" ""
+ sedder "$1" "CONFIG_VGA_BIOS_DGPU=y" ""
+ sedder "$1" "CONFIG_VGA_BIOS_DGPU_FILE=\"pci1002,6663.rom\"" ""
+ sedder "$1" "CONFIG_VGA_BIOS_DGPU_ID=\"1002,6663\"" ""
+ sedder "$1" "CONFIG_VGA_BIOS_DGPU_FILE=\"pci1002,6665.rom\"" ""
+ sedder "$1" "CONFIG_VGA_BIOS_DGPU_ID=\"1002,6665\"" ""
+ if yesno "Do you have a Discrete GPU?" "" ; then
+ printf "CONFIG_MULTIPLE_VGA_ADAPTERS=y\n" >> "$1"
+ printf "CONFIG_VGA_BIOS_DGPU=y\n" >> "$1"
+ if yesno "No for HD-8570M, Yes for R5-M230" "" ; then
+ printf "CONFIG_VGA_BIOS_DGPU_FILE=\"pci1002,6665.rom\"\n" >> "$1"
+ printf "CONFIG_VGA_BIOS_DGPU_ID=\"1002,6665\"\n" >> "$1"
+ else
+ printf "CONFIG_VGA_BIOS_DGPU_FILE=\"pci1002,6663.rom\"\n" >> "$1"
+ printf "CONFIG_VGA_BIOS_DGPU_ID=\"1002,6663\"\n" >> "$1"
+ fi
+ fi
+
+ sedder "$1" "# NATIVE" ""
+ sedder "$1" "CONFIG_HUDSON_SATA_MODE=0" ""
+
+ sedder "$1" "# RAID" ""
+ sedder "$1" "CONFIG_HUDSON_SATA_MODE=1" ""
+ sedder "$1" "CONFIG_RAID_ROM_ID=\"1022,7802\"" ""
+ sedder "$1" "CONFIG_RAID_ROM_FILE=\"src/southbridge/amd/agesa/hudson/raid.bin\"" ""
+ sedder "$1" "CONFIG_RAID_MISC_ROM_FILE=\"src/southbridge/amd/agesa/hudson/misc.bin\"" ""
+ sedder "$1" "CONFIG_RAID_MISC_ROM_POSITION=0xFFF00000" ""
+
+ sedder "$1" "# AHCI" ""
+ sedder "$1" "CONFIG_HUDSON_SATA_MODE=2" ""
+ sedder "$1" "CONFIG_AHCI_ROM_ID=\"1022,7801\"" ""
+ sedder "$1" "# CONFIG_HUDSON_AHCI_ROM is not set" ""
+
+ sedder "$1" "# LEGACY IDE" ""
+ sedder "$1" "CONFIG_HUDSON_SATA_MODE=3" ""
+
+ sedder "$1" "# IDE to AHCI" ""
+ sedder "$1" "CONFIG_HUDSON_SATA_MODE=4" ""
+
+ sedder "$1" "# AHCI7804" ""
+ sedder "$1" "CONFIG_HUDSON_SATA_MODE=5" ""
+ sedder "$1" "CONFIG_AHCI_ROM_ID=\"1022,7804\"" ""
+
+ sedder "$1" "# IDE to AHCI7804" ""
+ sedder "$1" "CONFIG_HUDSON_SATA_MODE=6" ""
+ sedder "$1" "# CONFIG_HUDSON_AHCI_ROM is not set" ""
+
+ if yesno "Do you have a SSD? (enable AHCI if Y)" "" ; then
+ printf "# AHCI\n" >> "$1"
+ printf "CONFIG_HUDSON_SATA_MODE=2\n" >> "$1"
+ printf "CONFIG_AHCI_ROM_ID=\"1022,7801\"\n" >> "$1"
+ printf "# CONFIG_HUDSON_AHCI_ROM is not set\n" >> "$1"
+ else
+ printf "# NATIVE\n" >> "$1"
+ printf "CONFIG_HUDSON_SATA_MODE=0\n" >> "$1"
+ fi
+ rm -f "$csb_configurer_tmp"
+ return 0
+ else
+ printf "\n\n${byellow}WARNING${bend}: sorry, I don't know how to configure a board of ${bold}$1${bend}\n"
+ encontinue
+ return 1
+ fi
+ else
+ return 1
+ fi
+}
+
+#
+# Conveniently and securely gets, checks SHA256 and installs a patch.
+# Arguments are the patch properties:
+# $1 - new diff name, could be also a part of extracted scripts' filename
+# $2 - change ID number, part of download link to review.coreboot.org
+# $3 - change revision number, part of download link to review.coreboot.org
+# $4 - diff filename inside the downloaded archive, will be renamed to $1
+# $5 - diff known good SHA256 checksum, will be used for SHA256 verification
+# $6 - filepath where to save a csb_patcher_log which will be printed later
+# $7 - info about the target of a patch, if not specified ("") it is common
+#
+csb_patcher () {
+ if ! wgetter "./patch?zip" "https://review.coreboot.org/changes/$2/revisions/$3/patch?zip" ; then
+ printf "${bold}^^^ ! Can't download a $7$1 patch ! Check your Internet.${bend}\n"
+ printf "%31s\n" "$7$1 - FAILURE_1" >> "$6"
+ csb_printer "$6"
+ exit 1
+ fi
+ unzipper "./patch?zip"
+ mover "./$4.diff" "./$1.diff"
+ csb_patcher_sha256sum_correct="$5 ./$1.diff"
+ csb_patcher_sha256sum_my=$( sha256sum "./$1.diff" )
+ printf "\n=== sha256sum should be:\n${bold}$csb_patcher_sha256sum_correct${bend}\n"
+ if [ "$csb_patcher_sha256sum_my" = "$csb_patcher_sha256sum_correct" ] ; then
+ printf "^^^ this is correct, "
+ csb_patcher_patch_title=$( grepper "Subject" "./$1.diff" )
+ csb_patcher_patch_title=${csb_patcher_patch_title#?????????????????}
+ if [ "$1" = "dgpu" ] ; then
+ printf "will extract a ${bold}$7$1${bend} patch now...\n"
+ rm -f "./sha256sums_$1_correct.txt"
+ rm -f "./"*"_$1_patches.sh"
+ patch -p1 < "./$1.diff"
+ chmod +x "./"*"_$1_patches.sh"
+ "./get_$1_patches.sh"
+ if ! "./check_$1_patches.sh" ; then
+ printf "%31s\n" "$7$1 - FAILURE_3" >> "$6"
+ csb_printer "$6"
+ exit 1
+ fi
+ else
+ printf "${bold}$7$1${bend} patch could be applied now...\n"
+ fi
+ if [ "$1" = "dgpu" ] || [ "$1" = "atombios" ] || \
+ [ "$1" = "tint" ] || [ "$1" = "seabios" ] ; then
+ printf "\n\n${bgreen}[PATCH]${bend} $csb_patcher_patch_title\n\n"
+ if ! grepcheck "how to submit coreboot changes" ./MAINTAINERS ; then
+ printf "\n${byellow}WARNING${bend}: not sure if I am inside the coreboot directory,"
+ printf "\n trying to add a ${bold}$1${bend} set from here - could fail.\n\n"
+ fi
+ if [ -f "./.$1" ] ; then
+ printf "\n${byellow}WARNING${bend}: found a '.$1' hidden file at the current directory,"
+ printf "\n maybe you have applied this patch already.\n\n"
+ fi
+ if yesno "Apply a ${bold}$7$1${bend} patch now?" "" ; then
+ if [ "$1" = "dgpu" ] ; then
+ "./apply_$1_patches.sh"
+ else
+ if [ "$1" = "atombios" ] ; then
+ rm -f "./sha256sums_$1_correct.txt"
+ rm -f "./"*"_$1_roms.sh"
+ rm -f "./pci1002\,"*".rom"
+ rm -f "./pci1002\,"*".rom.txt"
+ fi
+ if [ "$1" = "tint" ] ; then
+ rm -f "./payloads/external/tint/tint.sh"
+ rm -f "./payloads/external/tint/"*"_core.sh"
+ rm -f "./payloads/external/tint/tint-0.04-nmu1_libpayload.patch"
+ fi
+ if [ "$1" = "seabios" ] ; then
+ rm -f "./payloads/external/SeaBIOS/"*".patch"
+ fi
+ patch -p1 < "./$1.diff"
+ if [ "$1" = "atombios" ] ; then
+ chmod +x "./"*"_$1_roms.sh"
+ "./extract_$1_roms.sh"
+ printf "\n"
+ if ! "./check_$1_roms.sh" ; then
+ printf "%31s\n" "$7$1 - FAILURE_3" >> "$6"
+ csb_printer "$6"
+ exit 1
+ fi
+ fi
+ if [ "$1" = "tint" ] ; then
+ chmod +x "./payloads/external/tint/"*"_core.sh"
+ fi
+ fi
+ touch ".$1"
+ printf "%25s\n" "$7$1 - YES" >> "$6"
+ if [ "$1" = "atombios" ] ; then
+ encontinue
+ fi
+ else
+ printf "%24s\n" "$7$1 - NO" >> "$6"
+ printf "\n${bold}You can apply it later by running:${bend}"
+ if [ "$1" = "dgpu" ] ; then
+ printf "\n${bold} ./apply_$1_patches.sh${bend}\n"
+ else
+ printf "\n${bold} patch -p1 < ./$1.diff${bend}\n"
+ fi
+ encontinue
+ fi
+ fi
+ if checker "$1" "config" ; then
+ rm -f "./configs/$1_"*
+ patch -p1 < "./$1.diff"
+ printf "\n\n${bgreen}[PATCH]${bend} $csb_patcher_patch_title\n\n"
+ ls "./configs" > "./.csb_configs"
+ csb_patcher_config_name=$( grepper "$1" "./.csb_configs" )
+ rm -f "./.csb_configs"
+ printf "\n${bold}$csb_patcher_config_name could now be found at ./configs/${bend}"
+ printf "\n${bold}To use it, it should be copied to '.config' of your ./coreboot directory.${bend}\n\n"
+ if [ -f "./.config" ] ; then
+ printf "\n${byellow}WARNING${bend}: copying it to ./.config will overwrite your current '.config'\n\n"
+ fi
+ if yesno "Copy it to ./.config now?" "" ; then
+ copier "./configs/$csb_patcher_config_name" "./.config"
+ printf "\n"
+ printf "%25s\n" "$7$1 - YES" >> "$6"
+ if yesno "Configure this ./.config now?" "" ; then
+ csb_configurer "./.config"
+ else
+ printf "\n${bold}You can configure it later by running:${bend}"
+ printf "\n${bold} ./csb_patcher.sh config${bend}\n\n"
+ fi
+ else
+ printf "%24s\n" "$7$1 - NO" >> "$6"
+ printf "\n${bold}You can copy it later by running:${bend}"
+ printf "\n${bold} cp ./configs/$csb_patcher_config_name ./.config${bend}\n"
+ fi
+ printf "\n${byellow}WARNING${bend}: important README at the beginning of ./$1.diff\n"
+ encontinue
+ fi
+ printf "\n\n"
+ return 0
+ else
+ printf "${bold}^^^ ! MISMATCH for a $7$1 patch ! Check sha256sum manually: sha256sum ./$1.diff${bend}\n"
+ printf "%31s\n" "$7$1 - FAILURE_2" >> "$6"
+ csb_printer "$6"
+ exit 1
+ fi
+}
+
+#
+# Conveniently and securely gets, checks SHA256 and applies my collection of unofficial patches.
+# $1 - filepath where to save a csb_patcher_log which will be printed later
+#
+csb_mass_patcher () {
+###
+### https://review.coreboot.org/c/coreboot/+/31929
+### G505S dGPU support: scripts for applying the unofficial (not-merged-yet) patches
+###
+ csb_patcher "dgpu" "31929" "13" "ed0c44f" "eb461931a1f34a8263405138eb1bf8d32a1f460026449c9ec1a9b9e7d8383f1c" "$1" "G505S "
+###
+### https://review.coreboot.org/c/coreboot/+/31944
+### G505S AtomBIOS ROMs: known good binaries with a script to check their SHA256
+###
+ csb_patcher "atombios" "31944" "6" "78a8454" "9a8efff284bbdb81d5b912ccc8279162553e04673bde53e5288ba4bed0e4bc3d" "$1" "AMD "
+###
+### https://review.coreboot.org/c/coreboot/+/23856
+### tint: introduce the new tint build system with checksum verification
+###
+ csb_patcher "tint" "23856" "15" "14630b6" "7b9719f675d83750c7d4fb21b3abcbf1758ac6d1db20a9e8ef0db22f15761317" "$1" ""
+###
+### https://review.coreboot.org/c/coreboot/+/32351
+### SeaBIOS patches: advanced_bootmenu, multiple_floppies, writeprotected_usb
+###
+ csb_patcher "seabios" "32351" "5" "4a9c3cd" "58348b0514446856d07078af443ac8a24cd3be8178290e7361a48a86d213a43b" "$1" ""
+###
+### https://review.coreboot.org/c/coreboot/+/32352
+### configs: add Lenovo G505S sample configuration (use with dGPU patches)
+###
+csb_patcher "config.lenovo_g505s" "32352" "12" "348d8ce" "5b3b663b3afe3fe5729be2632201f3665e75ed3848996901322d3528ed6dd897" "$1" ""
+
+ return 0
+}
+
+# Prints a usage info for this ./csb_patcher.sh script.
+csb_usage () {
+ printf "${bold}===============${bend} ${bgreen}USAGE${bend} ${bold}================${bend}\n\n"
+ printf "${bold}./csb_patcher.sh${bend}\n"
+ printf " patch your coreboot source code\n\n"
+ printf "${bold}./csb_patcher.sh${bend} ${byellow}help${bend} ${bold}|${bend} ${byellow}usage${bend}\n"
+ printf " print this usage info\n\n"
+ printf "${bold}==================== Before building :${bend}\n\n"
+ printf "${bold}./csb_patcher.sh ${byellow}config${bend}\n"
+ printf " configure some popular options\n\n"
+ printf "${bold}==================== After building :${bend}\n\n"
+ printf "${bold}./csb_patcher.sh ${byellow}atom${bend}\n"
+ printf " add the AtomBIOS to coreboot.rom\n\n"
+ printf "${bold}./csb_patcher.sh ${byellow}flop${bend}\n"
+ printf " add the floppies to coreboot.rom\n\n"
+ printf "${bold}./csb_patcher.sh ${byellow}atomflop${bend}\n"
+ printf " both AtomBIOS VGA ROMs and floppies\n\n"
+ printf "${bold}./csb_patcher.sh${bend} ${byellow}print${bend}\n"
+ printf " print a ./.csb_patcher log\n\n"
+ return 0
+}
+
+#
+# MAIN PART OF A CSB_PATCHER SCRIPT
+#
+
+if [ -z "$1" ] ; then
+ csb_patcher_log="./.csb_patcher"
+ rm -f "$csb_patcher_log"
+ if ! command_exists "wget" || \
+ ! command_exists "unzip" || \
+ ! command_exists "sha256sum" || \
+ ! command_exists "patch" ; then
+ exit 1
+ fi
+ printf '\n\n' >> "$csb_patcher_log"
+ printf ' \\\\!//\n' >> "$csb_patcher_log"
+ printf ' (o o)\n' >> "$csb_patcher_log"
+ printf ' oOOo-(_)-oOOo\n' >> "$csb_patcher_log"
+ printf 'Hi! I am coreboot and SeaBIOS patcher\n' >> "$csb_patcher_log"
+ printf 'Please send your feedback to\n' >> "$csb_patcher_log"
+ printf ' Mike Banon <mikebdp2(a)gmail.com>\n' >> "$csb_patcher_log"
+ csb_printer "$csb_patcher_log"
+ encontinue
+ printf '\n=== CSB_PATCHER LOG. Patches applied?\n' >> "$csb_patcher_log"
+
+ csb_mass_patcher "$csb_patcher_log"
+
+ if yesno "Download a ${bold}floppies${bend} collection?" "" ; then
+ floppy_mass_downloader
+ printf "%25s\n" "floppies - YES" >> "$csb_patcher_log"
+ else
+ printf "\n"
+ printf "%24s\n" "floppies - NO" >> "$csb_patcher_log"
+ fi
+
+ printf '==================== Bad files found?\n' >> "$csb_patcher_log"
+ csb_finder "orig" "$csb_patcher_log" "applied correctly although at slightly different lines, can ignore it."
+ csb_finder "rej" "$csb_patcher_log" "perhaps failed to apply, could result in a broken build! ${bred}Please report${bend}"
+
+ printf '\n' >> "$csb_patcher_log"
+ csb_printer "$csb_patcher_log"
+ csb_usage
+else
+ case "$1" in
+ *"print"*)
+ csb_patcher_log="./.csb_patcher"
+ csb_printer "$csb_patcher_log"
+ ;;
+ *"config"*)
+ csb_configurer "./.config"
+ ;;
+ *"atom"*|*"flop"*)
+ if ! command_exists "wget" || \
+ ! command_exists "unzip" || \
+ ! command_exists "sha256sum" ; then
+ exit 1
+ fi
+ cbfs_mass_adder "$1" "./build/cbfstool" "./build/coreboot.rom" "./build/coreflop.rom"
+ ;;
+ *"help"*|*"usage"*)
+ printf "\n"
+ csb_usage
+ ;;
+ *)
+ printf "\n${bred}ERROR${bend}: unknown argument ${bold}$1${bend} !\n\n"
+ csb_usage
+ exit 1
+ ;;
+ esac
+fi
+
+exit 0
+
--
To view, visit https://review.coreboot.org/c/coreboot/+/33509
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I66f4f2865ac63ce0f2615669c7a3abd70a397e49
Gerrit-Change-Number: 33509
Gerrit-PatchSet: 1
Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com>
Gerrit-MessageType: newchange
17 hours, 31 minutes
- 4
- 69
Change in coreboot[master]: mb/google/zork/vilboz: Enable P sensor
by Peichao Li (Code Review)
Peichao Li has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43665 )
Change subject: mb/google/zork/vilboz: Enable P sensor
......................................................................
mb/google/zork/vilboz: Enable P sensor
BUG=b:161759253
TEST=flash the BIOS and insure firmware node will be generate
under the OS.
Signed-off-by: Peichao.Wang <peichao.wang(a)bitland.corp-partner.google.com>
Change-Id: I5e1a864bc156b434c39e8027fedf3a435757c1a7
---
M src/mainboard/google/zork/variants/vilboz/gpio.c
M src/mainboard/google/zork/variants/vilboz/overridetree.cb
2 files changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/43665/1
diff --git a/src/mainboard/google/zork/variants/vilboz/gpio.c b/src/mainboard/google/zork/variants/vilboz/gpio.c
index 4d292c2..29be3ae 100644
--- a/src/mainboard/google/zork/variants/vilboz/gpio.c
+++ b/src/mainboard/google/zork/variants/vilboz/gpio.c
@@ -9,6 +9,8 @@
static const struct soc_amd_gpio lte_gpio_set_stage_ram[] = {
/* LTE POWER ENABLE */
PAD_GPO(GPIO_32, HIGH),
+ /* P sensor INT */
+ PAD_SCI(GPIO_40, PULL_NONE, EDGE_LOW),
};
diff --git a/src/mainboard/google/zork/variants/vilboz/overridetree.cb b/src/mainboard/google/zork/variants/vilboz/overridetree.cb
index 49d21d5..63d3f7d 100644
--- a/src/mainboard/google/zork/variants/vilboz/overridetree.cb
+++ b/src/mainboard/google/zork/variants/vilboz/overridetree.cb
@@ -111,5 +111,12 @@
register "hid_desc_reg_offset" = "0x20"
device i2c 2c on end
end
+ chip drivers/i2c/generic
+ register "hid" = ""STH9324""
+ register "name" = ""SEMTECH SX9324""
+ register "desc" = ""SAR Proximity Sensor""
+ register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_40)"
+ device i2c 28 on end
+ end
end
end # chip soc/amd/picasso
--
To view, visit https://review.coreboot.org/c/coreboot/+/43665
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I5e1a864bc156b434c39e8027fedf3a435757c1a7
Gerrit-Change-Number: 43665
Gerrit-PatchSet: 1
Gerrit-Owner: Peichao Li <peichao.wang(a)bitland.corp-partner.google.com>
Gerrit-MessageType: newchange
19 hours, 42 minutes
- 3
- 7
Change in coreboot[master]: mb/google/zork/vilboz: enable LTE function
by Peichao Li (Code Review)
Peichao Li has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43663 )
Change subject: mb/google/zork/vilboz: enable LTE function
......................................................................
mb/google/zork/vilboz: enable LTE function
BUG=b:161736991
TEST=flash the BIOS and insure LTE function work properly
Signed-off-by: Peichao.Wang <peichao.wang(a)bitland.corp-partner.google.com>
Change-Id: I130bd76aad0a4b8f3a82090d97f140a0a7ed958e
---
M src/mainboard/google/zork/variants/vilboz/Makefile.inc
A src/mainboard/google/zork/variants/vilboz/gpio.c
2 files changed, 20 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/43663/1
diff --git a/src/mainboard/google/zork/variants/vilboz/Makefile.inc b/src/mainboard/google/zork/variants/vilboz/Makefile.inc
index dc1e411..51d19fe 100644
--- a/src/mainboard/google/zork/variants/vilboz/Makefile.inc
+++ b/src/mainboard/google/zork/variants/vilboz/Makefile.inc
@@ -2,4 +2,5 @@
subdirs-y += ./spd
+ramstage-y += gpio.c
ramstage-y += variant.c
diff --git a/src/mainboard/google/zork/variants/vilboz/gpio.c b/src/mainboard/google/zork/variants/vilboz/gpio.c
new file mode 100644
index 0000000..4d292c2
--- /dev/null
+++ b/src/mainboard/google/zork/variants/vilboz/gpio.c
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <boardid.h>
+#include <gpio.h>
+#include <soc/gpio.h>
+
+static const struct soc_amd_gpio lte_gpio_set_stage_ram[] = {
+ /* LTE POWER ENABLE */
+ PAD_GPO(GPIO_32, HIGH),
+};
+
+
+const struct soc_amd_gpio *variant_override_gpio_table(size_t *size)
+{
+ *size = ARRAY_SIZE(lte_gpio_set_stage_ram);
+ return lte_gpio_set_stage_ram;
+}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I130bd76aad0a4b8f3a82090d97f140a0a7ed958e
Gerrit-Change-Number: 43663
Gerrit-PatchSet: 1
Gerrit-Owner: Peichao Li <peichao.wang(a)bitland.corp-partner.google.com>
Gerrit-MessageType: newchange
20 hours, 32 minutes
- 3
- 4
Change in coreboot[master]: [WIP] mb/siemens/field_pg_m6: Add new mainboard
by Felix Singer (Code Review)
Hello Nico Huber, Thomas Heijligen,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/39976
to review the following change.
Change subject: [WIP] mb/siemens/field_pg_m6: Add new mainboard
......................................................................
[WIP] mb/siemens/field_pg_m6: Add new mainboard
Change-Id: I1d3508b615ec877edc8db756e9ad38132b37219c
Signed-off-by: Thomas Heijligen <thomas.heijligen(a)secunet.com>
Signed-off-by: Nico Huber <nico.huber(a)secunet.com>
Signed-off-by: Felix Singer <felix.singer(a)secunet.com>
---
A src/mainboard/siemens/field_pg_m6/Kconfig
A src/mainboard/siemens/field_pg_m6/Kconfig.name
A src/mainboard/siemens/field_pg_m6/Makefile.inc
A src/mainboard/siemens/field_pg_m6/board_info.txt
A src/mainboard/siemens/field_pg_m6/dsdt.asl
A src/mainboard/siemens/field_pg_m6/gma-mainboard.ads
A src/mainboard/siemens/field_pg_m6/mainboard.c
A src/mainboard/siemens/field_pg_m6/romstage.c
A src/mainboard/siemens/field_pg_m6/variant.h
A src/mainboard/siemens/field_pg_m6/variants/base/Makefile.inc
A src/mainboard/siemens/field_pg_m6/variants/base/board_info.txt
A src/mainboard/siemens/field_pg_m6/variants/base/data.vbt
A src/mainboard/siemens/field_pg_m6/variants/base/devicetree.cb
A src/mainboard/siemens/field_pg_m6/variants/base/gpio.c
14 files changed, 438 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/39976/1
diff --git a/src/mainboard/siemens/field_pg_m6/Kconfig b/src/mainboard/siemens/field_pg_m6/Kconfig
new file mode 100644
index 0000000..fec610c
--- /dev/null
+++ b/src/mainboard/siemens/field_pg_m6/Kconfig
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: GPL-2.0-only
+# This file is part of the coreboot project.
+
+if BOARD_SIEMENS_FIELD_PG_M6_BASE
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select BOARD_ROMSIZE_KB_32768
+ select DRIVERS_I2C_GENERIC
+ select DRIVERS_I2C_HID
+ select DRIVERS_UART_8250IO
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select MAINBOARD_HAS_LIBGFXINIT
+ select MAINBOARD_USES_IFD_GBE_REGION
+ select SOC_INTEL_CANNONLAKE_PCH_H
+ select SOC_INTEL_COFFEELAKE
+
+config MAINBOARD_DIR
+ string
+ default "siemens/field_pg_m6"
+
+config MAINBOARD_FAMILY
+ string
+ default "Field PG M6"
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "Field PG M6"
+
+config VARIANT_DIR
+ string
+ default "base" if BOARD_SIEMENS_FIELD_PG_M6_BASE
+
+config MAX_CPUS
+ int
+ default 12
+
+config DEVICETREE
+ string
+ default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb"
+
+config INTEL_GMA_VBT_FILE
+ string
+ default "src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/data.vbt"
+
+config DIMM_SPD_SIZE
+ int
+ default 512
+
+config CBFS_SIZE
+ hex
+ default 0xb00000
+
+endif
diff --git a/src/mainboard/siemens/field_pg_m6/Kconfig.name b/src/mainboard/siemens/field_pg_m6/Kconfig.name
new file mode 100644
index 0000000..00cba93
--- /dev/null
+++ b/src/mainboard/siemens/field_pg_m6/Kconfig.name
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-only
+# This file is part of the coreboot project.
+
+comment "Field PG M6"
+
+config BOARD_SIEMENS_FIELD_PG_M6_BASE
+ bool "-> Basic port"
diff --git a/src/mainboard/siemens/field_pg_m6/Makefile.inc b/src/mainboard/siemens/field_pg_m6/Makefile.inc
new file mode 100644
index 0000000..8c563df
--- /dev/null
+++ b/src/mainboard/siemens/field_pg_m6/Makefile.inc
@@ -0,0 +1,11 @@
+## SPDX-License-Identifier: GPL-2.0-only
+## This file is part of the coreboot project.
+
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)
+
+romstage-y += romstage.c
+
+ramstage-y += mainboard.c
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+
+subdirs-y += variants/$(VARIANT_DIR)
diff --git a/src/mainboard/siemens/field_pg_m6/board_info.txt b/src/mainboard/siemens/field_pg_m6/board_info.txt
new file mode 100644
index 0000000..cb5b428
--- /dev/null
+++ b/src/mainboard/siemens/field_pg_m6/board_info.txt
@@ -0,0 +1,5 @@
+Vendor name: Siemens
+Category: eval
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: n
diff --git a/src/mainboard/siemens/field_pg_m6/dsdt.asl b/src/mainboard/siemens/field_pg_m6/dsdt.asl
new file mode 100644
index 0000000..041fd4f
--- /dev/null
+++ b/src/mainboard/siemens/field_pg_m6/dsdt.asl
@@ -0,0 +1,25 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0-only
+ * This file is part of the coreboot project.
+ */
+
+#include <arch/acpi.h>
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, // DSDT revision: ACPI v2.0 and up
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20110725 // OEM revision
+)
+{
+ #include <soc/intel/cannonlake/acpi/platform.asl>
+ #include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+
+ Device (\_SB.PCI0) {
+ #include <soc/intel/common/block/acpi/acpi/northbridge.asl>
+ #include <soc/intel/cannonlake/acpi/southbridge.asl>
+ }
+
+ #include <southbridge/intel/common/acpi/sleepstates.asl>
+}
diff --git a/src/mainboard/siemens/field_pg_m6/gma-mainboard.ads b/src/mainboard/siemens/field_pg_m6/gma-mainboard.ads
new file mode 100644
index 0000000..82da885
--- /dev/null
+++ b/src/mainboard/siemens/field_pg_m6/gma-mainboard.ads
@@ -0,0 +1,26 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+-- This file is part of the coreboot project.
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+ -- For a three-pipe setup, bandwidth is shared between the 2nd and
+ -- the 3rd pipe (if it's not eDP). Thus, probe ports that likely
+ -- have a high-resolution display attached first, `Internal` last.
+
+ ports : constant Port_List :=
+ (DP2,
+ DP3,
+ HDMI1,
+ HDMI2,
+ HDMI3,
+ Analog,
+ eDP,
+ others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/siemens/field_pg_m6/mainboard.c b/src/mainboard/siemens/field_pg_m6/mainboard.c
new file mode 100644
index 0000000..508ba22
--- /dev/null
+++ b/src/mainboard/siemens/field_pg_m6/mainboard.c
@@ -0,0 +1,21 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0-only
+ * This file is part of the coreboot project.
+ */
+
+#include <device/device.h>
+#include <soc/gpio.h>
+#include "variant.h"
+
+static void mainboard_init(void *chip_info)
+{
+ const struct pad_config *pads;
+ size_t num;
+
+ pads = variant_gpio_table(&num);
+ gpio_configure_pads(pads, num);
+}
+
+struct chip_operations mainboard_ops = {
+ .init = mainboard_init,
+};
diff --git a/src/mainboard/siemens/field_pg_m6/romstage.c b/src/mainboard/siemens/field_pg_m6/romstage.c
new file mode 100644
index 0000000..380fc15
--- /dev/null
+++ b/src/mainboard/siemens/field_pg_m6/romstage.c
@@ -0,0 +1,26 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0-only
+ * This file is part of the coreboot project.
+ */
+
+#include <soc/cnl_memcfg_init.h>
+#include <soc/romstage.h>
+#include <spd_bin.h>
+
+void mainboard_memory_init_params(FSPM_UPD *memupd)
+{
+ const struct cnl_mb_cfg cfg = {
+ .spd = {
+ [0] = { READ_SMBUS, { 0x50 << 1 }},
+ [2] = { READ_SMBUS, { 0x52 << 1 }},
+ },
+ .rcomp_resistor = { 121, 75, 100 },
+ .rcomp_targets = { 50, 25, 20, 20, 26 },
+ .dq_pins_interleaved = 1,
+ .vref_ca_config = 2,
+ .ect = 0,
+ };
+ cannonlake_memcfg_init(&memupd->FspmConfig, &cfg);
+ memupd->FspmConfig.EccSupport = 1;
+ memupd->FspmConfig.UserBd = BOARD_TYPE_MOBILE;
+}
diff --git a/src/mainboard/siemens/field_pg_m6/variant.h b/src/mainboard/siemens/field_pg_m6/variant.h
new file mode 100644
index 0000000..68f9afb
--- /dev/null
+++ b/src/mainboard/siemens/field_pg_m6/variant.h
@@ -0,0 +1,11 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0-only
+ * This file is part of the coreboot project.
+ */
+
+#ifndef _VARIANT_H_
+#define _VARIANT_H_
+
+const struct pad_config *variant_gpio_table(size_t *num);
+
+#endif /* _VARIANT_H_ */
diff --git a/src/mainboard/siemens/field_pg_m6/variants/base/Makefile.inc b/src/mainboard/siemens/field_pg_m6/variants/base/Makefile.inc
new file mode 100644
index 0000000..fdd7104
--- /dev/null
+++ b/src/mainboard/siemens/field_pg_m6/variants/base/Makefile.inc
@@ -0,0 +1,4 @@
+## SPDX-License-Identifier: GPL-2.0-only
+## This file is part of the coreboot project.
+
+ramstage-y += gpio.c
diff --git a/src/mainboard/siemens/field_pg_m6/variants/base/board_info.txt b/src/mainboard/siemens/field_pg_m6/variants/base/board_info.txt
new file mode 100644
index 0000000..199a44e
--- /dev/null
+++ b/src/mainboard/siemens/field_pg_m6/variants/base/board_info.txt
@@ -0,0 +1 @@
+Board name: Field PG M6
diff --git a/src/mainboard/siemens/field_pg_m6/variants/base/data.vbt b/src/mainboard/siemens/field_pg_m6/variants/base/data.vbt
new file mode 100644
index 0000000..f79a6005
--- /dev/null
+++ b/src/mainboard/siemens/field_pg_m6/variants/base/data.vbt
Binary files differ
diff --git a/src/mainboard/siemens/field_pg_m6/variants/base/devicetree.cb b/src/mainboard/siemens/field_pg_m6/variants/base/devicetree.cb
new file mode 100644
index 0000000..8fd83dd
--- /dev/null
+++ b/src/mainboard/siemens/field_pg_m6/variants/base/devicetree.cb
@@ -0,0 +1,114 @@
+# SPDX-License-Identifier: GPL-2.0-only
+# This file is part of the coreboot project.
+
+chip soc/intel/cannonlake
+
+ # TODO
+ # FSP configuration
+ register "SaGv" = "SaGv_Enabled"
+ register "RMT" = "0"
+
+ register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)" # Type-C?
+ register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # single blue
+ register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # SIMATIC NET CP 5711
+ register "usb2_ports[7]" = "USB2_PORT_MID(OC1)" # upper blue
+ register "usb2_ports[8]" = "USB2_PORT_MID(OC4)" # lower blue
+ register "usb2_ports[11]" = "USB2_PORT_MID(OC_SKIP)" # STM SC?
+
+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-C?
+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # upper blue
+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC4)" # lower blue
+ register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Realtek storage?
+ register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)" # single blue
+
+ register "SataSalpSupport" = "1"
+ register "SataPortsEnable[0]" = "1"
+ register "SataPortsEnable[1]" = "1"
+ register "SataPortsEnable[2]" = "1"
+ register "SataPortsEnable[3]" = "1"
+
+ register "PchHdaDspEnable" = "0"
+ register "PchHdaAudioLinkHda" = "1"
+
+ register "PcieRpEnable[0]" = "1"
+ register "PcieRpEnable[5]" = "1"
+ register "PcieRpEnable[16]" = "1"
+
+ register "PcieClkSrcUsage[2]" = "0"
+ register "PcieClkSrcUsage[5]" = "5"
+ register "PcieClkSrcUsage[7]" = "16"
+
+ register "PcieClkSrcClkReq[2]" = "2"
+ register "PcieClkSrcClkReq[5]" = "5"
+ register "PcieClkSrcClkReq[7]" = "7"
+
+ # Enable "Intel Speed Shift Technology"
+ register "speed_shift_enable" = "1"
+
+ # HECI
+ register "HeciEnabled" = "1"
+
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
+
+ device domain 0 on
+ device pci 00.0 on end # Host Bridge
+ device pci 02.0 on end # Integrated Graphics Device
+ device pci 04.0 off end # SA Thermal device
+ device pci 12.0 on end # Thermal Subsystem
+ device pci 12.5 off end # UFS SCS
+ device pci 12.6 off end # GSPI #2
+ device pci 13.0 off end # ISH
+ device pci 14.0 on end # USB xHCI
+ device pci 14.1 off end # USB xDCI (OTG)
+ device pci 14.2 on end # Shared SRAM
+ device pci 14.5 off end # SDCard
+ device pci 15.0 off end # I2C #0
+ device pci 15.1 off end # I2C #1
+ device pci 15.2 off end # I2C #2
+ device pci 15.3 off end # I2C #3
+ device pci 16.0 on end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT Redirection
+ device pci 16.4 off end # Management Engine Interface 3
+ device pci 16.5 off end # Management Engine Interface 4
+ device pci 17.0 on end # SATA
+ device pci 19.0 off end # I2C #4
+ device pci 19.2 off end # UART #2
+ device pci 1a.0 off end # eMMC
+ device pci 1c.0 on end # PCI Express Port 1
+ device pci 1c.1 off end # PCI Express Port 2
+ device pci 1c.2 off end # PCI Express Port 3
+ device pci 1c.3 off end # PCI Express Port 4
+ device pci 1c.4 off end # PCI Express Port 5
+ device pci 1c.5 on end # PCI Express Port 6
+ device pci 1c.6 off end # PCI Express Port 7
+ device pci 1c.7 off end # PCI Express Port 8
+ device pci 1d.0 off end # PCI Express Port 9
+ device pci 1d.1 off end # PCI Express Port 10
+ device pci 1d.2 off end # PCI Express Port 11
+ device pci 1d.3 off end # PCI Express Port 12
+ device pci 1d.4 off end # PCI Express Port 13
+ device pci 1d.5 off end # PCI Express Port 14
+ device pci 1d.6 off end # PCI Express Port 15
+ device pci 1d.7 off end # PCI Express Port 16
+ device pci 1b.0 on end # PCI Express Port 17 x4
+ device pci 1b.4 off end # PCI Express Port 21
+ device pci 1b.5 off end # PCI Express Port 22
+ device pci 1b.6 off end # PCI Express Port 23
+ device pci 1b.7 off end # PCI Express Port 24
+ device pci 1e.0 off end # UART #0
+ device pci 1e.1 off end # UART #1
+ device pci 1e.2 off end # GSPI #0
+ device pci 1e.3 off end # GSPI #1
+ device pci 1f.0 on end # LPC Interface
+ device pci 1f.1 on end # P2SB
+ device pci 1f.2 on end # Power Management Controller
+ device pci 1f.3 on end # Intel HDA
+ device pci 1f.4 on end # SMBus
+ device pci 1f.5 on end # PCH SPI
+ device pci 1f.6 on end # GbE
+ end
+end
diff --git a/src/mainboard/siemens/field_pg_m6/variants/base/gpio.c b/src/mainboard/siemens/field_pg_m6/variants/base/gpio.c
new file mode 100644
index 0000000..005d12c
--- /dev/null
+++ b/src/mainboard/siemens/field_pg_m6/variants/base/gpio.c
@@ -0,0 +1,132 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0-only
+ * This file is part of the coreboot project.
+ */
+
+#include <soc/gpio.h>
+#include "variant.h"
+
+static const struct pad_config gpio_table[] = {
+/* GPP_A14 GPIO 0x0000002644000300 */ PAD_NC(GPP_A14, NONE),
+/* GPP_A16 GPIO 0x0000002444000300 */ PAD_NC(GPP_A16, DN_20K),
+/* GPP_B4 GPIO 0x0000003444000200 */ PAD_CFG_GPO(GPP_B4, 0, DEEP),
+/* GPP_B5 GPIO 0x0000003544000300 */ PAD_NC(GPP_B5, NONE),
+/* GPP_B6 GPIO 0x0000003644000300 */ PAD_NC(GPP_B6, NONE),
+/* GPP_B8 GPIO 0x0000003844000300 */ PAD_NC(GPP_B8, NONE),
+/* GPP_B10 GPIO 0x0000003a44000300 */ PAD_NC(GPP_B10, NONE),
+/* GPP_B11 GPIO 0x0000003b44000201 */ PAD_CFG_GPO(GPP_B11, 1, DEEP),
+/* GPP_B14 SPKR 0x0000003e44000600 */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
+/* GPP_B18 GPIO 0x0000004244000300 */ PAD_NC(GPP_B18, NONE),
+/* GPP_B22 GPIO 0x0000004644000300 */ PAD_NC(GPP_B22, NONE),
+/* GPP_C2 GPIO 0x0000004a44000300 */ PAD_NC(GPP_C2, NONE),
+/* GPP_C5 GPIO 0x0000004d44000300 */ PAD_NC(GPP_C5, NONE),
+/* GPP_C6 SML1CLK 0x0000004e44000703 */ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),
+/* GPP_C7 SML1DATA 0x0000004f44000703 */ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),
+/* GPP_C8 GPIO 0x0000005044000300 */ PAD_NC(GPP_C8, NONE),
+/* GPP_C9 GPIO 0x0000005144000300 */ PAD_NC(GPP_C9, NONE),
+/* GPP_C12 GPIO 0x0000005444000102 */ PAD_CFG_GPI(GPP_C12, NONE, DEEP),
+/* GPP_C13 GPIO 0x0000005544000102 */ PAD_CFG_GPI(GPP_C13, NONE, DEEP),
+/* GPP_C14 GPIO 0x0000005644000102 */ PAD_CFG_GPI(GPP_C14, NONE, DEEP),
+/* GPP_C15 GPIO 0x0000005744000100 */ PAD_CFG_GPI(GPP_C15, NONE, DEEP),
+/* GPP_C16 I2C0_SDA 0x0000005884800402 */ PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1),
+/* GPP_C17 I2C0_SCL 0x0000005944000602 */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
+/* GPP_C20 UART2_RXD 0x0000005c44000500 */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
+/* GPP_C21 UART2_TXD 0x0000005d44000600 */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
+/* GPP_C22 UART2_RTS# 0x0000005e44000500 */ PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1),
+/* GPP_C23 UART2_CTS# 0x0000005f44000502 */ PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1),
+/* GPP_D1 GPIO 0x0000006144000102 */ PAD_CFG_GPI(GPP_D1, NONE, DEEP),
+/* GPP_D2 GPIO 0x0000006244800102 */ PAD_CFG_GPI(GPP_D2, NONE, DEEP),
+/* GPP_D3 GPIO 0x0000006344000201 */ PAD_CFG_GPO(GPP_D3, 1, DEEP),
+/* GPP_D7 GPIO 0x0000006784000102 */ PAD_CFG_GPI(GPP_D7, NONE, PLTRST),
+/* GPP_D8 GPIO 0x0000006884000100 */ PAD_CFG_GPI(GPP_D8, NONE, PLTRST),
+/* GPP_D17 DMIC_CLK1 0x0000007144000700 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
+/* GPP_D18 DMIC_DATA1 0x0000007244000700 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
+/* GPP_D19 DMIC_CLK0 0x0000007344000700 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
+/* GPP_D20 DMIC_DATA0 0x0000007444000700 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
+/* GPP_D21 GPIO 0x0000007544000201 */ PAD_CFG_GPO(GPP_D21, 1, DEEP),
+/* GPP_D22 GPIO 0x0000007644800100 */ PAD_CFG_GPI(GPP_D22, NONE, DEEP),
+/* GPP_G1 GPIO 0x0000006d84000201 */ PAD_CFG_GPO(GPP_G1, 1, PLTRST),
+/* GPP_G2 GPIO 0x0000006e84800102 */ PAD_CFG_GPI(GPP_G2, NONE, PLTRST),
+/* GPP_G3 GPIO 0x0000006f40880102 */ PAD_CFG_GPI_APIC(GPP_G3, NONE, DEEP, LEVEL, INVERT),
+/* GPIO_RSVD_9 GPIO 0x0000000040000300 */ PAD_NC(GPIO_RSVD_9, NONE),
+/* GPIO_RSVD_10 GPIO 0x0000000040000300 */ PAD_NC(GPIO_RSVD_10, NONE),
+/* GPD0 BATLOW# 0x0000006044000702 */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
+/* GPD1 ACPRESENT 0x00003c6144000502 */ PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1),
+/* GPD7 GPIO 0x00000067c4000200 */ PAD_CFG_GPO(GPD7, 0, RSMRST),
+/* GPP_K0 GPIO 0x0000001884000102 */ PAD_CFG_GPI(GPP_K0, NONE, PLTRST),
+/* GPP_K1 GPIO 0x0000001984000100 */ PAD_CFG_GPI(GPP_K1, NONE, PLTRST),
+/* GPP_K2 GPIO 0x0000001a84000100 */ PAD_CFG_GPI(GPP_K2, NONE, PLTRST),
+/* GPP_K3 GPIO 0x0000001b84000102 */ PAD_CFG_GPI(GPP_K3, NONE, PLTRST),
+/* GPP_K4 GPIO 0x0000001c04000201 */ PAD_CFG_GPO(GPP_K4, 1, PWROK),
+/* GPP_K5 GPIO 0x0000001d04000201 */ PAD_CFG_GPO(GPP_K5, 1, PWROK),
+/* GPP_K8 GPIO 0x0000002044000300 */ PAD_NC(GPP_K8, NONE),
+/* GPP_K9 GPIO 0x0000002144000300 */ PAD_NC(GPP_K9, NONE),
+/* GPP_K10 GPIO 0x0000002244000300 */ PAD_NC(GPP_K10, NONE),
+/* GPP_K11 GPIO 0x0000002344000300 */ PAD_NC(GPP_K11, NONE),
+/* GPP_K20 GPIO 0x0000002c84000201 */ PAD_CFG_GPO(GPP_K20, 1, PLTRST),
+/* GPP_K21 GPIO 0x0000002d44000300 */ PAD_NC(GPP_K21, NONE),
+/* GPP_H0 GPIO 0x0000004884000102 */ PAD_CFG_GPI(GPP_H0, NONE, PLTRST),
+/* GPP_H2 GPIO 0x0000004a44000300 */ PAD_NC(GPP_H2, NONE),
+/* GPP_H3 GPIO 0x0000004b44000300 */ PAD_NC(GPP_H3, NONE),
+/* GPP_H10 GPIO 0x0000005244800102 */ PAD_CFG_GPI(GPP_H10, NONE, DEEP),
+/* GPP_H15 GPIO 0x0000005744000201 */ PAD_CFG_GPO(GPP_H15, 1, DEEP),
+/* GPP_H17 GPIO 0x0000005944000201 */ PAD_CFG_GPO(GPP_H17, 1, DEEP),
+/* GPP_E0 SATAXPCIE0 0x0000001844800502 */ PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1),
+/* GPP_E1 GPIO 0x0000001944000300 */ PAD_NC(GPP_E1, NONE),
+/* GPP_E2 GPIO 0x0000001a44000300 */ PAD_NC(GPP_E2, NONE),
+/* GPP_E4 SATA_DEVSLP0 0x0000001c44000600 */ PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1),
+/* GPP_E5 GPIO 0x0000301d44800102 */ PAD_CFG_GPI(GPP_E5, NONE, DEEP),
+/* GPP_E6 GPIO 0x0000001e44800102 */ PAD_CFG_GPI(GPP_E6, NONE, DEEP),
+/* GPP_E8 SATALED# 0x0000002044000700 */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
+/* GPP_E9 USB2_OC0# 0x0000302144000702 */ PAD_CFG_NF(GPP_E9, UP_20K, DEEP, NF1),
+/* GPP_E10 USB2_OC1# 0x0000302244000702 */ PAD_CFG_NF(GPP_E10, UP_20K, DEEP, NF1),
+/* GPP_E11 USB2_OC2# 0x0000302344000702 */ PAD_CFG_NF(GPP_E11, UP_20K, DEEP, NF1),
+/* GPP_E12 GPIO 0x0000002484000201 */ PAD_CFG_GPO(GPP_E12, 1, PLTRST),
+/* GPP_F1 GPIO 0x0000003144000300 */ PAD_NC(GPP_F1, NONE),
+/* GPP_F2 GPIO 0x0000003244000300 */ PAD_NC(GPP_F2, NONE),
+/* GPP_F3 GPIO 0x0000003344000300 */ PAD_NC(GPP_F3, NONE),
+/* GPP_F4 GPIO 0x0000003444000300 */ PAD_NC(GPP_F4, NONE),
+/* GPP_F5 GPIO 0x0000003584000201 */ PAD_CFG_GPO(GPP_F5, 1, PLTRST),
+/* GPP_F6 SATA_DEVSLP4 0x0000003644000700 */ PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
+/* GPP_F8 GPIO 0x0000003844800000 */ PAD_CFG_GPO(GPP_F8, 0, DEEP),
+/* GPP_F9 GPIO 0x0000003944000200 */ PAD_CFG_GPO(GPP_F9, 0, DEEP),
+/* GPP_F10 GPIO 0x0000003a84000100 */ PAD_CFG_GPI(GPP_F10, NONE, PLTRST),
+/* GPP_F13 GPIO 0x0000003d82800102 */ PAD_CFG_GPI(GPP_F13, NONE, PLTRST),
+/* GPP_F14 GPIO 0x0000003e44000300 */ PAD_NC(GPP_F14, NONE),
+/* GPP_F15 USB2_OC4# 0x0000303f44000702 */ PAD_CFG_NF(GPP_F15, UP_20K, DEEP, NF1),
+/* GPP_F16 USB2_OC5# 0x0000304044000702 */ PAD_CFG_NF(GPP_F16, UP_20K, DEEP, NF1),
+/* GPP_F17 USB2_OC6# 0x0000304144000702 */ PAD_CFG_NF(GPP_F17, UP_20K, DEEP, NF1),
+/* GPP_F18 GPIO 0x0000004240880102 */ PAD_CFG_GPI_APIC(GPP_F18, NONE, DEEP, LEVEL, INVERT),
+/* GPP_F19 eDP_VDDEN 0x0000004344000700 */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
+/* GPP_F20 eDP_BKLTEN 0x0000004444000700 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
+/* GPP_F21 eDP_BKLTCTL 0x0000004544000700 */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
+/* GPP_F22 DDPF_CTRLCLK 0x0000004644000700 */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
+/* GPP_F23 DDPF_CTRLDATA 0x0000004744000702 */ PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1),
+/* GPP_I0 DDPB_HPD0 0x00003c0040000700 */ PAD_CFG_NF(GPP_I0, NATIVE, DEEP, NF1),
+/* GPP_I1 DDPB_HPD1 0x00003c0040000700 */ PAD_CFG_NF(GPP_I1, NATIVE, DEEP, NF1),
+/* GPP_I2 DDPB_HPD2 0x00003c0040000700 */ PAD_CFG_NF(GPP_I2, NATIVE, DEEP, NF1),
+/* GPP_I3 DDPB_HPD3 0x0000000040000700 */ PAD_CFG_NF(GPP_I3, NONE, DEEP, NF1),
+/* GPP_I4 EDP_HPD 0x0000000040000700 */ PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1),
+/* GPP_I5 DDPB_CTRLCLK 0x0000000040000700 */ PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1),
+/* GPP_I6 DDPB_CTRLDATA 0x0000000040000702 */ PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1),
+/* GPP_I7 DDPC_CTRLCLK 0x0000000040000700 */ PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1),
+/* GPP_I8 DDPC_CTRLDATA 0x0000000040000700 */ PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1),
+/* GPP_I9 DDPD_CTRLCLK 0x0000100040000700 */ PAD_CFG_NF(GPP_I9, DN_20K, DEEP, NF1),
+/* GPP_I10 DDPD_CTRLDATA 0x0000100040000700 */ PAD_CFG_NF(GPP_I10, DN_20K, DEEP, NF1),
+/* GPP_J2 n/a 0x0000003044000700 */ PAD_CFG_NF(GPP_J2, NONE, DEEP, NF1),
+/* GPP_J3 n/a 0x0000003144000700 */ PAD_CFG_NF(GPP_J3, NONE, DEEP, NF1),
+/* GPP_J4 CNV_BRI_DT 0x0000003244000702 */ PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1),
+/* GPP_J5 CNV_BRI_RSP 0x0000003344000702 */ PAD_CFG_NF(GPP_J5, NONE, DEEP, NF1),
+/* GPP_J6 CNV_RGI_DT 0x0000003444000700 */ PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1),
+/* GPP_J7 CNV_RGI_RSP 0x0000003544000700 */ PAD_CFG_NF(GPP_J7, NONE, DEEP, NF1),
+/* GPP_J8 CNV_MFUART2_RXD 0x0000003644000602 */ PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1),
+/* GPP_J9 CNV_MFUART2_TXD 0x0000003744000702 */ PAD_CFG_NF(GPP_J9, NONE, DEEP, NF1),
+/* GPP_J10 n/a 0x0000003844000602 */ PAD_CFG_NF(GPP_J10, NONE, DEEP, NF1),
+/* GPP_J11 A4WP_PRESENT 0x0000003944000700 */ PAD_CFG_NF(GPP_J11, NONE, DEEP, NF1),
+};
+
+const struct pad_config *variant_gpio_table(size_t *num)
+{
+ *num = ARRAY_SIZE(gpio_table);
+ return gpio_table;
+}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I1d3508b615ec877edc8db756e9ad38132b37219c
Gerrit-Change-Number: 39976
Gerrit-PatchSet: 1
Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net>
Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de>
Gerrit-MessageType: newchange
23 hours, 53 minutes
- 8
- 35
Change in ...coreboot[master]: Documentation: Fix spelling of *assumptions*
by Paul Menzel (Code Review)
Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33742
Change subject: Documentation: Fix spelling of *assumptions*
......................................................................
Documentation: Fix spelling of *assumptions*
Change-Id: I36e0e713647cfc0d25e6b4ead81aa212be530afb
Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de>
---
M Documentation/arch/x86/index.md
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/33742/1
diff --git a/Documentation/arch/x86/index.md b/Documentation/arch/x86/index.md
index 0d8acf1..b4ad5c8 100644
--- a/Documentation/arch/x86/index.md
+++ b/Documentation/arch/x86/index.md
@@ -17,7 +17,7 @@
The following features enhance x86_64 support:
* The CPU supports 1GiB hugepages
-## Assuptions for ARCH_ROMSTAGE_X86_64 reference implementation
+## Assumptions for ARCH_ROMSTAGE_X86_64 reference implementation
* 0-4GiB are identity mapped as WB
* Memory above 4GiB isn't accessible
* pagetables reside in CAR area `_pagetables`
@@ -38,7 +38,7 @@
* 0-4GiB are identity mapped as WB
* page tables reside in heap
-## Assuptions for ARCH_RAMSTAGE_X86_64 reference implementation
+## Assumptions for ARCH_RAMSTAGE_X86_64 reference implementation
* pagetable are stored in fixed size heap area, initialized by assembly code
* Memory above 4GiB is not accessible
--
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Gerrit-Change-Id: I36e0e713647cfc0d25e6b4ead81aa212be530afb
Gerrit-Change-Number: 33742
Gerrit-PatchSet: 1
Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-MessageType: newchange
1 day, 4 hours
- 5
- 7