coreboot-gerrit July 2020

coreboot-gerrit@coreboot.org

1 participants
3167 discussions

Change in coreboot[master]: abuild: Fix board variant handling
by Keith Hui (Code Review) 17 Aug '23

17 Aug '23

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41918 ) Change subject: abuild: Fix board variant handling ...................................................................... abuild: Fix board variant handling Problem: Me: $ util/abuild/abuild -t asus/p2b -b p2b-ls abuild: No such target: asus/p2b, variant: p2b-ls Cause: We identify boards and variants using path names in tree, so I type in the test command above. abuild identifies all board variants the Kconfig way, in all caps and all underscores. Result: Expectation gap and abuild can't find anything where we expect it to. All variants with a hyphen in their names are affected. Fix: Add a substitution to replace hyphens with underscores. Test: I get my abuild with the command above, even a variant-specific test config works. Change-Id: I10d5b471dac41c50a85c4a309ec561b02687bb9a Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M util/abuild/abuild 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/41918/1 diff --git a/util/abuild/abuild b/util/abuild/abuild index b6a6bfe..ca8a0cf 100755 --- a/util/abuild/abuild +++ b/util/abuild/abuild @@ -165,7 +165,7 @@ local targets local VARIANT_UC - VARIANT_UC=$(echo "${variant}" | tr '[:lower:]' '[:upper:]') + VARIANT_UC=$(echo "${variant}" | tr '[:lower:]' '[:upper:]' | tr '-' '_') targets=$(get_mainboards "$1") if [ -n "$targets" ]; then -- To view, visit https://review.coreboot.org/c/coreboot/+/41918 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I10d5b471dac41c50a85c4a309ec561b02687bb9a Gerrit-Change-Number: 41918 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-MessageType: newchange

5 9

Change in coreboot[master]: mb/asus/p2b: Add ACPI support for p3b-f
by Keith Hui (Code Review) 14 Aug '23

14 Aug '23

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41098 ) Change subject: mb/asus/p2b: Add ACPI support for p3b-f ...................................................................... mb/asus/p2b: Add ACPI support for p3b-f Finally! Power button works to turn board on and off. ACPI hooks to manipulate power and message LEDs work. Change-Id: I3736532df0efde4399fb36eb19df8db511fac6ea Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/mainboard/asus/p2b/Kconfig M src/mainboard/asus/p2b/dsdt.asl A src/mainboard/asus/p2b/suspend.asl A src/mainboard/asus/p2b/variants/p3b-f/suspend.asl 4 files changed, 393 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/41098/1 diff --git a/src/mainboard/asus/p2b/Kconfig b/src/mainboard/asus/p2b/Kconfig index 1ad25e1..45018d6 100644 --- a/src/mainboard/asus/p2b/Kconfig +++ b/src/mainboard/asus/p2b/Kconfig @@ -29,7 +29,7 @@ select HAVE_PIRQ_TABLE select BOARD_ROMSIZE_KB_256 select SDRAMPWR_4DIMM if BOARD_ASUS_P2B_LS || BOARD_ASUS_P3B_F - select HAVE_ACPI_TABLES if BOARD_ASUS_P2B || BOARD_ASUS_P2B_LS + select HAVE_ACPI_TABLES if BOARD_ASUS_P2B || BOARD_ASUS_P2B_LS || BOARD_ASUS_P3B_F select BASE_ASUS_P2B_D if BOARD_ASUS_P2B_D || BOARD_ASUS_P2B_DS config MAX_CPUS diff --git a/src/mainboard/asus/p2b/dsdt.asl b/src/mainboard/asus/p2b/dsdt.asl index 88be9ba..623b575 100644 --- a/src/mainboard/asus/p2b/dsdt.asl +++ b/src/mainboard/asus/p2b/dsdt.asl @@ -53,6 +53,7 @@ { Offset (0x03), TO12, 1, /* Device trap 12 */ +#if !CONFIG(BOARD_ASUS_P3B_F) Offset (0x08), FANM, 1, /* GPO0, meant for fan */ Offset (0x09), @@ -61,33 +62,25 @@ , 2, , 16, MSG0, 1 /* GPO30, message LED */ +#endif } - /* Prepare To Sleep, Arg0 is target S-state */ - Method (\_PTS, 1, NotSerialized) + OperationRegion (ECOS, SystemIO, 0x72, 0x02) + Field (ECOS, ByteAcc, NoLock, Preserve) { - /* Disable fan, blink power LED, if not turning off */ - If (LNotEqual (Arg0, 0x05)) - { - Store (Zero, FANM) - Store (Zero, PLED) - } - - /* Arms SMI for device 12 */ - Store (One, TO12) - /* Put out a POST code */ - Or (Arg0, 0xF0, P80) + CIDX, 8, + CDAT, 8 } - Method (\_WAK, 1, NotSerialized) + IndexField (CIDX, CDAT, ByteAcc, NoLock, Preserve) { - /* Re-enable fan, stop power led blinking */ - Store (One, FANM) - Store (One, PLED) - /* wake OK */ - Return(Package(0x02){0x00, 0x00}) + Offset (0x58), + RTCS, 8, + Offset (0x5F), + SUS3, 1, + , 3, + SLST, 4 } - /* Root of the bus hierarchy */ Scope (\_SB) { @@ -169,19 +162,9 @@ } } - /* ACPI Message */ - Scope (\_SI) - { - Method (_MSG, 1, NotSerialized) - { - If (LEqual (Arg0, Zero)) - { - Store (One, MSG0) - } - Else - { - Store (Zero, MSG0) - } - } - } +#if CONFIG(BOARD_ASUS_P3B_F) +#include "variants/p3b-f/suspend.asl" +#else +#include "suspend.asl" +#endif } diff --git a/src/mainboard/asus/p2b/suspend.asl b/src/mainboard/asus/p2b/suspend.asl new file mode 100644 index 0000000..5d2b540 --- /dev/null +++ b/src/mainboard/asus/p2b/suspend.asl @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +/* ASUS P2B family board DSDT declarations (at top level) that does not apply to P3B-F */ + +/** + * ACPI message indicator. + * + * @param Arg0 Number of waiting messages + */ +Scope (\_SI) +{ + Method (_MSG, 1, NotSerialized) + { + If (LEqual (Arg0, Zero)) + { + Store (One, MSG0) + } + Else + { + Store (Zero, MSG0) + } + } +} + +/** + * Prepare To Sleep. + * + * @param Arg0 Target ACPI S-state + */ +Method (\_PTS, 1, NotSerialized) +{ + /*SLST = Arg0*/ + /* Disable fan, blink power LED. S5 will turn them off too */ + If (Arg0 != 5) + { + FANM = 0 + PLED = 0 + } + + /* Arms SMI for device 12 */ + Store (One, TO12) + /* Put out a POST code */ + P80 = 0xF0 | Arg0 +} + +/** + * System wake. + * + * Returns a 2-DWORD package of: + * Status: Wake status (0 = success, 1 = failure (power), 2 = failure (thermal)) + * PSS: Actual S-state power supply entered if not 0 + * + * @param Arg0 Target ACPI S-state + * @return See description + */ +Method (\_WAK, 1, NotSerialized) +{ + /* Re-enable fan, stop power led blinking */ + FANM = 1 + PLED = 1 + /* wake OK */ + Return(Package(0x02){0x00, 0x00}) +} + diff --git a/src/mainboard/asus/p2b/variants/p3b-f/suspend.asl b/src/mainboard/asus/p2b/variants/p3b-f/suspend.asl new file mode 100644 index 0000000..a84c700 --- /dev/null +++ b/src/mainboard/asus/p2b/variants/p3b-f/suspend.asl @@ -0,0 +1,309 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include "southbridge/intel/i82371eb/i82371eb.h" + +/* ASUS P3B-F board specific (top level) DSDT declarations */ + +Name (PRW1, Package (0x04) +{ + Package (0x02) {0x09, 0x01}, + Package (0x02) {0x08, 0x01}, + Package (0x02) {0x0A, 0x01}, + Package (0x02) {0x0B, 0x01} +}) + +Name (PRW3, Package (0x04) +{ + Package (0x02) { 0x09, 0x03 }, + Package (0x02) { 0x08, 0x03 }, + Package (0x02) { 0x0A, 0x03 }, + Package (0x02) { 0x0B, 0x04 } +}) + +Name (PRWT, Package (0x04) +{ + 0x09, + 0x08, + 0x0A, + 0x0B +}) + +/* SPRW(n) = (SUS3==0) ? PRW1[n] : PRW3[n] */ +Method (SPRW, 1, NotSerialized) +{ + Store (Match (PRWT, MEQ, Arg0, MTR, 0x00, 0x00), Local0) + If (LEqual (SUS3, Zero)) + { + Return (DerefOf (Index (PRW1, Local0))) + } + Else + { + Return (DerefOf (Index (PRW3, Local0))) + } +} + +/* + * SMBus driver functions + * + * These functions communicate with the AS99127F ASIC on the P3B-F to handle hardware + * sequencing required around S3 suspend and resume. This chip is undocumented except it has + * W83781D-compatible hardware monitoring features, and seems to be responsible for hiding the + * flashchip from internal programming via flashrom. + * + * Note: The SMBus host controller interface is located in the southbridge. + */ + /* The SMBus controller hardware interface. Only byte accesses covered. */ + OperationRegion (SM00, SystemIO, SMBUS_IO_BASE, 7) + Field (SM00, ByteAcc, NoLock, Preserve) + { + HSTS, 8, + Offset (0x02), + CTLR, 8, + CMDR, 8, + ADDR, 8, + DAT0, 8, + DAT1, 8 + } + /* Wait for SMBus activity to complete, error or not */ + Method (SWFS, 0, NotSerialized) + { + And (HSTS, 0x06, Local0) + While (Local0 == 0) + { + Stall (1) + And (HSTS, 0x06, Local0) + } + } + + /** + * Writes a byte to a SMBus device. + * + * @param Arg0 SMBus device ID << 1 + * @param Arg1 Command (register index in our case) + * @param Arg2 Data + */ + Method (WBYT, 3, NotSerialized) + { + Store (Arg0, ADDR) + Store (Arg1, CMDR) + Store (Arg2, DAT0) + Store (0xFF, HSTS) + Store (0x48, CTLR) /* Start a byte data R/W access */ + SWFS () + } + + /** + * Reads a byte from a SMBus device. + * + * @param Arg0 SMBus device ID << 1 + * @param Arg1 Command (register index in our case) + * @return Data read + */ + Method (RBYT, 2, NotSerialized) + { + Or (Arg0, 0x01, ADDR) /* Set bit 0, this will be a read */ + Store (Arg1, CMDR) + Store (0xFF, HSTS) + Store (0x48, CTLR) /* Start a byte data R/W access */ + + /* If interrupted without success, restart and try again */ + And (HSTS, 0x02, Local0) + While (LEqual (Local0, Zero)) + { + Store (0xFF, HSTS) + Store (0x48, CTLR) + SWFS () + And (HSTS, 0x02, Local0) + } + + Return (DAT0) /* \DAT0 */ + } + + Method (SGOH, 2, NotSerialized) + { + /* SMBus address 0x48 */ + Store (0x90, Local0) + Store (RBYT (Local0, Arg0), Local1) + Or (Local1, Arg1, Local1) + WBYT (Local0, Arg0, Local1) + } + + Method (SGOL, 2, NotSerialized) + { + Store (0x90, Local0) + Store (RBYT (Local0, Arg0), Local1) + Not (Arg1, Local2) + And (Local1, Local2, Local1) + WBYT (Local0, Arg0, Local1) + } + + Method (FANC, 1, NotSerialized) + { + /* SMBus address 0x2d */ + WBYT (0x5A, 0x59, Arg0) + } + + Method (FANP, 1, NotSerialized) + { + WBYT (0x5A, 0x5A, Arg0) + } + + Method (EN18, 0, NotSerialized) + { + Store (0x5A, Local0) + Store (RBYT (Local0, 0x5F), Local1) + And (Local1, 0xDF, Local1) + WBYT (Local0, 0x5F, Local1) + } + + Method (DS18, 0, NotSerialized) + { + Store (0x5A, Local0) + Store (RBYT (Local0, 0x5F), Local1) + Or (Local1, 0x20, Local1) + WBYT (Local0, 0x5F, Local1) + } + +/** + * Prepare To Sleep, + * + * @param Arg0 Target ACPI S-state + */ + Method (\_PTS, 1, NotSerialized) + { + SLST = Arg0 + If (Arg0 == 0x01) + { + /* Disable BX.PMCR[CRst_En] */ + Store (\_SB.PCI0.NB.PMCR, Local0) + And (Local0, 0xFE, \_SB.PCI0.NB.PMCR) + + /* Isolate CPU_STP# and SUS_STAT1# signals at GENCFG register */ + Store (\_SB.PCI0.PX40.FXS1, Local0) + Or (Local0, 0x24, Local1) + Store (Local1, \_SB.PCI0.PX40.FXS1) + + \_SB.PCI0.ENTER_CONFIG_MODE (0x0A) + /* In SIO Dev A CR E4 = xxxx01xx (these bits are reserved per datasheet?) */ + And (\_SB.PCI0.KBWK, 0xF7, Local0) + Or (Local0, 0x04, \_SB.PCI0.KBWK) + \_SB.PCI0.EXIT_CONFIG_MODE () + } + + If (Arg0 == 0x03) + { + SGOH (0x83, 0x04) + SGOL (0x80, 0x04) + SGOH (0x80, 0x04) + SGOH (0x83, 0x01) + EN18 () + } + + /* Arms SMI for device 12 */ + TO12 = 1 + /* Put out a POST code */ + P80 = 0xF0 | Arg0 + } + +/** + * System wake. + * + * Returns a 2-DWORD package of: + * Status: Wake status (0 = success, 1 = failure (power), 2 = failure (thermal)) + * PSS: Actual S-state power supply entered if not 0 + * + * @param Arg0 Target ACPI S-state + * @return See description + */ + Method (\_WAK, 1, NotSerialized) // _WAK: Wake + { + DS18 () + Store (Zero, TO12) + /* Restore CPU_STP# and SUS_STAT1# signals */ + Store (\_SB.PCI0.PX40.FXS1, Local0) + And (Local0, 0xDB, \_SB.PCI0.PX40.FXS1) + SGOL (0x83, 0x01) + \_SB.PCI0.ENTER_CONFIG_MODE (0x0A) + And (\_SB.PCI0.MSWK, 0xFD, Local1) + Store (Local1, \_SB.PCI0.MSWK) + /* In SIO Dev A CR E4 = xxxx00xx */ + And (\_SB.PCI0.KBWK, 0xF3, Local0) + Store (Local0, \_SB.PCI0.KBWK) + \_SB.PCI0.EXIT_CONFIG_MODE () + /* Put out a POST code */ + P80 = 0xFF + Return(Package(0x02){0x00, 0x00}) + } + + Scope (\_GPE) + { + Method (_L0A, 0, NotSerialized) // _Lxx: Level-Triggered GPE + { + Notify (\_SB.PCI0.SER2, 0x02) // Device Wake + Notify (\_SB.PCI0.SER3, 0x02) // Device Wake + } + + Method (_L09, 0, NotSerialized) // _Lxx: Level-Triggered GPE + { + Notify (\_SB.PCI0, 0x02) // Device Wake + } + } + +Scope (\_SI) +{ + /** + * ACPI message indicator + * + * @param Arg0 Number of waiting messages + */ + Method (_MSG, 1, NotSerialized) + { + If (LEqual (Arg0, Zero)) + { + SGOL (0x81, 0x02) + SGOH (0x81, 0x01) + SGOL (0x81, 0x01) + } + Else + { + SGOH (0x81, 0x02) + SGOL (0x81, 0x02) + } + } + + + /** + * System Status. OS calls to set system status indicator. + * Arg0: + * 0 = Indicator off + * 1 = Working + * 2 = Waking + * 3 = Sleeping: States S1, S2, S3 + * 4 = Sleeping with context saved to non-volatile storage. + * + * @param Arg0 System status indicator + */ + Method (_SST, 1, NotSerialized) // _SST: System Status + { + If (LEqual (Arg0, 0x00)) + { + SGOH (0x80, 0x40) + } + ElseIf (LEqual (Arg0, 0x03)) + { + SGOL (0x80, 0x40) + SGOL (0x80, 0x80) + FANC (0x81) + FANP (0x81) + } + Else + { + SGOL (0x80, 0x40) + SGOH (0x80, 0x80) + FANC (0x8F) + FANP (0x8F) + } + } +} + -- To view, visit https://review.coreboot.org/c/coreboot/+/41098 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3736532df0efde4399fb36eb19df8db511fac6ea Gerrit-Change-Number: 41098 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-MessageType: newchange

5 23

Change in coreboot[master]: bootsplash: Allow bootsplash compression
by Michał Żygowski (Code Review) 10 Aug '23

10 Aug '23

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42806 ) Change subject: bootsplash: Allow bootsplash compression ...................................................................... bootsplash: Allow bootsplash compression TEST=include BMP bootsplash and select the compression, boot Protectli FW6 with SeaBIOS and observe the bootsplash on the screen Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Id9abc6f72e3f82ce60cd06376cdc4f49f0198823 --- M Makefile.inc M src/Kconfig 2 files changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/42806/1 diff --git a/Makefile.inc b/Makefile.inc index 7f61a5e..af931f7 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -1218,9 +1218,16 @@ revision-type := raw BOOTSPLASH_SUFFIX=$(suffix $(call strip_quotes,$(CONFIG_BOOTSPLASH_FILE))) +ifeq ($(CONFIG_COMPRESS_BOOTSPLASH),) cbfs-files-$(CONFIG_BOOTSPLASH_IMAGE) += bootsplash$(BOOTSPLASH_SUFFIX) bootsplash$(BOOTSPLASH_SUFFIX)-file := $(call strip_quotes,$(CONFIG_BOOTSPLASH_FILE)) bootsplash$(BOOTSPLASH_SUFFIX)-type := bootsplash +else +cbfs-files-$(CONFIG_BOOTSPLASH_IMAGE) += bootsplash$(BOOTSPLASH_SUFFIX).lzma +bootsplash$(BOOTSPLASH_SUFFIX).lzma-file := $(call strip_quotes,$(CONFIG_BOOTSPLASH_FILE)) +bootsplash$(BOOTSPLASH_SUFFIX).lzma-compression := $(CBFS_COMPRESS_FLAG) +bootsplash$(BOOTSPLASH_SUFFIX).lzma-type := bootsplash +endif # Ensure that no payload segment overlaps with memory regions used by ramstage # (not for x86 since it can relocate itself in that case) diff --git a/src/Kconfig b/src/Kconfig index 1b49e2b..ec3a274 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -315,6 +315,15 @@ This will only add the image to the ROM. To actually run it check options under 'Display' section. +config COMPRESS_BOOTSPLASH + bool "Compress bootsplash image" + depends on PAYLOAD_SEABIOS + help + The bootsplash image can be compressed with LZMA. This is especially + useful when BMP bootsplash is used and occupies too much SPI flash + space. The bootsplash CBFS file name will be compressed and suffixed + with lzma extension to indicate SeaBIOS to decompress it when loaded. + config BOOTSPLASH_FILE string "Bootsplash path and filename" depends on BOOTSPLASH_IMAGE -- To view, visit https://review.coreboot.org/c/coreboot/+/42806 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9abc6f72e3f82ce60cd06376cdc4f49f0198823 Gerrit-Change-Number: 42806 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: soc/intel/common/block/cpu/car: Enable caching before FSP-T
by Gaggery Tsai (Code Review) 07 Aug '23

07 Aug '23

Gaggery Tsai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38252 ) Change subject: soc/intel/common/block/cpu/car: Enable caching before FSP-T ...................................................................... soc/intel/common/block/cpu/car: Enable caching before FSP-T This patch is required for Boot Guard enabled platform. Enable caching before entering FSP-T. TEST=Stitch boot guard ACM with signed KM and BPM && Enable FSP-T and boot all the way to the OS && Read MSR 0x13a and esnure boot guard verified boot and measured boot are enabled. Change-Id: Ie1def754f7b0024725638fcea481fd3273ef3d24 --- M src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/38252/1 diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S index 091fc4a..fd22903 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S @@ -35,6 +35,12 @@ cache_as_ram: post_code(0x21) + /* Enable caching */ + mov %cr0, %eax + and $~(CR0_CD | CR0_NW), %eax + invd + mov %eax, %cr0 + /* find fsp in cbfs */ lea fsp_name, %esi mov $1f, %esp -- To view, visit https://review.coreboot.org/c/coreboot/+/38252 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie1def754f7b0024725638fcea481fd3273ef3d24 Gerrit-Change-Number: 38252 Gerrit-PatchSet: 1 Gerrit-Owner: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-MessageType: newchange

12 29

Change in ...coreboot[master]: mb/*/romstage: Drop defines already set by raminit code
by Patrick Rudolph (Code Review) 07 Aug '23

07 Aug '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32070 Change subject: mb/*/romstage: Drop defines already set by raminit code ...................................................................... mb/*/romstage: Drop defines already set by raminit code Drop defines that are set by raminit code. Change-Id: Ica844a70b50486b4db3744cb123b3e4b8d5bedb0 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/asrock/h81m-hds/romstage.c M src/mainboard/google/beltino/romstage.c M src/mainboard/google/butterfly/romstage.c M src/mainboard/google/link/romstage.c M src/mainboard/google/parrot/romstage.c M src/mainboard/google/slippy/variants/falco/romstage.c M src/mainboard/google/slippy/variants/leon/romstage.c M src/mainboard/google/slippy/variants/peppy/romstage.c M src/mainboard/google/slippy/variants/wolf/romstage.c M src/mainboard/google/stout/romstage.c M src/mainboard/intel/dcp847ske/romstage.c M src/mainboard/intel/emeraldlake2/romstage.c M src/mainboard/kontron/ktqm77/romstage.c M src/mainboard/lenovo/x220/romstage.c M src/mainboard/roda/rv11/variants/rv11/romstage.c M src/mainboard/roda/rv11/variants/rw11/romstage.c M src/mainboard/samsung/lumpy/romstage.c M src/mainboard/samsung/stumpy/romstage.c M src/mainboard/supermicro/x10slm-f/romstage.c 19 files changed, 0 insertions(+), 265 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/32070/1 diff --git a/src/mainboard/asrock/h81m-hds/romstage.c b/src/mainboard/asrock/h81m-hds/romstage.c index a917722..68ed658 100644 --- a/src/mainboard/asrock/h81m-hds/romstage.c +++ b/src/mainboard/asrock/h81m-hds/romstage.c @@ -74,20 +74,6 @@ { struct pei_data pei_data = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = HPET_ADDR, - .rcba = (uintptr_t)DEFAULT_RCBA, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .temp_mmio_base = 0xfed08000, - .system_type = 1, /* desktop/server */ - .tseg_size = CONFIG_SMM_TSEG_SIZE, .spd_addresses = { 0xa0, 0x00, 0xa4, 0x00 }, .ec_present = 0, .dimm_channel0_disabled = 2, /* Disable DIMM 1 on channel 0. */ diff --git a/src/mainboard/google/beltino/romstage.c b/src/mainboard/google/beltino/romstage.c index 70a8c19..6417f0d 100644 --- a/src/mainboard/google/beltino/romstage.c +++ b/src/mainboard/google/beltino/romstage.c @@ -71,20 +71,6 @@ { struct pei_data pei_data = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = HPET_ADDR, - .rcba = (uintptr_t)DEFAULT_RCBA, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .temp_mmio_base = 0xfed08000, - .system_type = 5, /* ULT */ - .tseg_size = CONFIG_SMM_TSEG_SIZE, .spd_addresses = { 0xa0, 0x00, 0xa4, 0x00 }, .ec_present = 0, // 0 = leave channel enabled diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c index d34b1e4..cbd9f3d 100644 --- a/src/mainboard/google/butterfly/romstage.c +++ b/src/mainboard/google/butterfly/romstage.c @@ -132,20 +132,6 @@ { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .thermalbase = 0xfed08000, - .system_type = 0, // 0 Mobile, 1 Desktop/Server - .tseg_size = CONFIG_SMM_TSEG_SIZE, .spd_addresses = { 0xA0, 0x00,0xA4,0x00 }, .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, .ec_present = 1, diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index 66a503d0..6617dc4 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -127,20 +127,6 @@ { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .thermalbase = 0xfed08000, - .system_type = 0, // 0 Mobile, 1 Desktop/Server - .tseg_size = CONFIG_SMM_TSEG_SIZE, .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, .ec_present = 1, .ddr3lv_support = 1, diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c index 76a4b4b..d76d814 100644 --- a/src/mainboard/google/parrot/romstage.c +++ b/src/mainboard/google/parrot/romstage.c @@ -101,20 +101,6 @@ { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .thermalbase = 0xfed08000, - .system_type = 0, // 0 Mobile, 1 Desktop/Server - .tseg_size = CONFIG_SMM_TSEG_SIZE, .spd_addresses = { 0xA0, 0x00,0xA4,0x00 }, .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, .ec_present = 1, diff --git a/src/mainboard/google/slippy/variants/falco/romstage.c b/src/mainboard/google/slippy/variants/falco/romstage.c index 25f8d27..2244119 100644 --- a/src/mainboard/google/slippy/variants/falco/romstage.c +++ b/src/mainboard/google/slippy/variants/falco/romstage.c @@ -109,20 +109,6 @@ { struct pei_data pei_data = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = HPET_ADDR, - .rcba = (uintptr_t)DEFAULT_RCBA, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .temp_mmio_base = 0xfed08000, - .system_type = 5, /* ULT */ - .tseg_size = CONFIG_SMM_TSEG_SIZE, .spd_addresses = { 0xff, 0x00, 0xff, 0x00 }, .ec_present = 1, // 0 = leave channel enabled diff --git a/src/mainboard/google/slippy/variants/leon/romstage.c b/src/mainboard/google/slippy/variants/leon/romstage.c index b95c6e1..35345d0 100644 --- a/src/mainboard/google/slippy/variants/leon/romstage.c +++ b/src/mainboard/google/slippy/variants/leon/romstage.c @@ -106,20 +106,6 @@ { struct pei_data pei_data = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = HPET_ADDR, - .rcba = (uintptr_t)DEFAULT_RCBA, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .temp_mmio_base = 0xfed08000, - .system_type = 5, /* ULT */ - .tseg_size = CONFIG_SMM_TSEG_SIZE, .spd_addresses = { 0xff, 0x00, 0xff, 0x00 }, .ec_present = 1, // 0 = leave channel enabled diff --git a/src/mainboard/google/slippy/variants/peppy/romstage.c b/src/mainboard/google/slippy/variants/peppy/romstage.c index e47edc7..a5de6c0 100644 --- a/src/mainboard/google/slippy/variants/peppy/romstage.c +++ b/src/mainboard/google/slippy/variants/peppy/romstage.c @@ -124,20 +124,6 @@ { struct pei_data pei_data = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = HPET_ADDR, - .rcba = (uintptr_t)DEFAULT_RCBA, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .temp_mmio_base = 0xfed08000, - .system_type = 5, /* ULT */ - .tseg_size = CONFIG_SMM_TSEG_SIZE, .spd_addresses = { 0xff, 0x00, 0xff, 0x00 }, .ec_present = 1, // 0 = leave channel enabled diff --git a/src/mainboard/google/slippy/variants/wolf/romstage.c b/src/mainboard/google/slippy/variants/wolf/romstage.c index 3125efe..5a8c972 100644 --- a/src/mainboard/google/slippy/variants/wolf/romstage.c +++ b/src/mainboard/google/slippy/variants/wolf/romstage.c @@ -111,20 +111,7 @@ { struct pei_data pei_data = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = HPET_ADDR, - .rcba = (uintptr_t)DEFAULT_RCBA, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .temp_mmio_base = 0xfed08000, .system_type = 5, /* ULT */ - .tseg_size = CONFIG_SMM_TSEG_SIZE, .spd_addresses = { 0xff, 0x00, 0xff, 0x00 }, .ec_present = 1, // 0 = leave channel enabled diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c index 7539dd7..6e32145 100644 --- a/src/mainboard/google/stout/romstage.c +++ b/src/mainboard/google/stout/romstage.c @@ -137,20 +137,6 @@ { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .thermalbase = 0xfed08000, - .system_type = 0, // 0 Mobile, 1 Desktop/Server - .tseg_size = CONFIG_SMM_TSEG_SIZE, .spd_addresses = { 0xA0, 0x00,0xA4,0x00 }, .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, .ec_present = 1, diff --git a/src/mainboard/intel/dcp847ske/romstage.c b/src/mainboard/intel/dcp847ske/romstage.c index 24ec912..2043cf6 100644 --- a/src/mainboard/intel/dcp847ske/romstage.c +++ b/src/mainboard/intel/dcp847ske/romstage.c @@ -29,20 +29,6 @@ { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .thermalbase = 0xfed08000, - .system_type = 0, // 0 Mobile, 1 Desktop/Server - .tseg_size = CONFIG_SMM_TSEG_SIZE, .spd_addresses = { 0xa0, 0x00, 0xa2, 0x00 }, .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, .ec_present = 0, diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index 9a9fc24..8cd7ec2 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -94,20 +94,6 @@ { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .thermalbase = 0xfed08000, - .system_type = 0, // 0 Mobile, 1 Desktop/Server - .tseg_size = CONFIG_SMM_TSEG_SIZE, .spd_addresses = { 0xa0, 0x00, 0xa4, 0x00 }, .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, .ec_present = 0, diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c index f778f96..e0f8954 100644 --- a/src/mainboard/kontron/ktqm77/romstage.c +++ b/src/mainboard/kontron/ktqm77/romstage.c @@ -80,20 +80,6 @@ { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .thermalbase = 0xfed08000, - .system_type = 0, /* 0 Mobile, 1 Desktop/Server */ - .tseg_size = CONFIG_SMM_TSEG_SIZE, .spd_addresses = { 0xA0, 0x00,0xA4,0x00 }, .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, .ec_present = 1, diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/romstage.c index a5b0c81..d398d81 100644 --- a/src/mainboard/lenovo/x220/romstage.c +++ b/src/mainboard/lenovo/x220/romstage.c @@ -50,20 +50,6 @@ { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .thermalbase = 0xfed08000, - .system_type = 0, // 0 Mobile, 1 Desktop/Server - .tseg_size = CONFIG_SMM_TSEG_SIZE, .spd_addresses = { 0xa0, 0x00,0xa2,0x00 }, .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, .ec_present = 1, diff --git a/src/mainboard/roda/rv11/variants/rv11/romstage.c b/src/mainboard/roda/rv11/variants/rv11/romstage.c index 685e942..df679f1 100644 --- a/src/mainboard/roda/rv11/variants/rv11/romstage.c +++ b/src/mainboard/roda/rv11/variants/rv11/romstage.c @@ -37,20 +37,6 @@ { const struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .thermalbase = 0xfed08000, - .system_type = 0, // 0 Mobile, 1 Desktop/Server - .tseg_size = CONFIG_SMM_TSEG_SIZE, .spd_addresses = { 0xA0, 0x00, 0xA4, 0x00 }, .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, .ec_present = 1, diff --git a/src/mainboard/roda/rv11/variants/rw11/romstage.c b/src/mainboard/roda/rv11/variants/rw11/romstage.c index 97d9d2b..56ac32c 100644 --- a/src/mainboard/roda/rv11/variants/rw11/romstage.c +++ b/src/mainboard/roda/rv11/variants/rw11/romstage.c @@ -66,20 +66,6 @@ { const struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .thermalbase = 0xfed08000, - .system_type = 0, // 0 Mobile, 1 Desktop/Server - .tseg_size = CONFIG_SMM_TSEG_SIZE, .spd_addresses = { 0xA0, 0xA2, 0xA4, 0xA6 }, .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, .ec_present = 1, diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index 1080689..29fe08b 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -156,20 +156,6 @@ { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .thermalbase = 0xfed08000, - .system_type = 0, // 0 Mobile, 1 Desktop/Server - .tseg_size = CONFIG_SMM_TSEG_SIZE, .spd_addresses = { 0xa0, 0x00,0x00,0x00 }, .ts_addresses = { 0x30, 0x00, 0x00, 0x00 }, .ec_present = 1, diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index a8e28d6..510efbe 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -144,20 +144,6 @@ { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .thermalbase = 0xfed08000, - .system_type = 0, // 0 Mobile, 1 Desktop/Server - .tseg_size = CONFIG_SMM_TSEG_SIZE, .spd_addresses = { 0xa0, 0x00,0xa4,0x00 }, .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, .ec_present = 0, diff --git a/src/mainboard/supermicro/x10slm-f/romstage.c b/src/mainboard/supermicro/x10slm-f/romstage.c index 84ad047..702e8bb 100644 --- a/src/mainboard/supermicro/x10slm-f/romstage.c +++ b/src/mainboard/supermicro/x10slm-f/romstage.c @@ -66,20 +66,6 @@ { struct pei_data pei_data = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = HPET_ADDR, - .rcba = (uintptr_t)DEFAULT_RCBA, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .temp_mmio_base = 0xfed08000, - .system_type = 1, /* desktop/server */ - .tseg_size = CONFIG_SMM_TSEG_SIZE, .spd_addresses = { 0xa0, 0xa2, 0xa4, 0xa6 }, .ec_present = 0, .ddr_refresh_2x = 1, -- To view, visit https://review.coreboot.org/c/coreboot/+/32070 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica844a70b50486b4db3744cb123b3e4b8d5bedb0 Gerrit-Change-Number: 32070 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

4 13

Change in coreboot[master]: [TESTME]x4x/i82801jx/socket_LGA775: Add x86_64 support
by Patrick Rudolph (Code Review) 07 Aug '23

07 Aug '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36779 ) Change subject: [TESTME]x4x/i82801jx/socket_LGA775: Add x86_64 support ...................................................................... [TESTME]x4x/i82801jx/socket_LGA775: Add x86_64 support Use correct datasize to compile on x86_64. Change-Id: Ib4851932975e99e06ba5650c2359a835b46d702d Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/arch/x86/walkcbfs.S M src/cpu/intel/model_1067x/Kconfig M src/cpu/intel/model_6fx/Kconfig M src/cpu/intel/model_f3x/Kconfig M src/cpu/intel/model_f4x/Kconfig M src/cpu/intel/socket_LGA775/Kconfig M src/cpu/x86/mp_init.c M src/cpu/x86/smm/smm_module_handler.c M src/drivers/net/atl1e.c M src/northbridge/intel/x4x/dq_dqs.c M src/northbridge/intel/x4x/northbridge.c M src/northbridge/intel/x4x/raminit_ddr23.c M src/northbridge/intel/x4x/rcven.c M src/northbridge/intel/x4x/x4x.h M src/southbridge/intel/common/spi.c M src/southbridge/intel/i82801jx/hdaudio.c M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/i82801jx/sata.c 18 files changed, 63 insertions(+), 40 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/36779/1 diff --git a/src/arch/x86/walkcbfs.S b/src/arch/x86/walkcbfs.S index ded6558..01382e4 100644 --- a/src/arch/x86/walkcbfs.S +++ b/src/arch/x86/walkcbfs.S @@ -33,6 +33,7 @@ .section .text .global walkcbfs_asm +.code32 /* * input %esi: filename diff --git a/src/cpu/intel/model_1067x/Kconfig b/src/cpu/intel/model_1067x/Kconfig index 564a428..93604d6 100644 --- a/src/cpu/intel/model_1067x/Kconfig +++ b/src/cpu/intel/model_1067x/Kconfig @@ -1,9 +1,14 @@ config CPU_INTEL_MODEL_1067X bool - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 + select ARCH_BOOTBLOCK_X86_32 if !ARCH_EXP_X86_64 + select ARCH_VERSTAGE_X86_32 if !ARCH_EXP_X86_64 + select ARCH_ROMSTAGE_X86_32 if !ARCH_EXP_X86_64 + select ARCH_RAMSTAGE_X86_32 if !ARCH_EXP_X86_64 + select ARCH_BOOTBLOCK_X86_64 if ARCH_EXP_X86_64 + select ARCH_VERSTAGE_X86_64 if ARCH_EXP_X86_64 + select ARCH_ROMSTAGE_X86_64 if ARCH_EXP_X86_64 + select ARCH_RAMSTAGE_X86_64 if ARCH_EXP_X86_64 + select SMP select SSE2 select UDELAY_TSC diff --git a/src/cpu/intel/model_6fx/Kconfig b/src/cpu/intel/model_6fx/Kconfig index cfd3e7c..8c86226 100644 --- a/src/cpu/intel/model_6fx/Kconfig +++ b/src/cpu/intel/model_6fx/Kconfig @@ -1,9 +1,14 @@ config CPU_INTEL_MODEL_6FX bool - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 + select ARCH_BOOTBLOCK_X86_32 if !ARCH_EXP_X86_64 + select ARCH_VERSTAGE_X86_32 if !ARCH_EXP_X86_64 + select ARCH_ROMSTAGE_X86_32 if !ARCH_EXP_X86_64 + select ARCH_RAMSTAGE_X86_32 if !ARCH_EXP_X86_64 + + select ARCH_BOOTBLOCK_X86_64 if ARCH_EXP_X86_64 + select ARCH_VERSTAGE_X86_64 if ARCH_EXP_X86_64 + select ARCH_ROMSTAGE_X86_64 if ARCH_EXP_X86_64 + select ARCH_RAMSTAGE_X86_64 if ARCH_EXP_X86_64 select SMP select SSE2 select UDELAY_TSC diff --git a/src/cpu/intel/model_f3x/Kconfig b/src/cpu/intel/model_f3x/Kconfig index 9a5e2a1..ae67337 100644 --- a/src/cpu/intel/model_f3x/Kconfig +++ b/src/cpu/intel/model_f3x/Kconfig @@ -1,9 +1,14 @@ config CPU_INTEL_MODEL_F3X bool - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 + select ARCH_BOOTBLOCK_X86_32 if !ARCH_EXP_X86_64 + select ARCH_VERSTAGE_X86_32 if !ARCH_EXP_X86_64 + select ARCH_ROMSTAGE_X86_32 if !ARCH_EXP_X86_64 + select ARCH_RAMSTAGE_X86_32 if !ARCH_EXP_X86_64 + + select ARCH_BOOTBLOCK_X86_64 if ARCH_EXP_X86_64 + select ARCH_VERSTAGE_X86_64 if ARCH_EXP_X86_64 + select ARCH_ROMSTAGE_X86_64 if ARCH_EXP_X86_64 + select ARCH_RAMSTAGE_X86_64 if ARCH_EXP_X86_64 select SMP select SUPPORT_CPU_UCODE_IN_CBFS select CPU_INTEL_COMMON diff --git a/src/cpu/intel/model_f4x/Kconfig b/src/cpu/intel/model_f4x/Kconfig index 4ef60b5..84c6863 100644 --- a/src/cpu/intel/model_f4x/Kconfig +++ b/src/cpu/intel/model_f4x/Kconfig @@ -1,8 +1,12 @@ config CPU_INTEL_MODEL_F4X bool - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 + select ARCH_BOOTBLOCK_X86_32 if !ARCH_EXP_X86_64 + select ARCH_VERSTAGE_X86_32 if !ARCH_EXP_X86_64 + select ARCH_ROMSTAGE_X86_32 if !ARCH_EXP_X86_64 + select ARCH_RAMSTAGE_X86_32 if !ARCH_EXP_X86_64 + select ARCH_BOOTBLOCK_X86_64 if ARCH_EXP_X86_64 + select ARCH_VERSTAGE_X86_64 if ARCH_EXP_X86_64 + select ARCH_ROMSTAGE_X86_64 if ARCH_EXP_X86_64 + select ARCH_RAMSTAGE_X86_64 if ARCH_EXP_X86_64 select SMP select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/socket_LGA775/Kconfig b/src/cpu/intel/socket_LGA775/Kconfig index 8b227bd..8f60d2c 100644 --- a/src/cpu/intel/socket_LGA775/Kconfig +++ b/src/cpu/intel/socket_LGA775/Kconfig @@ -3,6 +3,10 @@ if CPU_INTEL_SOCKET_LGA775 +config ARCH_EXP_X86_64 + bool "Enable experimental 64bit support" + default n + config SOCKET_SPECIFIC_OPTIONS # dummy def_bool y select CPU_INTEL_MODEL_6FX diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 29ae3de..ea70453 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -122,7 +122,7 @@ /* The SIPI vector is loaded at the SMM_DEFAULT_BASE. The reason is at the * memory range is already reserved so the OS cannot use it. That region is * free to use for AP bringup before SMM is initialized. */ -static const uint32_t sipi_vector_location = SMM_DEFAULT_BASE; +static const uintptr_t sipi_vector_location = SMM_DEFAULT_BASE; static const int sipi_vector_location_size = SMM_DEFAULT_SIZE; struct mp_flight_plan { @@ -348,16 +348,16 @@ setup_default_sipi_vector_params(sp); /* Setup MSR table. */ - sp->msr_table_ptr = (uint32_t)&mod_loc[module_size]; + sp->msr_table_ptr = (uintptr_t)&mod_loc[module_size]; sp->msr_count = num_msrs; /* Provide pointer to microcode patch. */ - sp->microcode_ptr = (uint32_t)mp_params->microcode_pointer; + sp->microcode_ptr = (uintptr_t)mp_params->microcode_pointer; /* Pass on abiility to load microcode in parallel. */ if (mp_params->parallel_microcode_load) sp->microcode_lock = 0; else sp->microcode_lock = ~0; - sp->c_handler = (uint32_t)&ap_init; + sp->c_handler = (uintptr_t)&ap_init; ap_count = &sp->ap_count; atomic_set(ap_count, 0); diff --git a/src/cpu/x86/smm/smm_module_handler.c b/src/cpu/x86/smm/smm_module_handler.c index bd4d48c..82ad37d 100644 --- a/src/cpu/x86/smm/smm_module_handler.c +++ b/src/cpu/x86/smm/smm_module_handler.c @@ -107,7 +107,7 @@ /* This function assumes all save states start at top of default * SMRAM size space and are staggered down by save state size. */ - base = (void *)smm_runtime->smbase; + base = (void *)(uintptr_t)smm_runtime->smbase; base += SMM_DEFAULT_SIZE; base -= (cpu + 1) * smm_runtime->save_state_size; diff --git a/src/drivers/net/atl1e.c b/src/drivers/net/atl1e.c index 51470b0..d68ea0d 100644 --- a/src/drivers/net/atl1e.c +++ b/src/drivers/net/atl1e.c @@ -86,7 +86,7 @@ } } -static void program_mac_address(u32 mem_base) +static void program_mac_address(uintptr_t mem_base) { u8 macstrbuf[MACLEN] = { 0 }; /* Default MAC Address of 90:e6:ba:24:f9:d2 */ @@ -110,7 +110,7 @@ printk(BIOS_DEBUG, "done\n"); } -static int atl1e_eeprom_exist(u32 mem_base) +static int atl1e_eeprom_exist(uintptr_t mem_base) { u32 value = read32((void *)mem_base + REG_SPI_FLASH_CTRL); if (value & SPI_FLASH_CTRL_EN_VPD) { diff --git a/src/northbridge/intel/x4x/dq_dqs.c b/src/northbridge/intel/x4x/dq_dqs.c index ed372b5..080262e 100644 --- a/src/northbridge/intel/x4x/dq_dqs.c +++ b/src/northbridge/intel/x4x/dq_dqs.c @@ -178,7 +178,7 @@ static u8 test_dq_aligned(const struct sysinfo *s, const u8 channel) { - u32 address; + uintptr_t address; int rank, lane; u8 count, count1; u8 data[8]; @@ -374,7 +374,7 @@ { int i, rank, lane; volatile u8 data[8]; - u32 address; + uintptr_t address; u8 bytelane_error = 0; FOR_EACH_POPULATED_RANK_IN_CHANNEL(s->dimms, channel, rank) { @@ -453,7 +453,8 @@ int do_read_training(struct sysinfo *s) { int loop, channel, i, lane, rank; - u32 address, content; + uintptr_t address; + u32 content; u8 dqs_lower[TOTAL_BYTELANES]; u8 dqs_upper[TOTAL_BYTELANES]; struct rt_dqs_setting dqs_setting[TOTAL_BYTELANES]; @@ -643,7 +644,7 @@ static void sample_dq(const struct sysinfo *s, u8 channel, u8 rank, u8 high_found[8]) { - u32 address = test_address(channel, rank); + uintptr_t address = test_address(channel, rank); int samples, lane; memset(high_found, 0, TOTAL_BYTELANES * sizeof(high_found[0])); diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index 39f24d3..592a2e0 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -89,7 +89,7 @@ /* cbmem_top can be shifted downwards due to alignment. Mark the region between cbmem_top and tomk as unusable */ - delta_cbmem = tomk - ((uint32_t)cbmem_top() >> 10); + delta_cbmem = tomk - ((uintptr_t)cbmem_top() >> 10); tomk -= delta_cbmem; uma_sizek += delta_cbmem; diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c index efdcbb6..31e94f4 100644 --- a/src/northbridge/intel/x4x/raminit_ddr23.c +++ b/src/northbridge/intel/x4x/raminit_ddr23.c @@ -1316,7 +1316,7 @@ void send_jedec_cmd(const struct sysinfo *s, u8 r, u8 ch, u8 cmd, u32 val) { - u32 addr = test_address(ch, r); + uintptr_t addr = test_address(ch, r); u8 data8 = cmd; u32 data32; @@ -2160,7 +2160,7 @@ if (s->boot_path == BOOT_PATH_NORMAL) { FOR_EACH_POPULATED_RANK(s->dimms, ch, r) { for (bank = 0; bank < 4; bank++) - read32((u32 *)(test_address(ch, r) | 0x800000 | (bank << 12))); + read32((u32 *)((uintptr_t)test_address(ch, r) | 0x800000 | (bank << 12))); } } printk(BIOS_DEBUG, "Done dummy reads\n"); diff --git a/src/northbridge/intel/x4x/rcven.c b/src/northbridge/intel/x4x/rcven.c index 36a6ebd..c41bb07 100644 --- a/src/northbridge/intel/x4x/rcven.c +++ b/src/northbridge/intel/x4x/rcven.c @@ -39,7 +39,7 @@ asm volatile("mfence":::); } -static u8 sampledqs(u32 addr, u8 lane, u8 channel) +static u8 sampledqs(uintptr_t addr, u8 lane, u8 channel) { u32 sample_offset = 0x400 * channel + 0x561 + lane * 4; diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index 76d94c6..4809ee7 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -84,9 +84,9 @@ * MCHBAR */ -#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x)))) +#define MCHBAR8(x) (*((volatile u8 *)((uintptr_t)DEFAULT_MCHBAR + (x)))) +#define MCHBAR16(x) (*((volatile u16 *)((uintptr_t)DEFAULT_MCHBAR + (x)))) +#define MCHBAR32(x) (*((volatile u32 *)((uintptr_t)DEFAULT_MCHBAR + (x)))) #define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) #define MCHBAR8_OR(x, or) (MCHBAR8(x) = MCHBAR8(x) | (or)) #define MCHBAR8_AND_OR(x, and, or) \ diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index a84a0df..a9c8863 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -275,7 +275,7 @@ { struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); uint8_t *rcrb; /* Root Complex Register Block */ - uint32_t rcba; /* Root Complex Base Address */ + uintptr_t rcba; /* Root Complex Base Address */ uint8_t bios_cntl; struct ich9_spi_regs *ich9_spi; struct ich7_spi_regs *ich7_spi; diff --git a/src/southbridge/intel/i82801jx/hdaudio.c b/src/southbridge/intel/i82801jx/hdaudio.c index 0628c43..2273e6c 100644 --- a/src/southbridge/intel/i82801jx/hdaudio.c +++ b/src/southbridge/intel/i82801jx/hdaudio.c @@ -276,10 +276,8 @@ if (!res) return; - // NOTE this will break as soon as the Azalia get's a bar above - // 4G. Is there anything we can do about it? base = res2mmio(res, 0, 0); - printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base); + printk(BIOS_DEBUG, "Azalia: base = %p\n", base); codec_mask = codec_detect(base); if (codec_mask) { diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index a395069..412e97f 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -669,7 +669,7 @@ /* Add it to SSDT. */ acpigen_write_scope("\\"); - acpigen_write_name_dword("NVSA", (u32) gnvs); + acpigen_write_name_dword("NVSA", (u32)(uintptr_t) gnvs); acpigen_pop_len(); } } diff --git a/src/southbridge/intel/i82801jx/sata.c b/src/southbridge/intel/i82801jx/sata.c index e6e08a3..70c5e69 100644 --- a/src/southbridge/intel/i82801jx/sata.c +++ b/src/southbridge/intel/i82801jx/sata.c @@ -37,7 +37,7 @@ u32 reg32; /* Initialize AHCI memory-mapped space */ - u8 *abar = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5); + u8 *abar = (u8 *)(uintptr_t)pci_read_config32(dev, PCI_BASE_ADDRESS_5); printk(BIOS_DEBUG, "ABAR: %p\n", abar); /* Set AHCI access mode. -- To view, visit https://review.coreboot.org/c/coreboot/+/36779 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4851932975e99e06ba5650c2359a835b46d702d Gerrit-Change-Number: 36779 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

5 15

Change in coreboot[master]: soc/intel/common/block: Update microcode for each core
by Patrick Rudolph (Code Review) 07 Aug '23

07 Aug '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35739 ) Change subject: soc/intel/common/block: Update microcode for each core ...................................................................... soc/intel/common/block: Update microcode for each core On Hyper-Threading enabled platform update the microcde only once for each core, not for each thread. Follow Intel Software Developer Guidelines as the added comment also states. Change-Id: I72804753e567a137a5648ca6950009fed332531b Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/common/block/cpu/mp_init.c 1 file changed, 20 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/35739/1 diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index 2c5061f..e7689cf 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -26,6 +26,7 @@ #include <intelblocks/fast_spi.h> #include <intelblocks/mp_init.h> #include <intelblocks/msr.h> +#include <cpu/intel/common/common.h> #include <soc/cpu.h> static const void *microcode_patch; @@ -44,7 +45,24 @@ static void init_one_cpu(struct device *dev) { soc_core_init(dev); - intel_microcode_load_unlocked(microcode_patch); + + /* + * Update just on the first CPU in the core. Other siblings + * get the update automatically according to Document: 253668-060US + * Intel SDM Chapter 9.11.6.3 + * "Update in a System Supporting Intel Hyper-Threading Technology" + * Intel Hyper-Threading Technology has implications on the loading of the + * microcode update. The update must be loaded for each core in a physical + * processor. Thus, for a processor supporting Intel Hyper-Threading + * Technology, only one logical processor per core is required to load the + * microcode update. Each individual logical processor can independently + * load the update. However, MP initialization must provide some mechanism + * (e.g. a software semaphore) to force serialization of microcode update + * loads and to prevent simultaneous load attempts to the same core. + */ + if (!intel_ht_sibling()) { + intel_microcode_load_unlocked(microcode_patch); + } } static struct device_operations cpu_dev_ops = { @@ -141,6 +159,7 @@ if (CONFIG(USE_INTEL_FSP_MP_INIT)) return; + /* Update microcode on BSP */ microcode_patch = intel_microcode_find(); intel_microcode_load_unlocked(microcode_patch); -- To view, visit https://review.coreboot.org/c/coreboot/+/35739 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72804753e567a137a5648ca6950009fed332531b Gerrit-Change-Number: 35739 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

9 52

Change in coreboot[master]: drivers/intel/fsp2_0: Allow including FSPT at specified offset
by Michał Żygowski (Code Review) 07 Aug '23

07 Aug '23

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43398 ) Change subject: drivers/intel/fsp2_0: Allow including FSPT at specified offset ...................................................................... drivers/intel/fsp2_0: Allow including FSPT at specified offset FSPT is executed by assembly code and is not being automatically relocated, thus it must be at specified offset. Add options to specify FSPT location in CBFS and user option to include FSPT. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I997c7465fd7ac56633c3e7e3fa5b95384dcf5ad2 --- M src/drivers/intel/fsp2_0/Kconfig M src/drivers/intel/fsp2_0/Makefile.inc 2 files changed, 11 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/43398/1 diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 3caa04a..5d27f32 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -89,6 +89,14 @@ help The path and filename of the Intel FSP-T binary for this platform. +config FSP_T_CBFS_LOCATION + hex "Intel FSP-T Binary location in CBFS" + default 0xfffd1000 + help + Specify the location of FSP-T binary. FSP-T is executed early by + assembly code and is not automatically relocated. The location must + match the binary base address in FSP-T header. + config FSP_M_FILE string "Intel FSP-M (memory init) binary path and filename" if !FSP_USE_REPO depends on ADD_FSP_BINARIES @@ -104,7 +112,7 @@ The path and filename of the Intel FSP-S binary for this platform. config FSP_CAR - bool + bool "Use FSP to setup temporary memory" default n help Use FSP APIs to initialize & Tear Down the Cache-As-Ram diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index 278036a..a1758ea 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -42,8 +42,9 @@ cbfs-files-$(CONFIG_FSP_CAR) += $(FSP_T_CBFS) $(FSP_T_CBFS)-file := $(call strip_quotes,$(CONFIG_FSP_T_FILE)) $(FSP_T_CBFS)-type := fsp +$(FSP_T_CBFS)-options := -b $(CONFIG_FSP_T_CBFS_LOCATION) ifeq ($(CONFIG_FSP_T_XIP),y) -$(FSP_T_CBFS)-options := --xip $(TXTIBB) $(BTGIBB) +$(FSP_T_CBFS)-options := --xip $(TXTIBB) $(BTGIBB) -b $(CONFIG_FSP_T_CBFS_LOCATION) endif cbfs-files-$(CONFIG_ADD_FSP_BINARIES) += $(FSP_M_CBFS) -- To view, visit https://review.coreboot.org/c/coreboot/+/43398 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I997c7465fd7ac56633c3e7e3fa5b95384dcf5ad2 Gerrit-Change-Number: 43398 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

5 13

Change in coreboot[master]: soc/intel/tigerlake: Remove SW CM PM changes for FW CM
by Shreesh Chhabbi (Code Review) 07 Aug '23

07 Aug '23

Shreesh Chhabbi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42768 ) Change subject: soc/intel/tigerlake: Remove SW CM PM changes for FW CM ...................................................................... soc/intel/tigerlake: Remove SW CM PM changes for FW CM This patch is not to be merged. It is only for cherry-picking to build the image with FW CM configuration. Change-Id: I89db2557e33dc222ae1cb54401c738ded474202b Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> --- M src/soc/intel/tigerlake/acpi/tcss.asl M src/soc/intel/tigerlake/acpi/tcss_dma.asl M src/soc/intel/tigerlake/acpi/tcss_pcierp.asl M src/soc/intel/tigerlake/acpi/tcss_xhci.asl 4 files changed, 220 insertions(+), 219 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/42768/1 diff --git a/src/soc/intel/tigerlake/acpi/tcss.asl b/src/soc/intel/tigerlake/acpi/tcss.asl index 2fda693..48f2689 100644 --- a/src/soc/intel/tigerlake/acpi/tcss.asl +++ b/src/soc/intel/tigerlake/acpi/tcss.asl @@ -29,19 +29,9 @@ #define MAILBOX_BIOS_CMD_TCSS_DEVEN_INTERFACE 0x00000015 #define TCSS_DEVEN_MAILBOX_SUBCMD_GET_STATUS 0 /* Sub-command 0 */ #define TCSS_DEVEN_MAILBOX_SUBCMD_TCSS_CHANGE_REQ 1 /* Sub-command 1 */ + #define TCSS_IOM_ACK_TIMEOUT_IN_MS 100 -#define MCHBAR_TCSS_DEVEN_OFFSET 0x7090 - -#define REVISION_ID 1 -#define UNRECOGNIZED_UUID 0x4 -#define UNRECOGNIZED_REVISION 0x8 - -#define USB_TUNNELING 0x1 -#define DISPLAY_PORT_TUNNELING 0x2 -#define PCIE_TUNNELING 0x4 -#define INTER_DOMAIN_USB4_INTERNET_PROTOCOL 0x8 - Scope (\_SB) { /* Device base address */ @@ -136,46 +126,6 @@ } Return (0) } - - Method (_OSC, 4, Serialized) - { - /* - * Operating System Capabilities for USB4 - * Arg0: UUID = {23A0D13A-26AB-486C-9C5F-0FFA525A575A} - * Arg1: Revision ID = 1 - * Arg2: Count of entries (DWORD) in Arg3 (Integer): 3 - * Arg3: DWORD capabilities buffer: - * First DWORD: The standard definition bits are used to return errors. - * Second DWORD: OSPM support field for USB4, bits [31:0] reserved. - * Third DWORD: OSPM control field for USB4. - * bit 0: USB tunneling - * bit 1: DisplayPort tunneling - * bit 2: PCIe tunneling - * bit 3: Inter-domain USB4 internet protocol - * bit 31:4: reserved - * Return: The platform acknowledges the capabilities buffer by returning - * a buffer of DWORD of the same length. Masked/Cleared bits in the - * control field indicate that the platform does not permit OSPM - * control of the respectively capabilities or features. - */ - Name (CTRL, 0) /* Control field value */ - If (Arg0 == ToUUID("23A0D13A-26AB-486C-9C5F-0FFA525A575A")) { - CreateDWordField(Arg3, 0, CDW1) - CreateDWordField(Arg3, 2, CDW3) - CTRL = CDW3 - - If (Arg1 != REVISION_ID) { - CDW1 |= UNRECOGNIZED_REVISION - } - CTRL |= USB_TUNNELING | DISPLAY_PORT_TUNNELING | PCIE_TUNNELING | - INTER_DOMAIN_USB4_INTERNET_PROTOCOL - CDW3 = CTRL - Return (Arg3) - } Else { - CDW1 |= UNRECOGNIZED_UUID - Return (Arg3) - } - } } Scope (_GPE) @@ -302,25 +252,6 @@ Scope (\_SB.PCI0) { /* - * Operation region defined to access the TCSS_DEVEN. Get the MCHBAR in offset - * 0x48 in B0:D0:F0. TCSS device enable base address is in offset 0x7090 of MCHBAR. - */ - OperationRegion (TDEN, SystemMemory, (GMHB() + MCHBAR_TCSS_DEVEN_OFFSET), 0x4) - Field (TDEN, ByteAcc, NoLock, Preserve) - { - TRE0, 1, /* PCIE0_EN */ - TRE1, 1, /* PCIE1_EN */ - TRE2, 1, /* PCIE2_EN */ - TRE3, 1, /* PCIE3_EN */ - , 4, - THCE, 1, /* XHCI_EN */ - TDCE, 1, /* XDCI_EN */ - DME0, 1, /* TBT_DMA0_EN */ - DME1, 1, /* TBT_DMA1_EN */ - , 20 - } - - /* * Operation region defined to access the IOM REGBAR. Get the MCHBAR in offset * 0x48 in B0:D0:F0. REGBAR Base address is in offset 0x7110 of MCHBAR. */ @@ -493,6 +424,17 @@ } /* + * Below is a variable to store devices connect state for TBT PCIe RP before + * entering D3 cold. + * Value 0 - no device connected before enter D3 cold, no need to send + * CONNECT_TOPOLOGY in D3 cold exit. + * Value 1 - has device connected before enter D3 cold, need to send + * CONNECT_TOPOLOGY in D3 cold exit. + */ + Name (CTP0, 0) /* Variable of device connecet status for TBT0 group. */ + Name (CTP1, 0) /* Variable of device connecet status for TBT1 group. */ + + /* * TBT Group0 ON method */ Method (TG0N, 0) @@ -513,6 +455,28 @@ /* RP1 D3 cold exit. */ \_SB.PCI0.TRP1.D3CX() } + + /* + * Need to send Connect-Topology command when TBT host + * controller back to D0 from D3. + */ + If (\_SB.PCI0.TDM0.ALCT == 1) { + If (CTP0 == 1) { + /* + * Send Connect-Topology command if there is + * device present on PCIe RP. + */ + \_SB.PCI0.TDM0.CNTP() + + /* Indicate to wait Connect-Topology command. */ + \_SB.PCI0.TDM0.WACT = 1 + + /* Clear the connect states. */ + CTP0 = 0 + } + /* Disallow to send Connect-Topology command. */ + \_SB.PCI0.TDM0.ALCT = 0 + } } Else { Printf("Drop TG0N due to it is already exit D3 cold.") } @@ -536,10 +500,16 @@ Printf("Push TBT RPs to D3Cold together") If (\_SB.PCI0.TRP0.VDID != 0xFFFFFFFF) { + If (\_SB.PCI0.TRP0.PDSX == 1) { + CTP0 = 1 + } /* Put RP0 to D3 cold. */ \_SB.PCI0.TRP0.D3CE() } If (\_SB.PCI0.TRP1.VDID != 0xFFFFFFFF) { + If (\_SB.PCI0.TRP1.PDSX == 1) { + CTP0 = 1 + } /* Put RP1 to D3 cold. */ \_SB.PCI0.TRP1.D3CE() } @@ -568,6 +538,28 @@ /* RP3 D3 cold exit. */ \_SB.PCI0.TRP3.D3CX() } + + /* + * Need to send Connect-Topology command when TBT host + * controller back to D0 from D3. + */ + If (\_SB.PCI0.TDM1.ALCT == 1) { + If (CTP1 == 1) { + /* + * Send Connect-Topology command if there is + * device present on PCIe RP. + */ + \_SB.PCI0.TDM1.CNTP() + + /* Indicate to wait Connect-Topology command. */ + \_SB.PCI0.TDM1.WACT = 1 + + /* Clear the connect states. */ + CTP1 = 0 + } + /* Disallow to send Connect-Topology cmd. */ + \_SB.PCI0.TDM1.ALCT = 0 + } } Else { Printf("Drop TG1N due to it is already exit D3 cold.") } @@ -591,10 +583,16 @@ Printf("Push TBT RPs to D3Cold together") If (\_SB.PCI0.TRP2.VDID != 0xFFFFFFFF) { + If (\_SB.PCI0.TRP2.PDSX == 1) { + CTP1 = 1 + } /* Put RP2 to D3 cold. */ \_SB.PCI0.TRP2.D3CE() } If (\_SB.PCI0.TRP3.VDID != 0xFFFFFFFF) { + If (\_SB.PCI0.TRP3.PDSX == 1) { + CTP1 = 1 + } /* Put RP3 to D3 cold */ \_SB.PCI0.TRP3.D3CE() } @@ -765,11 +763,7 @@ Method (_STA, 0x0, NotSerialized) { - If (THCE == 1) { - Return (0x0F) - } Else { - Return (0x0) - } + Return (0x0F) } #include "tcss_xhci.asl" } @@ -787,11 +781,7 @@ Method (_STA, 0x0, NotSerialized) { - If (DME0 == 1) { - Return (0x0F) - } Else { - Return (0x0) - } + Return (0x0F) } #include "tcss_dma.asl" } @@ -809,11 +799,7 @@ Method (_STA, 0x0, NotSerialized) { - If (DME1 == 1) { - Return (0x0F) - } Else { - Return (0x0) - } + Return (0x0F) } #include "tcss_dma.asl" } @@ -832,13 +818,8 @@ Method (_STA, 0x0, NotSerialized) { - If (TRE0 == 1) { - Return (0x0F) - } Else { - Return (0x0) - } + Return (0x0F) } - Method (_INI) { LTEN = 0 @@ -862,13 +843,8 @@ Method (_STA, 0x0, NotSerialized) { - If (TRE1 == 1) { - Return (0x0F) - } Else { - Return (0x0) - } + Return (0x0F) } - Method (_INI) { LTEN = 0 @@ -892,13 +868,8 @@ Method (_STA, 0x0, NotSerialized) { - If (TRE2 == 1) { - Return (0x0F) - } Else { - Return (0x0) - } + Return (0x0F) } - Method (_INI) { LTEN = 0 @@ -922,13 +893,8 @@ Method (_STA, 0x0, NotSerialized) { - If (TRE3 == 1) { - Return (0x0F) - } Else { - Return (0x0) - } + Return (0x0F) } - Method (_INI) { LTEN = 0 diff --git a/src/soc/intel/tigerlake/acpi/tcss_dma.asl b/src/soc/intel/tigerlake/acpi/tcss_dma.asl index 8eab92f..66950a6 100644 --- a/src/soc/intel/tigerlake/acpi/tcss_dma.asl +++ b/src/soc/intel/tigerlake/acpi/tcss_dma.asl @@ -26,7 +26,118 @@ DMAD, 8 /* 31:24 DMA Active Delay */ } +/* + * TBT MailBox Command Method + * Arg0 - MailBox Cmd ID + */ +Method (ITMB, 1, Serialized) +{ + Local0 = Arg0 | 0x1 /* 0x1, PCIE2TBT_VLD_B */ + P2TB = Local0 +} + +/* + * Wait For Command Completed + * Arg0 - TimeOut value (unit is 1 millisecond) + */ +Method (WFCC, 1, Serialized) +{ + WTBS (Arg0) + P2TB = 0 + WTBC (Arg0) +} + +/* + * Wait For Command Set + * Arg0 - TimeOut value + */ +Method (WTBS, 1, Serialized) +{ + Local0 = Arg0 + While (Local0 > 0) { + /* Wait for Bit to Set. */ + If (TB2P & 0x1) { /* 0x1, TBT2PCIE_DON_R */ + Break + } + Local0-- + Sleep (1) + } +} + +/* + * Wait For Command Clear + * Arg0 - TimeOut value + */ +Method (WTBC, 1, Serialized) +{ + Local0 = Arg0 + While (Local0 > 0) { + /* Wait for Bit to Clear. */ + If ((TB2P & 0x1) != 0x0) { /* 0x1, TBT2PCIE_DON_R */ + Break + } + Local0-- + Sleep (1) + } +} + +/* + * TCSS TBT CONNECT_TOPOLOGY MailBox Command Method + */ +Method (CNTP, 0, Serialized) +{ + Local0 = 0 + /* Set Force Power if it is not set */ + If (DFPE == 0) { + DMAD = 0x22 + DFPE = 1 + /* + * Poll the TBT NVM FW Ready bit with timeout(default is 500ms) before + * send the TBT MailBox command. + */ + While ((INFR == 0) && (Local0 < 500)) { + Sleep (1) + Local0++ + } + } + If (Local0 != 100) { + ITMB (0x3E) /* 0x3E, PCIE2TBT_CONNECT_TOPOLOGY_COMMAND */ + } +} + Name (STAT, 0x1) /* Variable to save power state 1 - D0, 0 - D3C */ +Name (ALCT, 0x0) /* Connect-Topology cmd can be sent or not 1 - yes, 0 - no */ +/* + * Wait Connect-Topology cmd done + * 0 - no need to wait + * 1 - need to wait + * 2 - wait in progress + */ +Name (WACT, 0x0) + +Method (_PS0, 0, Serialized) +{ + If (WACT == 1) { + /* + * PCIe rp0/rp1 is grouped with DMA0 and PCIe rp2/rp3 is grouped wit DMA1. + * Whenever the Connect-Topology command is in the process, WACT flag is set 1. + * PCIe root ports 0/1/2/3/ and DMA 0/1 _PS0 method set WACT to 2 to indicate + * other thread's _PS0 to wait for the command completion. WACT is cleared to + * be 0 after command is finished. + */ + WACT = 2 + WFCC (100) /* Wait for command complete. */ + WACT = 0 + } ElseIf (WACT == 2) { + While (WACT != 0) { + Sleep (5) + } + } +} + +Method (_PS3, 0, Serialized) +{ +} Method (_S0W, 0x0) { @@ -67,6 +178,7 @@ { DD3E = 1 /* Enable DMA RTD3 */ STAT = 0 + ALCT = 0x1 /* Allow to send Connect-Topology cmd. */ } /* diff --git a/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl b/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl index 096a673..a7eafa4 100644 --- a/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl +++ b/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl @@ -64,7 +64,7 @@ */ Method (_DSM, 4, Serialized) { - Return (Buffer() { 0x00 }) + Return (Buffer() {0x00}) } Device (PXSX) @@ -195,8 +195,34 @@ If (PMEX == 1) { PMEX = 0 /* Disable Power Management SCI */ } - - Sleep(100) /* Wait for 100ms before return to OS starts any OS activities. */ + Sleep(100) /* Wait for 100ms before return to OS starts any DS activities. */ + If ((TUID == 0) || (TUID == 1)) { + If (\_SB.PCI0.TDM0.WACT == 1) { + /* + * Indicate other thread's _PS0 to wait the response. + */ + \_SB.PCI0.TDM0.WACT = 2 + \_SB.PCI0.TDM0.WFCC (10) /* Wait for command complete. */ + \_SB.PCI0.TDM0.WACT = 0 + } ElseIf (\_SB.PCI0.TDM0.WACT == 2) { + While (\_SB.PCI0.TDM0.WACT != 0) { + Sleep (5) + } + } + } Else { + If (\_SB.PCI0.TDM1.WACT == 1) { + /* + * Indicate other thread's _PS0 to wait the response. + */ + \_SB.PCI0.TDM1.WACT = 2 + \_SB.PCI0.TDM1.WFCC (10) /* Wait for command complete. */ + \_SB.PCI0.TDM1.WACT = 0 + } ElseIf (\_SB.PCI0.TDM1.WACT == 2) { + While (\_SB.PCI0.TDM1.WACT != 0) { + Sleep (5) + } + } + } } Method (_PS3, 0, Serialized) @@ -220,8 +246,8 @@ } Method (_DSD, 0) { - If ((TUID == 0) || (TUID == 1)) { - Return ( Package() { + Return ( + Package () { /* acpi_pci_bridge_d3 at ../drivers/pci/pci-acpi.c */ ToUUID("6211E2C0-58A3-4AF3-90E1-927A4E0C55A4"), Package () @@ -238,64 +264,9 @@ * (NumOfTBTRP - 1). */ Package (2) { "UID", TUID }, - }, - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package (2) { "usb4-host-interface", \_SB.PCI0.TDM0 }, - Package (2) { "usb4-port-number", TUID }, } - }) - } ElseIf (TUID == 2) { - Return ( Package () { - /* acpi_pci_bridge_d3 at ../drivers/pci/pci-acpi.c */ - ToUUID("6211E2C0-58A3-4AF3-90E1-927A4E0C55A4"), - Package () - { - Package (2) { "HotPlugSupportInD3", 1 }, - }, - - /* pci_acpi_set_untrusted at ../drivers/pci/pci-acpi.c */ - ToUUID("EFCC06CC-73AC-4BC3-BFF0-76143807C389"), - Package () { - Package (2) { "ExternalFacingPort", 1 }, /* TBT/CIO port */ - /* - * UID of the TBT RP on platform, range is: 0, 1 ..., - * (NumOfTBTRP - 1). - */ - Package (2) { "UID", TUID }, - }, - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package (2) { "usb4-host-interface", \_SB.PCI0.TDM1 }, - Package (2) { "usb4-port-number", 0 }, - } - }) - } Else { /* TUID == 3 */ - Return ( Package () { - /* acpi_pci_bridge_d3 at ../drivers/pci/pci-acpi.c */ - ToUUID("6211E2C0-58A3-4AF3-90E1-927A4E0C55A4"), - Package () - { - Package (2) { "HotPlugSupportInD3", 1 }, - }, - - /* pci_acpi_set_untrusted at ../drivers/pci/pci-acpi.c */ - ToUUID("EFCC06CC-73AC-4BC3-BFF0-76143807C389"), - Package () { - Package (2) { "ExternalFacingPort", 1 }, /* TBT/CIO port */ - /* - * UID of the TBT RP on platform, range is: 0, 1 ..., - * (NumOfTBTRP - 1). - */ - Package (2) { "UID", TUID }, - }, - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package (2) { "usb4-host-interface", \_SB.PCI0.TDM1 }, - Package (2) { "usb4-port-number", 1 }, - } - }) - } + } + ) } Method (_S0W, 0x0, NotSerialized) diff --git a/src/soc/intel/tigerlake/acpi/tcss_xhci.asl b/src/soc/intel/tigerlake/acpi/tcss_xhci.asl index c32deed..259b92a 100644 --- a/src/soc/intel/tigerlake/acpi/tcss_xhci.asl +++ b/src/soc/intel/tigerlake/acpi/tcss_xhci.asl @@ -118,68 +118,20 @@ Device (SS01) { Name (_ADR, 0x02) - Method (_DSD, 0, NotSerialized) - { - Return( Package () - { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package (2) { "usb4-host-interface", \_SB.PCI0.TDM0 }, - Package (2) { "usb4-port-number", 0 } - } - }) - } } Device (SS02) { Name (_ADR, 0x03) - Method (_DSD, 0, NotSerialized) - { - Return( Package () - { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package (2) { "usb4-host-interface", \_SB.PCI0.TDM0 }, - Package (2) { "usb4-port-number", 1 } - } - }) - } } Device (SS03) { Name (_ADR, 0x04) - Method (_DSD, 0, NotSerialized) - { - Return( Package () - { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package (2) { "usb4-host-interface", \_SB.PCI0.TDM1 }, - Package (2) { "usb4-port-number", 0 } - } - }) - } } Device (SS04) { Name (_ADR, 0x05) - Method (_DSD, 0, NotSerialized) - { - Return( Package () - { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package (2) { "usb4-host-interface", \_SB.PCI0.TDM1 }, - Package (2) { "usb4-port-number", 1 } - } - }) - } } } -- To view, visit https://review.coreboot.org/c/coreboot/+/42768 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I89db2557e33dc222ae1cb54401c738ded474202b Gerrit-Change-Number: 42768 Gerrit-PatchSet: 1 Gerrit-Owner: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: Enable TCSS devices PM based on platform device tree setting
by Shreesh Chhabbi (Code Review) 07 Aug '23

07 Aug '23

Hello John Zhao, Shreesh Chhabbi, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/42771 to review the following change. Change subject: Enable TCSS devices PM based on platform device tree setting ...................................................................... Enable TCSS devices PM based on platform device tree setting Signed-off-by: John Zhao <john.zhao(a)intel.com> Change-Id: I3044d5f4a882849abd87e313e65189659d503bfb Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> --- M src/soc/intel/tigerlake/acpi/tcss.asl 1 file changed, 58 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/42771/1 diff --git a/src/soc/intel/tigerlake/acpi/tcss.asl b/src/soc/intel/tigerlake/acpi/tcss.asl index 48f2689..24ca891 100644 --- a/src/soc/intel/tigerlake/acpi/tcss.asl +++ b/src/soc/intel/tigerlake/acpi/tcss.asl @@ -252,6 +252,25 @@ Scope (\_SB.PCI0) { /* + * Operation region defined to access the TCSS_DEVEN. Get the MCHBAR in offset + * 0x48 in B0:D0:F0. TCSS device enable base address is in offset 0x7090 of MCHBAR. + */ + OperationRegion (TDEN, SystemMemory, (GMHB() + 0x7090), 0x4) + Field (TDEN, ByteAcc, NoLock, Preserve) + { + TRE0, 1, /* PCIE0_EN */ + TRE1, 1, /* PCIE1_EN */ + TRE2, 1, /* PCIE2_EN */ + TRE3, 1, /* PCIE3_EN */ + , 4, + THCE, 1, /* XHCI_EN */ + TDCE, 1, /* XDCI_EN */ + DME0, 1, /* TBT_DMA0_EN */ + DME1, 1, /* TBT_DMA1_EN */ + , 20 + } + + /* * Operation region defined to access the IOM REGBAR. Get the MCHBAR in offset * 0x48 in B0:D0:F0. REGBAR Base address is in offset 0x7110 of MCHBAR. */ @@ -763,7 +782,11 @@ Method (_STA, 0x0, NotSerialized) { - Return (0x0F) + If (THCE == 1) { + Return (0x0F) + } Else { + Return (0x0) + } } #include "tcss_xhci.asl" } @@ -781,7 +804,11 @@ Method (_STA, 0x0, NotSerialized) { - Return (0x0F) + If (DME0 == 1) { + Return (0x0F) + } Else { + Return (0x0) + } } #include "tcss_dma.asl" } @@ -799,7 +826,11 @@ Method (_STA, 0x0, NotSerialized) { - Return (0x0F) + If (DME1 == 1) { + Return (0x0F) + } Else { + Return (0x0) + } } #include "tcss_dma.asl" } @@ -818,8 +849,13 @@ Method (_STA, 0x0, NotSerialized) { - Return (0x0F) + If (TRE0 == 1) { + Return (0x0F) + } Else { + Return (0x0) + } } + Method (_INI) { LTEN = 0 @@ -843,8 +879,13 @@ Method (_STA, 0x0, NotSerialized) { - Return (0x0F) + If (TRE1 == 1) { + Return (0x0F) + } Else { + Return (0x0) + } } + Method (_INI) { LTEN = 0 @@ -868,8 +909,13 @@ Method (_STA, 0x0, NotSerialized) { - Return (0x0F) + If (TRE2 == 1) { + Return (0x0F) + } Else { + Return (0x0) + } } + Method (_INI) { LTEN = 0 @@ -893,8 +939,13 @@ Method (_STA, 0x0, NotSerialized) { - Return (0x0F) + If (TRE3 == 1) { + Return (0x0F) + } Else { + Return (0x0) + } } + Method (_INI) { LTEN = 0 -- To view, visit https://review.coreboot.org/c/coreboot/+/42771 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3044d5f4a882849abd87e313e65189659d503bfb Gerrit-Change-Number: 42771 Gerrit-PatchSet: 1 Gerrit-Owner: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Gerrit-MessageType: newchange

2 3

← Newer
1
2
3
4
5
6
7
...
317
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit July 2020