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Change in coreboot[master]: src/superio: Add it8987e
by Sergey Larin (Code Review) 07 Aug '23

07 Aug '23

Sergey Larin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38253 ) Change subject: src/superio: Add it8987e ...................................................................... src/superio: Add it8987e Add support for IT8987E SuperIO. Based on it8528e. Currently untested. Signed-off-by: cerg2010cerg2010 <cerg2010cerg2010(a)mail.ru> Change-Id: I3e39be986ffbdebe873ff9b9dbc6902ed1ceaf6f --- A src/superio/ite/it8987e/Kconfig A src/superio/ite/it8987e/Makefile.inc A src/superio/ite/it8987e/it8987e.h A src/superio/ite/it8987e/superio.c 4 files changed, 135 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/38253/1 diff --git a/src/superio/ite/it8987e/Kconfig b/src/superio/ite/it8987e/Kconfig new file mode 100644 index 0000000..b8e3258 --- /dev/null +++ b/src/superio/ite/it8987e/Kconfig @@ -0,0 +1,18 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 Sergey Larin <cerg2010cerg2010(a)mail.ru> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config SUPERIO_ITE_IT8987E + bool + select SUPERIO_ITE_COMMON_PRE_RAM diff --git a/src/superio/ite/it8987e/Makefile.inc b/src/superio/ite/it8987e/Makefile.inc new file mode 100644 index 0000000..01e4d3e --- /dev/null +++ b/src/superio/ite/it8987e/Makefile.inc @@ -0,0 +1,17 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 Sergey Larin <cerg2010cerg2010(a)mail.ru> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-$(CONFIG_SUPERIO_ITE_IT8987E) += superio.c diff --git a/src/superio/ite/it8987e/it8987e.h b/src/superio/ite/it8987e/it8987e.h new file mode 100644 index 0000000..4e265df --- /dev/null +++ b/src/superio/ite/it8987e/it8987e.h @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Sergey Larin <cerg2010cerg2010(a)mail.ru> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SUPERIO_ITE_IT8987E_H +#define SUPERIO_ITE_IT8987E_H + +#define IT8987E_SWUC 0x04 /* System Wake-Up */ +#define IT8987E_KBCM 0x05 /* PS/2 mouse */ +#define IT8987E_KBCK 0x06 /* PS/2 keyboard */ +#define IT8987E_IR 0x0a /* Consumer IR */ +#define IT8987E_SMFI 0x0f /* Shared Memory/Flash Interface */ +#define IT8987E_RTCT 0x10 /* RTC-like Timer */ +#define IT8987E_PMC1 0x11 /* Power Management Channel 1 */ +#define IT8987E_PMC2 0x12 /* Power Management Channel 2 */ +#define IT8987E_SSPI 0x13 /* Serial Peripheral Interface */ +#define IT8987E_PECI 0x14 /* Platform EC Interface */ +#define IT8987E_PMC3 0x17 /* Power Management Channel 3 */ +#define IT8987E_PMC4 0x18 /* Power Management Channel 4 */ +#define IT8987E_PMC5 0x19 /* Power Management Channel 5 */ + + +#endif /* SUPERIO_ITE_IT8987E_H */ diff --git a/src/superio/ite/it8987e/superio.c b/src/superio/ite/it8987e/superio.c new file mode 100644 index 0000000..dce7a6f --- /dev/null +++ b/src/superio/ite/it8987e/superio.c @@ -0,0 +1,65 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Sergey Larin <cerg2010cerg2010(a)mail.ru> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <device/pnp.h> +#include <superio/conf_mode.h> + +#include "it8987e.h" + +static void it8987e_init(struct device *dev) +{ +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = it8987e_init, + .ops_pnp_mode = &pnp_conf_mode_870155_aa, +}; + +static struct pnp_info pnp_dev_info[] = { + { NULL, IT8987E_SWUC, PNP_IO0 | PNP_IRQ0, 0xfff0, }, + { NULL, IT8987E_KBCM, PNP_IRQ0, }, + { NULL, IT8987E_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07ff, }, + { NULL, IT8987E_IR, PNP_IO0 | PNP_IRQ0, 0xfff8, }, + { NULL, IT8987E_SMFI, PNP_IO0 | PNP_IRQ0 | PNP_MSC4, 0xfff0, }, + { NULL, IT8987E_RTCT, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IO3 | PNP_IRQ0 + | PNP_MSC0 | PNP_MSC1 | PNP_MSC2, + 0xfffe, 0xfffe, 0xfffe, 0xfffe}, + { NULL, IT8987E_PMC1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07ff }, + { NULL, IT8987E_PMC2, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IRQ0 | PNP_MSC0, + 0x07fc, 0x07fc, 0xfff0 }, + { NULL, IT8987E_SSPI, PNP_IO0 | PNP_IRQ0, 0xfff8 }, + { NULL, IT8987E_PECI, PNP_IO0, 0xfff8 }, + { NULL, IT8987E_PMC3, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07ff }, + { NULL, IT8987E_PMC4, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC0, + 0x07ff, 0x07ff }, + { NULL, IT8987E_PMC5, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC0, + 0x07ff, 0x07ff }, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_ite_it8987e_ops = { + CHIP_NAME("ITE IT8987E Super I/O") + .enable_dev = enable_dev, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/38253 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e39be986ffbdebe873ff9b9dbc6902ed1ceaf6f Gerrit-Change-Number: 38253 Gerrit-PatchSet: 1 Gerrit-Owner: Sergey Larin <cerg2010cerg2010(a)mail.ru> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: ok
by Name of user not set (Code Review) 07 Aug '23

07 Aug '23

Name of user not set #1002723 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39705 ) Change subject: ok ...................................................................... ok Change-Id: I1049a15110e671b334ab29411b4c148b33f207a6 --- M Documentation/contributing/project_ideas.md A grub.cfg A src/mainboard/dell/Kconfig A src/mainboard/dell/Kconfig.name A src/mainboard/dell/dell_system_vostro_3360/Kconfig A src/mainboard/dell/dell_system_vostro_3360/Kconfig.name A src/mainboard/dell/dell_system_vostro_3360/Makefile.inc A src/mainboard/dell/dell_system_vostro_3360/acpi/ec.asl A src/mainboard/dell/dell_system_vostro_3360/acpi/platform.asl A src/mainboard/dell/dell_system_vostro_3360/acpi/superio.asl A src/mainboard/dell/dell_system_vostro_3360/acpi_tables.c A src/mainboard/dell/dell_system_vostro_3360/board_info.txt A src/mainboard/dell/dell_system_vostro_3360/devicetree.cb A src/mainboard/dell/dell_system_vostro_3360/dsdt.asl A src/mainboard/dell/dell_system_vostro_3360/early_init.c A src/mainboard/dell/dell_system_vostro_3360/gma-mainboard.ads A src/mainboard/dell/dell_system_vostro_3360/gpio.c A src/mainboard/dell/dell_system_vostro_3360/hda_verb.c A src/mainboard/dell/dell_system_vostro_3360/mainboard.c 19 files changed, 782 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/39705/1 diff --git a/Documentation/contributing/project_ideas.md b/Documentation/contributing/project_ideas.md index 2c621f4..141023f 100644 --- a/Documentation/contributing/project_ideas.md +++ b/Documentation/contributing/project_ideas.md @@ -184,3 +184,66 @@ ### Mentors * TODO + +## Fix POST code handling +coreboot supports writing POST codes to I/O port 80. +There are various Kconfigs that deal with POST codes, which don't have +effect on most platforms. +The code to send POST codes is scattered in C and Assembly, some use +functions, some use macros and others simply use the `outb` instruction. +The POST codes are duplicated between stages and aren't documented properly. + + +Tasks: +* Guard Kconfigs with a *depends on* to only show on supported platforms +* Remove duplicated Kconfigs +* Replace `outb(0x80, ...)` with calls to `post_code(...)` +* Update Documentation/POSTCODES +* Use defines from console/post_codes.h where possible +* Drop duplicated POST codes +* Make use of all possible 255 values + +### Requirements +* knowledge in the coreboot build system and the concept of stages +* other knowledge: Little experience with C and x86 Assembly +* hardware requirements: Nothing special + +### Mentors +* Patrick Rudolph <patrick.rudolph(a)9elements.com> +* Christian Walter <christian.walter(a)9elements.com> + +## Board status replacement +The [Board status page](https://coreboot.org/status/board-status.html) allows +to see last working commit of a board. The page is generated by a cron job +that runs on a huge git repository. + +Build an open source replacement written in Golang using existing tools +and libraries, consisting of a backend, a frontend and client side +scripts. The backend should connect to an SQL database with can be +controlled using a RESTful API. The RESTful API should have basic authentication +for managment tasks and new board status uploads. + +At least one older test result should be keept in the database. + +The frontend should use established UI libraries or frameworks (for example +Angular) to display the current board status, that is if it's working or not +and some details provided with the last test. If a board isn't working the last +working commit (if any) should be shown in addition to the broken one. + +Provide a script/tool that allows to: +1. Push mainboard details from coreboot master CI +2. Push mainboard test results from authenticated users containing + * working + * commit hash + * bootlog (if any) + * dmesg (if it's booting) + * timestamps (if it's booting) + * coreboot config + +### Requirements +* coreboot knowledge: Non-technical, needed to perform requirements analysis +* software knowledge: Golang, SQL for the backend, JS for the frontend + +### Mentors +* Patrick Rudolph <patrick.rudolph(a)9elements.com> +* Christian Walter <christian.walter(a)9elements.com> diff --git a/grub.cfg b/grub.cfg new file mode 100644 index 0000000..fd425c3 --- /dev/null +++ b/grub.cfg @@ -0,0 +1,4 @@ +configfile (ahci0,3)/boot/grub/grub.cfg +terminal_output --append cbmemc +set debug=atkeyb + diff --git a/src/mainboard/dell/Kconfig b/src/mainboard/dell/Kconfig new file mode 100644 index 0000000..298c62b --- /dev/null +++ b/src/mainboard/dell/Kconfig @@ -0,0 +1,16 @@ +if VENDOR_DELL + +choice + prompt "Mainboard model" + +source "src/mainboard/dell/*/Kconfig.name" + +endchoice + +source "src/mainboard/dell/*/Kconfig" + +config MAINBOARD_VENDOR + string + default "Dell Inc." + +endif # VENDOR_DELL diff --git a/src/mainboard/dell/Kconfig.name b/src/mainboard/dell/Kconfig.name new file mode 100644 index 0000000..3d2fefd --- /dev/null +++ b/src/mainboard/dell/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_DELL + bool "Dell Inc." diff --git a/src/mainboard/dell/dell_system_vostro_3360/Kconfig b/src/mainboard/dell/dell_system_vostro_3360/Kconfig new file mode 100644 index 0000000..dfcc0e1 --- /dev/null +++ b/src/mainboard/dell/dell_system_vostro_3360/Kconfig @@ -0,0 +1,43 @@ +if BOARD_DELL_DELL_SYSTEM_VOSTRO_3360 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select GFX_GMA_PANEL_1_ON_LVDS + select MAINBOARD_HAS_LIBGFXINIT # FIXME: check this + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_C216 + select USE_NATIVE_RAMINIT + +config MAINBOARD_DIR + string + default dell/dell_system_vostro_3360 + +config MAINBOARD_PART_NUMBER + string + default "Dell System Vostro 3360" + +config VGA_BIOS_FILE + string + default "pci8086,0156.rom" + +config VGA_BIOS_ID + string + default "8086,0156" + +config DRAM_RESET_GATE_GPIO # FIXME: check this + int + default 60 + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX # FIXME: check this + int + default 2 +endif diff --git a/src/mainboard/dell/dell_system_vostro_3360/Kconfig.name b/src/mainboard/dell/dell_system_vostro_3360/Kconfig.name new file mode 100644 index 0000000..8925217 --- /dev/null +++ b/src/mainboard/dell/dell_system_vostro_3360/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_DELL_DELL_SYSTEM_VOSTRO_3360 + bool "Dell System Vostro 3360" diff --git a/src/mainboard/dell/dell_system_vostro_3360/Makefile.inc b/src/mainboard/dell/dell_system_vostro_3360/Makefile.inc new file mode 100644 index 0000000..18391d8 --- /dev/null +++ b/src/mainboard/dell/dell_system_vostro_3360/Makefile.inc @@ -0,0 +1,5 @@ +bootblock-y += early_init.c +bootblock-y += gpio.c +romstage-y += early_init.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/dell/dell_system_vostro_3360/acpi/ec.asl b/src/mainboard/dell/dell_system_vostro_3360/acpi/ec.asl new file mode 100644 index 0000000..a9177df --- /dev/null +++ b/src/mainboard/dell/dell_system_vostro_3360/acpi/ec.asl @@ -0,0 +1 @@ +#include<drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/dell/dell_system_vostro_3360/acpi/platform.asl b/src/mainboard/dell/dell_system_vostro_3360/acpi/platform.asl new file mode 100644 index 0000000..552fb6c --- /dev/null +++ b/src/mainboard/dell/dell_system_vostro_3360/acpi/platform.asl @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method(_WAK, 1) +{ + Return(Package() {0, 0}) +} + +Method(_PTS, 1) +{ +} diff --git a/src/mainboard/dell/dell_system_vostro_3360/acpi/superio.asl b/src/mainboard/dell/dell_system_vostro_3360/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/dell/dell_system_vostro_3360/acpi/superio.asl diff --git a/src/mainboard/dell/dell_system_vostro_3360/acpi_tables.c b/src/mainboard/dell/dell_system_vostro_3360/acpi_tables.c new file mode 100644 index 0000000..cfc2061 --- /dev/null +++ b/src/mainboard/dell/dell_system_vostro_3360/acpi_tables.c @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/bd82x6x/nvs.h> + +/* FIXME: check this function. */ +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + /* The lid is open by default. */ + gnvs->lids = 1; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/dell/dell_system_vostro_3360/board_info.txt b/src/mainboard/dell/dell_system_vostro_3360/board_info.txt new file mode 100644 index 0000000..be6bff8 --- /dev/null +++ b/src/mainboard/dell/dell_system_vostro_3360/board_info.txt @@ -0,0 +1,4 @@ +Category: desktop +ROM protocol: SPI +Flashrom support: n +FIXME: check category, , put ROM package, ROM socketed, Release year diff --git a/src/mainboard/dell/dell_system_vostro_3360/devicetree.cb b/src/mainboard/dell/dell_system_vostro_3360/devicetree.cb new file mode 100644 index 0000000..d234325 --- /dev/null +++ b/src/mainboard/dell/dell_system_vostro_3360/devicetree.cb @@ -0,0 +1,111 @@ +chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply. + register "gfx.link_frequency_270_mhz" = "1" + register "gfx.use_spread_spectrum_clock" = "1" + register "gpu_cpu_backlight" = "0x00001312" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "gpu_panel_port_select" = "0" + register "gpu_panel_power_backlight_off_delay" = "3000" + register "gpu_panel_power_backlight_on_delay" = "1700" + register "gpu_panel_power_cycle_delay" = "5" + register "gpu_panel_power_down_delay" = "300" + register "gpu_panel_power_up_delay" = "300" + register "gpu_pch_backlight" = "0x13121312" + device cpu_cluster 0x0 on + chip cpu/intel/model_206ax # FIXME: check all registers + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0x0 on + end + device lapic 0xacac off + end + end + end + device domain 0x0 on + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "1" + register "gen1_dec" = "0x00040069" + register "gen2_dec" = "0x00040911" + register "gen3_dec" = "0x00000000" + register "gen4_dec" = "0x000c06a1" + register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x1" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + register "superspeed_capable_ports" = "0x0000000f" + register "xhci_overcurrent_mapping" = "0x00000c03" + register "xhci_switchable_ports" = "0x0000000f" + device pci 14.0 on # USB 3.0 Controller + subsystemid 0x1028 0x055c + end + device pci 16.0 off # Management Engine Interface 1 + end + device pci 16.1 off # Management Engine Interface 2 + end + device pci 16.2 off # Management Engine IDE-R + end + device pci 16.3 off # Management Engine KT + end + device pci 19.0 off # Intel Gigabit Ethernet + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x1028 0x055c + end + device pci 1b.0 on # High Definition Audio + subsystemid 0x1028 0x055c + end + device pci 1c.0 on # PCIe Port #1 + subsystemid 0x1028 0x055c + end + device pci 1c.1 off # PCIe Port #2 + end + device pci 1c.2 off # PCIe Port #3 + end + device pci 1c.3 off # PCIe Port #4 + end + device pci 1c.4 on # PCIe Port #5 + subsystemid 0x1028 0x055c + end + device pci 1c.5 off # PCIe Port #6 + end + device pci 1c.6 off # PCIe Port #7 + end + device pci 1c.7 off # PCIe Port #8 + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x1028 0x055c + end + device pci 1e.0 off # PCI bridge + end + device pci 1f.0 on # LPC bridge PCI-LPC bridge + subsystemid 0x1028 0x055c + end + device pci 1f.2 on # SATA Controller 1 + subsystemid 0x1028 0x055c + end + device pci 1f.3 on # SMBus + subsystemid 0x1028 0x055c + end + device pci 1f.5 off # SATA Controller 2 + end + device pci 1f.6 off # Thermal + end + end + device pci 00.0 on # Host bridge Host bridge + subsystemid 0x1028 0x055c + end + device pci 01.0 off # PEG + end + device pci 02.0 on # iGPU + subsystemid 0x1028 0x055c + end + end +end diff --git a/src/mainboard/dell/dell_system_vostro_3360/dsdt.asl b/src/mainboard/dell/dell_system_vostro_3360/dsdt.asl new file mode 100644 index 0000000..98c2ad4 --- /dev/null +++ b/src/mainboard/dell/dell_system_vostro_3360/dsdt.asl @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 + + +#include <arch/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI 2.0 and up */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 /* OEM revision */ +) +{ + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } +} diff --git a/src/mainboard/dell/dell_system_vostro_3360/early_init.c b/src/mainboard/dell/dell_system_vostro_3360/early_init.c new file mode 100644 index 0000000..6dbf226 --- /dev/null +++ b/src/mainboard/dell/dell_system_vostro_3360/early_init.c @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* FIXME: Check if all includes are needed. */ + +#include <stdint.h> +#include <string.h> +#include <timestamp.h> +#include <arch/byteorder.h> +#include <device/mmio.h> +#include <device/pci_ops.h> +#include <device/pnp_ops.h> +#include <console/console.h> +#include <bootblock_common.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/gpio.h> + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 1, 0 }, + { 1, 1, 0 }, + { 1, 1, 1 }, + { 1, 1, 1 }, + { 1, 1, 2 }, + { 1, 1, 2 }, + { 0, 1, 3 }, + { 0, 1, 3 }, + { 1, 1, 4 }, + { 0, 1, 4 }, + { 1, 1, 5 }, + { 0, 1, 5 }, + { 1, 1, 6 }, + { 0, 1, 6 }, +}; + +void bootblock_mainboard_early_init(void) +{ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); +} + +/* FIXME: Put proper SPD map here. */ +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x51, id_only); + read_spd(&spd[2], 0x52, id_only); + read_spd(&spd[3], 0x53, id_only); +} diff --git a/src/mainboard/dell/dell_system_vostro_3360/gma-mainboard.ads b/src/mainboard/dell/dell_system_vostro_3360/gma-mainboard.ads new file mode 100644 index 0000000..6cb572a --- /dev/null +++ b/src/mainboard/dell/dell_system_vostro_3360/gma-mainboard.ads @@ -0,0 +1,35 @@ +-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + -- FIXME: check this + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Analog, + LVDS, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/dell/dell_system_vostro_3360/gpio.c b/src/mainboard/dell/dell_system_vostro_3360/gpio.c new file mode 100644 index 0000000..d7db210 --- /dev/null +++ b/src/mainboard/dell/dell_system_vostro_3360/gpio.c @@ -0,0 +1,241 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_GPIO, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_GPIO, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_GPIO, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_OUTPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio18 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_OUTPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio25 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_LOW, + .gpio22 = GPIO_LEVEL_HIGH, + .gpio23 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio31 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio3 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_GPIO, + .gpio41 = GPIO_MODE_GPIO, + .gpio42 = GPIO_MODE_GPIO, + .gpio43 = GPIO_MODE_GPIO, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_GPIO, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_GPIO, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_GPIO, + .gpio62 = GPIO_MODE_GPIO, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_OUTPUT, + .gpio38 = GPIO_DIR_OUTPUT, + .gpio39 = GPIO_DIR_OUTPUT, + .gpio40 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio47 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_OUTPUT, + .gpio53 = GPIO_DIR_INPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_INPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio59 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_OUTPUT, + .gpio61 = GPIO_DIR_INPUT, + .gpio62 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio33 = GPIO_LEVEL_HIGH, + .gpio34 = GPIO_LEVEL_HIGH, + .gpio37 = GPIO_LEVEL_LOW, + .gpio38 = GPIO_LEVEL_HIGH, + .gpio39 = GPIO_LEVEL_HIGH, + .gpio49 = GPIO_LEVEL_HIGH, + .gpio52 = GPIO_LEVEL_LOW, + .gpio60 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, + .gpio74 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/dell/dell_system_vostro_3360/hda_verb.c b/src/mainboard/dell/dell_system_vostro_3360/hda_verb.c new file mode 100644 index 0000000..c55bf3c --- /dev/null +++ b/src/mainboard/dell/dell_system_vostro_3360/hda_verb.c @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10134213, /* Codec Vendor / Device ID: Cirrus */ + 0x1028055c, /* Subsystem ID */ + 6, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0x0, 0x1028055c), + AZALIA_PIN_CFG(0x0, 0x04, 0x0421101f), + AZALIA_PIN_CFG(0x0, 0x05, 0x90170010), + AZALIA_PIN_CFG(0x0, 0x06, 0x04a1103e), + AZALIA_PIN_CFG(0x0, 0x07, 0x40f000f0), + AZALIA_PIN_CFG(0x0, 0x08, 0x90a60030), + + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0x3, 0x80860101), + AZALIA_PIN_CFG(0x3, 0x05, 0x18560010), + AZALIA_PIN_CFG(0x3, 0x06, 0x58560020), + AZALIA_PIN_CFG(0x3, 0x07, 0x58560030), + +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/dell/dell_system_vostro_3360/mainboard.c b/src/mainboard/dell/dell_system_vostro_3360/mainboard.c new file mode 100644 index 0000000..e6f8258 --- /dev/null +++ b/src/mainboard/dell/dell_system_vostro_3360/mainboard.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <pc80/keyboard.h> +#include <southbridge/intel/bd82x6x/pch.h> + +static void mainboard_init(struct device *const dev) + { + printk(BIOS_DEBUG, "Vostro3360: Initializing keyboard.\n"); + pc_keyboard_init(NO_AUX_DEVICE); + } + +static void mainboard_enable(struct device *dev) +{ + /* FIXME: fix these values. */ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); + dev->ops->init = mainboard_init; +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/39705 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1049a15110e671b334ab29411b4c148b33f207a6 Gerrit-Change-Number: 39705 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1002723 Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: Revert "console: Update for vboot before bootblock"
by Nico Huber (Code Review) 07 Aug '23

07 Aug '23

Hello build bot (Jenkins), Raul Rangel, Martin Roth, Patrick Georgi, Furquan Shaikh, Eric Peers, Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/42165 to review the following change. Change subject: Revert "console: Update for vboot before bootblock" ...................................................................... Revert "console: Update for vboot before bootblock" This reverts commit baba3e961072bfb7ffb4f0031ada27046a58d29e. Reason for revert: Submitted during review. Change-Id: I657a6170aba5aba685531380353aa9ba999f9c4e --- M src/console/Makefile.inc 1 file changed, 2 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/42165/1 diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc index e2a20d7..2154eb9 100644 --- a/src/console/Makefile.inc +++ b/src/console/Makefile.inc @@ -11,14 +11,12 @@ smm-y += die.c smm-y += post.c -ifneq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) +verstage-y += init.c verstage-y += printk.c +verstage-y += vtxprintf.c vsprintf.c verstage-y += console.c -endif verstage-y += post.c verstage-y += die.c -verstage-y += init.c -verstage-y += vtxprintf.c vsprintf.c romstage-y += vtxprintf.c printk.c vsprintf.c romstage-y += init.c console.c -- To view, visit https://review.coreboot.org/c/coreboot/+/42165 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I657a6170aba5aba685531380353aa9ba999f9c4e Gerrit-Change-Number: 42165 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: soc/intel/baytrail: Start VBOOT in bootblock
by Arthur Heymans (Code Review) 07 Aug '23

07 Aug '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36874 ) Change subject: soc/intel/baytrail: Start VBOOT in bootblock ...................................................................... soc/intel/baytrail: Start VBOOT in bootblock The earlier the more that can be updated via RW fmap regions. Change-Id: Ifcaf6ad8e27c09fee99cf6a8b12f9fadcb0cef2c Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/google/rambi/Makefile.inc M src/soc/intel/baytrail/Kconfig M src/soc/intel/baytrail/Makefile.inc M src/soc/intel/baytrail/pmutil.c 4 files changed, 9 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/36874/1 diff --git a/src/mainboard/google/rambi/Makefile.inc b/src/mainboard/google/rambi/Makefile.inc index 0e80b64..6660d23 100644 --- a/src/mainboard/google/rambi/Makefile.inc +++ b/src/mainboard/google/rambi/Makefile.inc @@ -13,6 +13,7 @@ ## GNU General Public License for more details. ## +verstage-$(CONFIG_CHROMEOS) += chromeos.c romstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index cfea93a..e4e8c30 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -41,11 +41,8 @@ config VBOOT select VBOOT_MUST_REQUEST_DISPLAY - select VBOOT_STARTS_IN_ROMSTAGE - -config BOOTBLOCK_CPU_INIT - string - default "soc/intel/baytrail/bootblock/bootblock.c" + select VBOOT_STARTS_IN_BOOTBLOCK + select VBOOT_SEPARATE_VERSTAGE config MMCONF_BASE_ADDRESS hex diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index eda3e25..d21f744 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -16,6 +16,8 @@ bootblock-y += ../../../cpu/x86/early_reset.S bootblock-y += bootblock/bootblock.c +verstage-y += pmutil.c + romstage-y += iosf.c romstage-y += memmap.c romstage-y += pmutil.c diff --git a/src/soc/intel/baytrail/pmutil.c b/src/soc/intel/baytrail/pmutil.c index 51174fc..2d14d84 100644 --- a/src/soc/intel/baytrail/pmutil.c +++ b/src/soc/intel/baytrail/pmutil.c @@ -368,7 +368,10 @@ { uint32_t gen_pmcon1; int rtc_fail; - struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); + struct chipset_power_state *ps = NULL; + + if (ENV_RAMSTAGE) + ps = cbmem_find(CBMEM_ID_POWER_STATE); if (ps != NULL) gen_pmcon1 = ps->gen_pmcon1; -- To view, visit https://review.coreboot.org/c/coreboot/+/36874 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifcaf6ad8e27c09fee99cf6a8b12f9fadcb0cef2c Gerrit-Change-Number: 36874 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: mb/gigabyte/ga-g41m-es2l: Prepare for a variant
by Arthur Heymans (Code Review) 07 Aug '23

07 Aug '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41867 ) Change subject: mb/gigabyte/ga-g41m-es2l: Prepare for a variant ...................................................................... mb/gigabyte/ga-g41m-es2l: Prepare for a variant To ease the review of adding a variant (ga-g41m-combo) move a few things around without yet adding the variant. Change-Id: I0b22731849e157b76be97dbe02a7538f1cea472d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/gigabyte/ga-g41m-es2l/Kconfig M src/mainboard/gigabyte/ga-g41m-es2l/Makefile.inc M src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb M src/mainboard/gigabyte/ga-g41m-es2l/early_init.c A src/mainboard/gigabyte/ga-g41m-es2l/include/mainboard/superio.h A src/mainboard/gigabyte/ga-g41m-es2l/superio.h R src/mainboard/gigabyte/ga-g41m-es2l/variants/ga-g41m-es2l/gpio.c R src/mainboard/gigabyte/ga-g41m-es2l/variants/ga-g41m-es2l/hda_verb.c A src/mainboard/gigabyte/ga-g41m-es2l/variants/ga-g41m-es2l/overridetree.cb A src/mainboard/gigabyte/ga-g41m-es2l/variants/ga-g41m-es2l/superio.c 10 files changed, 166 insertions(+), 119 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/41867/1 diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig index fa6783d1..97f155a 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig +++ b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig @@ -7,7 +7,7 @@ select CPU_INTEL_SOCKET_LGA775 select NORTHBRIDGE_INTEL_X4X select SOUTHBRIDGE_INTEL_I82801GX - select SUPERIO_ITE_IT8718F + select SUPERIO_ITE_IT8718F if BOARD_GIGABYTE_GA_G41M_ES2L select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_1024 select PCIEXP_ASPM @@ -24,9 +24,17 @@ string default "gigabyte/ga-g41m-es2l" +config VARIANT_DIR + string + default "ga-g41m-es2l" if BOARD_GIGABYTE_GA_G41M_ES2L + +config OVERRIDE_DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" + config MAINBOARD_PART_NUMBER string - default "GA-G41M-ES2L" + default "GA-G41M-ES2L" if BOARD_GIGABYTE_GA_G41M_ES2L config MAX_CPUS int diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/Makefile.inc b/src/mainboard/gigabyte/ga-g41m-es2l/Makefile.inc index 4100476..cf8ce96 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/Makefile.inc +++ b/src/mainboard/gigabyte/ga-g41m-es2l/Makefile.inc @@ -1,7 +1,11 @@ ramstage-y += cstates.c -romstage-y += gpio.c bootblock-y += early_init.c romstage-y += early_init.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include +bootblock-y += variants/$(VARIANT_DIR)/superio.c +romstage-y += variants/$(VARIANT_DIR)/gpio.c +ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb index 6328bc6..bdeda72 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb @@ -68,79 +68,6 @@ device pci 1e.3 off end # AC'97 Modem device pci 1f.0 on # ISA bridge subsystemid 0x1458 0x5001 - chip superio/ite/it8718f # Super I/O - register "TMPIN1.mode" = "THERMAL_RESISTOR" - register "TMPIN2.mode" = "THERMAL_RESISTOR" - register "TMPIN3.mode" = "THERMAL_DIODE" - register "TMPIN3.offset" = "0" - register "ec.vin_mask" = "VIN7 | VIN4 | VIN3 | VIN2 | VIN1 | VIN0" - - register "FAN1.mode" = "FAN_SMART_AUTOMATIC" - register "FAN1.smart.tmpin" = "3" - register "FAN1.smart.tmp_off" = "25" - register "FAN1.smart.tmp_start" = "30" - register "FAN1.smart.tmp_full" = "65" - register "FAN1.smart.tmp_delta" = "3" - register "FAN1.smart.smoothing" = "1" - register "FAN1.smart.pwm_start" = "0" - register "FAN1.smart.slope" = "10" - - register "FAN2.mode" = "FAN_SMART_AUTOMATIC" - register "FAN2.smart.tmpin" = "3" - register "FAN2.smart.tmp_off" = "25" - register "FAN2.smart.tmp_start" = "30" - register "FAN2.smart.tmp_full" = "65" - register "FAN2.smart.tmp_delta" = "3" - register "FAN2.smart.smoothing" = "1" - register "FAN2.smart.pwm_start" = "0" - register "FAN2.smart.slope" = "10" - - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - irq 0xf0 = 0x00 - irq 0xf1 = 0x80 - end - device pnp 2e.1 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - io 0x62 = 0x000 - drq 0x74 = 4 - irq 0xf0 = 0x08 - end - device pnp 2e.4 on # Environment controller - io 0x60 = 0x290 - irq 0x70 = 0x00 - io 0x62 = 0x000 - irq 0xf0 = 0x80 - irq 0xf1 = 0x00 - irq 0xf2 = 0x0a - irq 0xf3 = 0x80 - irq 0xf4 = 0x00 - irq 0xf5 = 0x00 - irq 0xf6 = 0xff - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - irq 0x70 = 1 - io 0x62 = 0x64 - irq 0xf0 = 0x48 - end - device pnp 2e.6 on # Mouse - irq 0x70 = 12 - irq 0x71 = 2 - irq 0xf0 = 0 - end - end end device pci 1f.1 on # PATA/IDE subsystemid 0x1458 0xb004 diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/early_init.c b/src/mainboard/gigabyte/ga-g41m-es2l/early_init.c index 4b0ea16..c204070 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/early_init.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/early_init.c @@ -4,12 +4,7 @@ #include <device/pci_ops.h> #include <southbridge/intel/i82801gx/i82801gx.h> #include <northbridge/intel/x4x/x4x.h> -#include <superio/ite/it8718f/it8718f.h> -#include <superio/ite/common/ite.h> - -#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) -#define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) -#define EC_DEV PNP_DEV(0x2e, IT8718F_EC) +#include <mainboard/superio.h> /* Early mainboard specific GPIO setup. * We should use standard gpio.h eventually @@ -17,43 +12,7 @@ void bootblock_mainboard_early_init(void) { - /* Set default GPIOs on superio */ - ite_reg_write(GPIO_DEV, 0x25, 0x00); - ite_reg_write(GPIO_DEV, 0x26, 0xc7); - ite_reg_write(GPIO_DEV, 0x27, 0x80); - ite_reg_write(GPIO_DEV, 0x28, 0x41); - ite_reg_write(GPIO_DEV, 0x29, 0x0a); - ite_reg_write(GPIO_DEV, 0x2c, 0x01); - ite_reg_write(GPIO_DEV, 0x62, 0x08); - ite_reg_write(GPIO_DEV, 0x72, 0x00); - ite_reg_write(GPIO_DEV, 0x73, 0x00); - ite_reg_write(GPIO_DEV, 0xb8, 0x00); - ite_reg_write(GPIO_DEV, 0xbb, 0x40); - ite_reg_write(GPIO_DEV, 0xc0, 0x00); - ite_reg_write(GPIO_DEV, 0xc1, 0xc7); - ite_reg_write(GPIO_DEV, 0xc2, 0x80); - ite_reg_write(GPIO_DEV, 0xc3, 0x01); - ite_reg_write(GPIO_DEV, 0xc4, 0x0a); - ite_reg_write(GPIO_DEV, 0xc8, 0x00); - ite_reg_write(GPIO_DEV, 0xc9, 0x04); - ite_reg_write(GPIO_DEV, 0xcb, 0x00); - ite_reg_write(GPIO_DEV, 0xcc, 0x02); - ite_reg_write(GPIO_DEV, 0xf0, 0x10); - ite_reg_write(GPIO_DEV, 0xf1, 0x40); - ite_reg_write(GPIO_DEV, 0xf6, 0x26); - ite_reg_write(GPIO_DEV, 0xfc, 0x52); - - ite_reg_write(EC_DEV, 0xf0, 0x80); - ite_reg_write(EC_DEV, 0xf1, 0x00); - ite_reg_write(EC_DEV, 0xf2, 0x0a); - ite_reg_write(EC_DEV, 0xf3, 0x80); - ite_reg_write(EC_DEV, 0x70, 0x00); // Don't use IRQ9 - ite_reg_write(EC_DEV, 0x30, 0x01); // Enable - - ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - - /* Disable SIO reboot */ - ite_reg_write(GPIO_DEV, 0xEF, 0x7E); + mainboard_early_superio(); /* IRQ routing */ RCBA32(D31IP) = 0x00002210; diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/include/mainboard/superio.h b/src/mainboard/gigabyte/ga-g41m-es2l/include/mainboard/superio.h new file mode 100644 index 0000000..ddc7d04 --- /dev/null +++ b/src/mainboard/gigabyte/ga-g41m-es2l/include/mainboard/superio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_GIGABYTE_GA_G41M_ES2l_SUPERIO +#define MAINBOARD_GIGABYTE_GA_G41M_ES2l_SUPERIO + +void mainboard_early_superio(void); + +#endif diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/superio.h b/src/mainboard/gigabyte/ga-g41m-es2l/superio.h new file mode 100644 index 0000000..62bf591 --- /dev/null +++ b/src/mainboard/gigabyte/ga-g41m-es2l/superio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifdef MAINBOARD_GIGABYTE_GA_G41M_ES2l_SUPERIO +#define MAINBOARD_GIGABYTE_GA_G41M_ES2l_SUPERIO + + + +#endif diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/gpio.c b/src/mainboard/gigabyte/ga-g41m-es2l/variants/ga-g41m-es2l/gpio.c similarity index 100% rename from src/mainboard/gigabyte/ga-g41m-es2l/gpio.c rename to src/mainboard/gigabyte/ga-g41m-es2l/variants/ga-g41m-es2l/gpio.c diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/hda_verb.c b/src/mainboard/gigabyte/ga-g41m-es2l/variants/ga-g41m-es2l/hda_verb.c similarity index 100% rename from src/mainboard/gigabyte/ga-g41m-es2l/hda_verb.c rename to src/mainboard/gigabyte/ga-g41m-es2l/variants/ga-g41m-es2l/hda_verb.c diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/variants/ga-g41m-es2l/overridetree.cb b/src/mainboard/gigabyte/ga-g41m-es2l/variants/ga-g41m-es2l/overridetree.cb new file mode 100644 index 0000000..f481195 --- /dev/null +++ b/src/mainboard/gigabyte/ga-g41m-es2l/variants/ga-g41m-es2l/overridetree.cb @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +chip northbridge/intel/x4x # Northbridge + device domain 0 on # PCI domain + chip southbridge/intel/i82801gx # Southbridge + device pci 1f.0 on # ISA bridge + subsystemid 0x1458 0x5001 + chip superio/ite/it8718f # Super I/O + register "TMPIN1.mode" = "THERMAL_RESISTOR" + register "TMPIN2.mode" = "THERMAL_RESISTOR" + register "TMPIN3.mode" = "THERMAL_DIODE" + register "TMPIN3.offset" = "0" + register "ec.vin_mask" = "VIN7 | VIN4 | VIN3 | VIN2 | VIN1 | VIN0" + + register "FAN1.mode" = "FAN_SMART_AUTOMATIC" + register "FAN1.smart.tmpin" = "3" + register "FAN1.smart.tmp_off" = "25" + register "FAN1.smart.tmp_start" = "30" + register "FAN1.smart.tmp_full" = "65" + register "FAN1.smart.tmp_delta" = "3" + register "FAN1.smart.smoothing" = "1" + register "FAN1.smart.pwm_start" = "0" + register "FAN1.smart.slope" = "10" + + register "FAN2.mode" = "FAN_SMART_AUTOMATIC" + register "FAN2.smart.tmpin" = "3" + register "FAN2.smart.tmp_off" = "25" + register "FAN2.smart.tmp_start" = "30" + register "FAN2.smart.tmp_full" = "65" + register "FAN2.smart.tmp_delta" = "3" + register "FAN2.smart.smoothing" = "1" + register "FAN2.smart.pwm_start" = "0" + register "FAN2.smart.slope" = "10" + + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + irq 0xf0 = 0x00 + irq 0xf1 = 0x80 + end + device pnp 2e.1 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + io 0x62 = 0x000 + drq 0x74 = 4 + irq 0xf0 = 0x08 + end + device pnp 2e.4 on # Environment controller + io 0x60 = 0x290 + irq 0x70 = 0x00 + io 0x62 = 0x000 + irq 0xf0 = 0x80 + irq 0xf1 = 0x00 + irq 0xf2 = 0x0a + irq 0xf3 = 0x80 + irq 0xf4 = 0x00 + irq 0xf5 = 0x00 + irq 0xf6 = 0xff + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + irq 0x70 = 1 + io 0x62 = 0x64 + irq 0xf0 = 0x48 + end + device pnp 2e.6 on # Mouse + irq 0x70 = 12 + irq 0x71 = 2 + irq 0xf0 = 0 + end + end + end + end + end +end diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/variants/ga-g41m-es2l/superio.c b/src/mainboard/gigabyte/ga-g41m-es2l/variants/ga-g41m-es2l/superio.c new file mode 100644 index 0000000..c759532 --- /dev/null +++ b/src/mainboard/gigabyte/ga-g41m-es2l/variants/ga-g41m-es2l/superio.c @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <mainboard/superio.h> +#include <superio/ite/it8718f/it8718f.h> +#include <superio/ite/common/ite.h> + +#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) +#define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) +#define EC_DEV PNP_DEV(0x2e, IT8718F_EC) + +void mainboard_early_superio(void) +{ + /* Set default GPIOs on superio */ + ite_reg_write(GPIO_DEV, 0x25, 0x00); + ite_reg_write(GPIO_DEV, 0x26, 0xc7); + ite_reg_write(GPIO_DEV, 0x27, 0x80); + ite_reg_write(GPIO_DEV, 0x28, 0x41); + ite_reg_write(GPIO_DEV, 0x29, 0x0a); + ite_reg_write(GPIO_DEV, 0x2c, 0x01); + ite_reg_write(GPIO_DEV, 0x62, 0x08); + ite_reg_write(GPIO_DEV, 0x72, 0x00); + ite_reg_write(GPIO_DEV, 0x73, 0x00); + ite_reg_write(GPIO_DEV, 0xb8, 0x00); + ite_reg_write(GPIO_DEV, 0xbb, 0x40); + ite_reg_write(GPIO_DEV, 0xc0, 0x00); + ite_reg_write(GPIO_DEV, 0xc1, 0xc7); + ite_reg_write(GPIO_DEV, 0xc2, 0x80); + ite_reg_write(GPIO_DEV, 0xc3, 0x01); + ite_reg_write(GPIO_DEV, 0xc4, 0x0a); + ite_reg_write(GPIO_DEV, 0xc8, 0x00); + ite_reg_write(GPIO_DEV, 0xc9, 0x04); + ite_reg_write(GPIO_DEV, 0xcb, 0x00); + ite_reg_write(GPIO_DEV, 0xcc, 0x02); + ite_reg_write(GPIO_DEV, 0xf0, 0x10); + ite_reg_write(GPIO_DEV, 0xf1, 0x40); + ite_reg_write(GPIO_DEV, 0xf6, 0x26); + ite_reg_write(GPIO_DEV, 0xfc, 0x52); + + ite_reg_write(EC_DEV, 0xf0, 0x80); + ite_reg_write(EC_DEV, 0xf1, 0x00); + ite_reg_write(EC_DEV, 0xf2, 0x0a); + ite_reg_write(EC_DEV, 0xf3, 0x80); + ite_reg_write(EC_DEV, 0x70, 0x00); // Don't use IRQ9 + ite_reg_write(EC_DEV, 0x30, 0x01); // Enable + + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + + /* Disable SIO reboot */ + ite_reg_write(GPIO_DEV, 0xEF, 0x7E); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/41867 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b22731849e157b76be97dbe02a7538f1cea472d Gerrit-Change-Number: 41867 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: The .config is overwritten when added to coreboot.rom via CBFS at the...
by Jeremy Jackson (Code Review) 07 Aug '23

07 Aug '23

Jeremy Jackson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42028 ) Change subject: The .config is overwritten when added to coreboot.rom via CBFS at the end of the build (if you choose that option)... should this be a separate file for each of fallback and normal? Since there can be two different versions and/or configurations, would fallback/config and normal/config make more sense? Also the "revision" file might benefit from similar treatment. ...................................................................... The .config is overwritten when added to coreboot.rom via CBFS at the end of the build (if you choose that option)... should this be a separate file for each of fallback and normal? Since there can be two different versions and/or configurations, would fallback/config and normal/config make more sense? Also the "revision" file might benefit from similar treatment. Signed-off-by: Jeremy Jackson <jerj(a)coplanar.net> Change-Id: I3e904e44137f731f239f51dbf224965f33838e19 --- M Makefile.inc 1 file changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/42028/1 diff --git a/Makefile.inc b/Makefile.inc index 86467a6..b547f11 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -1195,13 +1195,13 @@ vgaroms/seavgabios.bin-file := $(CONFIG_PAYLOAD_VGABIOS_FILE) vgaroms/seavgabios.bin-type := raw -cbfs-files-$(CONFIG_INCLUDE_CONFIG_FILE) += config -config-file := $(DOTCONFIG):defconfig -config-type := raw +cbfs-files-$(CONFIG_INCLUDE_CONFIG_FILE) += $(CONFIG_CBFS_PREFIX)/config +$(CONFIG_CBFS_PREFIX)/config-file := $(DOTCONFIG):defconfig +$(CONFIG_CBFS_PREFIX)/config-type := raw -cbfs-files-$(CONFIG_INCLUDE_CONFIG_FILE) += revision -revision-file := $(obj)/build.h -revision-type := raw +cbfs-files-$(CONFIG_INCLUDE_CONFIG_FILE) += $(CONFIG_CBFS_PREFIX)/revision +$(CONFIG_CBFS_PREFIX)/revision-file := $(obj)/build.h +$(CONFIG_CBFS_PREFIX)/revision-type := raw BOOTSPLASH_SUFFIX=$(suffix $(call strip_quotes,$(CONFIG_BOOTSPLASH_FILE))) cbfs-files-$(CONFIG_BOOTSPLASH_IMAGE) += bootsplash$(BOOTSPLASH_SUFFIX) -- To view, visit https://review.coreboot.org/c/coreboot/+/42028 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e904e44137f731f239f51dbf224965f33838e19 Gerrit-Change-Number: 42028 Gerrit-PatchSet: 1 Gerrit-Owner: Jeremy Jackson <jerj(a)coplanar.net> Gerrit-MessageType: newchange

7 14

Change in coreboot[master]: WIP: Hash RAM contents on S3 entry and verify on S3 resume
by Raul Rangel (Code Review) 07 Aug '23

07 Aug '23

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42890 ) Change subject: WIP: Hash RAM contents on S3 entry and verify on S3 resume ...................................................................... WIP: Hash RAM contents on S3 entry and verify on S3 resume I used murmur3 since it's supposed to be fast. Though I don't think the license is really compatible. The ram_hash code still needs some refactoring to reduce duplication and to add the ability to handle unaligned blocks. BUG=b:159081993 TEST=Boot trembyle and see no verification failures. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I6b38facba17bdd57a94987cfb49e71067ff8b769 --- M Makefile.inc M src/arch/x86/acpi_s3.c A src/include/murmur3.h A src/include/ram_hash.h M src/lib/Makefile.inc A src/lib/murmur3.c A src/lib/ram_hash.c M src/soc/amd/picasso/chip.c M src/soc/amd/picasso/memlayout.ld M src/soc/amd/picasso/smihandler.c 10 files changed, 595 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/42890/1 diff --git a/Makefile.inc b/Makefile.inc index 86335d9..b7020e8 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -410,8 +410,8 @@ CFLAGS_common += -Wwrite-strings -Wredundant-decls -Wno-trigraphs -Wimplicit-fallthrough CFLAGS_common += -Wstrict-aliasing -Wshadow -Wdate-time -Wtype-limits -Wvla CFLAGS_common += -Wlogical-op -Wduplicated-cond -Wdangling-else -CFLAGS_common += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer -CFLAGS_common += -ffunction-sections -fdata-sections -fno-pie +CFLAGS_common += -fno-common -ffreestanding -fno-builtin -fmit-frame-pointer +CFLAGS_common += -ffunction-sections -fdata-sections -fno-pie -Wno-implicit-fallthrough ifeq ($(CONFIG_COMPILER_GCC),y) # Don't add these GCC specific flags when running scan-build ifeq ($(CCC_ANALYZER_OUTPUT_FORMAT),) diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c index d4c697e..9c209b2 100644 --- a/src/arch/x86/acpi_s3.c +++ b/src/arch/x86/acpi_s3.c @@ -9,6 +9,7 @@ #include <cpu/x86/smm.h> #include <fallback.h> #include <timestamp.h> +#include <ram_hash.h> #include <romstage_handoff.h> #if ENV_RAMSTAGE || ENV_POSTCAR @@ -70,6 +71,8 @@ timestamp_add_now(TS_ACPI_WAKE_JUMP); + verify_ram(); + acpi_do_wakeup((uintptr_t)vector); } diff --git a/src/include/murmur3.h b/src/include/murmur3.h new file mode 100644 index 0000000..138f87f --- /dev/null +++ b/src/include/murmur3.h @@ -0,0 +1,29 @@ +//----------------------------------------------------------------------------- +// MurmurHash3 was written by Austin Appleby, and is placed in the +// public domain. The author hereby disclaims copyright to this source +// code. + +#ifndef _MURMURHASH3_H_ +#define _MURMURHASH3_H_ + +#include <stdint.h> + +#ifdef __cplusplus +extern "C" { +#endif + +//----------------------------------------------------------------------------- + +void MurmurHash3_x86_32 (const void *key, int len, uint32_t seed, uint32_t *out); + +void MurmurHash3_x86_128(const void *key, int len, uint32_t seed, void *out); + +void MurmurHash3_x64_128(const void *key, int len, uint32_t seed, void *out); + +//----------------------------------------------------------------------------- + +#ifdef __cplusplus +} +#endif + +#endif // _MURMURHASH3_H_ diff --git a/src/include/ram_hash.h b/src/include/ram_hash.h new file mode 100644 index 0000000..67eaa76 --- /dev/null +++ b/src/include/ram_hash.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef RAM_HASH_H +#define RAM_HASH_H + +void hash_ram(void); +void verify_ram(void); + +#endif /* RAM_HASH_H */ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index e0003bd..5bf0df2 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -145,6 +145,10 @@ ramstage-y += imd_cbmem.c ramstage-y += imd.c +bootblock-y += ram_hash.c crc32.c murmur3.c +ramstage-y += ram_hash.c crc32.c murmur3.c +smm-y += ram_hash.c crc32.c murmur3.c + postcar-$(CONFIG_VENDOR_EMULATION) += ramdetect.c postcar-y += cbmem_common.c postcar-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c diff --git a/src/lib/murmur3.c b/src/lib/murmur3.c new file mode 100644 index 0000000..f2b6b18 --- /dev/null +++ b/src/lib/murmur3.c @@ -0,0 +1,314 @@ +//----------------------------------------------------------------------------- +// MurmurHash3 was written by Austin Appleby, and is placed in the public +// domain. The author hereby disclaims copyright to this source code. + +// Note - The x86 and x64 versions do _not_ produce the same results, as the +// algorithms are optimized for their respective platforms. You can still +// compile and run any of them on any platform, but your performance with the +// non-native version will be less than optimal. + +#include "murmur3.h" + +//----------------------------------------------------------------------------- +// Platform-specific functions and macros + +#ifdef __GNUC__ +#define FORCE_INLINE __attribute__((always_inline)) inline +#else +#define FORCE_INLINE inline +#endif + +static FORCE_INLINE uint32_t rotl32 ( uint32_t x, int8_t r ) +{ + return (x << r) | (x >> (32 - r)); +} + +static FORCE_INLINE uint64_t rotl64 ( uint64_t x, int8_t r ) +{ + return (x << r) | (x >> (64 - r)); +} + +#define ROTL32(x,y) rotl32(x,y) +#define ROTL64(x,y) rotl64(x,y) + +#define BIG_CONSTANT(x) (x##LLU) + +//----------------------------------------------------------------------------- +// Block read - if your platform needs to do endian-swapping or can only +// handle aligned reads, do the conversion here + +#define getblock(p, i) (p[i]) + +//----------------------------------------------------------------------------- +// Finalization mix - force all bits of a hash block to avalanche + +static FORCE_INLINE uint32_t fmix32 ( uint32_t h ) +{ + h ^= h >> 16; + h *= 0x85ebca6b; + h ^= h >> 13; + h *= 0xc2b2ae35; + h ^= h >> 16; + + return h; +} + +//---------- + +static FORCE_INLINE uint64_t fmix64 ( uint64_t k ) +{ + k ^= k >> 33; + k *= BIG_CONSTANT(0xff51afd7ed558ccd); + k ^= k >> 33; + k *= BIG_CONSTANT(0xc4ceb9fe1a85ec53); + k ^= k >> 33; + + return k; +} + +//----------------------------------------------------------------------------- + +void MurmurHash3_x86_32 ( const void * key, int len, + uint32_t seed, uint32_t * out ) +{ + const uint8_t * data = (const uint8_t*)key; + const int nblocks = len / 4; + int i; + + uint32_t h1 = seed; + + uint32_t c1 = 0xcc9e2d51; + uint32_t c2 = 0x1b873593; + + //---------- + // body + + const uint32_t * blocks = (const uint32_t *)(data + nblocks*4); + + for(i = -nblocks; i; i++) + { + uint32_t k1 = getblock(blocks,i); + + k1 *= c1; + k1 = ROTL32(k1,15); + k1 *= c2; + + h1 ^= k1; + h1 = ROTL32(h1,13); + h1 = h1*5+0xe6546b64; + } + + //---------- + // tail + + const uint8_t * tail = (const uint8_t*)(data + nblocks*4); + + uint32_t k1 = 0; + + switch(len & 3) + { + case 3: k1 ^= tail[2] << 16; + case 2: k1 ^= tail[1] << 8; + case 1: k1 ^= tail[0]; + k1 *= c1; k1 = ROTL32(k1,15); k1 *= c2; h1 ^= k1; + }; + + //---------- + // finalization + + h1 ^= len; + + h1 = fmix32(h1); + + *(uint32_t*)out = h1; +} + +//----------------------------------------------------------------------------- + +void MurmurHash3_x86_128 ( const void * key, const int len, + uint32_t seed, void * out ) +{ + const uint8_t * data = (const uint8_t*)key; + const int nblocks = len / 16; + int i; + + uint32_t h1 = seed; + uint32_t h2 = seed; + uint32_t h3 = seed; + uint32_t h4 = seed; + + uint32_t c1 = 0x239b961b; + uint32_t c2 = 0xab0e9789; + uint32_t c3 = 0x38b34ae5; + uint32_t c4 = 0xa1e38b93; + + //---------- + // body + + const uint32_t * blocks = (const uint32_t *)(data + nblocks*16); + + for(i = -nblocks; i; i++) + { + uint32_t k1 = getblock(blocks,i*4+0); + uint32_t k2 = getblock(blocks,i*4+1); + uint32_t k3 = getblock(blocks,i*4+2); + uint32_t k4 = getblock(blocks,i*4+3); + + k1 *= c1; k1 = ROTL32(k1,15); k1 *= c2; h1 ^= k1; + + h1 = ROTL32(h1,19); h1 += h2; h1 = h1*5+0x561ccd1b; + + k2 *= c2; k2 = ROTL32(k2,16); k2 *= c3; h2 ^= k2; + + h2 = ROTL32(h2,17); h2 += h3; h2 = h2*5+0x0bcaa747; + + k3 *= c3; k3 = ROTL32(k3,17); k3 *= c4; h3 ^= k3; + + h3 = ROTL32(h3,15); h3 += h4; h3 = h3*5+0x96cd1c35; + + k4 *= c4; k4 = ROTL32(k4,18); k4 *= c1; h4 ^= k4; + + h4 = ROTL32(h4,13); h4 += h1; h4 = h4*5+0x32ac3b17; + } + + //---------- + // tail + + const uint8_t * tail = (const uint8_t*)(data + nblocks*16); + + uint32_t k1 = 0; + uint32_t k2 = 0; + uint32_t k3 = 0; + uint32_t k4 = 0; + + switch(len & 15) + { + case 15: k4 ^= tail[14] << 16; + case 14: k4 ^= tail[13] << 8; + case 13: k4 ^= tail[12] << 0; + k4 *= c4; k4 = ROTL32(k4,18); k4 *= c1; h4 ^= k4; + + case 12: k3 ^= tail[11] << 24; + case 11: k3 ^= tail[10] << 16; + case 10: k3 ^= tail[ 9] << 8; + case 9: k3 ^= tail[ 8] << 0; + k3 *= c3; k3 = ROTL32(k3,17); k3 *= c4; h3 ^= k3; + + case 8: k2 ^= tail[ 7] << 24; + case 7: k2 ^= tail[ 6] << 16; + case 6: k2 ^= tail[ 5] << 8; + case 5: k2 ^= tail[ 4] << 0; + k2 *= c2; k2 = ROTL32(k2,16); k2 *= c3; h2 ^= k2; + + case 4: k1 ^= tail[ 3] << 24; + case 3: k1 ^= tail[ 2] << 16; + case 2: k1 ^= tail[ 1] << 8; + case 1: k1 ^= tail[ 0] << 0; + k1 *= c1; k1 = ROTL32(k1,15); k1 *= c2; h1 ^= k1; + }; + + //---------- + // finalization + + h1 ^= len; h2 ^= len; h3 ^= len; h4 ^= len; + + h1 += h2; h1 += h3; h1 += h4; + h2 += h1; h3 += h1; h4 += h1; + + h1 = fmix32(h1); + h2 = fmix32(h2); + h3 = fmix32(h3); + h4 = fmix32(h4); + + h1 += h2; h1 += h3; h1 += h4; + h2 += h1; h3 += h1; h4 += h1; + + ((uint32_t*)out)[0] = h1; + ((uint32_t*)out)[1] = h2; + ((uint32_t*)out)[2] = h3; + ((uint32_t*)out)[3] = h4; +} + +//----------------------------------------------------------------------------- + +void MurmurHash3_x64_128 ( const void * key, const int len, + const uint32_t seed, void * out ) +{ + const uint8_t * data = (const uint8_t*)key; + const int nblocks = len / 16; + int i; + + uint64_t h1 = seed; + uint64_t h2 = seed; + + uint64_t c1 = BIG_CONSTANT(0x87c37b91114253d5); + uint64_t c2 = BIG_CONSTANT(0x4cf5ad432745937f); + + //---------- + // body + + const uint64_t * blocks = (const uint64_t *)(data); + + for(i = 0; i < nblocks; i++) + { + uint64_t k1 = getblock(blocks,i*2+0); + uint64_t k2 = getblock(blocks,i*2+1); + + k1 *= c1; k1 = ROTL64(k1,31); k1 *= c2; h1 ^= k1; + + h1 = ROTL64(h1,27); h1 += h2; h1 = h1*5+0x52dce729; + + k2 *= c2; k2 = ROTL64(k2,33); k2 *= c1; h2 ^= k2; + + h2 = ROTL64(h2,31); h2 += h1; h2 = h2*5+0x38495ab5; + } + + //---------- + // tail + + const uint8_t * tail = (const uint8_t*)(data + nblocks*16); + + uint64_t k1 = 0; + uint64_t k2 = 0; + + switch(len & 15) + { + case 15: k2 ^= (uint64_t)(tail[14]) << 48; + case 14: k2 ^= (uint64_t)(tail[13]) << 40; + case 13: k2 ^= (uint64_t)(tail[12]) << 32; + case 12: k2 ^= (uint64_t)(tail[11]) << 24; + case 11: k2 ^= (uint64_t)(tail[10]) << 16; + case 10: k2 ^= (uint64_t)(tail[ 9]) << 8; + case 9: k2 ^= (uint64_t)(tail[ 8]) << 0; + k2 *= c2; k2 = ROTL64(k2,33); k2 *= c1; h2 ^= k2; + + case 8: k1 ^= (uint64_t)(tail[ 7]) << 56; + case 7: k1 ^= (uint64_t)(tail[ 6]) << 48; + case 6: k1 ^= (uint64_t)(tail[ 5]) << 40; + case 5: k1 ^= (uint64_t)(tail[ 4]) << 32; + case 4: k1 ^= (uint64_t)(tail[ 3]) << 24; + case 3: k1 ^= (uint64_t)(tail[ 2]) << 16; + case 2: k1 ^= (uint64_t)(tail[ 1]) << 8; + case 1: k1 ^= (uint64_t)(tail[ 0]) << 0; + k1 *= c1; k1 = ROTL64(k1,31); k1 *= c2; h1 ^= k1; + }; + + //---------- + // finalization + + h1 ^= len; h2 ^= len; + + h1 += h2; + h2 += h1; + + h1 = fmix64(h1); + h2 = fmix64(h2); + + h1 += h2; + h2 += h1; + + ((uint64_t*)out)[0] = h1; + ((uint64_t*)out)[1] = h2; +} + +//----------------------------------------------------------------------------- diff --git a/src/lib/ram_hash.c b/src/lib/ram_hash.c new file mode 100644 index 0000000..9f07183 --- /dev/null +++ b/src/lib/ram_hash.c @@ -0,0 +1,223 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdint.h> +#include <murmur3.h> +#include <ram_hash.h> +#include <string.h> +#include <lib.h> +#include <console/console.h> +#include <commonlib/bsd/helpers.h> + +#define HASH_BUFFER 0x2BD000 +#define EHASH_BUFFER 0x3BD000 +// extern char HASH_BUFFER[]; +// extern char EHASH_BUFFER[]; + +struct hash_range { + uintptr_t start; + uintptr_t end; + unsigned int block_size; + unsigned int diff; +}; + +struct hash_entry { + uint32_t hash; + uint32_t data[]; +}; + +struct hash_range mem_layout[] = { + { + .start = 0x1000, + .end = 0xa0000, + .block_size = 1 * KiB, + .diff = 1 + }, + { + .start = 0x3bd000, + .end = 0x3c0000, + .block_size = 4 * KiB, + .diff = 0 + }, + { + .start = 0x3c0000, + .end = 0xcc4c0000, + .block_size = 256 * KiB, + .diff = 0 + }, + { + .start = 0xcc4c0000, + .end = 0xcc51c000, + .block_size = 4 * KiB, + .diff = 0 + }, +}; + +static struct hash_entry *hash_range(const struct hash_range *range, struct hash_entry *entry, + size_t buffer_size) +{ + unsigned int total_blocks = (range->end - range->start) / range->block_size; + void *current; + unsigned int i; + + for (i = 0; i < total_blocks; ++i) { + current = (void *)(range->start + i * range->block_size); + + if (!(i % 256)) + printk(BIOS_DEBUG, "%s: block %u/%u @ %p\n", __func__, i, total_blocks, + current); + + // printk(BIOS_ERR, "%s: buffer_size: %zd\n", __func__, buffer_size); + + if (buffer_size < sizeof(*entry)) { + printk(BIOS_ERR, "%s: Hash buffer is too small for entry\n", __func__); + return NULL; + } + + // printk(BIOS_ERR, "%s: current: %p\n", __func__, current); + // printk(BIOS_ERR, "%s: current_entry: %p\n", __func__, entry); + + /* Allocate one entry in the buffer */ + buffer_size -= sizeof(*entry); + + MurmurHash3_x86_32(current, range->block_size, 0xDEADBEEF, &entry->hash); + // printk(BIOS_ERR, "%s: crc: %#x\n", __func__, entry->hash); + + if (range->diff) { + if (buffer_size < range->block_size) { + printk(BIOS_DEBUG, "%s: Hash buffer is too small for data\n", + __func__); + return NULL; + } + + /* Allocate diff size in buffer */ + buffer_size -= range->block_size; + memcpy(entry->data, current, range->block_size); + + entry = (struct hash_entry *)((uintptr_t)(entry + 1) + + range->block_size); + } else { + entry++; + } + // printk(BIOS_ERR, "%s: next_entry: %p\n", __func__, entry); + } + + return entry; +} + +void hash_ram(void) +{ + struct hash_entry *current_entry = (struct hash_entry *)HASH_BUFFER; + struct hash_range *range; + unsigned int i; + + printk(BIOS_INFO, "%s: Start: HASH_BUFFER: %#x, EHASH_BUFFER: %#x\n", __func__, + HASH_BUFFER, EHASH_BUFFER); + + for (i = 0; i < ARRAY_SIZE(mem_layout); ++i) { + range = &mem_layout[i]; + printk(BIOS_DEBUG, "%s: Hashing range %p -> %p\n", __func__, + (void *)range->start, (void *)range->end); + current_entry = + hash_range(range, current_entry, + ((uintptr_t)EHASH_BUFFER - (uintptr_t)current_entry)); + + if (!current_entry) { + printk(BIOS_ERR, "%s: Hash buffer is too small\n", __func__); + break; + } + } + + printk(BIOS_INFO, "%s: Done\n", __func__); +} + +static struct hash_entry *verify_range(const struct hash_range *range, struct hash_entry *entry, + size_t buffer_size) +{ + unsigned int total_blocks = (range->end - range->start) / range->block_size; + void *current; + unsigned int i; + uint32_t crc; + + for (i = 0; i < total_blocks; ++i) { + current = (void *)(range->start + i * range->block_size); + + if (!(i % 256)) + printk(BIOS_DEBUG, "%s: block %u/%u @ %p\n", __func__, i, total_blocks, + current); + + // printk(BIOS_ERR, "%s: buffer_size: %zd\n", __func__, buffer_size); + + if (buffer_size < sizeof(*entry)) { + printk(BIOS_ERR, "%s: Hash buffer is too small for entry\n", __func__); + return NULL; + } + + // printk(BIOS_ERR, "%s: current: %p\n", __func__, current); + // printk(BIOS_ERR, "%s: current_entry: %p\n", __func__, entry); + + /* Allocate one entry in the buffer */ + buffer_size -= sizeof(*entry); + + MurmurHash3_x86_32(current, range->block_size, 0xDEADBEEF, &crc); + // printk(BIOS_ERR, "%s: crc: %#x\n", __func__, entry->hash); + + if (crc != entry->hash) { + printk(BIOS_ERR, "%s: crc error at %p. %x != %x\n", __func__, current, + crc, entry->hash); + } + + if (range->diff) { + if (buffer_size < range->block_size) { + printk(BIOS_DEBUG, "%s: Hash buffer is too small for data\n", + __func__); + return NULL; + } + + /* Allocate diff size in buffer */ + buffer_size -= range->block_size; + + if (crc != entry->hash) { + + printk(BIOS_ERR, "Expected:\n"); + hexdump(entry->data, range->block_size); + + printk(BIOS_ERR, "Actual:\n"); + hexdump(current, range->block_size); + } + + entry = (struct hash_entry *)((uintptr_t)(entry + 1) + + range->block_size); + } else { + entry++; + } + // printk(BIOS_ERR, "%s: next_entry: %p\n", __func__, entry); + } + + return entry; +} + +void verify_ram() +{ + struct hash_entry *current_entry = (struct hash_entry *)HASH_BUFFER; + struct hash_range *range; + unsigned int i; + + printk(BIOS_INFO, "%s: Start: HASH_BUFFER: %#x, EHASH_BUFFER: %#x\n", __func__, + HASH_BUFFER, EHASH_BUFFER); + + for (i = 0; i < ARRAY_SIZE(mem_layout); ++i) { + range = &mem_layout[i]; + printk(BIOS_DEBUG, "%s: Verifying range %p -> %p\n", __func__, + (void *)range->start, (void *)range->end); + current_entry = + verify_range(range, current_entry, + ((uintptr_t)EHASH_BUFFER - (uintptr_t)current_entry)); + + if (!current_entry) { + printk(BIOS_ERR, "%s: Hash buffer is too small\n", __func__); + break; + } + } + + printk(BIOS_INFO, "%s: Done\n", __func__); +} diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c index 2abe54e..678ce03 100644 --- a/src/soc/amd/picasso/chip.c +++ b/src/soc/amd/picasso/chip.c @@ -14,6 +14,7 @@ #include <soc/southbridge.h> #include "chip.h" #include <fsp/api.h> +#include <ram_hash.h> /* Supplied by i2c.c */ extern struct device_operations picasso_i2c_mmio_ops; @@ -184,6 +185,7 @@ static void picasso_os_entry(void *unused) { picasso_disable_paging(NULL); + verify_ram(); } struct chip_operations soc_amd_picasso_ops = { diff --git a/src/soc/amd/picasso/memlayout.ld b/src/soc/amd/picasso/memlayout.ld index 27c72a2..a128019 100644 --- a/src/soc/amd/picasso/memlayout.ld +++ b/src/soc/amd/picasso/memlayout.ld @@ -92,6 +92,7 @@ REGION(pagetables, CONFIG_PAGE_TABLE_ADDR, 4096 * 12, 8) REGION(pdpt, ., 32, 32) + REGION(hash_buffer, 0x2BD000, 1M, 4) EARLY_RESERVED_DRAM_END(.) RAMSTAGE(CONFIG_RAMBASE, 8M) diff --git a/src/soc/amd/picasso/smihandler.c b/src/soc/amd/picasso/smihandler.c index 992dc2b..616f116 100644 --- a/src/soc/amd/picasso/smihandler.c +++ b/src/soc/amd/picasso/smihandler.c @@ -3,6 +3,7 @@ #include <arch/io.h> #include <console/console.h> #include <cpu/x86/smm.h> +#include <ram_hash.h> #include <cpu/x86/cache.h> #include <cpu/amd/amd64_save_state.h> #include <acpi/acpi.h> @@ -144,6 +145,13 @@ printk(BIOS_SPEW, "SMI#: SLP = 0x%04x\n", pm1cnt); slp_typ = acpi_sleep_from_pm1(pm1cnt); + /* + * Hash RAM as soon as we know we are entering S3 to catch any problems + * caused by the SMM handler, PSP, or SMU. + */ + if (slp_typ == ACPI_S3) + hash_ram(); + /* Do any mainboard sleep handling */ mainboard_smi_sleep(slp_typ); -- To view, visit https://review.coreboot.org/c/coreboot/+/42890 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b38facba17bdd57a94987cfb49e71067ff8b769 Gerrit-Change-Number: 42890 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

3 8

Change in coreboot[master]: WIP: lib: Add murmur3 algorithm for RAM hash
by Raul Rangel (Code Review) 07 Aug '23

07 Aug '23

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43301 ) Change subject: WIP: lib: Add murmur3 algorithm for RAM hash ...................................................................... WIP: lib: Add murmur3 algorithm for RAM hash This is the murmur3 algorithm from https://github.com/PeterScott/murmur3. I'm not sure we can even include this since it's public domain. We might need to use another hash algorithm. I picked it because it's supposed to be fast. I didn't cleanup the code at all. This is why -Wno-implicit-fallthrough was added to the CFLAGS. BUG=b:159081993 TEST=Suspend trembyle and see hashes being generated. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I9dfd371c67966bf7a342fdb5562445e63afce664 --- M Makefile.inc A src/include/murmur3.h M src/lib/Kconfig M src/lib/Makefile.inc A src/lib/murmur3.c A src/lib/ram_hash_murmur.c 6 files changed, 362 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/43301/1 diff --git a/Makefile.inc b/Makefile.inc index 89bb3e4..9b39b39 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -421,7 +421,7 @@ CFLAGS_common += -Wstrict-aliasing -Wshadow -Wdate-time -Wtype-limits -Wvla CFLAGS_common += -Wlogical-op -Wduplicated-cond -Wdangling-else CFLAGS_common += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer -CFLAGS_common += -ffunction-sections -fdata-sections -fno-pie +CFLAGS_common += -ffunction-sections -fdata-sections -fno-pie -Wno-implicit-fallthrough ifeq ($(CONFIG_COMPILER_GCC),y) # Don't add these GCC specific flags when running scan-build ifeq ($(CCC_ANALYZER_OUTPUT_FORMAT),) diff --git a/src/include/murmur3.h b/src/include/murmur3.h new file mode 100644 index 0000000..138f87f --- /dev/null +++ b/src/include/murmur3.h @@ -0,0 +1,29 @@ +//----------------------------------------------------------------------------- +// MurmurHash3 was written by Austin Appleby, and is placed in the +// public domain. The author hereby disclaims copyright to this source +// code. + +#ifndef _MURMURHASH3_H_ +#define _MURMURHASH3_H_ + +#include <stdint.h> + +#ifdef __cplusplus +extern "C" { +#endif + +//----------------------------------------------------------------------------- + +void MurmurHash3_x86_32 (const void *key, int len, uint32_t seed, uint32_t *out); + +void MurmurHash3_x86_128(const void *key, int len, uint32_t seed, void *out); + +void MurmurHash3_x64_128(const void *key, int len, uint32_t seed, void *out); + +//----------------------------------------------------------------------------- + +#ifdef __cplusplus +} +#endif + +#endif // _MURMURHASH3_H_ diff --git a/src/lib/Kconfig b/src/lib/Kconfig index 8eeceec..0e4fa88 100644 --- a/src/lib/Kconfig +++ b/src/lib/Kconfig @@ -111,6 +111,8 @@ depends on ENABLE_RAM_HASH help The hash algorithm to use for RAM hash. -# TODO: Add algorithms + +config RAM_HASH_ALGO_MURMUR3 + bool "murmur3" endchoice diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 05df3c6..54b23e2 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -148,6 +148,9 @@ ramstage-$(CONFIG_ENABLE_RAM_HASH) += ram_hash.c smm-$(CONFIG_ENABLE_RAM_HASH) += ram_hash.c +ramstage-$(CONFIG_RAM_HASH_ALGO_MURMUR3) += ram_hash_murmur.c murmur3.c +smm-$(CONFIG_RAM_HASH_ALGO_MURMUR3) += ram_hash_murmur.c murmur3.c + postcar-$(CONFIG_VENDOR_EMULATION) += ramdetect.c postcar-y += cbmem_common.c postcar-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c diff --git a/src/lib/murmur3.c b/src/lib/murmur3.c new file mode 100644 index 0000000..f2b6b18 --- /dev/null +++ b/src/lib/murmur3.c @@ -0,0 +1,314 @@ +//----------------------------------------------------------------------------- +// MurmurHash3 was written by Austin Appleby, and is placed in the public +// domain. The author hereby disclaims copyright to this source code. + +// Note - The x86 and x64 versions do _not_ produce the same results, as the +// algorithms are optimized for their respective platforms. You can still +// compile and run any of them on any platform, but your performance with the +// non-native version will be less than optimal. + +#include "murmur3.h" + +//----------------------------------------------------------------------------- +// Platform-specific functions and macros + +#ifdef __GNUC__ +#define FORCE_INLINE __attribute__((always_inline)) inline +#else +#define FORCE_INLINE inline +#endif + +static FORCE_INLINE uint32_t rotl32 ( uint32_t x, int8_t r ) +{ + return (x << r) | (x >> (32 - r)); +} + +static FORCE_INLINE uint64_t rotl64 ( uint64_t x, int8_t r ) +{ + return (x << r) | (x >> (64 - r)); +} + +#define ROTL32(x,y) rotl32(x,y) +#define ROTL64(x,y) rotl64(x,y) + +#define BIG_CONSTANT(x) (x##LLU) + +//----------------------------------------------------------------------------- +// Block read - if your platform needs to do endian-swapping or can only +// handle aligned reads, do the conversion here + +#define getblock(p, i) (p[i]) + +//----------------------------------------------------------------------------- +// Finalization mix - force all bits of a hash block to avalanche + +static FORCE_INLINE uint32_t fmix32 ( uint32_t h ) +{ + h ^= h >> 16; + h *= 0x85ebca6b; + h ^= h >> 13; + h *= 0xc2b2ae35; + h ^= h >> 16; + + return h; +} + +//---------- + +static FORCE_INLINE uint64_t fmix64 ( uint64_t k ) +{ + k ^= k >> 33; + k *= BIG_CONSTANT(0xff51afd7ed558ccd); + k ^= k >> 33; + k *= BIG_CONSTANT(0xc4ceb9fe1a85ec53); + k ^= k >> 33; + + return k; +} + +//----------------------------------------------------------------------------- + +void MurmurHash3_x86_32 ( const void * key, int len, + uint32_t seed, uint32_t * out ) +{ + const uint8_t * data = (const uint8_t*)key; + const int nblocks = len / 4; + int i; + + uint32_t h1 = seed; + + uint32_t c1 = 0xcc9e2d51; + uint32_t c2 = 0x1b873593; + + //---------- + // body + + const uint32_t * blocks = (const uint32_t *)(data + nblocks*4); + + for(i = -nblocks; i; i++) + { + uint32_t k1 = getblock(blocks,i); + + k1 *= c1; + k1 = ROTL32(k1,15); + k1 *= c2; + + h1 ^= k1; + h1 = ROTL32(h1,13); + h1 = h1*5+0xe6546b64; + } + + //---------- + // tail + + const uint8_t * tail = (const uint8_t*)(data + nblocks*4); + + uint32_t k1 = 0; + + switch(len & 3) + { + case 3: k1 ^= tail[2] << 16; + case 2: k1 ^= tail[1] << 8; + case 1: k1 ^= tail[0]; + k1 *= c1; k1 = ROTL32(k1,15); k1 *= c2; h1 ^= k1; + }; + + //---------- + // finalization + + h1 ^= len; + + h1 = fmix32(h1); + + *(uint32_t*)out = h1; +} + +//----------------------------------------------------------------------------- + +void MurmurHash3_x86_128 ( const void * key, const int len, + uint32_t seed, void * out ) +{ + const uint8_t * data = (const uint8_t*)key; + const int nblocks = len / 16; + int i; + + uint32_t h1 = seed; + uint32_t h2 = seed; + uint32_t h3 = seed; + uint32_t h4 = seed; + + uint32_t c1 = 0x239b961b; + uint32_t c2 = 0xab0e9789; + uint32_t c3 = 0x38b34ae5; + uint32_t c4 = 0xa1e38b93; + + //---------- + // body + + const uint32_t * blocks = (const uint32_t *)(data + nblocks*16); + + for(i = -nblocks; i; i++) + { + uint32_t k1 = getblock(blocks,i*4+0); + uint32_t k2 = getblock(blocks,i*4+1); + uint32_t k3 = getblock(blocks,i*4+2); + uint32_t k4 = getblock(blocks,i*4+3); + + k1 *= c1; k1 = ROTL32(k1,15); k1 *= c2; h1 ^= k1; + + h1 = ROTL32(h1,19); h1 += h2; h1 = h1*5+0x561ccd1b; + + k2 *= c2; k2 = ROTL32(k2,16); k2 *= c3; h2 ^= k2; + + h2 = ROTL32(h2,17); h2 += h3; h2 = h2*5+0x0bcaa747; + + k3 *= c3; k3 = ROTL32(k3,17); k3 *= c4; h3 ^= k3; + + h3 = ROTL32(h3,15); h3 += h4; h3 = h3*5+0x96cd1c35; + + k4 *= c4; k4 = ROTL32(k4,18); k4 *= c1; h4 ^= k4; + + h4 = ROTL32(h4,13); h4 += h1; h4 = h4*5+0x32ac3b17; + } + + //---------- + // tail + + const uint8_t * tail = (const uint8_t*)(data + nblocks*16); + + uint32_t k1 = 0; + uint32_t k2 = 0; + uint32_t k3 = 0; + uint32_t k4 = 0; + + switch(len & 15) + { + case 15: k4 ^= tail[14] << 16; + case 14: k4 ^= tail[13] << 8; + case 13: k4 ^= tail[12] << 0; + k4 *= c4; k4 = ROTL32(k4,18); k4 *= c1; h4 ^= k4; + + case 12: k3 ^= tail[11] << 24; + case 11: k3 ^= tail[10] << 16; + case 10: k3 ^= tail[ 9] << 8; + case 9: k3 ^= tail[ 8] << 0; + k3 *= c3; k3 = ROTL32(k3,17); k3 *= c4; h3 ^= k3; + + case 8: k2 ^= tail[ 7] << 24; + case 7: k2 ^= tail[ 6] << 16; + case 6: k2 ^= tail[ 5] << 8; + case 5: k2 ^= tail[ 4] << 0; + k2 *= c2; k2 = ROTL32(k2,16); k2 *= c3; h2 ^= k2; + + case 4: k1 ^= tail[ 3] << 24; + case 3: k1 ^= tail[ 2] << 16; + case 2: k1 ^= tail[ 1] << 8; + case 1: k1 ^= tail[ 0] << 0; + k1 *= c1; k1 = ROTL32(k1,15); k1 *= c2; h1 ^= k1; + }; + + //---------- + // finalization + + h1 ^= len; h2 ^= len; h3 ^= len; h4 ^= len; + + h1 += h2; h1 += h3; h1 += h4; + h2 += h1; h3 += h1; h4 += h1; + + h1 = fmix32(h1); + h2 = fmix32(h2); + h3 = fmix32(h3); + h4 = fmix32(h4); + + h1 += h2; h1 += h3; h1 += h4; + h2 += h1; h3 += h1; h4 += h1; + + ((uint32_t*)out)[0] = h1; + ((uint32_t*)out)[1] = h2; + ((uint32_t*)out)[2] = h3; + ((uint32_t*)out)[3] = h4; +} + +//----------------------------------------------------------------------------- + +void MurmurHash3_x64_128 ( const void * key, const int len, + const uint32_t seed, void * out ) +{ + const uint8_t * data = (const uint8_t*)key; + const int nblocks = len / 16; + int i; + + uint64_t h1 = seed; + uint64_t h2 = seed; + + uint64_t c1 = BIG_CONSTANT(0x87c37b91114253d5); + uint64_t c2 = BIG_CONSTANT(0x4cf5ad432745937f); + + //---------- + // body + + const uint64_t * blocks = (const uint64_t *)(data); + + for(i = 0; i < nblocks; i++) + { + uint64_t k1 = getblock(blocks,i*2+0); + uint64_t k2 = getblock(blocks,i*2+1); + + k1 *= c1; k1 = ROTL64(k1,31); k1 *= c2; h1 ^= k1; + + h1 = ROTL64(h1,27); h1 += h2; h1 = h1*5+0x52dce729; + + k2 *= c2; k2 = ROTL64(k2,33); k2 *= c1; h2 ^= k2; + + h2 = ROTL64(h2,31); h2 += h1; h2 = h2*5+0x38495ab5; + } + + //---------- + // tail + + const uint8_t * tail = (const uint8_t*)(data + nblocks*16); + + uint64_t k1 = 0; + uint64_t k2 = 0; + + switch(len & 15) + { + case 15: k2 ^= (uint64_t)(tail[14]) << 48; + case 14: k2 ^= (uint64_t)(tail[13]) << 40; + case 13: k2 ^= (uint64_t)(tail[12]) << 32; + case 12: k2 ^= (uint64_t)(tail[11]) << 24; + case 11: k2 ^= (uint64_t)(tail[10]) << 16; + case 10: k2 ^= (uint64_t)(tail[ 9]) << 8; + case 9: k2 ^= (uint64_t)(tail[ 8]) << 0; + k2 *= c2; k2 = ROTL64(k2,33); k2 *= c1; h2 ^= k2; + + case 8: k1 ^= (uint64_t)(tail[ 7]) << 56; + case 7: k1 ^= (uint64_t)(tail[ 6]) << 48; + case 6: k1 ^= (uint64_t)(tail[ 5]) << 40; + case 5: k1 ^= (uint64_t)(tail[ 4]) << 32; + case 4: k1 ^= (uint64_t)(tail[ 3]) << 24; + case 3: k1 ^= (uint64_t)(tail[ 2]) << 16; + case 2: k1 ^= (uint64_t)(tail[ 1]) << 8; + case 1: k1 ^= (uint64_t)(tail[ 0]) << 0; + k1 *= c1; k1 = ROTL64(k1,31); k1 *= c2; h1 ^= k1; + }; + + //---------- + // finalization + + h1 ^= len; h2 ^= len; + + h1 += h2; + h2 += h1; + + h1 = fmix64(h1); + h2 = fmix64(h2); + + h1 += h2; + h2 += h1; + + ((uint64_t*)out)[0] = h1; + ((uint64_t*)out)[1] = h2; +} + +//----------------------------------------------------------------------------- diff --git a/src/lib/ram_hash_murmur.c b/src/lib/ram_hash_murmur.c new file mode 100644 index 0000000..4f6ac9b --- /dev/null +++ b/src/lib/ram_hash_murmur.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdint.h> +#include <murmur3.h> +#include <ram_hash.h> + +uint32_t generate_hash(const void *buffer, unsigned int size) +{ + uint32_t hash; + MurmurHash3_x86_32(buffer, size, 0xDEADBEEF, &hash); + return hash; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/43301 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9dfd371c67966bf7a342fdb5562445e63afce664 Gerrit-Change-Number: 43301 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: soc/amd/picasso: Add support for RAM hash
by Raul Rangel (Code Review) 07 Aug '23

07 Aug '23

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43302 ) Change subject: soc/amd/picasso: Add support for RAM hash ...................................................................... soc/amd/picasso: Add support for RAM hash This CL allocates a region in EARLY_DRAM to store the RAM hashes. It also introduces a hard coded memory map based on the current e820 map. In the future we could maybe automate the generate of the hash_ranges. Until now we will need to keep it updated. To enable, add the following to your .config: CONFIG_ENABLE_RAM_HASH=y Hashing RAM from the SMM handler is pretty slow compared to trying it in bootblock. Not sure if the OS has reset the MTRRs. Example of entering S3: coreboot-4.12-1163-gd9cc83a4ce58-dirty Tue Jul 7 21:34:13 UTC 2020 smm starting (log level: 8)... SMI# #0 SMI#: SLP = 0x0c01 hash_ram: Start for_each_range: Processing range 0x1000 -> 0xa0000 Processed block 128: crc: 0x7f00c996. Remaining: 0 MiB Processed block 256: crc: 0x7f00c996. Remaining: 0 MiB Processed block 384: crc: 0x7f00c996. Remaining: 0 MiB Processed block 512: crc: 0x7f00c996. Remaining: 0 MiB for_each_range: Processing range 0x100000 -> 0x2000000 for_each_range: Processing range 0x22cd000 -> 0xcc50c000 Processed block 128: crc: 0x9a22c19c. Remaining: 3107 MiB Processed block 256: crc: 0x9a22c19c. Remaining: 2979 MiB Processed block 384: crc: 0x9a22c19c. Remaining: 2851 MiB ... Example of exiting S3: Timestamp - ACPI wake jump: 36887335255 verify_ram: Start for_each_range: Processing range 0x1000 -> 0xa0000 Processed block 128: crc: 0x7f00c996. Remaining: 0 MiB Processed block 256: crc: 0x7f00c996. Remaining: 0 MiB Processed block 384: crc: 0x7f00c996. Remaining: 0 MiB Processed block 512: crc: 0x7f00c996. Remaining: 0 MiB for_each_range: Processing range 0x100000 -> 0x2000000 for_each_range: Processing range 0x22cd000 -> 0xcc50c000 Processed block 128: crc: 0x9a22c19c. Remaining: 3107 MiB Processed block 256: crc: 0x9a22c19c. Remaining: 2979 MiB Processed block 384: crc: 0x9a22c19c. Remaining: 2851 MiB Processed block 512: crc: 0x9a22c19c. Remaining: 2723 MiB Processed block 640: crc: 0x9a22c19c. Remaining: 2595 MiB Processed block 768: crc: 0x9a22c19c. Remaining: 2467 MiB Processed block 896: crc: 0x9a22c19c. Remaining: 2339 MiB Processed block 1024: crc: 0x9a22c19c. Remaining: 2211 MiB Processed block 1152: crc: 0x9a22c19c. Remaining: 2083 MiB Processed block 1280: crc: 0x9a22c19c. Remaining: 1955 MiB Processed block 1408: crc: 0x9a22c19c. Remaining: 1827 MiB Processed block 1536: crc: 0x9a22c19c. Remaining: 1699 MiB Processed block 1664: crc: 0x9a22c19c. Remaining: 1571 MiB Processed block 1792: crc: 0x9a22c19c. Remaining: 1443 MiB Processed block 1920: crc: 0x9a22c19c. Remaining: 1315 MiB Processed block 2048: crc: 0x9a22c19c. Remaining: 1187 MiB Processed block 2176: crc: 0x9a22c19c. Remaining: 1059 MiB Processed block 2304: crc: 0x9a22c19c. Remaining: 931 MiB Processed block 2432: crc: 0x9a22c19c. Remaining: 803 MiB Processed block 2560: crc: 0x9a22c19c. Remaining: 675 MiB Processed block 2688: crc: 0x9a22c19c. Remaining: 547 MiB Processed block 2816: crc: 0x9a22c19c. Remaining: 419 MiB Processed block 2944: crc: 0x9a22c19c. Remaining: 291 MiB Processed block 3072: crc: 0x9a22c19c. Remaining: 163 MiB Processed block 3200: crc: 0x9a22c19c. Remaining: 35 MiB verify_ram: Done BUG=b:159081993 TEST=S3 suspend and resume on trembyle Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ia9b80044dd794ddfb0b661d517367259917cd944 --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc M src/soc/amd/picasso/memlayout.ld A src/soc/amd/picasso/ram_hash.c M src/soc/amd/picasso/smihandler.c 5 files changed, 65 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/43302/1 diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index fd2a205..2e7ce89 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -57,6 +57,7 @@ select HAVE_CF9_RESET select SUPPORT_CPU_UCODE_IN_CBFS select ACPI_NO_SMI_GNVS + select HAS_RAM_HASH config MEMLAYOUT_LD_FILE string @@ -174,6 +175,20 @@ Sets the size of DRAM allocation for verstage in linker script if running as a separate stage on x86. +config RAM_HASH_ADDR + hex + depends on ENABLE_RAM_HASH + default 0x21CD000 + help + Where in memory to store the hashes. + +config RAM_HASH_SIZE + hex + depends on ENABLE_RAM_HASH + default 0x100000 + help + Size of the RAM_HASH buffer. + config RAMBASE hex default 0x10000000 diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 39269e9..679ee98 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -89,6 +89,9 @@ smm-y += smu.c smm-y += config.c +ramstage-$(CONFIG_ENABLE_RAM_HASH) += ram_hash.c +smm-$(CONFIG_ENABLE_RAM_HASH) += ram_hash.c + CPPFLAGS_common += -I$(src)/soc/amd/picasso CPPFLAGS_common += -I$(src)/soc/amd/picasso/include CPPFLAGS_common += -I$(src)/soc/amd/picasso/acpi diff --git a/src/soc/amd/picasso/memlayout.ld b/src/soc/amd/picasso/memlayout.ld index 6f43ba1..bb15263 100644 --- a/src/soc/amd/picasso/memlayout.ld +++ b/src/soc/amd/picasso/memlayout.ld @@ -89,6 +89,10 @@ VERSTAGE(CONFIG_VERSTAGE_ADDR, CONFIG_VERSTAGE_SIZE) #endif +#if CONFIG(ENABLE_RAM_HASH) + REGION(hash_buffer, 0x21CD000, 1M, 4) +#endif + EARLY_RESERVED_DRAM_END(.) RAMSTAGE(CONFIG_RAMBASE, 8M) diff --git a/src/soc/amd/picasso/ram_hash.c b/src/soc/amd/picasso/ram_hash.c new file mode 100644 index 0000000..c7f0be4 --- /dev/null +++ b/src/soc/amd/picasso/ram_hash.c @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdint.h> +#include <ram_hash.h> +#include <commonlib/bsd/helpers.h> + +struct hash_range mem_layout[] = { + { + .start = 0x1000, + .end = 0xa0000, + .block_size = 1 * KiB, + .diff = 1 + }, + { + .start = 0x100000, + .end = 0x2000000, + .block_size = 1 * MiB, + .diff = 0 + }, + { + .start = 0x22cd000, + .end = 0xcc50c000, + .block_size = 1 * MiB, + .diff = 0 + }, +}; + +void soc_hash_ram(void) +{ + hash_ram(mem_layout, ARRAY_SIZE(mem_layout)); +} +void soc_verify_ram(void) +{ + verify_ram(mem_layout, ARRAY_SIZE(mem_layout)); +} diff --git a/src/soc/amd/picasso/smihandler.c b/src/soc/amd/picasso/smihandler.c index 7e762a9..6832526 100644 --- a/src/soc/amd/picasso/smihandler.c +++ b/src/soc/amd/picasso/smihandler.c @@ -3,6 +3,7 @@ #include <arch/io.h> #include <console/console.h> #include <cpu/x86/smm.h> +#include <ram_hash.h> #include <cpu/x86/cache.h> #include <cpu/amd/amd64_save_state.h> #include <acpi/acpi.h> @@ -144,6 +145,13 @@ printk(BIOS_SPEW, "SMI#: SLP = 0x%04x\n", pm1cnt); slp_typ = acpi_sleep_from_pm1(pm1cnt); + /* + * Hash RAM as soon as we know we are entering S3 to catch any problems + * caused by the SMM handler, PSP, or SMU. + */ + if (slp_typ == ACPI_S3) + soc_hash_ram(); + /* Do any mainboard sleep handling */ mainboard_smi_sleep(slp_typ); -- To view, visit https://review.coreboot.org/c/coreboot/+/43302 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia9b80044dd794ddfb0b661d517367259917cd944 Gerrit-Change-Number: 43302 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

2 3

Change in ...coreboot[master]: nb/intel/sandybridge: Introduce soc/iomap.h
by Patrick Rudolph (Code Review) 07 Aug '23

07 Aug '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32075 Change subject: nb/intel/sandybridge: Introduce soc/iomap.h ...................................................................... nb/intel/sandybridge: Introduce soc/iomap.h Defines the memory ranges used by the northbridge in a separate header. Include the new header and rename the defines to match the one found in soc/intel/common. Change-Id: I93aa0e78ff52e46256debd26601600a96404509f Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/northbridge/intel/sandybridge/Makefile.inc M src/northbridge/intel/sandybridge/acpi.c M src/northbridge/intel/sandybridge/early_init.c A src/northbridge/intel/sandybridge/include/soc/iomap.h M src/northbridge/intel/sandybridge/northbridge.c M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/raminit_mrc.c M src/northbridge/intel/sandybridge/sandybridge.h 8 files changed, 92 insertions(+), 54 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/32075/1 diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index 54a4057..c3d9079 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -15,6 +15,8 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE)$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE),y) +CFLAGS_common += -Isrc/northbridge/intel/sandybridge/include + ramstage-y += ram_calc.c ramstage-y += northbridge.c ramstage-y += pcie.c diff --git a/src/northbridge/intel/sandybridge/acpi.c b/src/northbridge/intel/sandybridge/acpi.c index 4afb546..af2f37b 100644 --- a/src/northbridge/intel/sandybridge/acpi.c +++ b/src/northbridge/intel/sandybridge/acpi.c @@ -92,7 +92,8 @@ unsigned long tmp; tmp = current; - current += acpi_create_dmar_drhd(current, 0, 0, IOMMU_BASE1); + current += acpi_create_dmar_drhd(current, 0, 0, + GFXVT_BASE_ADDRESS); current += acpi_create_dmar_ds_pci(current, 0, 2, 0); current += acpi_create_dmar_ds_pci(current, 0, 2, 1); acpi_dmar_drhd_fixup(tmp, current); @@ -107,8 +108,8 @@ } const unsigned long tmp = current; - current += acpi_create_dmar_drhd(current, - DRHD_INCLUDE_PCI_ALL, 0, IOMMU_BASE2); + current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, + VTVC0_BASE_ADDRESS); current += acpi_create_dmar_ds_ioapic(current, 2, PCH_IOAPIC_PCI_BUS, PCH_IOAPIC_PCI_SLOT, 0); size_t i; diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index 5307a2c..2e0f087 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -35,20 +35,20 @@ return; /* setup BARs */ - MCHBAR32(0x5404) = IOMMU_BASE1 >> 32; - MCHBAR32(0x5400) = IOMMU_BASE1 | 1; - MCHBAR32(0x5414) = IOMMU_BASE2 >> 32; - MCHBAR32(0x5410) = IOMMU_BASE2 | 1; + MCHBAR32(0x5404) = GFXVT_BASE_ADDRESS >> 32; + MCHBAR32(0x5400) = GFXVT_BASE_ADDRESS | 1; + MCHBAR32(0x5414) = VTVC0_BASE_ADDRESS >> 32; + MCHBAR32(0x5410) = VTVC0_BASE_ADDRESS | 1; /* lock policies */ - write32((void *)(IOMMU_BASE1 + 0xff0), 0x80000000); + write32((void *)(GFXVT_BASE_ADDRESS + 0xff0), 0x80000000); const struct device *const azalia = pcidev_on_root(0x1b, 0); if (azalia && azalia->enabled) { - write32((void *)(IOMMU_BASE2 + 0xff0), 0x20000000); - write32((void *)(IOMMU_BASE2 + 0xff0), 0xa0000000); + write32((void *)(VTVC0_BASE_ADDRESS + 0xff0), 0x20000000); + write32((void *)(VTVC0_BASE_ADDRESS + 0xff0), 0xa0000000); } else { - write32((void *)(IOMMU_BASE2 + 0xff0), 0x80000000); + write32((void *)(VTVC0_BASE_ADDRESS + 0xff0), 0x80000000); } } @@ -67,12 +67,12 @@ { printk(BIOS_DEBUG, "Setting up static northbridge registers..."); /* Set up all hardcoded northbridge BARs */ - pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1); - pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR + 4, (0LL+DEFAULT_EPBAR) >> 32); - pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1); - pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4, (0LL+(uintptr_t)DEFAULT_MCHBAR) >> 32); - pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1); - pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, (0LL+(uintptr_t)DEFAULT_DMIBAR) >> 32); + pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, EP_BASE_ADDRESS | 1); + pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR + 4, EP_BASE_ADDRESS >> 32); + pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, MCH_BASE_ADDRESS | 1); + pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4, MCH_BASE_ADDRESS >> 32); + pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, DMI_BASE_ADDRESS | 1); + pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, DMI_BASE_ADDRESS >> 32); printk(BIOS_DEBUG, " done\n"); } diff --git a/src/northbridge/intel/sandybridge/include/soc/iomap.h b/src/northbridge/intel/sandybridge/include/soc/iomap.h new file mode 100644 index 0000000..75fd9d9 --- /dev/null +++ b/src/northbridge/intel/sandybridge/include/soc/iomap.h @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_SANDYBRIDGE_IOMAP_H_ +#define _SOC_SANDYBRIDGE_IOMAP_H_ + +/* + * Memory-mapped I/O registers. + */ +#define MCFG_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS +#define MCFG_BASE_SIZE 0x4000000 + +/* Intel Enhanced Debug region must be 4MB */ + +#define IED_SIZE CONFIG_IED_REGION_SIZE + +#define ILB_BASE_ADDRESS 0xfed08000ULL +#define ILB_BASE_SIZE 0x400 + +#define DMI_BASE_ADDRESS 0xfed18000ULL +#define DMI_BASE_SIZE 0x1000 + +#define MCH_BASE_ADDRESS 0xfed10000ULL +#define MCH_BASE_SIZE 0x4000 + +#define EP_BASE_ADDRESS 0xfed19000ULL +#define EP_BASE_SIZE 0x1000 + +#define GFXVT_BASE_ADDRESS 0xfed90000ULL +#define GFXVT_BASE_SIZE 0x1000 + +#define VTVC0_BASE_ADDRESS 0xfed91000ULL +#define VTVC0_BASE_SIZE 0x1000 + +#define TPM_BASE_ADDRESS 0xfed40000ULL +#define TPM_BASE_SIZE 0x5000 + + +#endif diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 5aa06c8..71dea62 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -112,8 +112,8 @@ /* Reserve IOMMU BARs */ const u32 capid0_a = pci_read_config32(dev, 0xe4); if (!(capid0_a & (1 << 23))) { - mmio_resource(dev, index++, IOMMU_BASE1 >> 10, 4); - mmio_resource(dev, index++, IOMMU_BASE2 >> 10, 4); + mmio_resource(dev, index++, GFXVT_BASE_ADDRESS / KiB, 4); + mmio_resource(dev, index++, VTVC0_BASE_ADDRESS / KiB, 4); } } diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 55df03b..72ae5b0 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -41,23 +41,23 @@ * Channel X = [0, 1] * Command queue index Y = [0, 1, 2, 3] * - * DEFAULT_MCHBAR + 0x4220 + 0x400 * X + 4 * Y: command io register + * MCH_BASE_ADDRESS + 0x4220 + 0x400 * X + 4 * Y: command io register * Controls the DRAM command signals * Bit 0: !RAS * Bit 1: !CAS * Bit 2: !WE * - * DEFAULT_MCHBAR + 0x4200 + 0x400 * X + 4 * Y: addr bankslot io register + * MCH_BASE_ADDRESS + 0x4200 + 0x400 * X + 4 * Y: addr bankslot io register * Controls the address, bank address and slotrank signals * Bit 0-15 : Address * Bit 20-22: Bank Address * Bit 24-25: slotrank * - * DEFAULT_MCHBAR + 0x4230 + 0x400 * X + 4 * Y: idle register + * MCH_BASE_ADDRESS + 0x4230 + 0x400 * X + 4 * Y: idle register * Controls the idle time after issuing this DRAM command * Bit 16-32: number of clock-cylces to idle * - * DEFAULT_MCHBAR + 0x4284 + 0x400 * channel: execute command queue + * MCH_BASE_ADDRESS + 0x4284 + 0x400 * channel: execute command queue * Starts to execute all queued commands * Bit 0 : start DRAM command execution * Bit 18-19 : number of queued commands - 1 diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index c544a74..2382084 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -277,10 +277,10 @@ static void northbridge_fill_pei_data(struct pei_data *pei_data) { - pei_data->mchbar = (uintptr_t)DEFAULT_MCHBAR; - pei_data->dmibar = (uintptr_t)DEFAULT_DMIBAR; - pei_data->epbar = DEFAULT_EPBAR; - pei_data->pciexbar = CONFIG_MMCONF_BASE_ADDRESS; + pei_data->mchbar = MCH_BASE_ADDRESS; + pei_data->dmibar = DMI_BASE_ADDRESS; + pei_data->epbar = EP_BASE_ADDRESS; + pei_data->pciexbar = MCFG_BASE_ADDRESS; pei_data->smbusbar = SMBUS_IO_BASE; pei_data->wdbbar = 0x4000000; pei_data->wdbsize = 0x1000; diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index d7de843..dc9f889 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -17,6 +17,8 @@ #ifndef __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__ #define __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__ +#include <northbridge/intel/sandybridge/include/soc/iomap.h> + /* Device ID for SandyBridge and IvyBridge */ #define BASE_REV_SNB 0x00 #define BASE_REV_IVB 0x50 @@ -34,24 +36,6 @@ #define IVB_STEP_K0 (BASE_REV_IVB + 5) #define IVB_STEP_D0 (BASE_REV_IVB + 6) -/* Intel Enhanced Debug region must be 4MB */ - -#define IED_SIZE CONFIG_IED_REGION_SIZE - -/* Northbridge BARs */ -#ifndef __ACPI__ -#define DEFAULT_MCHBAR ((u8 *)0xfed10000) /* 16 KB */ -#define DEFAULT_DMIBAR ((u8 *)0xfed18000) /* 4 KB */ -#else -#define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */ -#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ -#endif -#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ -#define DEFAULT_RCBABASE ((u8 *)0xfed1c000) - -#define IOMMU_BASE1 0xfed90000ULL -#define IOMMU_BASE2 0xfed91000ULL - /* Everything below this line is ignored in the DSDT */ #ifndef __ACPI__ #include <cpu/intel/model_206ax/model_206ax.h> @@ -118,9 +102,9 @@ * MCHBAR */ -#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x)))) +#define MCHBAR8(x) (*((volatile u8 *)((uintptr_t)MCH_BASE_ADDRESS + (x)))) +#define MCHBAR16(x) (*((volatile u16 *)((uintptr_t)MCH_BASE_ADDRESS + (x)))) +#define MCHBAR32(x) (*((volatile u32 *)((uintptr_t)MCH_BASE_ADDRESS + (x)))) #define MCHBAR32_OR(x, or) (MCHBAR32(x) = (MCHBAR32(x) | (or))) #define MCHBAR32_AND(x, and) (MCHBAR32(x) = (MCHBAR32(x) & (and))) #define MCHBAR32_AND_OR(x, and, or) \ @@ -133,9 +117,9 @@ * EPBAR - Egress Port Root Complex Register Block */ -#define EPBAR8(x) (*((volatile u8 *)(DEFAULT_EPBAR + (x)))) -#define EPBAR16(x) (*((volatile u16 *)(DEFAULT_EPBAR + (x)))) -#define EPBAR32(x) (*((volatile u32 *)(DEFAULT_EPBAR + (x)))) +#define EPBAR8(x) (*((volatile u8 *)((uintptr_t)EP_BASE_ADDRESS + (x)))) +#define EPBAR16(x) (*((volatile u16 *)((uintptr_t)EP_BASE_ADDRESS + (x)))) +#define EPBAR32(x) (*((volatile u32 *)((uintptr_t)EP_BASE_ADDRESS + (x)))) #define EPPVCCAP1 0x004 /* 32bit */ #define EPPVCCAP2 0x008 /* 32bit */ @@ -164,9 +148,9 @@ * DMIBAR */ -#define DMIBAR8(x) (*((volatile u8 *)(DEFAULT_DMIBAR + (x)))) -#define DMIBAR16(x) (*((volatile u16 *)(DEFAULT_DMIBAR + (x)))) -#define DMIBAR32(x) (*((volatile u32 *)(DEFAULT_DMIBAR + (x)))) +#define DMIBAR8(x) (*((volatile u8 *)((uintptr_t)DMI_BASE_ADDRESS + (x)))) +#define DMIBAR16(x) (*((volatile u16 *)((uintptr_t)DMI_BASE_ADDRESS + (x)))) +#define DMIBAR32(x) (*((volatile u32 *)((uintptr_t)DMI_BASE_ADDRESS + (x)))) #define DMIVCECH 0x000 /* 32bit */ #define DMIPVCCAP1 0x004 /* 32bit */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32075 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93aa0e78ff52e46256debd26601600a96404509f Gerrit-Change-Number: 32075 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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