coreboot-gerrit October 2013

coreboot-gerrit@coreboot.org

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159 discussions

Patch set updated for coreboot: c17d83a vortex86ex: Change PCI S/B resource reservation functions for more I/O devices.

by Andrew Wu

Andrew Wu (arw(a)dmp.com.tw) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3976 -gerrit commit c17d83a4185923cf904bef86b2d402b92b9241f7 Author: Andrew Wu <arw(a)dmp.com.tw> Date: Thu Oct 31 20:12:09 2013 +0800 vortex86ex: Change PCI S/B resource reservation functions for more I/O devices. Originally, Vortex86EX PCI S/B internal resource reservation functions can only support one big legacy I/O device space (0-0xfff). Change function signature to support other non-legacy I/O device space in the future. Change-Id: I22f5c877ed441d59f29801d925ee40b24fb796ce Signed-off-by: Andrew Wu <arw(a)dmp.com.tw> --- src/southbridge/dmp/vortex86ex/southbridge.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/src/southbridge/dmp/vortex86ex/southbridge.c b/src/southbridge/dmp/vortex86ex/southbridge.c index ddb99b8..c6370db 100644 --- a/src/southbridge/dmp/vortex86ex/southbridge.c +++ b/src/southbridge/dmp/vortex86ex/southbridge.c @@ -500,21 +500,21 @@ static void fix_cmos_rtc_time(void) } } -static void vortex86_sb_set_io_resv(device_t dev, u32 io_resv_size) +static void vortex86_sb_set_io_resv(device_t dev, unsigned index, u32 base, u32 size) { struct resource *res; - res = new_resource(dev, 1); - res->base = 0x0UL; - res->size = io_resv_size; + res = new_resource(dev, index); + res->base = base; + res->size = size; res->limit = 0xffffUL; res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -static void vortex86_sb_set_spi_flash_size(device_t dev, u32 flash_size) +static void vortex86_sb_set_spi_flash_size(device_t dev, unsigned index, u32 flash_size) { /* SPI flash is in topmost of 4G memory space */ struct resource *res; - res = new_resource(dev, 2); + res = new_resource(dev, index); res->base = 0x100000000LL - flash_size; res->size = flash_size; res->limit = 0xffffffffUL; @@ -537,11 +537,11 @@ static void vortex86_sb_read_resources(device_t dev) flash_size = 64 * 1024 * 1024; } - /* Reserve space for I/O */ - vortex86_sb_set_io_resv(dev, 0x1000UL); + /* Reserve space for legacy I/O */ + vortex86_sb_set_io_resv(dev, 1, 0, 0x1000UL); /* Reserve space for flash */ - vortex86_sb_set_spi_flash_size(dev, flash_size); + vortex86_sb_set_spi_flash_size(dev, 2, flash_size); } static void southbridge_init_func1(struct device *dev)

8 years, 2 months

Patch merged into coreboot/master: d0299e4 southbridge/intel/i82801ix/lpc.c: Remove unused variable `dummy`

by gerrit＠coreboot.org

the following patch was just integrated into master: commit d0299e4b5178ce8f8b986674cece3e07519f2dff Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Mon Oct 21 09:28:19 2013 +0200 southbridge/intel/i82801ix/lpc.c: Remove unused variable `dummy` Removing `-Wno-unused-but-set-variable` from `CFLAGS` the build for QEMU Q35 and Roda RK9, both using the Intel 82801Ix southbridge, fail with the following error. src/southbridge/intel/i82801ix/lpc.c: In function 'i82801ix_enable_apic': src/southbridge/intel/i82801ix/lpc.c:45:5: error: variable 'dummy' set but not used [-Werror=unused-but-set-variable] cc1: all warnings being treated as errors Removing `dummy` should be safe as GCC probably optimizes it away before anyway. That no dummy variable is used for an RCBA [1] access in Intel Lynx Point supports that this can be dropped safely. [1] root complex base address [2] src/southbridge/intel/lynxpoint/early_pch.c Change-Id: I1c138a3498228dbd025f68d5e6af0acc29ed3460 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3982 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)google.com> See http://review.coreboot.org/3982 for details. -gerrit

8 years, 2 months

New patch to review for coreboot: 297bc18 usbdebug: Fix build for ROMCC boards

by Kyösti Mälkki

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4006 -gerrit commit 297bc181112a79f7f7c63f964302a9e8b547223d Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Oct 30 15:03:25 2013 +0200 usbdebug: Fix build for ROMCC boards Header file is not compatible with romcc, just drop it as a romstage built with romcc cannot use usbdebug anyway. Change-Id: If7f8f22d6a8fa1f02157df281f82f02b72b6a609 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/include/console/console.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/include/console/console.h b/src/include/console/console.h index 7a55ae1..4e9b988 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -27,7 +27,7 @@ #if CONFIG_CONSOLE_SERIAL #include <uart.h> #endif -#if CONFIG_USBDEBUG +#if CONFIG_USBDEBUG && !defined(__ROMCC__) #include <usbdebug.h> #endif #if CONFIG_CONSOLE_NE2K

8 years, 2 months

Patch set updated for coreboot: d3e262c dmp/vortex86ex: Initialize I2C controller base address/IRQ

by Andrew Wu

Andrew Wu (arw(a)dmp.com.tw) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3976 -gerrit commit d3e262ce929244f089a83c4ad559076af04c30a5 Author: Andrew Wu <arw(a)dmp.com.tw> Date: Wed Oct 16 13:08:30 2013 +0800 dmp/vortex86ex: Initialize I2C controller base address/IRQ Change-Id: I22f5c877ed441d59f29801d925ee40b24fb796ce Signed-off-by: Andrew Wu <arw(a)dmp.com.tw> --- src/mainboard/dmp/vortex86ex/Kconfig | 5 +++++ src/southbridge/dmp/vortex86ex/southbridge.c | 33 ++++++++++++++++++++-------- src/southbridge/dmp/vortex86ex/southbridge.h | 1 + 3 files changed, 30 insertions(+), 9 deletions(-) diff --git a/src/mainboard/dmp/vortex86ex/Kconfig b/src/mainboard/dmp/vortex86ex/Kconfig index 723a251..b1db0dc 100644 --- a/src/mainboard/dmp/vortex86ex/Kconfig +++ b/src/mainboard/dmp/vortex86ex/Kconfig @@ -50,6 +50,11 @@ config ID_SECTION_OFFSET hex default 0x4800 +# SPI I/O base address control. +config I2C_BASE + hex + default 0xfb00 + # ROM Strap PLL config setting : choice diff --git a/src/southbridge/dmp/vortex86ex/southbridge.c b/src/southbridge/dmp/vortex86ex/southbridge.c index ddb99b8..2aab0ac 100644 --- a/src/southbridge/dmp/vortex86ex/southbridge.c +++ b/src/southbridge/dmp/vortex86ex/southbridge.c @@ -70,6 +70,7 @@ static const unsigned char irq_to_int_routing[16] = { #define PIDE_IRQ 5 #define SPI1_IRQ 10 +#define I2C0_IRQ 10 #define MOTOR_IRQ 11 /* RT0-3 IRQs. */ @@ -424,6 +425,16 @@ static void ex_sb_uart_init(struct device *dev) //pci_write_config16(SB, SB_REG_UART_CFG_IO_BASE, 0x0); } +static void i2c_init(struct device *dev) +{ + u8 mapped_irq = irq_to_int_routing[I2C0_IRQ]; + u32 cfg = 0; + cfg |= 1 << 31; // UE = enabled. + cfg |= (mapped_irq << 16); // IIRT0. + cfg |= CONFIG_I2C_BASE; // UIOA. + pci_write_config32(dev, SB_REG_II2CCR, cfg); +} + static int get_rtc_update_in_progress(void) { if (cmos_read(RTC_REG_A) & RTC_UIP) @@ -500,21 +511,21 @@ static void fix_cmos_rtc_time(void) } } -static void vortex86_sb_set_io_resv(device_t dev, u32 io_resv_size) +static void vortex86_sb_set_io_resv(device_t dev, unsigned index, u32 base, u32 size) { struct resource *res; - res = new_resource(dev, 1); - res->base = 0x0UL; - res->size = io_resv_size; + res = new_resource(dev, index); + res->base = base; + res->size = size; res->limit = 0xffffUL; res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -static void vortex86_sb_set_spi_flash_size(device_t dev, u32 flash_size) +static void vortex86_sb_set_spi_flash_size(device_t dev, unsigned index, u32 flash_size) { /* SPI flash is in topmost of 4G memory space */ struct resource *res; - res = new_resource(dev, 2); + res = new_resource(dev, index); res->base = 0x100000000LL - flash_size; res->size = flash_size; res->limit = 0xffffffffUL; @@ -537,11 +548,14 @@ static void vortex86_sb_read_resources(device_t dev) flash_size = 64 * 1024 * 1024; } - /* Reserve space for I/O */ - vortex86_sb_set_io_resv(dev, 0x1000UL); + /* Reserve space for legacy I/O */ + vortex86_sb_set_io_resv(dev, 1, 0, 0x1000UL); /* Reserve space for flash */ - vortex86_sb_set_spi_flash_size(dev, flash_size); + vortex86_sb_set_spi_flash_size(dev, 2, flash_size); + + /* Reserve space for I2C */ + vortex86_sb_set_io_resv(dev, 3, CONFIG_I2C_BASE, 8); } static void southbridge_init_func1(struct device *dev) @@ -572,6 +586,7 @@ static void southbridge_init(struct device *dev) if (dev->device == 0x6011) { ex_sb_gpio_init(dev); ex_sb_uart_init(dev); + i2c_init(dev); } pci_routing_fixup(dev); diff --git a/src/southbridge/dmp/vortex86ex/southbridge.h b/src/southbridge/dmp/vortex86ex/southbridge.h index 0cc28fa..316d30a 100644 --- a/src/southbridge/dmp/vortex86ex/southbridge.h +++ b/src/southbridge/dmp/vortex86ex/southbridge.h @@ -36,6 +36,7 @@ #define SB_REG_IPFCR 0xc0 #define SB_REG_FRWPR 0xc4 #define SB_REG_STRAP 0xce +#define SB_REG_II2CCR 0xd4 #define SB1 PCI_DEV(0, 7, 1) #define SB1_REG_EXT_PIRQ_ROUTE2 0xb4

8 years, 2 months

Patch set updated for coreboot: 114707e dmp/vortex86ex: Add timeout for keyboard system flag checking.

by Andrew Wu

Andrew Wu (arw(a)dmp.com.tw) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3988 -gerrit commit 114707e603681b3aebb2f62ea1cb4ad4baf9f395 Author: Andrew Wu <arw(a)dmp.com.tw> Date: Thu Oct 24 20:37:48 2013 +0800 dmp/vortex86ex: Add timeout for keyboard system flag checking. If Vortex86EX PS/2 keyboard controller system flag bit times out, reload controller firmware code and try again. Change-Id: I24aec4b20d85c721c01e72686f3eb1259f9334b8 Signed-off-by: Andrew Wu <arw(a)dmp.com.tw> --- src/southbridge/dmp/vortex86ex/southbridge.c | 33 ++++++++++++++++++++++++---- 1 file changed, 29 insertions(+), 4 deletions(-) diff --git a/src/southbridge/dmp/vortex86ex/southbridge.c b/src/southbridge/dmp/vortex86ex/southbridge.c index ddb99b8..8cc453f 100644 --- a/src/southbridge/dmp/vortex86ex/southbridge.c +++ b/src/southbridge/dmp/vortex86ex/southbridge.c @@ -25,6 +25,7 @@ #include <pc80/mc146818rtc.h> #include <pc80/keyboard.h> #include <string.h> +#include <delay.h> #include "arch/io.h" #include "chip.h" #include "southbridge.h" @@ -93,8 +94,12 @@ static const unsigned char irq_to_int_routing[16] = { #define POST_KBD_FW_UPLOAD 0x06 #define POST_KBD_CHK_READY 0x07 #define POST_KBD_IS_READY 0x08 +#define POST_KBD_IS_BAD 0x09 #define POST_KBD_FW_VERIFY_FAILURE 0x82 +/* keyboard controller system flag timeout : 400 ms */ +#define KBC_TIMEOUT_SYS_FLAG 400 + static u8 get_pci_dev_func(device_t dev) { return PCI_FUNC(dev->path.pci.devfn); @@ -140,15 +145,21 @@ static void upload_dmp_keyboard_firmware(struct device *dev) pci_write_config32(dev, SB_REG_IPFCR, reg_sb_c0 & ~0x400L); } -static void kbc_wait_system_flag(void) +static int kbc_wait_system_flag(void) { /* wait keyboard controller ready by checking system flag * (status port bit 2). */ post_code(POST_KBD_CHK_READY); - while ((inb(0x64) & 0x4) == 0) { + u32 timeout; + for (timeout = KBC_TIMEOUT_SYS_FLAG; + timeout && ((inb(0x64) & 0x4) == 0); timeout--) + mdelay(1); + + if (!timeout) { + printk(BIOS_WARNING, "Keyboard controller system flag timeout\n"); } - post_code(POST_KBD_IS_READY); + return !!timeout; } static void pci_routing_fixup(struct device *dev) @@ -577,7 +588,21 @@ static void southbridge_init(struct device *dev) fix_cmos_rtc_time(); rtc_init(0); - kbc_wait_system_flag(); + /* Check keyboard controller ready. If timeout, reload firmware code + * and try again. + */ + u32 retries = 10; + while (!kbc_wait_system_flag()) { + if (!retries) { + post_code(POST_KBD_IS_BAD); + die("The keyboard timeout occurred too often. " + "Your CPU is probably defect. " + "Contact your dealer to replace it\n"); + } + upload_dmp_keyboard_firmware(dev); + retries--; + } + post_code(POST_KBD_IS_READY); pc_keyboard_init(0); }

8 years, 2 months

Patch set updated for coreboot: f54c949 dmp/vortex86ex: Add timeout for keyboard system flag checking.

by Andrew Wu

Andrew Wu (arw(a)dmp.com.tw) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3988 -gerrit commit f54c949e7b9b27cd3b0af481c5d01ccbdf52bc75 Author: Andrew Wu <arw(a)dmp.com.tw> Date: Thu Oct 24 20:37:48 2013 +0800 dmp/vortex86ex: Add timeout for keyboard system flag checking. If Vortex86EX PS/2 keyboard controller system flag bit times out, reload controller firmware code and try again. Change-Id: I24aec4b20d85c721c01e72686f3eb1259f9334b8 Signed-off-by: Andrew Wu <arw(a)dmp.com.tw> --- src/southbridge/dmp/vortex86ex/southbridge.c | 33 ++++++++++++++++++++++++---- 1 file changed, 29 insertions(+), 4 deletions(-) diff --git a/src/southbridge/dmp/vortex86ex/southbridge.c b/src/southbridge/dmp/vortex86ex/southbridge.c index ddb99b8..56c2923 100644 --- a/src/southbridge/dmp/vortex86ex/southbridge.c +++ b/src/southbridge/dmp/vortex86ex/southbridge.c @@ -25,6 +25,7 @@ #include <pc80/mc146818rtc.h> #include <pc80/keyboard.h> #include <string.h> +#include <delay.h> #include "arch/io.h" #include "chip.h" #include "southbridge.h" @@ -93,8 +94,12 @@ static const unsigned char irq_to_int_routing[16] = { #define POST_KBD_FW_UPLOAD 0x06 #define POST_KBD_CHK_READY 0x07 #define POST_KBD_IS_READY 0x08 +#define POST_KBD_IS_BAD 0x09 #define POST_KBD_FW_VERIFY_FAILURE 0x82 +/* keyboard controller system flag timeout : 400 ms */ +#define KBC_TIMEOUT_SYS_FLAG 400 + static u8 get_pci_dev_func(device_t dev) { return PCI_FUNC(dev->path.pci.devfn); @@ -140,15 +145,21 @@ static void upload_dmp_keyboard_firmware(struct device *dev) pci_write_config32(dev, SB_REG_IPFCR, reg_sb_c0 & ~0x400L); } -static void kbc_wait_system_flag(void) +static int kbc_wait_system_flag(void) { /* wait keyboard controller ready by checking system flag * (status port bit 2). */ post_code(POST_KBD_CHK_READY); - while ((inb(0x64) & 0x4) == 0) { + u32 timeout; + for (timeout = KBC_TIMEOUT_SYS_FLAG; + timeout && ((inb(0x64) & 0x4) == 0); timeout--) + mdelay(1); + + if (!timeout) { + printk(BIOS_WARNING, "Keyboard controller system flag timeout\n"); } - post_code(POST_KBD_IS_READY); + return !!timeout; } static void pci_routing_fixup(struct device *dev) @@ -577,7 +588,21 @@ static void southbridge_init(struct device *dev) fix_cmos_rtc_time(); rtc_init(0); - kbc_wait_system_flag(); + /* Check keyboard controller ready. If timeout, reload firmware code + * and try again. + */ + u32 retries = 10; + while (!kbc_wait_system_flag()) { + if (!retries) { + post_code(POST_KBD_IS_BAD); + die("The keyboard timeout occurred too often. " + "Your CPU is probably defect. " + "Contact your dealer to replace it\n"); + } + upload_dmp_keyboard_firmware(dev); + retries --; + } + post_code(POST_KBD_IS_READY); pc_keyboard_init(0); }

8 years, 2 months

New patch to review for coreboot: 14fbc60 AMD hudson: add imc fan control

by WANG Siyuan

WANG Siyuan (wangsiyuanbuaa(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4003 -gerrit commit 14fbc60efc4040232bf214c62beaf1f68063ab0a Author: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Date: Mon Oct 28 10:49:28 2013 +0800 AMD hudson: add imc fan control Use 3 imc functions to control fan: function 0x81: set imc thermal zone information function 0x83: set imc fan policy temperature thresholds function 0x85: set imc fan policy PWM settings Change-Id: I613fd195afffc5e26d59c61b33cdf834b8dbbfbb Signed-off-by: WANG Siyuan <SiYuan.Wang(a)amd.com> Signed-off-by: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> --- src/southbridge/amd/agesa/hudson/Makefile.inc | 1 + src/southbridge/amd/agesa/hudson/imc_fan_control.c | 85 ++++++++++++++++++++++ src/southbridge/amd/agesa/hudson/imc_fan_control.h | 14 ++++ 3 files changed, 100 insertions(+) diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index d50d09e..02bff34 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -9,6 +9,7 @@ ramstage-y += hda.c ramstage-y += pci.c ramstage-y += pcie.c ramstage-y += sd.c +ramstage-y += imc_fan_control.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.c ramstage-y += reset.c diff --git a/src/southbridge/amd/agesa/hudson/imc_fan_control.c b/src/southbridge/amd/agesa/hudson/imc_fan_control.c new file mode 100644 index 0000000..61f5d26 --- /dev/null +++ b/src/southbridge/amd/agesa/hudson/imc_fan_control.c @@ -0,0 +1,85 @@ +#include "imc_fan_control.h" +#include <delay.h> + +void imc_fan_control(void) +{ + u8 val; + val = read8(ACPI_MMIO_BASE + PMIO2_BASE + 0x01); + val |= BIT2; + write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x01, val); + write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x02, 0xf7); + write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x03, 0xff); + write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x04, 0xff); + + val = read8(ACPI_MMIO_BASE + PMIO2_BASE + 0x11); + val |= BIT2; + write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x11, val); + write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x12, 0xf7); + write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x13, 0xff); + write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x14, 0xff); + + imc_func_0x83(); + imc_func_0x85(); + imc_func_0x81(); +} + +void write_imc_msg(u8 idx, u8 val) +{ + outb(idx, 0x3e); + outb(val, 0x3f); +} + +void imc_func_0x81(void) +{ + write_imc_msg(MSG_REG0, 0); + write_imc_msg(MSG_REG1, 0); + write_imc_msg(MSG_REG2, 0x3d); + write_imc_msg(MSG_REG3, 0xe); + write_imc_msg(MSG_REG4, 0); + write_imc_msg(MSG_REG5, 0x54); + write_imc_msg(MSG_REG6, 0x98); + write_imc_msg(MSG_REG7, 0x2); + write_imc_msg(MSG_REG8, 0x1); + write_imc_msg(MSG_REG9, 0); + write_imc_msg(MSG_SYS_TO_IMC, Fun_81); + mdelay(50); +} + +void imc_func_0x83(void) +{ + write_imc_msg(MSG_REG0, 0); + write_imc_msg(MSG_REG1, 0); + write_imc_msg(MSG_REG2, 0x69); + write_imc_msg(MSG_REG3, 0x3c); + write_imc_msg(MSG_REG4, 0xff); + write_imc_msg(MSG_REG5, 0xff); + write_imc_msg(MSG_REG6, 0xff); + write_imc_msg(MSG_REG7, 0xff); + write_imc_msg(MSG_REG8, 0xff); + write_imc_msg(MSG_REG9, 0xff); + write_imc_msg(MSG_REGA, 0x69); + write_imc_msg(MSG_REGB, 0); + write_imc_msg(MSG_SYS_TO_IMC, Fun_83); + mdelay(50); +} + +void imc_func_0x85(void) +{ + write_imc_msg(MSG_REG0, 0); + write_imc_msg(MSG_REG1, 0); + write_imc_msg(MSG_REG2, 0x64); + write_imc_msg(MSG_REG3, 0xff); + write_imc_msg(MSG_REG4, 0xff); + write_imc_msg(MSG_REG5, 0xff); + write_imc_msg(MSG_REG6, 0xff); + write_imc_msg(MSG_REG7, 0xff); + write_imc_msg(MSG_REG8, 0xff); + write_imc_msg(MSG_REG9, 0xff); + write_imc_msg(MSG_SYS_TO_IMC, Fun_85); + mdelay(50); +} + +void imc_func_0x89(void) +{ + /* not use */ +} diff --git a/src/southbridge/amd/agesa/hudson/imc_fan_control.h b/src/southbridge/amd/agesa/hudson/imc_fan_control.h new file mode 100644 index 0000000..c7a134b --- /dev/null +++ b/src/southbridge/amd/agesa/hudson/imc_fan_control.h @@ -0,0 +1,14 @@ +#ifndef _IMC_FAN_CONTROL_H_ +#define _IMC_FAN_CONTROL_H_ + +#include <arch/io.h> +#include "FchPlatform.h" + +void imc_fan_control(void); +void write_imc_msg(u8 idx, u8 val); +void imc_func_0x81(void); +void imc_func_0x83(void); +void imc_func_0x85(void); +void imc_func_0x89(void); + +#endif

8 years, 2 months

New patch to review for coreboot: 0d5ce79 Add imc fan control to Parmer and Thatcher

by WANG Siyuan

WANG Siyuan (wangsiyuanbuaa(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4004 -gerrit commit 0d5ce799350d207a0bba40a75c6337cfcfefc436 Author: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Date: Mon Oct 28 11:02:15 2013 +0800 Add imc fan control to Parmer and Thatcher I have tested on Parmer and Thatcher. imc can control fan automatically. Change-Id: I8aef99e5336da1e0c5cbf1b63afe549830333c3b Signed-off-by: WANG Siyuan <SiYuan.Wang(a)amd.com> Signed-off-by: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> --- src/mainboard/amd/parmer/get_bus_conf.c | 5 +++++ src/mainboard/amd/thatcher/get_bus_conf.c | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/src/mainboard/amd/parmer/get_bus_conf.c b/src/mainboard/amd/parmer/get_bus_conf.c index c92fea9..d01d382 100644 --- a/src/mainboard/amd/parmer/get_bus_conf.c +++ b/src/mainboard/amd/parmer/get_bus_conf.c @@ -25,6 +25,7 @@ #include <stdlib.h> #include <cpu/amd/amdfam14.h> #include "agesawrapper.h" +#include "imc_fan_control.h" /* Global variables for MB layouts and these will be shared by irqtable mptable * and acpi_tables busnum is default. @@ -134,4 +135,8 @@ void get_bus_conf(void) bus_isa = 10; apicid_base = CONFIG_MAX_CPUS; apicid_hudson = apicid_base; + +#if defined CONFIG_HUDSON_IMC_FWM && (CONFIG_HUDSON_IMC_FWM == 1) + imc_fan_control(); +#endif } diff --git a/src/mainboard/amd/thatcher/get_bus_conf.c b/src/mainboard/amd/thatcher/get_bus_conf.c index c92fea9..d01d382 100644 --- a/src/mainboard/amd/thatcher/get_bus_conf.c +++ b/src/mainboard/amd/thatcher/get_bus_conf.c @@ -25,6 +25,7 @@ #include <stdlib.h> #include <cpu/amd/amdfam14.h> #include "agesawrapper.h" +#include "imc_fan_control.h" /* Global variables for MB layouts and these will be shared by irqtable mptable * and acpi_tables busnum is default. @@ -134,4 +135,8 @@ void get_bus_conf(void) bus_isa = 10; apicid_base = CONFIG_MAX_CPUS; apicid_hudson = apicid_base; + +#if defined CONFIG_HUDSON_IMC_FWM && (CONFIG_HUDSON_IMC_FWM == 1) + imc_fan_control(); +#endif }

8 years, 2 months

Patch set updated for coreboot: 7d6cff8 Lenovo X60: Native VGA init: Get rid of the memory corruptions.

by Denis Carikli

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4002 -gerrit commit 7d6cff88b67d003a95f288668b70e2ed4613a66b Author: Peter Stuge <peter(a)stuge.se> Date: Sun Oct 27 16:07:28 2013 +0100 Lenovo X60: Native VGA init: Get rid of the memory corruptions. Without that fix the GTT points at 0x00000000. The patch was made by Peter Stuge, I just split it and added a commit message. Change-Id: Ia378b600ba2faf00d42635c6503b94ff0cb1bc8c Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/mainboard/lenovo/x60/i915.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mainboard/lenovo/x60/i915.c b/src/mainboard/lenovo/x60/i915.c index 0f90168..f130c5c 100644 --- a/src/mainboard/lenovo/x60/i915.c +++ b/src/mainboard/lenovo/x60/i915.c @@ -139,7 +139,8 @@ int gtt_setup(unsigned int mmiobase) PGETBL_save = read32(mmiobase + PGETBL_CTL) & ~PGETBL_ENABLED; PGETBL_save |= PGETBL_ENABLED; - printk(BIOS_DEBUG, "PGETBL_save=0x%lx\n", PGETBL_save); + PGETBL_save |= pci_read_config32(dev_find_slot(0, PCI_DEVFN(2,0)), 0x5c) & 0xfffff000; + PGETBL_save |= 2; /* set GTT to 256kb */ write32(mmiobase + GFX_FLSH_CNTL, 0);

8 years, 2 months

Patch set updated for coreboot: 44aaf67 Northbridge: i945: Native VGA init: print the GMA and GTT addresses

by Denis Carikli

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4001 -gerrit commit 44aaf67b6f111185c12e2871fa9c4bdfc95c0227 Author: Peter Stuge <peter(a)stuge.se> Date: Sat Jun 8 01:31:44 2013 +0200 Northbridge: i945: Native VGA init: print the GMA and GTT addresses The patch was made by Peter Stuge, I just split it and added a commit message. Change-Id: Ieaaaa2611f7bb8968f01b16daefe7e2afe870f72 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/northbridge/intel/i945/gma.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 32fa9b4..deda2fa 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -57,6 +57,11 @@ static void gma_func0_init(struct device *dev) mmiobase = dev->resource_list[0].base; graphics_base = dev->resource_list[2].base + 0x20000; + printk(BIOS_SPEW, "GMADR=0x%08x GTTADR=0x%08x\n", + pci_read_config32(dev, 0x18), + pci_read_config32(dev, 0x1c) + ); + int i915lightup(u32 physbase, u32 iobase, u32 mmiobase, u32 gfx); i915lightup(uma_memory_base, iobase, mmiobase, graphics_base); #endif

8 years, 2 months

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coreboot-gerrit October 2013