coreboot-gerrit July 2020

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Change in coreboot[master]: nb/intel/haswell: Add RMRR for USB devices
by Angel Pons (Code Review) 03 May '22

03 May '22

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43807 ) Change subject: nb/intel/haswell: Add RMRR for USB devices ...................................................................... nb/intel/haswell: Add RMRR for USB devices FIXME: Figure out which address the RMRR corresponds to. VT-d checklist verifies that there's a RMRR entry for USB devices. If said devices are enabled, add the RMRR entry. Tested on Asrock B85M Pro4, verify VT-d check about USB RMRR passes. Change-Id: I800d6d1847f457827d64b39c5b7bbfc9cb04f230 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/haswell/acpi.c M src/southbridge/intel/lynxpoint/acpi.c M src/southbridge/intel/lynxpoint/pch.h 3 files changed, 36 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/43807/1 diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c index 6a6a124..5e28c82 100644 --- a/src/northbridge/intel/haswell/acpi.c +++ b/src/northbridge/intel/haswell/acpi.c @@ -87,7 +87,7 @@ acpi_dmar_drhd_fixup(tmp, current); } - return current; + return acpi_create_usb_rmrr(current); } unsigned long northbridge_write_acpi_tables(const struct device *const dev, diff --git a/src/southbridge/intel/lynxpoint/acpi.c b/src/southbridge/intel/lynxpoint/acpi.c index 8fee16b..6a2103b 100644 --- a/src/southbridge/intel/lynxpoint/acpi.c +++ b/src/southbridge/intel/lynxpoint/acpi.c @@ -77,3 +77,36 @@ ssdt->length = current - (unsigned long)ssdt; ssdt->checksum = acpi_checksum((void *)ssdt, ssdt->length); } + +unsigned long acpi_create_usb_rmrr(const unsigned long tmp) +{ + unsigned long current = tmp; + + struct device *const ehc1_dev = pcidev_on_root(0x1d, 0); + struct device *const ehc2_dev = pcidev_on_root(0x1a, 0); + struct device *const xhci_dev = pcidev_on_root(0x14, 0); + + const bool ehc1_enabled = ehc1_dev && ehc1_dev->enabled; + const bool ehc2_enabled = ehc2_dev && ehc2_dev->enabled; + const bool xhci_enabled = xhci_dev && xhci_dev->enabled; + + /* If no USB devices are enabled, do not generate the RMRR entry */ + if (!ehc1_enabled && !ehc2_enabled && !xhci_enabled) + return current; + + /* FIXME: This should be the address of the runtime register space instead! */ + current += acpi_create_dmar_rmrr(current, 0, 0x3e2e0000, 0x3e300000 - 1); + + if (ehc1_enabled) + current += acpi_create_dmar_ds_pci(current, 0, 0x1d, 0); + + if (ehc2_enabled) + current += acpi_create_dmar_ds_pci(current, 0, 0x1a, 0); + + if (xhci_enabled) + current += acpi_create_dmar_ds_pci(current, 0, 0x14, 0); + + acpi_dmar_rmrr_fixup(tmp, current); + + return current; +} diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 9946944..79d9dbc 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -122,6 +122,8 @@ void acpi_create_intel_hpet(acpi_hpet_t * hpet); void acpi_create_serialio_ssdt(acpi_header_t *ssdt); +unsigned long acpi_create_usb_rmrr(const unsigned long tmp); + void enable_usb_bar(void); int early_pch_init(void); void pch_enable_lpc(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/43807 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I800d6d1847f457827d64b39c5b7bbfc9cb04f230 Gerrit-Change-Number: 43807 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: haswell: Report only one HPET timer device
by Angel Pons (Code Review) 03 May '22

03 May '22

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43806 ) Change subject: haswell: Report only one HPET timer device ...................................................................... haswell: Report only one HPET timer device VT-d checklist fails if there are multiple devices for a single HPET timer block, and if the bus/dev/fn differs between HPET devices. Tested on Asrock B85M Pro4, verify VT-d check about HPET is successful. Change-Id: I68fd074f5440c634ff3ed28c5d423835c81d33b9 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/haswell/acpi.c M src/southbridge/intel/lynxpoint/lpc.c 2 files changed, 4 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/43806/1 diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c index 1df66bc..6a6a124 100644 --- a/src/northbridge/intel/haswell/acpi.c +++ b/src/northbridge/intel/haswell/acpi.c @@ -82,10 +82,8 @@ current += acpi_create_dmar_ds_ioapic(current, 2, PCH_IOAPIC_PCI_BUS, PCH_IOAPIC_PCI_SLOT, 0); - size_t i; - for (i = 0; i < 8; ++i) - current += acpi_create_dmar_ds_msi_hpet(current, 0, PCH_HPET_PCI_BUS, - PCH_HPET_PCI_SLOT, i); + current += acpi_create_dmar_ds_msi_hpet(current, 0, PCH_HPET_PCI_BUS, + PCH_HPET_PCI_SLOT, 0); acpi_dmar_drhd_fixup(tmp, current); } diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 85fab4d..93b45d0 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -370,10 +370,10 @@ u32 reg32; size_t i; - /* Assign unique bus/dev/fn for each HPET */ + /* Assign the same bus/dev/fn for each HPET */ for (i = 0; i < 8; ++i) pci_write_config16(dev, LPC_HnBDF(i), - PCH_HPET_PCI_BUS << 8 | PCH_HPET_PCI_SLOT << 3 | i); + PCH_HPET_PCI_BUS << 8 | PCH_HPET_PCI_SLOT << 3 | 0); /* Move HPET to default address 0xfed00000 and enable it */ reg32 = RCBA32(HPTC); -- To view, visit https://review.coreboot.org/c/coreboot/+/43806 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I68fd074f5440c634ff3ed28c5d423835c81d33b9 Gerrit-Change-Number: 43806 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

2 1

Change in coreboot[master]: mb/lenovo/{t420,t420s}: Convert to variant board
by Peter Lemenkov (Code Review) 02 May '22

02 May '22

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40381 ) Change subject: mb/lenovo/{t420,t420s}: Convert to variant board ...................................................................... mb/lenovo/{t420,t420s}: Convert to variant board Change-Id: If117c48cf8e6131b3d25112346d4ddd1ff366009 Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/lenovo/t420/Kconfig M src/mainboard/lenovo/t420/Kconfig.name M src/mainboard/lenovo/t420/Makefile.inc M src/mainboard/lenovo/t420/board_info.txt M src/mainboard/lenovo/t420/devicetree.cb M src/mainboard/lenovo/t420/early_init.c M src/mainboard/lenovo/t420/gma-mainboard.ads M src/mainboard/lenovo/t420/hda_verb.c A src/mainboard/lenovo/t420/variants/t420/board_info.txt R src/mainboard/lenovo/t420/variants/t420/data.vbt A src/mainboard/lenovo/t420/variants/t420/early_init.c R src/mainboard/lenovo/t420/variants/t420/gpio.c A src/mainboard/lenovo/t420/variants/t420/hda_verb.c A src/mainboard/lenovo/t420/variants/t420/overridetree.cb R src/mainboard/lenovo/t420/variants/t420s/board_info.txt R src/mainboard/lenovo/t420/variants/t420s/data.vbt A src/mainboard/lenovo/t420/variants/t420s/early_init.c R src/mainboard/lenovo/t420/variants/t420s/gpio.c R src/mainboard/lenovo/t420/variants/t420s/hda_verb.c A src/mainboard/lenovo/t420/variants/t420s/overridetree.cb D src/mainboard/lenovo/t420s/Kconfig D src/mainboard/lenovo/t420s/Kconfig.name D src/mainboard/lenovo/t420s/Makefile.inc D src/mainboard/lenovo/t420s/acpi/ec.asl D src/mainboard/lenovo/t420s/acpi/platform.asl D src/mainboard/lenovo/t420s/acpi/superio.asl D src/mainboard/lenovo/t420s/acpi_tables.c D src/mainboard/lenovo/t420s/cmos.default D src/mainboard/lenovo/t420s/cmos.layout D src/mainboard/lenovo/t420s/devicetree.cb D src/mainboard/lenovo/t420s/dsdt.asl D src/mainboard/lenovo/t420s/early_init.c D src/mainboard/lenovo/t420s/gma-mainboard.ads D src/mainboard/lenovo/t420s/mainboard.c D src/mainboard/lenovo/t420s/smihandler.c D src/mainboard/lenovo/t420s/vboot-ro-me_clean.fmd D src/mainboard/lenovo/t420s/vboot-ro.fmd D src/mainboard/lenovo/t420s/vboot-rwa.fmd 38 files changed, 150 insertions(+), 853 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/40381/1 diff --git a/src/mainboard/lenovo/t420/Kconfig b/src/mainboard/lenovo/t420/Kconfig index dfc8ed1..b0523f6 100644 --- a/src/mainboard/lenovo/t420/Kconfig +++ b/src/mainboard/lenovo/t420/Kconfig @@ -1,4 +1,4 @@ -if BOARD_LENOVO_T420 +if BOARD_LENOVO_T420 || BOARD_LENOVO_T420S config BOARD_SPECIFIC_OPTIONS def_bool y @@ -16,7 +16,7 @@ select HAVE_CMOS_DEFAULT select HAVE_ACPI_RESUME select INTEL_INT15 - select DRIVERS_RICOH_RCE822 + select DRIVERS_RICOH_RCE822 if BOARD_LENOVO_T420 select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 select MAINBOARD_HAS_LIBGFXINIT @@ -51,9 +51,19 @@ string default "lenovo/t420" +config VARIANT_DIR + string + default "t420" if BOARD_LENOVO_T420 + default "t420s" if BOARD_LENOVO_T420S + +config OVERRIDE_DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" + config MAINBOARD_PART_NUMBER string - default "ThinkPad T420" + default "ThinkPad T420" if BOARD_LENOVO_T420 + default "ThinkPad T420s" if BOARD_LENOVO_T420S config MAX_CPUS int @@ -81,4 +91,4 @@ config PS2M_EISAID default "LEN0015" -endif # BOARD_LENOVO_T420 +endif # BOARD_LENOVO_T420 || BOARD_LENOVO_T420S diff --git a/src/mainboard/lenovo/t420/Kconfig.name b/src/mainboard/lenovo/t420/Kconfig.name index 75570ad..c43ec9d 100644 --- a/src/mainboard/lenovo/t420/Kconfig.name +++ b/src/mainboard/lenovo/t420/Kconfig.name @@ -1,2 +1,5 @@ config BOARD_LENOVO_T420 bool "ThinkPad T420" + +config BOARD_LENOVO_T420S + bool "ThinkPad T420s" diff --git a/src/mainboard/lenovo/t420/Makefile.inc b/src/mainboard/lenovo/t420/Makefile.inc index 05befdd..df5ca02 100644 --- a/src/mainboard/lenovo/t420/Makefile.inc +++ b/src/mainboard/lenovo/t420/Makefile.inc @@ -15,7 +15,9 @@ smm-y += smihandler.c bootblock-y += gpio.c romstage-y += gpio.c - +ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +bootblock-y += variants/$(VARIANT_DIR)/early_init.c bootblock-y += early_init.c +romstage-y += variants/$(VARIANT_DIR)/early_init.c romstage-y += early_init.c diff --git a/src/mainboard/lenovo/t420/board_info.txt b/src/mainboard/lenovo/t420/board_info.txt index c0f04ca..05146ff 100644 --- a/src/mainboard/lenovo/t420/board_info.txt +++ b/src/mainboard/lenovo/t420/board_info.txt @@ -1,3 +1,5 @@ +Vendor name: Lenovo +Board name: ThinkPad T420 baseboard Category: laptop ROM package: SOIC-8 / WSON-8 ROM protocol: SPI diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb index 5ac9cf5..ec4a57a 100644 --- a/src/mainboard/lenovo/t420/devicetree.cb +++ b/src/mainboard/lenovo/t420/devicetree.cb @@ -82,13 +82,7 @@ device pci 1c.3 on smbios_slot_desc "7" "3" "ExpressCard Slot" "8" end # PCIe Port #4 ExpressCard - device pci 1c.4 on - chip drivers/ricoh/rce822 - register "sdwppol" = "1" - register "disable_mask" = "0x87" - device pci 00.0 on end - end - end # PCIe Port #5 (Ricoh SD & FW) + device pci 1c.4 on end # PCIe Port #5 device pci 1c.5 off end # PCIe Port #6 Intel Gigabit Ethernet PHY (not PCIe) device pci 1c.6 off end # PCIe Port #7 device pci 1c.7 off end # PCIe Port #8 diff --git a/src/mainboard/lenovo/t420/early_init.c b/src/mainboard/lenovo/t420/early_init.c index 6c189f4..7a06bf0 100644 --- a/src/mainboard/lenovo/t420/early_init.c +++ b/src/mainboard/lenovo/t420/early_init.c @@ -34,24 +34,6 @@ pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); } -// OC3 set in BIOS to port 2-7, OC7 set in BIOS to port 10-13 -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 1, 0 }, /* P0: system port 4, OC0 */ - { 1, 1, 1 }, /* P1: system port 2 (EHCI debug), OC 1 */ - { 1, 1, -1 }, /* P2: HALF MINICARD (WLAN) no oc */ - { 1, 0, -1 }, /* P3: WWAN, no OC */ - { 1, 0, -1 }, /* P4: smartcard, no OC */ - { 1, 1, -1 }, /* P5: ExpressCard, no OC */ - { 0, 0, -1 }, /* P6: empty */ - { 0, 0, -1 }, /* P7: empty */ - { 1, 1, 4 }, /* P8: system port 3, OC4*/ - { 1, 1, 5 }, /* P9: system port 1 (EHCI debug), OC 5 */ - { 1, 0, -1 }, /* P10: fingerprint reader, no OC */ - { 1, 0, -1 }, /* P11: bluetooth, no OC. */ - { 1, 1, -1 }, /* P12: docking, no OC */ - { 1, 1, -1 }, /* P13: camera (LCD), no OC */ -}; - void mainboard_get_spd(spd_raw_data *spd, bool id_only) { read_spd(&spd[0], 0x50, id_only); diff --git a/src/mainboard/lenovo/t420/gma-mainboard.ads b/src/mainboard/lenovo/t420/gma-mainboard.ads index a26b993..fae3544 100644 --- a/src/mainboard/lenovo/t420/gma-mainboard.ads +++ b/src/mainboard/lenovo/t420/gma-mainboard.ads @@ -1,4 +1,4 @@ --- SPDX-License-Identifier: GPL-2.0-only +-- SPDX-License-Identifier: GPL-2.0-or-later -- This file is part of the coreboot project. with HW.GFX.GMA; diff --git a/src/mainboard/lenovo/t420/hda_verb.c b/src/mainboard/lenovo/t420/hda_verb.c index 690c936..2997587 100644 --- a/src/mainboard/lenovo/t420/hda_verb.c +++ b/src/mainboard/lenovo/t420/hda_verb.c @@ -1,45 +1 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -/* Bits 31:28 - Codec Address */ -/* Bits 27:20 - NID */ -/* Bits 19:8 - Verb ID */ -/* Bits 7:0 - Payload */ - -#include <device/azalia_device.h> - -const u32 cim_verb_data[] = { - 0x14f1506e, /* Codec VID / DID: Conexant CX20590 - schematic shows CX20672 */ - 0x17aa21ce, /* Subsystem ID */ - 13, /* Number of 4 dword sets */ - AZALIA_SUBVENDOR(0, 0x17aa21d2), - AZALIA_PIN_CFG(0, 0x12, 0x90a60140), - AZALIA_PIN_CFG(0, 0x14, 0x90170110), - AZALIA_PIN_CFG(0, 0x15, 0x03211020), - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), - AZALIA_PIN_CFG(0, 0x18, 0x03a11830), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1d, 0x40138205), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), - - /* Misc entries */ - 0x00b707C0, /* Enable PortB as Output with HP amp */ - 0x00d70740, /* Enable PortD as Output */ - 0x0017a200, /* Disable ClkEn of PortSenseTst */ - 0x0017c621, /* Slave Port - Port A used as microphone input for - combo Jack - Master Port - Port B used for Jack Presence Detect - Enable Combo Jack Detection */ - 0x0017a208, /* Enable ClkEn of PortSenseTst */ - 0x00170500, /* Set power state to D0 */ - 0x00170500, /* Padding */ - 0x00170500, /* Padding */ -}; - -const u32 pc_beep_verbs[] = { - 0x02177a00, /* Digital PCBEEP Gain: 0h=-9db, 1h=-6db ... 4h=+3db, 5h=+6db */ -}; - -AZALIA_ARRAY_SIZES; +/* dummy */ diff --git a/src/mainboard/lenovo/t420/variants/t420/board_info.txt b/src/mainboard/lenovo/t420/variants/t420/board_info.txt new file mode 100644 index 0000000..c0f04ca --- /dev/null +++ b/src/mainboard/lenovo/t420/variants/t420/board_info.txt @@ -0,0 +1,6 @@ +Category: laptop +ROM package: SOIC-8 / WSON-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: n +Release year: 2011 diff --git a/src/mainboard/lenovo/t420/data.vbt b/src/mainboard/lenovo/t420/variants/t420/data.vbt similarity index 100% rename from src/mainboard/lenovo/t420/data.vbt rename to src/mainboard/lenovo/t420/variants/t420/data.vbt Binary files differ diff --git a/src/mainboard/lenovo/t420/variants/t420/early_init.c b/src/mainboard/lenovo/t420/variants/t420/early_init.c new file mode 100644 index 0000000..4b71060 --- /dev/null +++ b/src/mainboard/lenovo/t420/variants/t420/early_init.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <southbridge/intel/bd82x6x/pch.h> + +// OC3 set in BIOS to port 2-7, OC7 set in BIOS to port 10-13 +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 1, 0 }, /* P0: system port 4, OC0 */ + { 1, 1, 1 }, /* P1: system port 2 (EHCI debug), OC 1 */ + { 1, 1, -1 }, /* P2: HALF MINICARD (WLAN) no oc */ + { 1, 0, -1 }, /* P3: WWAN, no OC */ + { 1, 0, -1 }, /* P4: smartcard, no OC */ + { 1, 1, -1 }, /* P5: ExpressCard, no OC */ + { 0, 0, -1 }, /* P6: empty */ + { 0, 0, -1 }, /* P7: empty */ + { 1, 1, 4 }, /* P8: system port 3, OC4*/ + { 1, 1, 5 }, /* P9: system port 1 (EHCI debug), OC 5 */ + { 1, 0, -1 }, /* P10: fingerprint reader, no OC */ + { 1, 0, -1 }, /* P11: bluetooth, no OC. */ + { 1, 1, -1 }, /* P12: docking, no OC */ + { 1, 1, -1 }, /* P13: camera (LCD), no OC */ +}; diff --git a/src/mainboard/lenovo/t420/gpio.c b/src/mainboard/lenovo/t420/variants/t420/gpio.c similarity index 100% rename from src/mainboard/lenovo/t420/gpio.c rename to src/mainboard/lenovo/t420/variants/t420/gpio.c diff --git a/src/mainboard/lenovo/t420/variants/t420/hda_verb.c b/src/mainboard/lenovo/t420/variants/t420/hda_verb.c new file mode 100644 index 0000000..690c936 --- /dev/null +++ b/src/mainboard/lenovo/t420/variants/t420/hda_verb.c @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +/* Bits 31:28 - Codec Address */ +/* Bits 27:20 - NID */ +/* Bits 19:8 - Verb ID */ +/* Bits 7:0 - Payload */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x14f1506e, /* Codec VID / DID: Conexant CX20590 - schematic shows CX20672 */ + 0x17aa21ce, /* Subsystem ID */ + 13, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x17aa21d2), + AZALIA_PIN_CFG(0, 0x12, 0x90a60140), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x15, 0x03211020), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x03a11830), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x40138205), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + + /* Misc entries */ + 0x00b707C0, /* Enable PortB as Output with HP amp */ + 0x00d70740, /* Enable PortD as Output */ + 0x0017a200, /* Disable ClkEn of PortSenseTst */ + 0x0017c621, /* Slave Port - Port A used as microphone input for + combo Jack + Master Port - Port B used for Jack Presence Detect + Enable Combo Jack Detection */ + 0x0017a208, /* Enable ClkEn of PortSenseTst */ + 0x00170500, /* Set power state to D0 */ + 0x00170500, /* Padding */ + 0x00170500, /* Padding */ +}; + +const u32 pc_beep_verbs[] = { + 0x02177a00, /* Digital PCBEEP Gain: 0h=-9db, 1h=-6db ... 4h=+3db, 5h=+6db */ +}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/lenovo/t420/variants/t420/overridetree.cb b/src/mainboard/lenovo/t420/variants/t420/overridetree.cb new file mode 100644 index 0000000..c0b503c --- /dev/null +++ b/src/mainboard/lenovo/t420/variants/t420/overridetree.cb @@ -0,0 +1,13 @@ +chip northbridge/intel/sandybridge + device domain 0 on + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + device pci 1c.4 on + chip drivers/ricoh/rce822 + register "sdwppol" = "1" + register "disable_mask" = "0x87" + device pci 00.0 on end + end + end # PCIe Port #5 (Ricoh SD & FW) + end + end +end diff --git a/src/mainboard/lenovo/t420s/board_info.txt b/src/mainboard/lenovo/t420/variants/t420s/board_info.txt similarity index 100% rename from src/mainboard/lenovo/t420s/board_info.txt rename to src/mainboard/lenovo/t420/variants/t420s/board_info.txt diff --git a/src/mainboard/lenovo/t420s/data.vbt b/src/mainboard/lenovo/t420/variants/t420s/data.vbt similarity index 100% rename from src/mainboard/lenovo/t420s/data.vbt rename to src/mainboard/lenovo/t420/variants/t420s/data.vbt Binary files differ diff --git a/src/mainboard/lenovo/t420/variants/t420s/early_init.c b/src/mainboard/lenovo/t420/variants/t420s/early_init.c new file mode 100644 index 0000000..3066da5 --- /dev/null +++ b/src/mainboard/lenovo/t420/variants/t420s/early_init.c @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <southbridge/intel/bd82x6x/pch.h> + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 0, 1, -1 }, /* P0: empty */ + { 1, 1, 1 }, /* P1: system port 2 (To system port) (EHCI debug), OC 1 */ + { 1, 1, -1 }, /* P2: HALF MINICARD (WLAN) no oc */ + { 1, 0, -1 }, /* P3: WWAN, no OC */ + { 1, 1, -1 }, /* P4: smartcard, no OC */ + { 1, 1, -1 }, /* P5: ExpressCard, no OC */ + { 0, 0, -1 }, /* P6: empty */ + { 0, 0, -1 }, /* P7: empty */ + { 0, 1, -1 }, /* P8: empty (touch panel) */ + { 1, 0, 5 }, /* P9: system port 1 (To USBAO) (EHCI debug), OC 5 */ + { 1, 0, -1 }, /* P10: fingerprint reader, no OC */ + { 1, 1, -1 }, /* P11: bluetooth, no OC. */ + { 1, 1, -1 }, /* P12: docking, no OC */ + { 1, 1, -1 }, /* P13: camera (LCD), no OC */ +}; diff --git a/src/mainboard/lenovo/t420s/gpio.c b/src/mainboard/lenovo/t420/variants/t420s/gpio.c similarity index 100% rename from src/mainboard/lenovo/t420s/gpio.c rename to src/mainboard/lenovo/t420/variants/t420s/gpio.c diff --git a/src/mainboard/lenovo/t420s/hda_verb.c b/src/mainboard/lenovo/t420/variants/t420s/hda_verb.c similarity index 100% rename from src/mainboard/lenovo/t420s/hda_verb.c rename to src/mainboard/lenovo/t420/variants/t420s/hda_verb.c diff --git a/src/mainboard/lenovo/t420/variants/t420s/overridetree.cb b/src/mainboard/lenovo/t420/variants/t420s/overridetree.cb new file mode 100644 index 0000000..e12d7ea --- /dev/null +++ b/src/mainboard/lenovo/t420/variants/t420s/overridetree.cb @@ -0,0 +1,18 @@ +chip northbridge/intel/sandybridge + device domain 0 on + subsystemid 0x17aa 0x21d2 inherit + + device pci 02.0 on + subsystemid 0x17aa 0x21d3 + end # Integrated Graphics Controller + + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + # Enable SATA ports 0 (HDD bay) & 1 (ODD bay) & 2 (mSATA) & 4 (dock) + register "sata_port_map" = "0x17" + + device pci 19.0 on + subsystemid 0x17aa 0x21ce + end # Intel Gigabit Ethernet + end + end +end diff --git a/src/mainboard/lenovo/t420s/Kconfig b/src/mainboard/lenovo/t420s/Kconfig deleted file mode 100644 index e2fd824..0000000 --- a/src/mainboard/lenovo/t420s/Kconfig +++ /dev/null @@ -1,83 +0,0 @@ -if BOARD_LENOVO_T420S - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select SYSTEM_TYPE_LAPTOP - select NORTHBRIDGE_INTEL_SANDYBRIDGE - select USE_NATIVE_RAMINIT - select SOUTHBRIDGE_INTEL_BD82X6X - select EC_LENOVO_PMH7 - select EC_LENOVO_H8 - select H8_HAS_BAT_TRESHOLDS_IMPL - select NO_UART_ON_SUPERIO - select BOARD_ROMSIZE_KB_8192 - select HAVE_ACPI_TABLES - select HAVE_OPTION_TABLE - select HAVE_CMOS_DEFAULT - select HAVE_ACPI_RESUME - select INTEL_INT15 - select MAINBOARD_HAS_LPC_TPM - select MAINBOARD_HAS_TPM1 - select MAINBOARD_HAS_LIBGFXINIT - select GFX_GMA_PANEL_1_ON_LVDS - select DRIVERS_LENOVO_HYBRID_GRAPHICS - select INTEL_GMA_HAVE_VBT - select MAINBOARD_USES_IFD_GBE_REGION - - # Workaround for EC/KBC IRQ1. - select SERIRQ_CONTINUOUS_MODE - -config VBOOT - select VBOOT_VBNV_CMOS - select GBB_FLAG_DISABLE_LID_SHUTDOWN - select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC - select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC - select GBB_FLAG_DISABLE_FWMP - select HAS_RECOVERY_MRC_CACHE - -config VBOOT_SLOTS_RW_A - default y - -config VBOOT_VBNV_OFFSET - hex - default 0x2a - -config FMDFILE - string - default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT - -config MAINBOARD_DIR - string - default "lenovo/t420s" - -config MAINBOARD_PART_NUMBER - string - default "ThinkPad T420s" - -config MAX_CPUS - int - default 8 - -config USBDEBUG_HCD_INDEX - int - default 2 - -config DRAM_RESET_GATE_GPIO - int - default 10 - -config VGA_BIOS_FILE - string - default "pci8086,0126.rom" - -config VGA_BIOS_ID - string - default "8086,0126" - -config PS2K_EISAID - default "PNP0303" - -config PS2M_EISAID - default "LEN0015" - -endif # BOARD_LENOVO_T420S diff --git a/src/mainboard/lenovo/t420s/Kconfig.name b/src/mainboard/lenovo/t420s/Kconfig.name deleted file mode 100644 index 648688b..0000000 --- a/src/mainboard/lenovo/t420s/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_LENOVO_T420S - bool "ThinkPad T420s" diff --git a/src/mainboard/lenovo/t420s/Makefile.inc b/src/mainboard/lenovo/t420s/Makefile.inc deleted file mode 100644 index 05befdd..0000000 --- a/src/mainboard/lenovo/t420s/Makefile.inc +++ /dev/null @@ -1,21 +0,0 @@ -## -## This file is part of the coreboot project. -## -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -smm-y += smihandler.c -bootblock-y += gpio.c -romstage-y += gpio.c - -ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads -bootblock-y += early_init.c -romstage-y += early_init.c diff --git a/src/mainboard/lenovo/t420s/acpi/ec.asl b/src/mainboard/lenovo/t420s/acpi/ec.asl deleted file mode 100644 index 2dda5ec..0000000 --- a/src/mainboard/lenovo/t420s/acpi/ec.asl +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -#include <ec/lenovo/h8/acpi/ec.asl> - -Scope(\_SB.PCI0.LPCB.EC) -{ -} - -#include <ec/lenovo/h8/acpi/thinkpad_bat_thresholds_b0.asl> diff --git a/src/mainboard/lenovo/t420s/acpi/platform.asl b/src/mainboard/lenovo/t420s/acpi/platform.asl deleted file mode 100644 index dc46182..0000000 --- a/src/mainboard/lenovo/t420s/acpi/platform.asl +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -/* The _PTS method (Prepare To Sleep) is called before the OS is - * entering a sleep state. The sleep state number is passed in Arg0 - */ - -Method(_PTS,1) -{ - \_SB.PCI0.LPCB.EC.MUTE(1) - \_SB.PCI0.LPCB.EC.USBP(0) - \_SB.PCI0.LPCB.EC.RADI(0) -} - -/* The _WAK method is called on system wakeup */ - -Method(_WAK,1) -{ - /* ME may not be up yet. */ - Store (0, \_TZ.MEB1) - Store (0, \_TZ.MEB2) - - /* Wake the HKEY to init BT/WWAN */ - \_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0) - - /* Not implemented. */ - Return(Package(){0,0}) -} diff --git a/src/mainboard/lenovo/t420s/acpi/superio.asl b/src/mainboard/lenovo/t420s/acpi/superio.asl deleted file mode 100644 index f2b35ba..0000000 --- a/src/mainboard/lenovo/t420s/acpi/superio.asl +++ /dev/null @@ -1 +0,0 @@ -#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/lenovo/t420s/acpi_tables.c b/src/mainboard/lenovo/t420s/acpi_tables.c deleted file mode 100644 index 65c6019..0000000 --- a/src/mainboard/lenovo/t420s/acpi_tables.c +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -#include <southbridge/intel/bd82x6x/nvs.h> - -void acpi_create_gnvs(global_nvs_t *gnvs) -{ - /* The lid is open by default */ - gnvs->lids = 1; - - /* Temperature at which OS will shutdown */ - gnvs->tcrt = 100; - /* Temperature at which OS will throttle CPU */ - gnvs->tpsv = 90; -} diff --git a/src/mainboard/lenovo/t420s/cmos.default b/src/mainboard/lenovo/t420s/cmos.default deleted file mode 100644 index 467f965..0000000 --- a/src/mainboard/lenovo/t420s/cmos.default +++ /dev/null @@ -1,16 +0,0 @@ -boot_option=Fallback -debug_level=Debug -power_on_after_fail=Disable -nmi=Enable -volume=0x3 -first_battery=Primary -bluetooth=Enable -wwan=Enable -wlan=Enable -touchpad=Enable -sata_mode=AHCI -fn_ctrl_swap=Disable -sticky_fn=Disable -trackpoint=Enable -hybrid_graphics_mode=Integrated Only -usb_always_on=Disable diff --git a/src/mainboard/lenovo/t420s/cmos.layout b/src/mainboard/lenovo/t420s/cmos.layout deleted file mode 100644 index 26e6300..0000000 --- a/src/mainboard/lenovo/t420s/cmos.layout +++ /dev/null @@ -1,141 +0,0 @@ -## -## This file is part of the coreboot project. -## -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -# ----------------------------------------------------------------- -entries - -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused - -# ----------------------------------------------------------------- -# RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? - -# ----------------------------------------------------------------- -# coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused - -#400 8 r 0 reserved for century byte - -# coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail - -# coreboot config options: EC -411 1 e 8 first_battery -412 1 e 1 bluetooth -413 1 e 1 wwan -414 1 e 1 touchpad -415 1 e 1 wlan -416 1 e 1 trackpoint -417 1 e 1 fn_ctrl_swap -418 1 e 1 sticky_fn -419 1 e 1 power_management_beeps -421 1 e 9 sata_mode -422 2 e 13 usb_always_on - -# coreboot config options: cpu -#424 8 r 0 unused - -# coreboot config options: northbridge -432 3 e 11 gfx_uma_size -435 2 e 12 hybrid_graphics_mode -#437 3 r 0 unused - -440 8 h 0 volume - -# VBOOT -448 128 r 0 vbnv - -# SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 -960 16 r 0 mrc_scrambler_seed_chk - -# coreboot config options: check sums -984 16 h 0 check_sum - -# ----------------------------------------------------------------- - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 Secondary -8 1 Primary -9 0 AHCI -9 1 Compatible -10 0 Both -10 1 Keyboard only -10 2 Thinklight only -10 3 None -11 0 32M -11 1 64M -11 2 96M -11 3 128M -11 4 160M -11 5 192M -11 6 224M -12 0 Integrated Only -12 1 Discrete Only -12 2 Dual Graphics -13 0 Disable -13 1 AC and battery -13 2 AC only - -# ----------------------------------------------------------------- -checksums - -checksum 392 447 984 diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb deleted file mode 100644 index b3399c3..0000000 --- a/src/mainboard/lenovo/t420s/devicetree.cb +++ /dev/null @@ -1,175 +0,0 @@ -chip northbridge/intel/sandybridge - # IGD Displays - register "gfx" = "GMA_STATIC_DISPLAYS(1)" - - # Enable DisplayPort Hotplug with 6ms pulse - register "gpu_dp_d_hotplug" = "0x06" - - # Enable Panel as LVDS and configure power delays - register "gpu_panel_port_select" = "0" # LVDS - register "gpu_panel_power_cycle_delay" = "1" - register "gpu_panel_power_up_delay" = "300" # T1+T2: 30ms - register "gpu_panel_power_down_delay" = "300" # T5+T6: 30ms - register "gpu_panel_power_backlight_on_delay" = "2000" # T3: 200ms - register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms - register "gpu_cpu_backlight" = "0x1155" - register "gpu_pch_backlight" = "0x06100610" - - device cpu_cluster 0 on - chip cpu/intel/model_206ax - # Magic APIC ID to locate this chip - device lapic 0x0 on end - device lapic 0xacac off end - - register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) - - register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7) - end - end - - register "pci_mmio_size" = "2048" - - device domain 0 on - subsystemid 0x17aa 0x21d2 inherit - - device pci 00.0 on end # host bridge - device pci 01.0 on end # NVIDIA Corporation GF119M [NVS 4200M] - device pci 02.0 on - subsystemid 0x17aa 0x21d3 - end # Integrated Graphics Controller - - chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - # GPI routing - # 0 No effect (default) - # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) - # 2 SCI (if corresponding GPIO_EN bit is also set) - register "alt_gp_smi_en" = "0x0000" - register "gpi1_routing" = "2" - register "gpi13_routing" = "2" - - # Enable SATA ports 0 (HDD bay) & 1 (ODD bay) & 2 (mSATA) & 4 (dock) - register "sata_port_map" = "0x17" - # Set max SATA speed to 6.0 Gb/s - register "sata_interface_speed_support" = "0x3" - - register "gen1_dec" = "0x7c1601" - register "gen2_dec" = "0x0c15e1" - register "gen4_dec" = "0x0c06a1" - - register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" - - # Enable zero-based linear PCIe root port functions - register "pcie_port_coalesce" = "1" - - register "c2_latency" = "101" # c2 not supported - - # device specific SPI configuration - register "spi_uvscc" = "0x2005" - register "spi_lvscc" = "0x2005" - - device pci 16.0 off end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 on - subsystemid 0x17aa 0x21ce - end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB Enhanced Host Controller #2 - device pci 1b.0 on end # High Definition Audio Controller - device pci 1c.0 off end # PCIe Port #1 - device pci 1c.1 on end # PCIe Port #2 Integrated Wireless LAN - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 on - smbios_slot_desc "7" "3" "ExpressCard Slot" "8" - end # PCIe Port #4 ExpressCard - device pci 1c.4 on end # PCIe Port #5 NEC Corporation uPD720200A USB 3.0 Host Controller - device pci 1c.5 off end # PCIe Port #6 Intel Gigabit Ethernet PHY (not PCIe) - device pci 1c.6 off end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB Enhanced Host Controller #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on - chip ec/lenovo/pmh7 - device pnp ff.1 on end # dummy - register "backlight_enable" = "0x01" - register "dock_event_enable" = "0x01" - end - - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - - chip ec/lenovo/h8 - device pnp ff.2 on # dummy - io 0x60 = 0x62 - io 0x62 = 0x66 - io 0x64 = 0x1600 - io 0x66 = 0x1604 - end - - register "config0" = "0xa7" - register "config1" = "0x01" - register "config2" = "0xa0" - register "config3" = "0xe2" - - register "has_keyboard_backlight" = "0" - - register "beepmask0" = "0x02" - register "beepmask1" = "0x86" - register "has_power_management_beeps" = "1" - register "event2_enable" = "0xff" - register "event3_enable" = "0xff" - register "event4_enable" = "0xf0" - register "event5_enable" = "0x3c" - register "event6_enable" = "0x00" - register "event7_enable" = "0xa1" - register "event8_enable" = "0x7b" - register "event9_enable" = "0xff" - register "eventa_enable" = "0x00" - register "eventb_enable" = "0x00" - register "eventc_enable" = "0xff" - register "eventd_enable" = "0xff" - register "evente_enable" = "0x0d" - - register "has_bdc_detection" = "1" - register "bdc_gpio_num" = "54" - register "bdc_gpio_lvl" = "0" - end - chip drivers/lenovo/hybrid_graphics - device pnp ff.f on end # dummy - - register "detect_gpio" = "21" - - register "has_panel_hybrid_gpio" = "1" - register "panel_hybrid_gpio" = "52" - register "panel_integrated_lvl" = "1" - - register "has_backlight_gpio" = "0" - register "has_dgpu_power_gpio" = "0" - - register "has_thinker1" = "1" - end - end # LPC Controller - device pci 1f.2 on end # 6 port SATA AHCI Controller - device pci 1f.3 on - # eeprom, 8 virtual devices, same chip - chip drivers/i2c/at24rf08c - device i2c 54 on end - device i2c 55 on end - device i2c 56 on end - device i2c 57 on end - device i2c 5c on end - device i2c 5d on end - device i2c 5e on end - device i2c 5f on end - end - end # SMBus Controller - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 on end # Thermal - end - end -end diff --git a/src/mainboard/lenovo/t420s/dsdt.asl b/src/mainboard/lenovo/t420s/dsdt.asl deleted file mode 100644 index a03b252..0000000 --- a/src/mainboard/lenovo/t420s/dsdt.asl +++ /dev/null @@ -1,40 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -#define THINKPAD_EC_GPE 17 -#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB -#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB -#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 -#define EC_LENOVO_H8_ME_WORKAROUND 1 - -#include <arch/acpi.h> -DefinitionBlock( - "dsdt.aml", - "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up - OEM_ID, - ACPI_TABLE_CREATOR, - 0x20110725 // OEM revision -) -{ - #include <southbridge/intel/common/acpi/platform.asl> - - #include "acpi/platform.asl" - - // global NVS and variables - #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> - - #include <cpu/intel/common/acpi/cpu.asl> - - Scope (\_SB) { - Device (PCI0) - { - #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> - #include <southbridge/intel/bd82x6x/acpi/pch.asl> - - #include <drivers/intel/gma/acpi/default_brightness_levels.asl> - } - } - - #include <southbridge/intel/common/acpi/sleepstates.asl> -} diff --git a/src/mainboard/lenovo/t420s/early_init.c b/src/mainboard/lenovo/t420s/early_init.c deleted file mode 100644 index 4f5f69d..0000000 --- a/src/mainboard/lenovo/t420s/early_init.c +++ /dev/null @@ -1,63 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -#include <device/pci_ops.h> -#include <northbridge/intel/sandybridge/raminit_native.h> -#include <southbridge/intel/bd82x6x/pch.h> -#include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h> -#include <northbridge/intel/sandybridge/sandybridge.h> -#include <device/device.h> - -static void hybrid_graphics_init(void) -{ - bool peg, igd; - u32 reg32; - - early_hybrid_graphics(&igd, &peg); - - if (peg && igd) - return; - - /* Hide disabled devices */ - reg32 = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN); - reg32 &= ~(DEVEN_PEG10 | DEVEN_IGD); - - if (peg) - reg32 |= DEVEN_PEG10; - - if (igd) - reg32 |= DEVEN_IGD; - else - /* Disable IGD VGA decode, no GTT or GFX stolen */ - pci_write_config16(PCI_DEV(0, 0, 0), GGC, 2); - - pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); -} - -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 0, 1, -1 }, /* P0: empty */ - { 1, 1, 1 }, /* P1: system port 2 (To system port) (EHCI debug), OC 1 */ - { 1, 1, -1 }, /* P2: HALF MINICARD (WLAN) no oc */ - { 1, 0, -1 }, /* P3: WWAN, no OC */ - { 1, 1, -1 }, /* P4: smartcard, no OC */ - { 1, 1, -1 }, /* P5: ExpressCard, no OC */ - { 0, 0, -1 }, /* P6: empty */ - { 0, 0, -1 }, /* P7: empty */ - { 0, 1, -1 }, /* P8: empty (touch panel) */ - { 1, 0, 5 }, /* P9: system port 1 (To USBAO) (EHCI debug), OC 5 */ - { 1, 0, -1 }, /* P10: fingerprint reader, no OC */ - { 1, 1, -1 }, /* P11: bluetooth, no OC. */ - { 1, 1, -1 }, /* P12: docking, no OC */ - { 1, 1, -1 }, /* P13: camera (LCD), no OC */ -}; - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[2], 0x51, id_only); -} - -void mainboard_early_init(int s3resume) -{ - hybrid_graphics_init(); -} diff --git a/src/mainboard/lenovo/t420s/gma-mainboard.ads b/src/mainboard/lenovo/t420s/gma-mainboard.ads deleted file mode 100644 index fae3544..0000000 --- a/src/mainboard/lenovo/t420s/gma-mainboard.ads +++ /dev/null @@ -1,23 +0,0 @@ --- SPDX-License-Identifier: GPL-2.0-or-later --- This file is part of the coreboot project. - -with HW.GFX.GMA; -with HW.GFX.GMA.Display_Probing; - -use HW.GFX.GMA; -use HW.GFX.GMA.Display_Probing; - -private package GMA.Mainboard is - - ports : constant Port_List := - (DP1, - DP2, - DP3, - HDMI1, - HDMI2, - HDMI3, - Analog, - LVDS, - others => Disabled); - -end GMA.Mainboard; diff --git a/src/mainboard/lenovo/t420s/mainboard.c b/src/mainboard/lenovo/t420s/mainboard.c deleted file mode 100644 index 0890151..0000000 --- a/src/mainboard/lenovo/t420s/mainboard.c +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -#include <device/device.h> -#include <drivers/intel/gma/int15.h> -#include <ec/lenovo/h8/h8.h> - -static void mainboard_enable(struct device *dev) -{ - install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, - GMA_INT15_PANEL_FIT_DEFAULT, - GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/lenovo/t420s/smihandler.c b/src/mainboard/lenovo/t420s/smihandler.c deleted file mode 100644 index 4432995..0000000 --- a/src/mainboard/lenovo/t420s/smihandler.c +++ /dev/null @@ -1,69 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -#include <arch/io.h> -#include <console/console.h> -#include <cpu/x86/smm.h> -#include <ec/acpi/ec.h> -#include <ec/lenovo/h8/h8.h> -#include <southbridge/intel/bd82x6x/pch.h> -#include <southbridge/intel/common/pmutil.h> - -#define GPE_EC_SCI 1 -#define GPE_EC_WAKE 13 - -static void mainboard_smi_handle_ec_sci(void) -{ - u8 status = inb(EC_SC); - u8 event; - - if (!(status & EC_SCI_EVT)) - return; - - event = ec_query(); - printk(BIOS_DEBUG, "EC event %02x\n", event); -} - -void mainboard_smi_gpi(u32 gpi_sts) -{ - if (gpi_sts & (1 << GPE_EC_SCI)) - mainboard_smi_handle_ec_sci(); -} - -int mainboard_smi_apmc(u8 data) -{ - switch (data) { - case APM_CNT_ACPI_ENABLE: - /* use 0x1600/0x1604 to prevent races with userspace */ - ec_set_ports(0x1604, 0x1600); - /* route EC_SCI to SCI */ - gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SCI); - /* discard all events, and enable attention */ - ec_write(0x80, 0x01); - break; - case APM_CNT_ACPI_DISABLE: - /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't - provide a EC query function */ - ec_set_ports(0x66, 0x62); - /* route EC_SCI to SMI */ - gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SMI); - /* discard all events, and enable attention */ - ec_write(0x80, 0x01); - break; - default: - break; - } - return 0; -} - -void mainboard_smi_sleep(u8 slp_typ) -{ - if (slp_typ == 3) { - u8 ec_wake = ec_read(0x32); - /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ - if (ec_wake & 0x14) { - /* Redirect EC WAKE GPE to SCI. */ - gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI); - } - } -} diff --git a/src/mainboard/lenovo/t420s/vboot-ro-me_clean.fmd b/src/mainboard/lenovo/t420s/vboot-ro-me_clean.fmd deleted file mode 100644 index d1cbff7..0000000 --- a/src/mainboard/lenovo/t420s/vboot-ro-me_clean.fmd +++ /dev/null @@ -1,22 +0,0 @@ -FLASH@0xff800000 0x800000 { - SI_ALL 0x20000 { - SI_DESC 0x1000 - SI_GBE 0x2000 - SI_ME - } - SI_BIOS 0x7e0000 { - UNIFIED_MRC_CACHE 0x20000 { - RECOVERY_MRC_CACHE 0x10000 - RW_MRC_CACHE 0x10000 - } - - WP_RO { - FMAP 0x800 - RO_FRID 0x40 - RO_PADDING 0x7c0 - RO_VPD(PRESERVE) 0x1000 - GBB 0x1e000 - COREBOOT(CBFS) - } - } -} diff --git a/src/mainboard/lenovo/t420s/vboot-ro.fmd b/src/mainboard/lenovo/t420s/vboot-ro.fmd deleted file mode 100644 index 51df8a5..0000000 --- a/src/mainboard/lenovo/t420s/vboot-ro.fmd +++ /dev/null @@ -1,22 +0,0 @@ -FLASH@0xff800000 0x800000 { - SI_ALL 0x500000 { - SI_DESC 0x1000 - SI_GBE 0x2000 - SI_ME 0x4ed000 - } - SI_BIOS 0x300000 { - UNIFIED_MRC_CACHE 0x20000 { - RECOVERY_MRC_CACHE 0x10000 - RW_MRC_CACHE 0x10000 - } - - WP_RO { - FMAP 0x800 - RO_FRID 0x40 - RO_PADDING 0x7c0 - RO_VPD(PRESERVE) 0x1000 - GBB 0x1e000 - COREBOOT(CBFS) - } - } -} diff --git a/src/mainboard/lenovo/t420s/vboot-rwa.fmd b/src/mainboard/lenovo/t420s/vboot-rwa.fmd deleted file mode 100644 index 8a4cd3b..0000000 --- a/src/mainboard/lenovo/t420s/vboot-rwa.fmd +++ /dev/null @@ -1,29 +0,0 @@ -FLASH@0xff800000 0x800000 { - SI_ALL@0x0 0x500000 { - SI_DESC@0x0 0x1000 - SI_GBE@0x1000 0x2000 - SI_ME@0x3000 0x4ed000 - } - SI_BIOS@0x500000 0x300000 { - RW_SECTION_A@0x00000 0x180000 { - VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x16ffc0 - RW_FWID_A@0x17ffc0 0x40 - } - UNIFIED_MRC_CACHE@0x180000 0x20000 { - RECOVERY_MRC_CACHE@0x0 0x10000 - RW_MRC_CACHE@0x10000 0x10000 - } - RW_VPD(PRESERVE)@0x1a0000 0x1000 - SMMSTORE(PRESERVE)@0x1a1000 0x40000 - - WP_RO@0x1e1000 0x11f000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_PADDING@0x840 0x7c0 - RO_VPD(PRESERVE)@0x1000 0x1000 - GBB@0x2000 0x1e000 - COREBOOT(CBFS)@0x20000 0xff000 - } - } -} -- To view, visit https://review.coreboot.org/c/coreboot/+/40381 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If117c48cf8e6131b3d25112346d4ddd1ff366009 Gerrit-Change-Number: 40381 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 12

Change in coreboot[master]: soc/amd: Use uinptr_t over void *
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36562 ) Change subject: soc/amd: Use uinptr_t over void * ...................................................................... soc/amd: Use uinptr_t over void * This reduces the amount casts needed and makes it easier to catch type errors. Change-Id: I24792f45a8e6d70daabd43203df88310681af875 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/acpi_bert_storage.c M src/arch/x86/include/arch/bert_storage.h M src/security/memory/memory_clear.c M src/soc/amd/picasso/memmap.c M src/soc/amd/stoneyridge/memmap.c M src/soc/amd/stoneyridge/northbridge.c 6 files changed, 18 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/36562/1 diff --git a/src/arch/x86/acpi_bert_storage.c b/src/arch/x86/acpi_bert_storage.c index 130f97a..828b0e7 100644 --- a/src/arch/x86/acpi_bert_storage.c +++ b/src/arch/x86/acpi_bert_storage.c @@ -32,7 +32,7 @@ * manage the space. */ static int bert_region_broken; -static void *bert_region_base; +static uintptr_t bert_region_base; static size_t bert_region_size; static size_t bert_region_used; @@ -49,10 +49,10 @@ return bert_region_broken ? 0 : !!bert_region_used; } -void bert_errors_region(void **start, size_t *size) +void bert_errors_region(uintptr_t *start, size_t *size) { if (bert_region_broken) { - *start = NULL; + *start = 0; *size = 0; return; } @@ -538,11 +538,11 @@ /* The region must be in memory marked as reserved. If not implemented, * skip generating the information in the region. */ -__weak void bert_reserved_region(void **start, size_t *size) +__weak void bert_reserved_region(uintptr_t *start, size_t *size) { printk(BIOS_ERR, "Error: %s not implemented. BERT region generation disabled\n", __func__); - *start = NULL; + *start = 0; *size = 0; } @@ -562,7 +562,7 @@ return; } - memset(bert_region_base, 0, bert_region_size); + memset((void *)bert_region_base, 0, bert_region_size); } RAMSTAGE_CBMEM_INIT_HOOK(bert_storage_setup) diff --git a/src/arch/x86/include/arch/bert_storage.h b/src/arch/x86/include/arch/bert_storage.h index 644f24e..f277a67 100644 --- a/src/arch/x86/include/arch/bert_storage.h +++ b/src/arch/x86/include/arch/bert_storage.h @@ -53,12 +53,12 @@ */ /* Get implementation-specific reserved area for generating BERT info */ -void bert_reserved_region(void **start, size_t *size); +void bert_reserved_region(uintptr_t *start, size_t *size); /* Get the region where BERT error structures have been constructed for * generating the ACPI table */ -void bert_errors_region(void **start, size_t *size); +void bert_errors_region(uintptr_t *start, size_t *size); /* Get amount of available storage left for error info */ size_t bert_storage_remaining(void); diff --git a/src/security/memory/memory_clear.c b/src/security/memory/memory_clear.c index 45bee91..7394f81 100644 --- a/src/security/memory/memory_clear.c +++ b/src/security/memory/memory_clear.c @@ -88,14 +88,14 @@ BM_MEM_RAM); /* Add reserved entries */ - void *baseptr = NULL; + uintptr_t baseptr = 0; size_t size = 0; /* Only skip CBMEM, as RELOCATABLE_RAMSTAGE is a requirement, no need * to separately protect stack or heap */ cbmem_get_region(&baseptr, &size); - memranges_insert(&mem, (uintptr_t)baseptr, size, BM_MEM_TABLE); + memranges_insert(&mem, baseptr, size, BM_MEM_TABLE); if (CONFIG(PLATFORM_USES_FSP1_0)) { /* Protect CBMEM pointer */ diff --git a/src/soc/amd/picasso/memmap.c b/src/soc/amd/picasso/memmap.c index c56ac5e..b1465b2 100644 --- a/src/soc/amd/picasso/memmap.c +++ b/src/soc/amd/picasso/memmap.c @@ -49,12 +49,12 @@ #define BERT_REGION_MAX_SIZE 0 #endif -void bert_reserved_region(void **start, size_t *size) +void bert_reserved_region(uintptr_t *start, size_t *size) { if (CONFIG(ACPI_BERT)) - *start = (void *)cbmem_top(); + *start = cbmem_top(); else - *start = NULL; + *start = 0; *size = BERT_REGION_MAX_SIZE; } diff --git a/src/soc/amd/stoneyridge/memmap.c b/src/soc/amd/stoneyridge/memmap.c index 8304ba3..88eafde 100644 --- a/src/soc/amd/stoneyridge/memmap.c +++ b/src/soc/amd/stoneyridge/memmap.c @@ -49,12 +49,12 @@ #define BERT_REGION_MAX_SIZE 0 #endif -void bert_reserved_region(void **start, size_t *size) +void bert_reserved_region(uintptr_t *start, size_t *size) { if (CONFIG(ACPI_BERT)) - *start = (void *)cbmem_top(); + *start = cbmem_top(); else - *start = NULL; + *start = 0; *size = BERT_REGION_MAX_SIZE; } diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index d08722e..f873747 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -254,7 +254,7 @@ * a table with a 0-length region: * BERT: [Firmware Bug]: table invalid. */ - void *rgn; + uintptr_t rgn; size_t size; bert_errors_region(&rgn, &size); if (!rgn) { @@ -262,7 +262,7 @@ } else { current = ALIGN(current, 8); bert = (acpi_bert_t *)current; - acpi_write_bert(bert, (uintptr_t)rgn, size); + acpi_write_bert(bert, rgn, size); acpi_add_table(rsdp, (void *)current); current += bert->header.length; } -- To view, visit https://review.coreboot.org/c/coreboot/+/36562 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24792f45a8e6d70daabd43203df88310681af875 Gerrit-Change-Number: 36562 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: lib/imd: Use uintptr_t over void *
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36561 ) Change subject: lib/imd: Use uintptr_t over void * ...................................................................... lib/imd: Use uintptr_t over void * This reduces the number of casts. Change-Id: I3c41963202e5912da7c96ed8236e80e8bc27a4ed Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/include/cbmem.h M src/include/imd.h M src/lib/fit_payload.c M src/lib/imd.c M src/lib/imd_cbmem.c 5 files changed, 11 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/36561/1 diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 4767c80..c5d8d58 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -110,7 +110,7 @@ /* Add the cbmem memory used to the memory map at boot. */ void cbmem_add_bootmem(void); /* Return the cbmem memory used */ -void cbmem_get_region(void **baseptr, size_t *size); +void cbmem_get_region(uintptr_t *baseptr, size_t *size); void cbmem_list(void); void cbmem_add_records_to_cbtable(struct lb_header *header); diff --git a/src/include/imd.h b/src/include/imd.h index cd2d297..09db1d9 100644 --- a/src/include/imd.h +++ b/src/include/imd.h @@ -101,7 +101,7 @@ int imd_lockdown(struct imd *imd); /* Fill in base address and size of region used by imd. */ -int imd_region_used(struct imd *imd, void **base, size_t *size); +int imd_region_used(struct imd *imd, uintptr_t *base, size_t *size); /* Add an entry to the imd. If id already exists NULL is returned. */ const struct imd_entry *imd_entry_add(const struct imd *imd, uint32_t id, diff --git a/src/lib/fit_payload.c b/src/lib/fit_payload.c index 1b6c986..f719352 100644 --- a/src/lib/fit_payload.c +++ b/src/lib/fit_payload.c @@ -127,7 +127,7 @@ { u32 addr_cells = 1, size_cells = 1; u64 reg_addrs[2], reg_sizes[2]; - void *baseptr = NULL; + uintptr_t baseptr = 0; size_t size = 0; static const char *firmware_path[] = {"firmware", NULL}; @@ -163,7 +163,7 @@ return; } - reg_addrs[1] = (uintptr_t)baseptr; + reg_addrs[1] = baseptr; reg_sizes[1] = size; dt_add_reg_prop(coreboot_node, reg_addrs, reg_sizes, 2, addr_cells, diff --git a/src/lib/imd.c b/src/lib/imd.c index bedcfa8..b24a6f5 100644 --- a/src/lib/imd.c +++ b/src/lib/imd.c @@ -524,11 +524,11 @@ return 0; } -int imd_region_used(struct imd *imd, void **base, size_t *size) +int imd_region_used(struct imd *imd, uintptr_t *base, size_t *size) { struct imd_root *r; struct imd_entry *e; - void *low_addr; + uintptr_t low_addr; size_t sz_used; if (!imd->lg.limit) @@ -542,10 +542,10 @@ /* Use last entry to obtain lowest address. */ e = root_last_entry(r); - low_addr = relative_pointer(r, e->start_offset); + low_addr = (uintptr_t)r + e->start_offset; /* Total size used is the last entry's base up to the limit. */ - sz_used = imd->lg.limit - (uintptr_t)low_addr; + sz_used = imd->lg.limit - low_addr; *base = low_addr; *size = sz_used; diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c index be135c2..3d5f653 100644 --- a/src/lib/imd_cbmem.c +++ b/src/lib/imd_cbmem.c @@ -295,14 +295,14 @@ void cbmem_add_bootmem(void) { - void *baseptr = NULL; + uintptr_t baseptr = 0; size_t size = 0; cbmem_get_region(&baseptr, &size); - bootmem_add_range((uintptr_t)baseptr, size, BM_MEM_TABLE); + bootmem_add_range(baseptr, size, BM_MEM_TABLE); } -void cbmem_get_region(void **baseptr, size_t *size) +void cbmem_get_region(uintptr_t *baseptr, size_t *size) { imd_region_used(cbmem_get_imd(), baseptr, size); } -- To view, visit https://review.coreboot.org/c/coreboot/+/36561 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3c41963202e5912da7c96ed8236e80e8bc27a4ed Gerrit-Change-Number: 36561 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: lib/cbmem: Change the return type of cbmem_top to uinptr_t
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36559 ) Change subject: lib/cbmem: Change the return type of cbmem_top to uinptr_t ...................................................................... lib/cbmem: Change the return type of cbmem_top to uinptr_t This allows to remove a lot of casts. Change-Id: I13c592b81f088b84703ca2f69b08890284c69f26 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/cbmem.c M src/cpu/amd/family_10h-family_15h/ram_calc.c M src/cpu/ti/am335x/cbmem.c M src/drivers/amd/agesa/mtrr_fixme.c M src/drivers/intel/fsp1_1/car.c M src/drivers/intel/fsp1_1/raminit.c M src/drivers/intel/fsp2_0/hob_verify.c M src/include/cbmem.h M src/include/imd.h M src/lib/ext_stage_cache.c M src/lib/imd.c M src/mainboard/emulation/qemu-aarch64/cbmem.c M src/mainboard/emulation/qemu-armv7/cbmem.c M src/mainboard/emulation/qemu-i440fx/memmap.c M src/mainboard/emulation/qemu-power8/cbmem.c M src/northbridge/intel/e7505/memmap.c M src/northbridge/intel/fsp_rangeley/memmap.c M src/northbridge/intel/gm45/memmap.c M src/northbridge/intel/gm45/northbridge.c M src/northbridge/intel/haswell/memmap.c M src/northbridge/intel/i440bx/memmap.c M src/northbridge/intel/i945/memmap.c M src/northbridge/intel/i945/northbridge.c M src/northbridge/intel/nehalem/memmap.c M src/northbridge/intel/pineview/memmap.c M src/northbridge/intel/pineview/northbridge.c M src/northbridge/intel/sandybridge/memmap.c M src/northbridge/intel/x4x/memmap.c M src/northbridge/intel/x4x/northbridge.c M src/northbridge/via/vx900/memmap.c M src/soc/amd/picasso/memmap.c M src/soc/amd/picasso/northbridge.c M src/soc/amd/picasso/romstage.c M src/soc/amd/stoneyridge/memmap.c M src/soc/amd/stoneyridge/northbridge.c M src/soc/amd/stoneyridge/romstage.c M src/soc/cavium/cn81xx/cbmem.c M src/soc/imgtec/pistachio/cbmem.c M src/soc/intel/apollolake/memmap.c M src/soc/intel/baytrail/memmap.c M src/soc/intel/braswell/memmap.c M src/soc/intel/broadwell/memmap.c M src/soc/intel/broadwell/romstage/romstage.c M src/soc/intel/cannonlake/memmap.c M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/denverton_ns/memmap.c M src/soc/intel/fsp_baytrail/memmap.c M src/soc/intel/fsp_baytrail/northcluster.c M src/soc/intel/fsp_broadwell_de/memmap.c M src/soc/intel/icelake/memmap.c M src/soc/intel/quark/memmap.c M src/soc/intel/quark/northcluster.c M src/soc/intel/skylake/memmap.c M src/soc/mediatek/common/cbmem.c M src/soc/nvidia/tegra124/cbmem.c M src/soc/nvidia/tegra210/cbmem.c M src/soc/qualcomm/ipq40xx/cbmem.c M src/soc/qualcomm/ipq806x/cbmem.c M src/soc/qualcomm/qcs405/cbmem.c M src/soc/qualcomm/sc7180/cbmem.c M src/soc/qualcomm/sdm845/cbmem.c M src/soc/rockchip/common/cbmem.c M src/soc/samsung/exynos5250/cbmem.c M src/soc/samsung/exynos5420/cbmem.c M src/soc/sifive/fu540/cbmem.c M src/soc/ucb/riscv/cbmem.c 66 files changed, 146 insertions(+), 150 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/36559/1 diff --git a/src/arch/x86/cbmem.c b/src/arch/x86/cbmem.c index 16c35b5..caaa3d9 100644 --- a/src/arch/x86/cbmem.c +++ b/src/arch/x86/cbmem.c @@ -16,16 +16,16 @@ #if CONFIG(CBMEM_TOP_BACKUP) -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - static void *cbmem_top_backup; - void *top_backup; + static uintptr_t cbmem_top_backup; + uintptr_t top_backup; if (ENV_RAMSTAGE && cbmem_top_backup != NULL) return cbmem_top_backup; /* Top of CBMEM is at highest usable DRAM address below 4GiB. */ - top_backup = (void *)restore_top_of_low_cacheable(); + top_backup = restore_top_of_low_cacheable(); if (ENV_RAMSTAGE) cbmem_top_backup = top_backup; diff --git a/src/cpu/amd/family_10h-family_15h/ram_calc.c b/src/cpu/amd/family_10h-family_15h/ram_calc.c index 3946b67..f7326c7 100644 --- a/src/cpu/amd/family_10h-family_15h/ram_calc.c +++ b/src/cpu/amd/family_10h-family_15h/ram_calc.c @@ -86,9 +86,9 @@ return cc6_size; } -void *cbmem_top(void) +uintptr_t cbmem_top(void) { uint32_t topmem = rdmsr(TOP_MEM).lo; - return (void *) topmem - get_uma_memory_size(topmem) - get_cc6_memory_size(); + return topmem - get_uma_memory_size(topmem) - get_cc6_memory_size(); } diff --git a/src/cpu/ti/am335x/cbmem.c b/src/cpu/ti/am335x/cbmem.c index a626ec6..116d82d 100644 --- a/src/cpu/ti/am335x/cbmem.c +++ b/src/cpu/ti/am335x/cbmem.c @@ -15,7 +15,7 @@ #include <cbmem.h> #include <symbols.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return _dram + (CONFIG_DRAM_SIZE_MB << 20); + return (uintptr_t)_dram + (CONFIG_DRAM_SIZE_MB << 20); } diff --git a/src/drivers/amd/agesa/mtrr_fixme.c b/src/drivers/amd/agesa/mtrr_fixme.c index bbb9eb0..988eaf6 100644 --- a/src/drivers/amd/agesa/mtrr_fixme.c +++ b/src/drivers/amd/agesa/mtrr_fixme.c @@ -57,7 +57,7 @@ * writeback possible. */ - uintptr_t top_of_ram = (uintptr_t) cbmem_top(); + uintptr_t top_of_ram = cbmem_top(); top_of_ram = ALIGN_UP(top_of_ram, 4 * MiB); set_range_uc(top_of_ram - 4 * MiB, 4 * MiB); @@ -90,7 +90,7 @@ * speed make them WB after CAR teardown. */ if (s3resume) { - uintptr_t top_of_ram = (uintptr_t) cbmem_top(); + uintptr_t top_of_ram = cbmem_top(); top_of_ram = ALIGN_DOWN(top_of_ram, 4*MiB); postcar_frame_add_mtrr(pcf, top_of_ram - 4*MiB, 4*MiB, diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c index 2039c9c..2ea4e1b 100644 --- a/src/drivers/intel/fsp1_1/car.c +++ b/src/drivers/intel/fsp1_1/car.c @@ -29,7 +29,7 @@ /* Cache at least 8 MiB below the top of ram, and at most 8 MiB * above top of the ram. This satisfies MTRR alignment requirement * with different TSEG size configurations. */ - top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); + top_of_ram = ALIGN_DOWN(cbmem_top(), 8*MiB); postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB, MTRR_TYPE_WRBACK); } diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c index 59a60cf..21dc431 100644 --- a/src/drivers/intel/fsp1_1/raminit.c +++ b/src/drivers/intel/fsp1_1/raminit.c @@ -151,7 +151,7 @@ } /* Migrate CAR data */ - printk(BIOS_DEBUG, "0x%p: cbmem_top\n", cbmem_top()); + printk(BIOS_DEBUG, "0x%"PRIxPTR": cbmem_top\n", cbmem_top()); if (!s3wake) { cbmem_initialize_empty_id_size(CBMEM_ID_FSP_RESERVED_MEMORY, fsp_reserved_bytes); diff --git a/src/drivers/intel/fsp2_0/hob_verify.c b/src/drivers/intel/fsp2_0/hob_verify.c index e2937d7..e4901b4 100644 --- a/src/drivers/intel/fsp2_0/hob_verify.c +++ b/src/drivers/intel/fsp2_0/hob_verify.c @@ -61,8 +61,8 @@ die("Space between FSP reserved region and BIOS TOLUM!\n"); } - if (range_entry_end(&tolum) != (uintptr_t)cbmem_top()) { - printk(BIOS_CRIT, "TOLUM end: 0x%08llx != 0x%p: cbmem_top\n", + if (range_entry_end(&tolum) != cbmem_top()) { + printk(BIOS_CRIT, "TOLUM end: 0x%08llx != 0x%"PRIxPTR": cbmem_top\n", range_entry_end(&tolum), cbmem_top()); die("Space between cbmem_top and BIOS TOLUM!\n"); } diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 4005fa2..4767c80 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -73,7 +73,7 @@ * below 4GiB for 32bit coreboot builds. On 64bit coreboot builds there's no * upper limit. This should not be called before memory is initialized. */ -void *cbmem_top(void); +uintptr_t cbmem_top(void); /* Add a cbmem entry of a given size and id. These return NULL on failure. The * add function performs a find first and do not check against the original diff --git a/src/include/imd.h b/src/include/imd.h index 6575312..cd2d297 100644 --- a/src/include/imd.h +++ b/src/include/imd.h @@ -59,7 +59,7 @@ * to be called at least once before any other imd related functions * can be used. */ -void imd_handle_init(struct imd *imd, void *upper_limit); +void imd_handle_init(struct imd *imd, uintptr_t upper_limit); /* * Initialize a handle with a shallow recovery. This function doesn't diff --git a/src/lib/ext_stage_cache.c b/src/lib/ext_stage_cache.c index 354342d..52c0d6f 100644 --- a/src/lib/ext_stage_cache.c +++ b/src/lib/ext_stage_cache.c @@ -36,7 +36,7 @@ imd = imd_get(); stage_cache_external_region(&base, &size); - imd_handle_init(imd, (void *)(size + (uintptr_t)base)); + imd_handle_init(imd, size + (uintptr_t)base); printk(BIOS_DEBUG, "External stage cache:\n"); imd_create_tiered_empty(imd, 4096, 4096, 1024, 32); @@ -52,7 +52,7 @@ imd = imd_get(); stage_cache_external_region(&base, &size); - imd_handle_init(imd, (void *)(size + (uintptr_t)base)); + imd_handle_init(imd, size + (uintptr_t)base); if (imd_recover(imd)) printk(BIOS_DEBUG, "Unable to recover external stage cache.\n"); } diff --git a/src/lib/imd.c b/src/lib/imd.c index 17ec2d9..bedcfa8 100644 --- a/src/lib/imd.c +++ b/src/lib/imd.c @@ -132,9 +132,9 @@ e->id = id; } -static void imdr_init(struct imdr *ir, void *upper_limit) +static void imdr_init(struct imdr *ir, uintptr_t upper_limit) { - uintptr_t limit = (uintptr_t)upper_limit; + uintptr_t limit = upper_limit; /* Upper limit is aligned down to 4KiB */ ir->limit = ALIGN_DOWN(limit, LIMIT_ALIGN); ir->r = NULL; @@ -396,10 +396,10 @@ } /* Initialize imd handle. */ -void imd_handle_init(struct imd *imd, void *upper_limit) +void imd_handle_init(struct imd *imd, uintptr_t upper_limit) { imdr_init(&imd->lg, upper_limit); - imdr_init(&imd->sm, NULL); + imdr_init(&imd->sm, 0); } void imd_handle_init_partial_recovery(struct imd *imd) @@ -411,7 +411,7 @@ if (imd->lg.limit == 0) return; - imd_handle_init(imd, (void *)imd->lg.limit); + imd_handle_init(imd, imd->lg.limit); /* Initialize root pointer for the large regions. */ imdr = &imd->lg; @@ -468,7 +468,7 @@ return 0; fail: - imd_handle_init(imd, (void *)imdr->limit); + imd_handle_init(imd, imdr->limit); return -1; } @@ -495,7 +495,7 @@ /* Tear down any changes on failure. */ if (imdr_recover(&imd->sm) != 0) { - imd_handle_init(imd, (void *)imd->lg.limit); + imd_handle_init(imd, imd->lg.limit); return -1; } diff --git a/src/mainboard/emulation/qemu-aarch64/cbmem.c b/src/mainboard/emulation/qemu-aarch64/cbmem.c index c50254d..0675777 100644 --- a/src/mainboard/emulation/qemu-aarch64/cbmem.c +++ b/src/mainboard/emulation/qemu-aarch64/cbmem.c @@ -10,7 +10,7 @@ #include <ramdetect.h> #include <symbols.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return _dram + (probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB) * MiB); + return (uintptr_t)_dram + (probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB) * MiB); } diff --git a/src/mainboard/emulation/qemu-armv7/cbmem.c b/src/mainboard/emulation/qemu-armv7/cbmem.c index 542e08d..bdae66d 100644 --- a/src/mainboard/emulation/qemu-armv7/cbmem.c +++ b/src/mainboard/emulation/qemu-armv7/cbmem.c @@ -15,7 +15,7 @@ #include <symbols.h> #include <ramdetect.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return _dram + (probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB) * MiB); + return (uintptr_t)_dram + (probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB) * MiB); } diff --git a/src/mainboard/emulation/qemu-i440fx/memmap.c b/src/mainboard/emulation/qemu-i440fx/memmap.c index 8209379..c80cf2e 100644 --- a/src/mainboard/emulation/qemu-i440fx/memmap.c +++ b/src/mainboard/emulation/qemu-i440fx/memmap.c @@ -52,15 +52,15 @@ return tomk; } -void *cbmem_top(void) +uintptr_t cbmem_top(void) { uintptr_t top = 0; top = fw_cfg_tolud(); if (!top) - top = (uintptr_t)qemu_get_memory_size() * 1024; + top = qemu_get_memory_size() * 1024; - return (void *)top; + return top; } /* Nothing to do, MTRRs are no-op on QEMU. */ diff --git a/src/mainboard/emulation/qemu-power8/cbmem.c b/src/mainboard/emulation/qemu-power8/cbmem.c index 3df6b80..4391cdb 100644 --- a/src/mainboard/emulation/qemu-power8/cbmem.c +++ b/src/mainboard/emulation/qemu-power8/cbmem.c @@ -15,10 +15,9 @@ #include <cbmem.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { /* Top of cbmem is at lowest usable DRAM address below 4GiB. */ /* For now, last 1M of 4G */ - void *ptr = (void *) ((1ULL << 32) - 1048576); - return ptr; + return (1ULL << 32) - 1048576; } diff --git a/src/northbridge/intel/e7505/memmap.c b/src/northbridge/intel/e7505/memmap.c index c6a20fa..372004a 100644 --- a/src/northbridge/intel/e7505/memmap.c +++ b/src/northbridge/intel/e7505/memmap.c @@ -21,7 +21,7 @@ #include <program_loading.h> #include "e7505.h" -void *cbmem_top(void) +uintptr_t cbmem_top(void) { pci_devfn_t mch = PCI_DEV(0, 0, 0); uintptr_t tolm; @@ -30,7 +30,7 @@ tolm = pci_read_config16(mch, TOLM) >> 11; tolm <<= 27; - return (void *)tolm; + return tolm; } void northbridge_write_smram(u8 smram); @@ -58,7 +58,7 @@ postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); /* Cache CBMEM region as WB. */ - top_of_ram = (uintptr_t)cbmem_top(); + top_of_ram = cbmem_top(); postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); } diff --git a/src/northbridge/intel/fsp_rangeley/memmap.c b/src/northbridge/intel/fsp_rangeley/memmap.c index da9ed71..bdd6466 100644 --- a/src/northbridge/intel/fsp_rangeley/memmap.c +++ b/src/northbridge/intel/fsp_rangeley/memmap.c @@ -36,7 +36,7 @@ return tom; } -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return (void *) (smm_region_start() - FSP_RESERVE_MEMORY_SIZE); + return smm_region_start() - FSP_RESERVE_MEMORY_SIZE; } diff --git a/src/northbridge/intel/gm45/memmap.c b/src/northbridge/intel/gm45/memmap.c index 7479a78..d588088 100644 --- a/src/northbridge/intel/gm45/memmap.c +++ b/src/northbridge/intel/gm45/memmap.c @@ -117,10 +117,9 @@ * 1 MiB alignment. As this may cause very greedy MTRR setup, push * CBMEM top downwards to 4 MiB boundary. */ -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); - return (void *) top_of_ram; + return ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); } void smm_region(uintptr_t *start, size_t *size) @@ -136,7 +135,7 @@ /* Cache 8 MiB region below the top of ram and 2 MiB above top of * ram to cover both cbmem as the TSEG region. */ - top_of_ram = (uintptr_t)cbmem_top(); + top_of_ram = cbmem_top(); postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); postcar_frame_add_mtrr(pcf, northbridge_get_tseg_base(), diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index e652090..df24282 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -137,7 +137,7 @@ /* cbmem_top can be shifted downwards due to alignment. Mark the region between cbmem_top and tomk as unusable */ - delta_cbmem = tomk - ((uint32_t)cbmem_top() >> 10); + delta_cbmem = tomk - (cbmem_top() >> 10); tomk -= delta_cbmem; uma_sizek += delta_cbmem; diff --git a/src/northbridge/intel/haswell/memmap.c b/src/northbridge/intel/haswell/memmap.c index 007a67d..f0e874b 100644 --- a/src/northbridge/intel/haswell/memmap.c +++ b/src/northbridge/intel/haswell/memmap.c @@ -34,9 +34,9 @@ return tom & ~((1 << 20) - 1); } -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return (void *)smm_region_start(); + return smm_region_start(); } void smm_region(uintptr_t *start, size_t *size) diff --git a/src/northbridge/intel/i440bx/memmap.c b/src/northbridge/intel/i440bx/memmap.c index 75a6c7e..112eee3 100644 --- a/src/northbridge/intel/i440bx/memmap.c +++ b/src/northbridge/intel/i440bx/memmap.c @@ -23,7 +23,7 @@ #include <program_loading.h> #include "i440bx.h" -void *cbmem_top(void) +uintptr_t cbmem_top(void) { /* Base of TSEG is top of usable DRAM */ /* @@ -63,7 +63,7 @@ int tseg_size = 128 * KiB * (1 << (tseg >> 1)); tom -= tseg_size; } - return (void *)tom; + return tom; } void fill_postcar_frame(struct postcar_frame *pcf) @@ -71,7 +71,7 @@ uintptr_t top_of_ram; /* Cache CBMEM region as WB. */ - top_of_ram = (uintptr_t)cbmem_top(); + top_of_ram = cbmem_top(); postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); diff --git a/src/northbridge/intel/i945/memmap.c b/src/northbridge/intel/i945/memmap.c index 8207d06..d2423ff 100644 --- a/src/northbridge/intel/i945/memmap.c +++ b/src/northbridge/intel/i945/memmap.c @@ -71,10 +71,9 @@ * 1 MiB alignment. As this may cause very greedy MTRR setup, push * CBMEM top downwards to 4 MiB boundary. */ -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); - return (void *) top_of_ram; + return ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); } /** Decodes used Graphics Mode Select (GMS) to kilobytes. */ diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index dde1b11..10fcccb 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -105,7 +105,7 @@ /* cbmem_top can be shifted downwards due to alignment. Mark the region between cbmem_top and tomk as unusable */ - cbmem_topk = ((uint32_t)cbmem_top() >> 10); + cbmem_topk = cbmem_top() >> 10; delta_cbmem = tomk_stolen - cbmem_topk; tomk_stolen -= delta_cbmem; diff --git a/src/northbridge/intel/nehalem/memmap.c b/src/northbridge/intel/nehalem/memmap.c index 1c17b0d..1116b60 100644 --- a/src/northbridge/intel/nehalem/memmap.c +++ b/src/northbridge/intel/nehalem/memmap.c @@ -42,9 +42,9 @@ return CONFIG_SMM_TSEG_SIZE; } -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return (void *) smm_region_start(); + return smm_region_start(); } void smm_region(uintptr_t *start, size_t *size) diff --git a/src/northbridge/intel/pineview/memmap.c b/src/northbridge/intel/pineview/memmap.c index b4fef6b..c689c6e 100644 --- a/src/northbridge/intel/pineview/memmap.c +++ b/src/northbridge/intel/pineview/memmap.c @@ -132,11 +132,9 @@ * 1 MiB alignment. As this may cause very greedy MTRR setup, push * CBMEM top downwards to 4 MiB boundary. */ -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); - return (void *) top_of_ram; - + return ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); } void smm_region(uintptr_t *start, size_t *size) @@ -152,7 +150,7 @@ /* Cache 8 MiB region below the top of ram and 2 MiB above top of * ram to cover both cbmem as the TSEG region. */ - top_of_ram = (uintptr_t)cbmem_top(); + top_of_ram = cbmem_top(); postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); postcar_frame_add_mtrr(pcf, northbridge_get_tseg_base(), diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c index fc71bc3..c6fd7b7 100644 --- a/src/northbridge/intel/pineview/northbridge.c +++ b/src/northbridge/intel/pineview/northbridge.c @@ -103,7 +103,7 @@ /* cbmem_top can be shifted downwards due to alignment. Mark the region between cbmem_top and tomk as unusable */ - cbmem_topk = (uint32_t)cbmem_top() >> 10; + cbmem_topk = cbmem_top() >> 10; delta_cbmem = tomk - cbmem_topk; tomk -= delta_cbmem; diff --git a/src/northbridge/intel/sandybridge/memmap.c b/src/northbridge/intel/sandybridge/memmap.c index 67de344..65720ed 100644 --- a/src/northbridge/intel/sandybridge/memmap.c +++ b/src/northbridge/intel/sandybridge/memmap.c @@ -31,9 +31,9 @@ return tom; } -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return (void *) smm_region_start(); + return smm_region_start(); } static uintptr_t northbridge_get_tseg_base(void) @@ -56,7 +56,7 @@ { uintptr_t top_of_ram; - top_of_ram = (uintptr_t)cbmem_top(); + top_of_ram = cbmem_top(); /* Cache 8MiB below the top of ram. On sandybridge systems the top of * ram under 4GiB is the start of the TSEG region. It is required to * be 8MiB aligned. Set this area as cacheable so it can be used later diff --git a/src/northbridge/intel/x4x/memmap.c b/src/northbridge/intel/x4x/memmap.c index 41e4912..8ac63af 100644 --- a/src/northbridge/intel/x4x/memmap.c +++ b/src/northbridge/intel/x4x/memmap.c @@ -128,10 +128,9 @@ * 1 MiB alignment. As this may cause very greedy MTRR setup, push * CBMEM top downwards to 4 MiB boundary. */ -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); - return (void *) top_of_ram; + return ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); } void smm_region(uintptr_t *start, size_t *size) @@ -147,7 +146,7 @@ /* Cache 8 MiB region below the top of ram and 2 MiB above top of * ram to cover both cbmem as the TSEG region. */ - top_of_ram = (uintptr_t)cbmem_top(); + top_of_ram = cbmem_top(); postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); postcar_frame_add_mtrr(pcf, northbridge_get_tseg_base(), diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index 39f24d3..49476ae 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -89,7 +89,7 @@ /* cbmem_top can be shifted downwards due to alignment. Mark the region between cbmem_top and tomk as unusable */ - delta_cbmem = tomk - ((uint32_t)cbmem_top() >> 10); + delta_cbmem = tomk - (cbmem_top() >> 10); tomk -= delta_cbmem; uma_sizek += delta_cbmem; diff --git a/src/northbridge/via/vx900/memmap.c b/src/northbridge/via/vx900/memmap.c index d11dc65..8a3a2b7 100644 --- a/src/northbridge/via/vx900/memmap.c +++ b/src/northbridge/via/vx900/memmap.c @@ -120,7 +120,7 @@ return (pci_read_config16(MCU, 0x84) & 0xfff0) >> 4; } -void *cbmem_top(void) +uintptr_t cbmem_top(void) { uintptr_t tolm; uintptr_t fb_size; @@ -131,5 +131,5 @@ if (tolm > 0xfc0 || tolm <= 0x3ff || fb_size == 0x0) return NULL; - return (void *)((tolm - fb_size) << 20); + return (tolm - fb_size) << 20; } diff --git a/src/soc/amd/picasso/memmap.c b/src/soc/amd/picasso/memmap.c index 09af7e4..c56ac5e 100644 --- a/src/soc/amd/picasso/memmap.c +++ b/src/soc/amd/picasso/memmap.c @@ -52,13 +52,13 @@ void bert_reserved_region(void **start, size_t *size) { if (CONFIG(ACPI_BERT)) - *start = cbmem_top(); + *start = (void *)cbmem_top(); else - start = NULL; + *start = NULL; *size = BERT_REGION_MAX_SIZE; } -void *cbmem_top(void) +uintptr_t cbmem_top(void) { msr_t tom = rdmsr(TOP_MEM); @@ -66,14 +66,14 @@ return 0; /* 8MB alignment to keep MTRR usage low */ - return (void *)ALIGN_DOWN(restore_top_of_low_cacheable() - - CONFIG_SMM_TSEG_SIZE - - BERT_REGION_MAX_SIZE, 8*MiB); + return ALIGN_DOWN(restore_top_of_low_cacheable() + - CONFIG_SMM_TSEG_SIZE + - BERT_REGION_MAX_SIZE, 8*MiB); } static uintptr_t smm_region_start(void) { - return (uintptr_t)cbmem_top() + BERT_REGION_MAX_SIZE; + return cbmem_top() + BERT_REGION_MAX_SIZE; } static size_t smm_region_size(void) diff --git a/src/soc/amd/picasso/northbridge.c b/src/soc/amd/picasso/northbridge.c index 08807f3..901622d 100644 --- a/src/soc/amd/picasso/northbridge.c +++ b/src/soc/amd/picasso/northbridge.c @@ -263,7 +263,7 @@ { uint64_t uma_base = get_uma_base(); uint32_t uma_size = get_uma_size(); - uint32_t mem_useable = (uintptr_t)cbmem_top(); + uint32_t mem_useable = cbmem_top(); msr_t tom = rdmsr(TOP_MEM); msr_t high_tom = rdmsr(TOP_MEM2); uint64_t high_mem_useable; diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index 257ae67..9ccb11b 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -76,7 +76,7 @@ * location of ramstage in cbmem is not known. Instruct postcar to cache * 16 megs under cbmem top which is a safe bet to cover ramstage. */ - top_of_ram = (uintptr_t) cbmem_top(); + top_of_ram = cbmem_top(); postcar_frame_add_mtrr(&pcf, top_of_ram - 16*MiB, 16*MiB, MTRR_TYPE_WRBACK); diff --git a/src/soc/amd/stoneyridge/memmap.c b/src/soc/amd/stoneyridge/memmap.c index 09af7e4..8304ba3 100644 --- a/src/soc/amd/stoneyridge/memmap.c +++ b/src/soc/amd/stoneyridge/memmap.c @@ -52,13 +52,13 @@ void bert_reserved_region(void **start, size_t *size) { if (CONFIG(ACPI_BERT)) - *start = cbmem_top(); + *start = (void *)cbmem_top(); else - start = NULL; + *start = NULL; *size = BERT_REGION_MAX_SIZE; } -void *cbmem_top(void) +uintptr_t cbmem_top(void) { msr_t tom = rdmsr(TOP_MEM); @@ -73,7 +73,7 @@ static uintptr_t smm_region_start(void) { - return (uintptr_t)cbmem_top() + BERT_REGION_MAX_SIZE; + return cbmem_top() + BERT_REGION_MAX_SIZE; } static size_t smm_region_size(void) diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 044a1b0..d08722e 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -415,7 +415,7 @@ { uint64_t uma_base = get_uma_base(); uint32_t uma_size = get_uma_size(); - uint32_t mem_useable = (uintptr_t)cbmem_top(); + uint32_t mem_useable = cbmem_top(); msr_t tom = rdmsr(TOP_MEM); msr_t high_tom = rdmsr(TOP_MEM2); uint64_t high_mem_useable; diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 2228c1a..936907f 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -162,7 +162,7 @@ * location of ramstage in cbmem is not known. Instruct postcar to cache * 16 megs under cbmem top which is a safe bet to cover ramstage. */ - top_of_ram = (uintptr_t) cbmem_top(); + top_of_ram = cbmem_top(); postcar_frame_add_mtrr(&pcf, top_of_ram - 16*MiB, 16*MiB, MTRR_TYPE_WRBACK); diff --git a/src/soc/cavium/cn81xx/cbmem.c b/src/soc/cavium/cn81xx/cbmem.c index bb6fa18..a9fd213 100644 --- a/src/soc/cavium/cn81xx/cbmem.c +++ b/src/soc/cavium/cn81xx/cbmem.c @@ -20,7 +20,7 @@ #include <stdlib.h> #include <symbols.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { /* Make sure not to overlap with reserved ATF scratchpad */ return (void *)((uintptr_t)_dram + (sdram_size_mb() - 1) * MiB); diff --git a/src/soc/imgtec/pistachio/cbmem.c b/src/soc/imgtec/pistachio/cbmem.c index 112df7c..c5fffa6 100644 --- a/src/soc/imgtec/pistachio/cbmem.c +++ b/src/soc/imgtec/pistachio/cbmem.c @@ -18,7 +18,7 @@ #include <stdlib.h> #include <symbols.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { return _dram + (CONFIG_DRAM_SIZE_MB << 20); } diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c index 7b60270..a7f2ff6 100644 --- a/src/soc/intel/apollolake/memmap.c +++ b/src/soc/intel/apollolake/memmap.c @@ -26,10 +26,10 @@ #include "chip.h" -void *cbmem_top(void) +uintptr_t cbmem_top(void) { const config_t *config; - void *tolum = (void *)sa_get_tseg_base(); + uintptr_t tolum = sa_get_tseg_base(); if (!CONFIG(SOC_INTEL_GLK)) return tolum; @@ -58,7 +58,7 @@ * location of ramstage in cbmem is not known. Instruct postcar to cache * 16 megs under cbmem top which is a safe bet to cover ramstage. */ - top_of_ram = (uintptr_t) cbmem_top(); + top_of_ram = cbmem_top(); /* cbmem_top() needs to be at least 16 MiB aligned */ assert(ALIGN_DOWN(top_of_ram, 16*MiB) == top_of_ram); postcar_frame_add_mtrr(pcf, top_of_ram - 16*MiB, 16*MiB, diff --git a/src/soc/intel/baytrail/memmap.c b/src/soc/intel/baytrail/memmap.c index d9f6160..3a1bfd9 100644 --- a/src/soc/intel/baytrail/memmap.c +++ b/src/soc/intel/baytrail/memmap.c @@ -29,9 +29,9 @@ return CONFIG_SMM_TSEG_SIZE; } -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return (void *) smm_region_start(); + return smm_region_start(); } void smm_region(uintptr_t *start, size_t *size) @@ -48,7 +48,7 @@ * above top of the ram. This satisfies MTRR alignment requirement * with different TSEG size configurations. */ - top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); + top_of_ram = ALIGN_DOWN(cbmem_top(), 8*MiB); postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB, MTRR_TYPE_WRBACK); } diff --git a/src/soc/intel/braswell/memmap.c b/src/soc/intel/braswell/memmap.c index d502aed..dab9234 100644 --- a/src/soc/intel/braswell/memmap.c +++ b/src/soc/intel/braswell/memmap.c @@ -33,7 +33,7 @@ *size = smm_region_size(); } -void *cbmem_top(void) +uintptr_t cbmem_top(void) { uintptr_t smm_base; size_t smm_size; @@ -67,5 +67,5 @@ */ smm_region(&smm_base, &smm_size); - return (void *)smm_base; + return smm_base; } diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c index f4a9d0e..483e7be 100644 --- a/src/soc/intel/broadwell/memmap.c +++ b/src/soc/intel/broadwell/memmap.c @@ -41,9 +41,9 @@ return tom; } -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return (void *) dpr_region_start(); + return dpr_region_start(); } void smm_region(uintptr_t *start, size_t *size) diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index 96218f4..df446de 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -41,7 +41,7 @@ * above top of the ram. This satisfies MTRR alignment requirement * with different TSEG size configurations. */ - top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); + top_of_ram = ALIGN_DOWN(cbmem_top(), 8*MiB); postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB, MTRR_TYPE_WRBACK); } diff --git a/src/soc/intel/cannonlake/memmap.c b/src/soc/intel/cannonlake/memmap.c index 80aa97d..6d4aa9a 100644 --- a/src/soc/intel/cannonlake/memmap.c +++ b/src/soc/intel/cannonlake/memmap.c @@ -253,13 +253,13 @@ * | | * +-------------------------+ */ -void *cbmem_top(void) +uintptr_t cbmem_top(void) { struct ebda_config ebda_cfg; retrieve_ebda_object(&ebda_cfg); - return (void *)(uintptr_t)ebda_cfg.tolum_base; + return ebda_cfg.tolum_base; } void fill_postcar_frame(struct postcar_frame *pcf) @@ -271,7 +271,7 @@ * Instruct postcar to cache 16 megs under cbmem top which is * a safe bet to cover ramstage. */ - top_of_ram = (uintptr_t) cbmem_top(); + top_of_ram = cbmem_top(); printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); top_of_ram -= 16*MiB; postcar_frame_add_mtrr(pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index e03942f..8b99d17 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -154,7 +154,7 @@ uintptr_t top_of_ram; int index = *resource_count; - top_of_ram = (uintptr_t)cbmem_top(); + top_of_ram = cbmem_top(); /* 0 - > 0xa0000 */ base_k = 0; diff --git a/src/soc/intel/denverton_ns/memmap.c b/src/soc/intel/denverton_ns/memmap.c index 9f788dd..aca1d97 100644 --- a/src/soc/intel/denverton_ns/memmap.c +++ b/src/soc/intel/denverton_ns/memmap.c @@ -60,7 +60,10 @@ power_of_2(iqat_region_size + tseg_region_size); } -void *cbmem_top(void) { return (void *)top_of_32bit_ram(); } +uintptr_t cbmem_top(void) +{ + return top_of_32bit_ram(); +} static inline uintptr_t smm_region_start(void) { @@ -87,7 +90,7 @@ * location of ramstage in cbmem is not known. Instruct postcar to cache * 16 megs under cbmem top which is a safe bet to cover ramstage. */ - top_of_ram = (uintptr_t)cbmem_top(); + top_of_ram = cbmem_top(); postcar_frame_add_mtrr(pcf, top_of_ram - 16 * MiB, 16 * MiB, MTRR_TYPE_WRBACK); diff --git a/src/soc/intel/fsp_baytrail/memmap.c b/src/soc/intel/fsp_baytrail/memmap.c index 7fec7f9..4aee8a1 100644 --- a/src/soc/intel/fsp_baytrail/memmap.c +++ b/src/soc/intel/fsp_baytrail/memmap.c @@ -40,9 +40,9 @@ * @return pointer to the first byte of reserved memory */ -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return find_fsp_reserved_mem(*(void **)CBMEM_FSP_HOB_PTR); + return (uintptr_t)find_fsp_reserved_mem(*(void **)CBMEM_FSP_HOB_PTR); } void smm_region(uintptr_t *start, size_t *size) diff --git a/src/soc/intel/fsp_baytrail/northcluster.c b/src/soc/intel/fsp_baytrail/northcluster.c index 797039a..232263c 100644 --- a/src/soc/intel/fsp_baytrail/northcluster.c +++ b/src/soc/intel/fsp_baytrail/northcluster.c @@ -125,7 +125,7 @@ uint32_t fsp_mem_base = 0; GetHighMemorySize(&highmem_size); - fsp_mem_base=(uint32_t)cbmem_top(); + fsp_mem_base = cbmem_top(); bmbound = iosf_bunit_read(BUNIT_BMBOUND); bsmmrrl = iosf_bunit_read(BUNIT_SMRRL) << 20; diff --git a/src/soc/intel/fsp_broadwell_de/memmap.c b/src/soc/intel/fsp_broadwell_de/memmap.c index cbd3cf7..2e6f1f6 100644 --- a/src/soc/intel/fsp_broadwell_de/memmap.c +++ b/src/soc/intel/fsp_broadwell_de/memmap.c @@ -23,9 +23,9 @@ #include <soc/pci_devs.h> #include <device/pci_ops.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return find_fsp_reserved_mem(*(void **)CBMEM_FSP_HOB_PTR); + return (uintptr_t)find_fsp_reserved_mem(*(void **)CBMEM_FSP_HOB_PTR); } /* diff --git a/src/soc/intel/icelake/memmap.c b/src/soc/intel/icelake/memmap.c index 00f45cf..2afa849 100644 --- a/src/soc/intel/icelake/memmap.c +++ b/src/soc/intel/icelake/memmap.c @@ -232,13 +232,13 @@ * | | * +-------------------------+ */ -void *cbmem_top(void) +uintptr_t cbmem_top(void) { struct ebda_config ebda_cfg; retrieve_ebda_object(&ebda_cfg); - return (void *)(uintptr_t)ebda_cfg.tolum_base; + return ebda_cfg.tolum_base; } void fill_postcar_frame(struct postcar_frame *pcf) @@ -250,7 +250,7 @@ * Instruct postcar to cache 16 megs under cbmem top which is * a safe bet to cover ramstage. */ - top_of_ram = (uintptr_t) cbmem_top(); + top_of_ram = cbmem_top(); printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); top_of_ram -= 16*MiB; postcar_frame_add_mtrr(pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); diff --git a/src/soc/intel/quark/memmap.c b/src/soc/intel/quark/memmap.c index b8b8506..c0f326e 100644 --- a/src/soc/intel/quark/memmap.c +++ b/src/soc/intel/quark/memmap.c @@ -18,7 +18,7 @@ #include <cbmem.h> #include <soc/reg_access.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { uint32_t top_of_memory; @@ -32,7 +32,7 @@ top_of_memory -= 0x10000; /* Return the top of memory */ - return (void *)top_of_memory; + return top_of_memory; } void fill_postcar_frame(struct postcar_frame *pcf) @@ -41,7 +41,7 @@ uintptr_t top_of_low_usable_memory; /* Locate the top of RAM */ - top_of_low_usable_memory = (uintptr_t) cbmem_top(); + top_of_low_usable_memory = cbmem_top(); top_of_ram = ALIGN(top_of_low_usable_memory, 16 * MiB); /* Cache postcar and ramstage */ diff --git a/src/soc/intel/quark/northcluster.c b/src/soc/intel/quark/northcluster.c index 0507efc..c10f002 100644 --- a/src/soc/intel/quark/northcluster.c +++ b/src/soc/intel/quark/northcluster.c @@ -55,7 +55,7 @@ /* 0x100000 -> cbmem_top - cacheable and usable */ base_k += size_k; - size_k = (unsigned long)cbmem_top() - base_k; + size_k = cbmem_top() - base_k; ram_resource(dev, index++, RES_IN_KIB(base_k), RES_IN_KIB(size_k)); /* cbmem_top -> 0xc0000000 - reserved */ diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c index c6ccd71..688c69b 100644 --- a/src/soc/intel/skylake/memmap.c +++ b/src/soc/intel/skylake/memmap.c @@ -254,13 +254,13 @@ * | | * +-------------------------+ */ -void *cbmem_top(void) +uintptr_t cbmem_top(void) { struct ebda_config ebda_cfg; retrieve_ebda_object(&ebda_cfg); - return (void *)(uintptr_t)ebda_cfg.tolum_base; + return ebda_cfg.tolum_base; } void fill_postcar_frame(struct postcar_frame *pcf) @@ -273,7 +273,7 @@ * Instruct postcar to cache 16 megs under cbmem top which is * a safe bet to cover ramstage. */ - top_of_ram = (uintptr_t) cbmem_top(); + top_of_ram = cbmem_top(); printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); top_of_ram -= 16*MiB; postcar_frame_add_mtrr(pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); diff --git a/src/soc/mediatek/common/cbmem.c b/src/soc/mediatek/common/cbmem.c index 8906565..7d0aad6 100644 --- a/src/soc/mediatek/common/cbmem.c +++ b/src/soc/mediatek/common/cbmem.c @@ -21,7 +21,7 @@ #define MAX_DRAM_ADDRESS ((uintptr_t)4 * GiB) -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return (void *)min((uintptr_t)_dram + sdram_size(), MAX_DRAM_ADDRESS); + return min((uintptr_t)_dram + sdram_size(), MAX_DRAM_ADDRESS); } diff --git a/src/soc/nvidia/tegra124/cbmem.c b/src/soc/nvidia/tegra124/cbmem.c index 4b52a51..d11816a 100644 --- a/src/soc/nvidia/tegra124/cbmem.c +++ b/src/soc/nvidia/tegra124/cbmem.c @@ -17,7 +17,7 @@ #include <soc/display.h> #include <soc/sdram.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return (void *)((sdram_max_addressable_mb() - FB_SIZE_MB) << 20UL); + return ((sdram_max_addressable_mb() - FB_SIZE_MB) << 20UL); } diff --git a/src/soc/nvidia/tegra210/cbmem.c b/src/soc/nvidia/tegra210/cbmem.c index 63ae497..21f8819 100644 --- a/src/soc/nvidia/tegra210/cbmem.c +++ b/src/soc/nvidia/tegra210/cbmem.c @@ -16,7 +16,7 @@ #include <cbmem.h> #include <soc/addressmap.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { static uintptr_t addr; @@ -32,5 +32,5 @@ addr = end_mib << 20; } - return (void *)addr; + return addr; } diff --git a/src/soc/qualcomm/ipq40xx/cbmem.c b/src/soc/qualcomm/ipq40xx/cbmem.c index 05325cc..dc2c721 100644 --- a/src/soc/qualcomm/ipq40xx/cbmem.c +++ b/src/soc/qualcomm/ipq40xx/cbmem.c @@ -23,7 +23,7 @@ cbmem_backing_store_ready = 1; } -void *cbmem_top(void) +uintptr_t cbmem_top(void) { /* * In romstage, make sure that cbmem backing store is ready before @@ -32,7 +32,7 @@ * for loading ipq blobs before DRAM is initialized). */ if (ENV_ROMSTAGE && (cbmem_backing_store_ready == 0)) - return NULL; + return 0; - return _memlayout_cbmem_top; + return (uintptr_t)_memlayout_cbmem_top; } diff --git a/src/soc/qualcomm/ipq806x/cbmem.c b/src/soc/qualcomm/ipq806x/cbmem.c index 9674db6..54bdba2 100644 --- a/src/soc/qualcomm/ipq806x/cbmem.c +++ b/src/soc/qualcomm/ipq806x/cbmem.c @@ -23,7 +23,7 @@ cbmem_backing_store_ready = 1; } -void *cbmem_top(void) +uintptr_t cbmem_top(void) { /* * In romstage, make sure that cbmem backing store is ready before @@ -33,7 +33,7 @@ * initialized). */ if (ENV_ROMSTAGE && (cbmem_backing_store_ready == 0)) - return NULL; + return 0; - return _memlayout_cbmem_top; + return (uintptr_t)_memlayout_cbmem_top; } diff --git a/src/soc/qualcomm/qcs405/cbmem.c b/src/soc/qualcomm/qcs405/cbmem.c index e065409..b9f70a4 100644 --- a/src/soc/qualcomm/qcs405/cbmem.c +++ b/src/soc/qualcomm/qcs405/cbmem.c @@ -15,7 +15,7 @@ #include <cbmem.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return (void *)((uintptr_t)3 * GiB); + return 3 * GiB; } diff --git a/src/soc/qualcomm/sc7180/cbmem.c b/src/soc/qualcomm/sc7180/cbmem.c index 597e369..833c9d2 100644 --- a/src/soc/qualcomm/sc7180/cbmem.c +++ b/src/soc/qualcomm/sc7180/cbmem.c @@ -15,7 +15,7 @@ #include <cbmem.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return (void *)((uintptr_t)4 * GiB); + return 4 * GiB; } diff --git a/src/soc/qualcomm/sdm845/cbmem.c b/src/soc/qualcomm/sdm845/cbmem.c index 3b9ad4a..1cacbf4 100644 --- a/src/soc/qualcomm/sdm845/cbmem.c +++ b/src/soc/qualcomm/sdm845/cbmem.c @@ -15,7 +15,7 @@ #include <cbmem.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return (void *)((uintptr_t)4 * GiB); + return 4 * GiB; } diff --git a/src/soc/rockchip/common/cbmem.c b/src/soc/rockchip/common/cbmem.c index 401f8b2..105e178 100644 --- a/src/soc/rockchip/common/cbmem.c +++ b/src/soc/rockchip/common/cbmem.c @@ -19,8 +19,8 @@ #include <stdlib.h> #include <symbols.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return (void *)min((uintptr_t)_dram + sdram_size_mb() * MiB, + return min((uintptr_t)_dram + sdram_size_mb() * MiB, MAX_DRAM_ADDRESS); } diff --git a/src/soc/samsung/exynos5250/cbmem.c b/src/soc/samsung/exynos5250/cbmem.c index 1874495..dc02577 100644 --- a/src/soc/samsung/exynos5250/cbmem.c +++ b/src/soc/samsung/exynos5250/cbmem.c @@ -17,7 +17,7 @@ #include <cbmem.h> #include <soc/cpu.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return (void *)(get_fb_base_kb() * KiB); + return get_fb_base_kb() * KiB; } diff --git a/src/soc/samsung/exynos5420/cbmem.c b/src/soc/samsung/exynos5420/cbmem.c index e1999e8..de75663 100644 --- a/src/soc/samsung/exynos5420/cbmem.c +++ b/src/soc/samsung/exynos5420/cbmem.c @@ -17,7 +17,7 @@ #include <soc/cpu.h> #include <stddef.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return (void *)(get_fb_base_kb() * KiB); + return get_fb_base_kb() * KiB; } diff --git a/src/soc/sifive/fu540/cbmem.c b/src/soc/sifive/fu540/cbmem.c index 1c68de8..facc714 100644 --- a/src/soc/sifive/fu540/cbmem.c +++ b/src/soc/sifive/fu540/cbmem.c @@ -19,8 +19,7 @@ #include <stdlib.h> #include <symbols.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return (void *)min((uintptr_t)_dram + sdram_size_mb() * MiB, - FU540_MAXDRAM); + return min((uintptr_t)_dram + sdram_size_mb() * MiB, FU540_MAXDRAM); } diff --git a/src/soc/ucb/riscv/cbmem.c b/src/soc/ucb/riscv/cbmem.c index 542e08d..bdae66d 100644 --- a/src/soc/ucb/riscv/cbmem.c +++ b/src/soc/ucb/riscv/cbmem.c @@ -15,7 +15,7 @@ #include <symbols.h> #include <ramdetect.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return _dram + (probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB) * MiB); + return (uintptr_t)_dram + (probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB) * MiB); } -- To view, visit https://review.coreboot.org/c/coreboot/+/36559 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I13c592b81f088b84703ca2f69b08890284c69f26 Gerrit-Change-Number: 36559 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

6 13

Change in coreboot[master]: emulation/riscv: Don't probe for total DRAM
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36445 ) Change subject: emulation/riscv: Don't probe for total DRAM ...................................................................... emulation/riscv: Don't probe for total DRAM Trying accessing memory that is not there causes an exception. Change-Id: Ic4d9fbb727f41436798783a357b3cfb7b64d3edb Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/emulation/qemu-riscv/Kconfig M src/mainboard/emulation/qemu-riscv/mainboard.c M src/soc/ucb/riscv/cbmem.c 3 files changed, 4 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/36445/1 diff --git a/src/mainboard/emulation/qemu-riscv/Kconfig b/src/mainboard/emulation/qemu-riscv/Kconfig index fa6dccc..c3136c1 100644 --- a/src/mainboard/emulation/qemu-riscv/Kconfig +++ b/src/mainboard/emulation/qemu-riscv/Kconfig @@ -55,8 +55,8 @@ default 1 config DRAM_SIZE_MB - int - default 32768 + int "size of DRAM. Run qemu with the argument -m ***M" + default 1024 config OPENSBI_PLATFORM string diff --git a/src/mainboard/emulation/qemu-riscv/mainboard.c b/src/mainboard/emulation/qemu-riscv/mainboard.c index 88898087..eda43c9 100644 --- a/src/mainboard/emulation/qemu-riscv/mainboard.c +++ b/src/mainboard/emulation/qemu-riscv/mainboard.c @@ -27,7 +27,7 @@ die("No dev0; die\n"); } - dram_mb_detected = probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB); + dram_mb_detected = CONFIG_DRAM_SIZE_MB - CONFIG_ROM_SIZE; ram_resource(dev, 0, (uintptr_t)_dram / KiB, dram_mb_detected * MiB / KiB); cbmem_recovery(0); diff --git a/src/soc/ucb/riscv/cbmem.c b/src/soc/ucb/riscv/cbmem.c index 542e08d..9872760 100644 --- a/src/soc/ucb/riscv/cbmem.c +++ b/src/soc/ucb/riscv/cbmem.c @@ -13,9 +13,8 @@ #include <cbmem.h> #include <symbols.h> -#include <ramdetect.h> void *cbmem_top(void) { - return _dram + (probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB) * MiB); + return _dram + CONFIG_DRAM_SIZE_MB * MiB - CONFIG_ROM_SIZE; } -- To view, visit https://review.coreboot.org/c/coreboot/+/36445 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4d9fbb727f41436798783a357b3cfb7b64d3edb Gerrit-Change-Number: 36445 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 9

Change in coreboot[master]: mb/*/*: Don't guard serial setup
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36603 ) Change subject: mb/*/*: Don't guard serial setup ...................................................................... mb/*/*: Don't guard serial setup Even without using the console it might be useful to set up the console regardless, for instance with VBOOT or normal/fallback setups. This will be more meaningful once C_ENVIRONMENT_BOOTBLOCK is implemented. Change-Id: Ieca2ec1e376cdb26d76222126307fe016572d9d7 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/hp/compaq_8200_elite_sff/romstage.c M src/mainboard/hp/z220_sff_workstation/romstage.c M src/mainboard/ocp/wedge100s/romstage.c 3 files changed, 3 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/36603/1 diff --git a/src/mainboard/hp/compaq_8200_elite_sff/romstage.c b/src/mainboard/hp/compaq_8200_elite_sff/romstage.c index 258eac7..b0dd962 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/romstage.c +++ b/src/mainboard/hp/compaq_8200_elite_sff/romstage.c @@ -58,8 +58,7 @@ void mainboard_config_superio(void) { - if (CONFIG(CONSOLE_SERIAL)) - nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } void mainboard_get_spd(spd_raw_data *spd, bool id_only) diff --git a/src/mainboard/hp/z220_sff_workstation/romstage.c b/src/mainboard/hp/z220_sff_workstation/romstage.c index 6c139ed..e07007c 100644 --- a/src/mainboard/hp/z220_sff_workstation/romstage.c +++ b/src/mainboard/hp/z220_sff_workstation/romstage.c @@ -58,8 +58,7 @@ void mainboard_config_superio(void) { - if (CONFIG(CONSOLE_SERIAL)) - nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } void mainboard_get_spd(spd_raw_data *spd, bool id_only) diff --git a/src/mainboard/ocp/wedge100s/romstage.c b/src/mainboard/ocp/wedge100s/romstage.c index 108d7a1..c0d2ca0 100644 --- a/src/mainboard/ocp/wedge100s/romstage.c +++ b/src/mainboard/ocp/wedge100s/romstage.c @@ -42,8 +42,7 @@ pci_write_config32(PCI_DEV(0x0, LPC_DEV, LPC_FUNC), LPC_GEN2_DEC, (0 << 16) | ALIGN_DOWN(0xca2, 4) | 1); - if (CONFIG(CONSOLE_SERIAL)) - ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); /* -- To view, visit https://review.coreboot.org/c/coreboot/+/36603 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieca2ec1e376cdb26d76222126307fe016572d9d7 Gerrit-Change-Number: 36603 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

7 16

Change in coreboot[master]: *.asl: Don't define Devices by absolute path
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36600 ) Change subject: *.asl: Don't define Devices by absolute path ...................................................................... *.asl: Don't define Devices by absolute path Be consistent with the rest tree and set the scope first when defining devices. In general make the resulting code more readable as it avoid '^' symbols. Change-Id: I0b8dd33fac7cb1524d920b77e95c08b839157e8f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/asus/h61m-cs/dsdt.asl M src/mainboard/asus/p8z77-m_pro/dsdt.asl M src/mainboard/gigabyte/ga-h61m-s2pv/dsdt.asl M src/mainboard/lenovo/t440p/dsdt.asl M src/mainboard/msi/ms7707/dsdt.asl M src/mainboard/supermicro/x10slm-f/dsdt.asl M util/autoport/main.go 7 files changed, 42 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/36600/1 diff --git a/src/mainboard/asus/h61m-cs/dsdt.asl b/src/mainboard/asus/h61m-cs/dsdt.asl index 0e1cc3a..a1a70c0 100644 --- a/src/mainboard/asus/h61m-cs/dsdt.asl +++ b/src/mainboard/asus/h61m-cs/dsdt.asl @@ -32,9 +32,11 @@ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> #include <southbridge/intel/common/acpi/sleepstates.asl> - Device (\_SB.PCI0) { - #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> - #include <drivers/intel/gma/acpi/default_brightness_levels.asl> - #include <southbridge/intel/bd82x6x/acpi/pch.asl> + Scope (\_SB) { + Device (PCI0) { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } } } diff --git a/src/mainboard/asus/p8z77-m_pro/dsdt.asl b/src/mainboard/asus/p8z77-m_pro/dsdt.asl index 1c7a620..2c14e8f 100644 --- a/src/mainboard/asus/p8z77-m_pro/dsdt.asl +++ b/src/mainboard/asus/p8z77-m_pro/dsdt.asl @@ -34,10 +34,11 @@ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> #include <southbridge/intel/common/acpi/sleepstates.asl> - Device (\_SB.PCI0) - { - #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> - #include <drivers/intel/gma/acpi/default_brightness_levels.asl> - #include <southbridge/intel/bd82x6x/acpi/pch.asl> + Scope (\_SB) { + Device (PCI0) { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } } } diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/dsdt.asl b/src/mainboard/gigabyte/ga-h61m-s2pv/dsdt.asl index 7ee12a0..e54b01b 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/dsdt.asl +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/dsdt.asl @@ -37,10 +37,11 @@ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> #include <southbridge/intel/common/acpi/sleepstates.asl> - Device (\_SB.PCI0) - { - #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> - #include <drivers/intel/gma/acpi/default_brightness_levels.asl> - #include <southbridge/intel/bd82x6x/acpi/pch.asl> + Scope (\_SB) { + Device (PCI0) { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } } } diff --git a/src/mainboard/lenovo/t440p/dsdt.asl b/src/mainboard/lenovo/t440p/dsdt.asl index 82358aa..fd37f9e 100644 --- a/src/mainboard/lenovo/t440p/dsdt.asl +++ b/src/mainboard/lenovo/t440p/dsdt.asl @@ -37,10 +37,11 @@ #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> #include <southbridge/intel/common/acpi/sleepstates.asl> - Device (\_SB.PCI0) - { - #include <northbridge/intel/haswell/acpi/haswell.asl> - #include <drivers/intel/gma/acpi/default_brightness_levels.asl> - #include <southbridge/intel/lynxpoint/acpi/pch.asl> + Scope (\_SB) { + Device (PCI0) { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } } } diff --git a/src/mainboard/msi/ms7707/dsdt.asl b/src/mainboard/msi/ms7707/dsdt.asl index d3e3602..6df1394 100644 --- a/src/mainboard/msi/ms7707/dsdt.asl +++ b/src/mainboard/msi/ms7707/dsdt.asl @@ -32,10 +32,11 @@ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> #include <southbridge/intel/common/acpi/sleepstates.asl> - Device (\_SB.PCI0) - { - #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> - #include <drivers/intel/gma/acpi/default_brightness_levels.asl> - #include <southbridge/intel/bd82x6x/acpi/pch.asl> + Scope (\_SB) { + Device (PCI0) { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } } } diff --git a/src/mainboard/supermicro/x10slm-f/dsdt.asl b/src/mainboard/supermicro/x10slm-f/dsdt.asl index 6ed19ee..8649a95 100644 --- a/src/mainboard/supermicro/x10slm-f/dsdt.asl +++ b/src/mainboard/supermicro/x10slm-f/dsdt.asl @@ -24,10 +24,11 @@ #include <southbridge/intel/common/acpi/sleepstates.asl> #include <cpu/intel/common/acpi/cpu.asl> - Device (\_SB.PCI0) - { - #include <northbridge/intel/haswell/acpi/haswell.asl> - #include <southbridge/intel/lynxpoint/acpi/pch.asl> - #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + Scope (\_SB) { + Device (PCI0) { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } } } diff --git a/util/autoport/main.go b/util/autoport/main.go index 03523a2..51d10cf 100644 --- a/util/autoport/main.go +++ b/util/autoport/main.go @@ -876,17 +876,20 @@ } dsdt.WriteString(` - Device (\_SB.PCI0) + Scope (\_SB) { + Device (PCI0) + { `) for _, x := range DSDTPCI0Includes { if x.Comment != "" { fmt.Fprintf(dsdt, "\t/* %s. */\n", x.Comment) } - fmt.Fprintf(dsdt, "\t\t#include <%s>\n", x.File) + fmt.Fprintf(dsdt, "\t\t\t#include <%s>\n", x.File) } dsdt.WriteString( - ` } + ` } + } } `) -- To view, visit https://review.coreboot.org/c/coreboot/+/36600 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b8dd33fac7cb1524d920b77e95c08b839157e8f Gerrit-Change-Number: 36600 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/Kconfig: Move MMCONF_BASE_ADDRESS out of a common place
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35884 ) Change subject: soc/intel/Kconfig: Move MMCONF_BASE_ADDRESS out of a common place ...................................................................... soc/intel/Kconfig: Move MMCONF_BASE_ADDRESS out of a common place include/device/pci_mmio_cfg.h now has a compile time error if MMCONF_BASE_ADDRESS is not defined. This requires soc/intel target to explicitly set this in the SOC dir, instead of potentially using a possibly wrong common default. Change-Id: Idcfea1718cc36ae16b491604786c26c6ed320f06 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/apollolake/Kconfig M src/soc/intel/cannonlake/Kconfig M src/soc/intel/common/block/systemagent/Kconfig M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/skylake/Kconfig 5 files changed, 16 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/35884/1 diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index a1d3c07..24a4b7a 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -128,6 +128,10 @@ TPM part is conntected on Fast SPI interface, but the LPC MMIO TPM transactions are decoded and serialized over the SPI interface. +config MMCONF_BASE_ADDRESS + hex + default 0xe0000000 + config PCR_BASE_ADDRESS hex default 0xd0000000 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index c1fda95..aeef75c 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -109,6 +109,10 @@ select FSP_T_XIP if FSP_CAR select HECI_DISABLE_USING_SMM if !SOC_INTEL_COFFEELAKE && !SOC_INTEL_WHISKEYLAKE && !SOC_INTEL_COMETLAKE +config MMCONF_BASE_ADDRESS + hex + default 0xe0000000 + config DCACHE_RAM_BASE default 0xfef00000 diff --git a/src/soc/intel/common/block/systemagent/Kconfig b/src/soc/intel/common/block/systemagent/Kconfig index 1222573..d7619a0 100644 --- a/src/soc/intel/common/block/systemagent/Kconfig +++ b/src/soc/intel/common/block/systemagent/Kconfig @@ -3,10 +3,6 @@ help Intel Processor common System Agent support -config MMCONF_BASE_ADDRESS - hex - default 0xe0000000 - config SA_PCIEX_LENGTH hex default 0x10000000 if (PCIEX_LENGTH_256MB) diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index 2aadcae..d12e4e3 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -91,6 +91,10 @@ int default 16 +config MMCONF_BASE_ADDRESS + hex + default 0xe0000000 + config PCR_BASE_ADDRESS hex default 0xfd000000 diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 901e5f9..a9b8aaa 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -120,6 +120,10 @@ hex default 0x200000 +config MMCONF_BASE_ADDRESS + hex + default 0xe0000000 + config DCACHE_RAM_BASE hex default 0xfef00000 -- To view, visit https://review.coreboot.org/c/coreboot/+/35884 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idcfea1718cc36ae16b491604786c26c6ed320f06 Gerrit-Change-Number: 35884 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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