June 2019 - coreboot-gerrit - mail.coreboot.org

Change in ...coreboot[master]: sb/intel/fsp_rangeley: Remove variable set but not used
by HAOUAS Elyes (Code Review) June 3, 2019

June 3, 2019

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32942 Change subject: sb/intel/fsp_rangeley: Remove variable set but not used ...................................................................... sb/intel/fsp_rangeley: Remove variable set but not used Change-Id: Ia2bc9bb0f0ece5ae3a57662b54f3e7e78ce00b19 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/fsp_rangeley/romstage.c 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/32942/1 diff --git a/src/southbridge/intel/fsp_rangeley/romstage.c b/src/southbridge/intel/fsp_rangeley/romstage.c index 19e470e..2c2427e 100644 --- a/src/southbridge/intel/fsp_rangeley/romstage.c +++ b/src/southbridge/intel/fsp_rangeley/romstage.c @@ -90,7 +90,6 @@ * Memory is setup and the stack is set by the FSP. */ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) { - int cbmem_was_initted; void *cbmem_hob_ptr; timestamp_add_now(TS_AFTER_INITRAM); @@ -113,7 +112,7 @@ /* Decode E0000 and F0000 segment to DRAM */ sideband_write(B_UNIT, BMISC, sideband_read(B_UNIT, BMISC) | (1 << 1) | (1 << 0)); - cbmem_was_initted = !cbmem_recovery(0); + cbmem_recovery(0); /* Save the HOB pointer in CBMEM to be used in ramstage*/ cbmem_hob_ptr = cbmem_add(CBMEM_ID_HOB_POINTER, sizeof(*hob_list_ptr)); -- To view, visit https://review.coreboot.org/c/coreboot/+/32942 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia2bc9bb0f0ece5ae3a57662b54f3e7e78ce00b19 Gerrit-Change-Number: 32942 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

4 3

Change in ...coreboot[master]: nb/intel/sandybridge: Remove variable set but not used
by HAOUAS Elyes (Code Review) June 3, 2019

June 3, 2019

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32938 Change subject: nb/intel/sandybridge: Remove variable set but not used ...................................................................... nb/intel/sandybridge: Remove variable set but not used Change-Id: I75f5d821e018932d3f10d84b7ebed362777fb17d Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 6 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/32938/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 5347c5c..900633a 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1452,9 +1452,8 @@ int lane; FOR_ALL_LANES { - volatile u32 tmp; MCHBAR32(0x4340 + 0x400 * channel + 4 * lane) = 0; - tmp = MCHBAR32(0x4140 + 0x400 * channel + 4 * lane); + MCHBAR32(0x4140 + 0x400 * channel + 4 * lane); } wait_428c(channel); @@ -1997,9 +1996,8 @@ MCHBAR32_OR(0x5030, 8); FOR_ALL_POPULATED_CHANNELS { - volatile u32 tmp; MCHBAR32_AND(0x4020 + 0x400 * channel, ~0x00200000); - tmp = MCHBAR32(0x428c + 0x400 * channel); + MCHBAR32(0x428c + 0x400 * channel); wait_428c(channel); /* DRAM command ZQCS */ @@ -2344,9 +2342,8 @@ program_timings(ctrl, channel); FOR_ALL_LANES { - volatile u32 tmp; MCHBAR32(0x4340 + 0x400 * channel + 4 * lane) = 0; - tmp = MCHBAR32(0x400 * channel + 4 * lane + 0x4140); + MCHBAR32(0x400 * channel + 4 * lane + 0x4140); } wait_428c(channel); @@ -2425,8 +2422,7 @@ fill_pattern0(ctrl, channel, 0, 0); MCHBAR32(0x4288 + (channel << 10)) = 0; FOR_ALL_LANES { - volatile u32 tmp; - tmp = MCHBAR32(0x400 * channel + lane * 4 + 0x4140); + MCHBAR32(0x400 * channel + lane * 4 + 0x4140); } FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { @@ -2626,10 +2622,9 @@ program_timings(ctrl, channel); FOR_ALL_LANES { - volatile u32 tmp; MCHBAR32(0x4340 + 0x400 * channel + 4 * lane) = 0; - tmp = MCHBAR32(0x400 * channel + + MCHBAR32(0x400 * channel + 4 * lane + 0x4140); } wait_428c(channel); @@ -2674,8 +2669,7 @@ wait_428c(channel); FOR_ALL_LANES { - volatile u32 tmp; - tmp = MCHBAR32(0x4340 + + MCHBAR32(0x4340 + 0x400 * channel + lane * 4); } -- To view, visit https://review.coreboot.org/c/coreboot/+/32938 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I75f5d821e018932d3f10d84b7ebed362777fb17d Gerrit-Change-Number: 32938 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

4 8

Change in ...coreboot[master]: nb/intel/sandybridge: Remove variable set but not used
by HAOUAS Elyes (Code Review) June 3, 2019

June 3, 2019

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32926 Change subject: nb/intel/sandybridge: Remove variable set but not used ...................................................................... nb/intel/sandybridge: Remove variable set but not used Change-Id: Iaac05f73d2ba892d3ec7ee2ac0c16a98f2fce5bc Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/sandybridge/early_dmi.c 1 file changed, 64 insertions(+), 65 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/32926/1 diff --git a/src/northbridge/intel/sandybridge/early_dmi.c b/src/northbridge/intel/sandybridge/early_dmi.c index db49040..6d41a2d 100644 --- a/src/northbridge/intel/sandybridge/early_dmi.c +++ b/src/northbridge/intel/sandybridge/early_dmi.c @@ -19,7 +19,6 @@ void early_init_dmi(void) { - volatile u32 tmp; int i; DMIBAR32(0x0914) |= 0x80000000; @@ -39,133 +38,133 @@ DMIBAR32(0x090c) &= 0xfe1fffff; DMIBAR32(0x092c) &= 0xfe1fffff; - tmp = DMIBAR32(0x0904); // !!! = 0x7a1842ec + DMIBAR32(0x0904); // !!! = 0x7a1842ec DMIBAR32(0x0904) = 0x7a1842ec; - tmp = DMIBAR32(0x090c); // !!! = 0x00000208 + DMIBAR32(0x090c); // !!! = 0x00000208 DMIBAR32(0x090c) = 0x00000128; - tmp = DMIBAR32(0x0924); // !!! = 0x7a1842ec + DMIBAR32(0x0924); // !!! = 0x7a1842ec DMIBAR32(0x0924) = 0x7a1842ec; - tmp = DMIBAR32(0x092c); // !!! = 0x00000208 + DMIBAR32(0x092c); // !!! = 0x00000208 DMIBAR32(0x092c) = 0x00000128; - tmp = DMIBAR32(0x0700); // !!! = 0x46139008 + DMIBAR32(0x0700); // !!! = 0x46139008 DMIBAR32(0x0700) = 0x46139008; - tmp = DMIBAR32(0x0720); // !!! = 0x46139008 + DMIBAR32(0x0720); // !!! = 0x46139008 DMIBAR32(0x0720) = 0x46139008; - tmp = DMIBAR32(0x0c04); // !!! = 0x2e680008 + DMIBAR32(0x0c04); // !!! = 0x2e680008 DMIBAR32(0x0c04) = 0x2e680008; - tmp = DMIBAR32(0x0904); // !!! = 0x7a1842ec + DMIBAR32(0x0904); // !!! = 0x7a1842ec DMIBAR32(0x0904) = 0x3a1842ec; - tmp = DMIBAR32(0x0924); // !!! = 0x7a1842ec + DMIBAR32(0x0924); // !!! = 0x7a1842ec DMIBAR32(0x0924) = 0x3a1842ec; - tmp = DMIBAR32(0x0910); // !!! = 0x00006300 + DMIBAR32(0x0910); // !!! = 0x00006300 DMIBAR32(0x0910) = 0x00004300; - tmp = DMIBAR32(0x0930); // !!! = 0x00006300 + DMIBAR32(0x0930); // !!! = 0x00006300 DMIBAR32(0x0930) = 0x00004300; - tmp = DMIBAR32(0x0a00); // !!! = 0x03042010 + DMIBAR32(0x0a00); // !!! = 0x03042010 DMIBAR32(0x0a00) = 0x03042018; - tmp = DMIBAR32(0x0a10); // !!! = 0x03042010 + DMIBAR32(0x0a10); // !!! = 0x03042010 DMIBAR32(0x0a10) = 0x03042018; - tmp = DMIBAR32(0x0a20); // !!! = 0x03042010 + DMIBAR32(0x0a20); // !!! = 0x03042010 DMIBAR32(0x0a20) = 0x03042018; - tmp = DMIBAR32(0x0a30); // !!! = 0x03042010 + DMIBAR32(0x0a30); // !!! = 0x03042010 DMIBAR32(0x0a30) = 0x03042018; - tmp = DMIBAR32(0x0c00); // !!! = 0x29700c08 + DMIBAR32(0x0c00); // !!! = 0x29700c08 DMIBAR32(0x0c00) = 0x29700c08; - tmp = DMIBAR32(0x0a04); // !!! = 0x0c0708f0 + DMIBAR32(0x0a04); // !!! = 0x0c0708f0 DMIBAR32(0x0a04) = 0x0c0718f0; - tmp = DMIBAR32(0x0a14); // !!! = 0x0c0708f0 + DMIBAR32(0x0a14); // !!! = 0x0c0708f0 DMIBAR32(0x0a14) = 0x0c0718f0; - tmp = DMIBAR32(0x0a24); // !!! = 0x0c0708f0 + DMIBAR32(0x0a24); // !!! = 0x0c0708f0 DMIBAR32(0x0a24) = 0x0c0718f0; - tmp = DMIBAR32(0x0a34); // !!! = 0x0c0708f0 + DMIBAR32(0x0a34); // !!! = 0x0c0708f0 DMIBAR32(0x0a34) = 0x0c0718f0; - tmp = DMIBAR32(0x0900); // !!! = 0x50000000 + DMIBAR32(0x0900); // !!! = 0x50000000 DMIBAR32(0x0900) = 0x50000000; - tmp = DMIBAR32(0x0920); // !!! = 0x50000000 + DMIBAR32(0x0920); // !!! = 0x50000000 DMIBAR32(0x0920) = 0x50000000; - tmp = DMIBAR32(0x0908); // !!! = 0x51ffffff + DMIBAR32(0x0908); // !!! = 0x51ffffff DMIBAR32(0x0908) = 0x51ffffff; - tmp = DMIBAR32(0x0928); // !!! = 0x51ffffff + DMIBAR32(0x0928); // !!! = 0x51ffffff DMIBAR32(0x0928) = 0x51ffffff; - tmp = DMIBAR32(0x0a00); // !!! = 0x03042018 + DMIBAR32(0x0a00); // !!! = 0x03042018 DMIBAR32(0x0a00) = 0x03042018; - tmp = DMIBAR32(0x0a10); // !!! = 0x03042018 + DMIBAR32(0x0a10); // !!! = 0x03042018 DMIBAR32(0x0a10) = 0x03042018; - tmp = DMIBAR32(0x0a20); // !!! = 0x03042018 + DMIBAR32(0x0a20); // !!! = 0x03042018 DMIBAR32(0x0a20) = 0x03042018; - tmp = DMIBAR32(0x0a30); // !!! = 0x03042018 + DMIBAR32(0x0a30); // !!! = 0x03042018 DMIBAR32(0x0a30) = 0x03042018; - tmp = DMIBAR32(0x0700); // !!! = 0x46139008 + DMIBAR32(0x0700); // !!! = 0x46139008 DMIBAR32(0x0700) = 0x46139008; - tmp = DMIBAR32(0x0720); // !!! = 0x46139008 + DMIBAR32(0x0720); // !!! = 0x46139008 DMIBAR32(0x0720) = 0x46139008; - tmp = DMIBAR32(0x0904); // !!! = 0x3a1842ec + DMIBAR32(0x0904); // !!! = 0x3a1842ec DMIBAR32(0x0904) = 0x3a1846ec; - tmp = DMIBAR32(0x0924); // !!! = 0x3a1842ec + DMIBAR32(0x0924); // !!! = 0x3a1842ec DMIBAR32(0x0924) = 0x3a1846ec; - tmp = DMIBAR32(0x0a00); // !!! = 0x03042018 + DMIBAR32(0x0a00); // !!! = 0x03042018 DMIBAR32(0x0a00) = 0x03042018; - tmp = DMIBAR32(0x0a10); // !!! = 0x03042018 + DMIBAR32(0x0a10); // !!! = 0x03042018 DMIBAR32(0x0a10) = 0x03042018; - tmp = DMIBAR32(0x0a20); // !!! = 0x03042018 + DMIBAR32(0x0a20); // !!! = 0x03042018 DMIBAR32(0x0a20) = 0x03042018; - tmp = DMIBAR32(0x0a30); // !!! = 0x03042018 + DMIBAR32(0x0a30); // !!! = 0x03042018 DMIBAR32(0x0a30) = 0x03042018; - tmp = DMIBAR32(0x0908); // !!! = 0x51ffffff + DMIBAR32(0x0908); // !!! = 0x51ffffff DMIBAR32(0x0908) = 0x51ffffff; - tmp = DMIBAR32(0x0928); // !!! = 0x51ffffff + DMIBAR32(0x0928); // !!! = 0x51ffffff DMIBAR32(0x0928) = 0x51ffffff; - tmp = DMIBAR32(0x0c00); // !!! = 0x29700c08 + DMIBAR32(0x0c00); // !!! = 0x29700c08 DMIBAR32(0x0c00) = 0x29700c08; - tmp = DMIBAR32(0x0c0c); // !!! = 0x16063400 + DMIBAR32(0x0c0c); // !!! = 0x16063400 DMIBAR32(0x0c0c) = 0x00063400; - tmp = DMIBAR32(0x0700); // !!! = 0x46139008 + DMIBAR32(0x0700); // !!! = 0x46139008 DMIBAR32(0x0700) = 0x46339008; - tmp = DMIBAR32(0x0720); // !!! = 0x46139008 + DMIBAR32(0x0720); // !!! = 0x46139008 DMIBAR32(0x0720) = 0x46339008; - tmp = DMIBAR32(0x0700); // !!! = 0x46339008 + DMIBAR32(0x0700); // !!! = 0x46339008 DMIBAR32(0x0700) = 0x45339008; - tmp = DMIBAR32(0x0720); // !!! = 0x46339008 + DMIBAR32(0x0720); // !!! = 0x46339008 DMIBAR32(0x0720) = 0x45339008; - tmp = DMIBAR32(0x0700); // !!! = 0x45339008 + DMIBAR32(0x0700); // !!! = 0x45339008 DMIBAR32(0x0700) = 0x453b9008; - tmp = DMIBAR32(0x0720); // !!! = 0x45339008 + DMIBAR32(0x0720); // !!! = 0x45339008 DMIBAR32(0x0720) = 0x453b9008; - tmp = DMIBAR32(0x0700); // !!! = 0x453b9008 + DMIBAR32(0x0700); // !!! = 0x453b9008 DMIBAR32(0x0700) = 0x45bb9008; - tmp = DMIBAR32(0x0720); // !!! = 0x453b9008 + DMIBAR32(0x0720); // !!! = 0x453b9008 DMIBAR32(0x0720) = 0x45bb9008; - tmp = DMIBAR32(0x0700); // !!! = 0x45bb9008 + DMIBAR32(0x0700); // !!! = 0x45bb9008 DMIBAR32(0x0700) = 0x45fb9008; - tmp = DMIBAR32(0x0720); // !!! = 0x45bb9008 + DMIBAR32(0x0720); // !!! = 0x45bb9008 DMIBAR32(0x0720) = 0x45fb9008; - tmp = DMIBAR32(0x0914); // !!! = 0x9021a080 + DMIBAR32(0x0914); // !!! = 0x9021a080 DMIBAR32(0x0914) = 0x9021a280; - tmp = DMIBAR32(0x0934); // !!! = 0x9021a080 + DMIBAR32(0x0934); // !!! = 0x9021a080 DMIBAR32(0x0934) = 0x9021a280; - tmp = DMIBAR32(0x0914); // !!! = 0x9021a280 + DMIBAR32(0x0914); // !!! = 0x9021a280 DMIBAR32(0x0914) = 0x9821a280; - tmp = DMIBAR32(0x0934); // !!! = 0x9021a280 + DMIBAR32(0x0934); // !!! = 0x9021a280 DMIBAR32(0x0934) = 0x9821a280; - tmp = DMIBAR32(0x0a00); // !!! = 0x03042018 + DMIBAR32(0x0a00); // !!! = 0x03042018 DMIBAR32(0x0a00) = 0x03242018; - tmp = DMIBAR32(0x0a10); // !!! = 0x03042018 + DMIBAR32(0x0a10); // !!! = 0x03042018 DMIBAR32(0x0a10) = 0x03242018; - tmp = DMIBAR32(0x0a20); // !!! = 0x03042018 + DMIBAR32(0x0a20); // !!! = 0x03042018 DMIBAR32(0x0a20) = 0x03242018; - tmp = DMIBAR32(0x0a30); // !!! = 0x03042018 + DMIBAR32(0x0a30); // !!! = 0x03042018 DMIBAR32(0x0a30) = 0x03242018; - tmp = DMIBAR32(0x0258); // !!! = 0x40000600 + DMIBAR32(0x0258); // !!! = 0x40000600 DMIBAR32(0x0258) = 0x60000600; - tmp = DMIBAR32(0x0904); // !!! = 0x3a1846ec + DMIBAR32(0x0904); // !!! = 0x3a1846ec DMIBAR32(0x0904) = 0x2a1846ec; - tmp = DMIBAR32(0x0914); // !!! = 0x9821a280 + DMIBAR32(0x0914); // !!! = 0x9821a280 DMIBAR32(0x0914) = 0x98200280; - tmp = DMIBAR32(0x0924); // !!! = 0x3a1846ec + DMIBAR32(0x0924); // !!! = 0x3a1846ec DMIBAR32(0x0924) = 0x2a1846ec; - tmp = DMIBAR32(0x0934); // !!! = 0x9821a280 + DMIBAR32(0x0934); // !!! = 0x9821a280 DMIBAR32(0x0934) = 0x98200280; - tmp = DMIBAR32(0x022c); // !!! = 0x00c26460 + DMIBAR32(0x022c); // !!! = 0x00c26460 DMIBAR32(0x022c) = 0x00c2403c; early_pch_init_native_dmi_pre(); -- To view, visit https://review.coreboot.org/c/coreboot/+/32926 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaac05f73d2ba892d3ec7ee2ac0c16a98f2fce5bc Gerrit-Change-Number: 32926 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

5 7

Change in ...coreboot[master]: mb/google/hatch: Set VmxEnable to 1
by Furquan Shaikh (Code Review) June 3, 2019

June 3, 2019

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31438 Change subject: mb/google/hatch: Set VmxEnable to 1 ...................................................................... mb/google/hatch: Set VmxEnable to 1 This change sets VmxEnable to 1 to match the kernel setting. BUG=b:124518711 Change-Id: I20f9282a94dc502e963578c435061ffe52ce83d3 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/31438/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index aaef663..1cb570c 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -49,6 +49,7 @@ register "SataPortsEnable[1]" = "1" register "SataPortsDevSlp[1]" = "1" register "satapwroptimize" = "1" + register "VmxEnable" = "1" # Enable System Agent dynamic frequency register "SaGv" = "SaGv_Enabled" # Enable heci communication -- To view, visit https://review.coreboot.org/c/coreboot/+/31438 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20f9282a94dc502e963578c435061ffe52ce83d3 Gerrit-Change-Number: 31438 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

5 6

Change in ...coreboot[master]: soc/intel: Drop soc_uart_set_legacy_mode() implementations
by Nico Huber (Code Review) June 3, 2019

June 3, 2019

Hello Patrick Rudolph, Lance Zhao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/33093 to review the following change. Change subject: soc/intel: Drop soc_uart_set_legacy_mode() implementations ...................................................................... soc/intel: Drop soc_uart_set_legacy_mode() implementations They are never called: The only calling path is guarded by both !DRIVERS_UART_8250MEM_32 and INTEL_LPSS_UART_FOR_CONSOLE but the latter selects the former. If somebody figures out how this is supposed to be used, we can easily revive the implementation. Change-Id: I96e304bdee4eadb52725027d0d662ef75f3d4307 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/soc/intel/cannonlake/uart.c M src/soc/intel/icelake/uart.c M src/soc/intel/skylake/uart.c 3 files changed, 0 insertions(+), 45 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/33093/1 diff --git a/src/soc/intel/cannonlake/uart.c b/src/soc/intel/cannonlake/uart.c index 2bd906a..7174a9a 100644 --- a/src/soc/intel/cannonlake/uart.c +++ b/src/soc/intel/cannonlake/uart.c @@ -24,10 +24,6 @@ #include <soc/pci_devs.h> #include <soc/pcr_ids.h> -/* Serial IO UART controller legacy mode */ -#define PCR_SERIAL_IO_GPPRVRW7 0x618 -#define PCR_SIO_PCH_LEGACY_UART(idx) (1 << (idx)) - const struct uart_gpio_pad_config uart_gpio_pads[] = { { .console_index = 0, @@ -54,17 +50,6 @@ const int uart_max_index = ARRAY_SIZE(uart_gpio_pads); -void soc_uart_set_legacy_mode(void) -{ - pcr_write32(PID_SERIALIO, PCR_SERIAL_IO_GPPRVRW7, - PCR_SIO_PCH_LEGACY_UART(CONFIG_UART_FOR_CONSOLE)); - /* - * Dummy read after setting any of GPPRVRW7. - * Required for UART 16550 8-bit Legacy mode to become active - */ - lpss_clk_read(UART_BASE(CONFIG_UART_FOR_CONSOLE)); -} - struct device *soc_uart_console_to_device(int uart_console) { /* diff --git a/src/soc/intel/icelake/uart.c b/src/soc/intel/icelake/uart.c index 2bd906a..7174a9a 100644 --- a/src/soc/intel/icelake/uart.c +++ b/src/soc/intel/icelake/uart.c @@ -24,10 +24,6 @@ #include <soc/pci_devs.h> #include <soc/pcr_ids.h> -/* Serial IO UART controller legacy mode */ -#define PCR_SERIAL_IO_GPPRVRW7 0x618 -#define PCR_SIO_PCH_LEGACY_UART(idx) (1 << (idx)) - const struct uart_gpio_pad_config uart_gpio_pads[] = { { .console_index = 0, @@ -54,17 +50,6 @@ const int uart_max_index = ARRAY_SIZE(uart_gpio_pads); -void soc_uart_set_legacy_mode(void) -{ - pcr_write32(PID_SERIALIO, PCR_SERIAL_IO_GPPRVRW7, - PCR_SIO_PCH_LEGACY_UART(CONFIG_UART_FOR_CONSOLE)); - /* - * Dummy read after setting any of GPPRVRW7. - * Required for UART 16550 8-bit Legacy mode to become active - */ - lpss_clk_read(UART_BASE(CONFIG_UART_FOR_CONSOLE)); -} - struct device *soc_uart_console_to_device(int uart_console) { /* diff --git a/src/soc/intel/skylake/uart.c b/src/soc/intel/skylake/uart.c index 1b2a742..8b7c99e 100644 --- a/src/soc/intel/skylake/uart.c +++ b/src/soc/intel/skylake/uart.c @@ -24,10 +24,6 @@ #include <soc/pci_devs.h> #include <soc/pcr_ids.h> -/* Serial IO UART controller legacy mode */ -#define PCR_SERIAL_IO_GPPRVRW7 0x618 -#define PCR_SIO_PCH_LEGACY_UART(idx) (1 << (idx)) - /* UART pad configuration. Support RXD and TXD for now. */ const struct uart_gpio_pad_config uart_gpio_pads[] = { { @@ -55,17 +51,6 @@ const int uart_max_index = ARRAY_SIZE(uart_gpio_pads); -void soc_uart_set_legacy_mode(void) -{ - pcr_write32(PID_SERIALIO, PCR_SERIAL_IO_GPPRVRW7, - PCR_SIO_PCH_LEGACY_UART(CONFIG_UART_FOR_CONSOLE)); - /* - * Dummy read after setting any of GPPRVRW7. - * Required for UART 16550 8-bit Legacy mode to become active - */ - lpss_clk_read(UART_BASE(CONFIG_UART_FOR_CONSOLE)); -} - struct device *soc_uart_console_to_device(int uart_console) { /* -- To view, visit https://review.coreboot.org/c/coreboot/+/33093 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96e304bdee4eadb52725027d0d662ef75f3d4307 Gerrit-Change-Number: 33093 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/device: Prevent attack on null pointer dereference
by John Zhao (Code Review) June 3, 2019

June 3, 2019

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33101 Change subject: src/device: Prevent attack on null pointer dereference ...................................................................... src/device: Prevent attack on null pointer dereference Clang Static Analyzer version 8.0.0 detects access to field dev results in a dereference of a null pointer which is loaded from variable bus. Add sanity check for pointer bus to prevent null pointer dereference. TEST=Built and boot up to kernel. Change-Id: I084906c33065eaa834f50c545efcfab620658ec9 Signed-off-by: John Zhao <john.zhao(a)intel.com> --- M src/device/device.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/33101/1 diff --git a/src/device/device.c b/src/device/device.c index 1b4255b..5edc173 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -340,6 +340,9 @@ resource_t base; base = round(bridge->base, bridge->align); + if (!base) + return; + printk(BIOS_SPEW, "%s %s: base: %llx size: %llx align: %d gran: %d" " limit: %llx\n", dev_path(bus->dev), resource2str(bridge), base, bridge->size, bridge->align, @@ -484,6 +487,9 @@ resource_t base; base = bridge->base; + if (!base) + return; + printk(BIOS_SPEW, "%s %s: base:%llx size:%llx align:%d gran:%d " "limit:%llx\n", dev_path(bus->dev), resource2str(bridge), -- To view, visit https://review.coreboot.org/c/coreboot/+/33101 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I084906c33065eaa834f50c545efcfab620658ec9 Gerrit-Change-Number: 33101 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/common/uart: Correctly guard uart_platform_base()
by Nico Huber (Code Review) June 3, 2019

June 3, 2019

Hello Patrick Rudolph, Lance Zhao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/33097 to review the following change. Change subject: soc/intel/common/uart: Correctly guard uart_platform_base() ...................................................................... soc/intel/common/uart: Correctly guard uart_platform_base() We should only provide this implementation when the Intel LPSS UART is used. Otherwise, no other UART could be used for the console with these SoCs. Change-Id: Iebd89edb3f21d4a68587fd02659b4d529f3f4bbe Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/soc/intel/common/block/uart/uart.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/33097/1 diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index 47774b6..84ba1ee 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -43,7 +43,7 @@ CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL); } -#if CONFIG(DRIVERS_UART_8250MEM) +#if CONFIG(INTEL_LPSS_UART_FOR_CONSOLE) uintptr_t uart_platform_base(int idx) { if (idx == CONFIG_UART_FOR_CONSOLE) -- To view, visit https://review.coreboot.org/c/coreboot/+/33097 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebd89edb3f21d4a68587fd02659b4d529f3f4bbe Gerrit-Change-Number: 33097 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/common/uart: Only return valid UART base
by Nico Huber (Code Review) June 3, 2019

June 3, 2019

Hello Patrick Rudolph, Lance Zhao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/33096 to review the following change. Change subject: soc/intel/common/uart: Only return valid UART base ...................................................................... soc/intel/common/uart: Only return valid UART base We only configure the base address for the console UART, the other addresses are never assigned to the hardware. It seems better to return 0 for them instead of a spurious value. Change-Id: I3fa5c99958b56ca5b0b603917c086bdddb677fa2 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/soc/intel/common/block/uart/uart.c 1 file changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/33096/1 diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index 35c2c6c..47774b6 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -46,8 +46,9 @@ #if CONFIG(DRIVERS_UART_8250MEM) uintptr_t uart_platform_base(int idx) { - /* return Base address for UART console index */ - return UART_BASE_0_ADDR(idx); + if (idx == CONFIG_UART_FOR_CONSOLE) + return UART_BASE_0_ADDR(CONFIG_UART_FOR_CONSOLE); + return 0; } #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/33096 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3fa5c99958b56ca5b0b603917c086bdddb677fa2 Gerrit-Change-Number: 33096 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/common/uart: Drop dead call to soc_uart_set_legacy_mode()
by Nico Huber (Code Review) June 3, 2019

June 3, 2019

Hello Patrick Rudolph, Lance Zhao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/33095 to review the following change. Change subject: soc/intel/common/uart: Drop dead call to soc_uart_set_legacy_mode() ...................................................................... soc/intel/common/uart: Drop dead call to soc_uart_set_legacy_mode() The only path that leads here is guarded by both !DRIVERS_UART_ 8250MEM_32 and INTEL_LPSS_UART_FOR_CONSOLE but the latter selects the former. Change-Id: I6e0765b028572950991c45b45b2051f4f176a94a Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/soc/intel/common/block/include/intelblocks/uart.h M src/soc/intel/common/block/uart/uart.c 2 files changed, 0 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/33095/1 diff --git a/src/soc/intel/common/block/include/intelblocks/uart.h b/src/soc/intel/common/block/include/intelblocks/uart.h index ad2ddf4..55f259d 100644 --- a/src/soc/intel/common/block/include/intelblocks/uart.h +++ b/src/soc/intel/common/block/include/intelblocks/uart.h @@ -91,10 +91,4 @@ */ struct device *soc_uart_console_to_device(int uart_console); -/* - * Set UART to legacy mode - * Put UART in byte access mode for 16550 compatibility - */ -void soc_uart_set_legacy_mode(void); - #endif /* SOC_INTEL_COMMON_BLOCK_UART_H */ diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index a8e5792..35c2c6c 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -139,10 +139,6 @@ uart_common_init(uart_get_device(), UART_BASE(CONFIG_UART_FOR_CONSOLE)); - if (!CONFIG(DRIVERS_UART_8250MEM_32)) - /* Put UART in byte access mode for 16550 compatibility */ - soc_uart_set_legacy_mode(); - /* Configure the 2 pads per UART. */ uart_configure_gpio_pads(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/33095 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e0765b028572950991c45b45b2051f4f176a94a Gerrit-Change-Number: 33095 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/common/lpss: Drop now unused lpss_clk_read()
by Nico Huber (Code Review) June 3, 2019

June 3, 2019

Hello Patrick Rudolph, Lance Zhao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/33094 to review the following change. Change subject: soc/intel/common/lpss: Drop now unused lpss_clk_read() ...................................................................... soc/intel/common/lpss: Drop now unused lpss_clk_read() Change-Id: I7def72e820ee1a4fa47c34b26dab9e0886ba74e6 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/soc/intel/common/block/include/intelblocks/lpss.h M src/soc/intel/common/block/lpss/lpss.c 2 files changed, 0 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/33094/1 diff --git a/src/soc/intel/common/block/include/intelblocks/lpss.h b/src/soc/intel/common/block/include/intelblocks/lpss.h index ca55689..eb38f13 100644 --- a/src/soc/intel/common/block/include/intelblocks/lpss.h +++ b/src/soc/intel/common/block/include/intelblocks/lpss.h @@ -30,7 +30,4 @@ /* Check if controller is in reset. */ bool lpss_is_controller_in_reset(uintptr_t base); -/* Read LPSS CLK register */ -uint32_t lpss_clk_read(uintptr_t base); - #endif /* SOC_INTEL_COMMON_BLOCK_LPSS_H */ diff --git a/src/soc/intel/common/block/lpss/lpss.c b/src/soc/intel/common/block/lpss/lpss.c index 1168871..6b6d17b 100644 --- a/src/soc/intel/common/block/lpss/lpss.c +++ b/src/soc/intel/common/block/lpss/lpss.c @@ -69,12 +69,3 @@ write32(addr, clk_sel); } - -uint32_t lpss_clk_read(uintptr_t base) -{ - uint8_t *addr = (void *)base; - - addr += LPSS_CLOCK_CTL_REG; - - return read32(addr); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/33094 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7def72e820ee1a4fa47c34b26dab9e0886ba74e6 Gerrit-Change-Number: 33094 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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