coreboot-gerrit June 2019

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Change in ...coreboot[master]: cpu/intel/haswell: Select TSC_MONOTONIC_TIMER
by Arthur Heymans (Code Review) 04 Jun '19

04 Jun '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33178 Change subject: cpu/intel/haswell: Select TSC_MONOTONIC_TIMER ...................................................................... cpu/intel/haswell: Select TSC_MONOTONIC_TIMER Also removes superfluous Kconfig options from some mainboard Kconfig's. Change-Id: I9c5f90fa28452bd2bdf39691e75a30843b01df9b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/haswell/Kconfig M src/mainboard/asrock/h81m-hds/Kconfig M src/mainboard/supermicro/x10slm-f/Kconfig 3 files changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/33178/1 diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index 5936953..b3a596e 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -16,6 +16,7 @@ select SSE2 select UDELAY_TSC select TSC_CONSTANT_RATE + select TSC_MONOTONIC_TIMER select SMM_TSEG select SUPPORT_CPU_UCODE_IN_CBFS #select AP_IN_SIPI_WAIT diff --git a/src/mainboard/asrock/h81m-hds/Kconfig b/src/mainboard/asrock/h81m-hds/Kconfig index 928a010..6974cda 100644 --- a/src/mainboard/asrock/h81m-hds/Kconfig +++ b/src/mainboard/asrock/h81m-hds/Kconfig @@ -34,7 +34,6 @@ select SOUTHBRIDGE_INTEL_LYNXPOINT select SUPERIO_NUVOTON_NCT6776 select SUPERIO_NUVOTON_NCT6776_COM_A - select TSC_MONOTONIC_TIMER config CBFS_SIZE hex diff --git a/src/mainboard/supermicro/x10slm-f/Kconfig b/src/mainboard/supermicro/x10slm-f/Kconfig index 430bed3..3945c09 100644 --- a/src/mainboard/supermicro/x10slm-f/Kconfig +++ b/src/mainboard/supermicro/x10slm-f/Kconfig @@ -30,7 +30,6 @@ select SOUTHBRIDGE_INTEL_LYNXPOINT select SUPERIO_NUVOTON_NCT6776 select SUPERIO_NUVOTON_NCT6776_COM_A - select TSC_MONOTONIC_TIMER config CBFS_SIZE hex -- To view, visit https://review.coreboot.org/c/coreboot/+/33178 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c5f90fa28452bd2bdf39691e75a30843b01df9b Gerrit-Change-Number: 33178 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/cannonlake: Dump ME status info before notify EndOfFirmware
by Bora Guvendik (Code Review) 04 Jun '19

04 Jun '19

Bora Guvendik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32991 Change subject: soc/intel/cannonlake: Dump ME status info before notify EndOfFirmware ...................................................................... soc/intel/cannonlake: Dump ME status info before notify EndOfFirmware Dumping ME status displays wrong information if we disable Heci1 because it is called after fsp notifies EndOfFirmware and disables Heci1. This patch moves the ME status dump before fsp notify EndOfFirmware. TEST=Boot to OS, check ME dump information Change-Id: Ifd8b18a41c502c4ecfb84698a7669028394589fd Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> --- M src/soc/intel/cannonlake/finalize.c M src/soc/intel/cannonlake/include/soc/me.h M src/soc/intel/cannonlake/me.c 3 files changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/32991/1 diff --git a/src/soc/intel/cannonlake/finalize.c b/src/soc/intel/cannonlake/finalize.c index eb4c5c2..4dfd15b 100644 --- a/src/soc/intel/cannonlake/finalize.c +++ b/src/soc/intel/cannonlake/finalize.c @@ -26,7 +26,6 @@ #include <intelblocks/tco.h> #include <reg_script.h> #include <spi-generic.h> -#include <soc/me.h> #include <soc/p2sb.h> #include <soc/pci_devs.h> #include <soc/pcr_ids.h> @@ -95,8 +94,6 @@ { printk(BIOS_DEBUG, "Finalizing chipset.\n"); - dump_me_status(); - pch_finalize(); printk(BIOS_DEBUG, "Finalizing SMM.\n"); diff --git a/src/soc/intel/cannonlake/include/soc/me.h b/src/soc/intel/cannonlake/include/soc/me.h index 1d782c1..9084209 100644 --- a/src/soc/intel/cannonlake/include/soc/me.h +++ b/src/soc/intel/cannonlake/include/soc/me.h @@ -16,6 +16,6 @@ #ifndef _CANNONLAKE_ME_H_ #define _CANNONLAKE_ME_H_ -void dump_me_status(void); +void dump_me_status(void* unused); #endif /* _CANNONLAKE_ME_H_ */ diff --git a/src/soc/intel/cannonlake/me.c b/src/soc/intel/cannonlake/me.c index 3fedc63..55afbe3 100644 --- a/src/soc/intel/cannonlake/me.c +++ b/src/soc/intel/cannonlake/me.c @@ -235,7 +235,7 @@ } BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_EXIT, print_me_version, NULL); -void dump_me_status(void) +void dump_me_status(void* unused) { union hfsts1 hfsts1; union hfsts2 hfsts2; @@ -297,3 +297,6 @@ printk(BIOS_DEBUG, "ME: TXT Support : %s\n", hfsts6.fields.txt_support ? "YES" : "NO"); } + +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_ENTRY, dump_me_status, NULL); +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME_CHECK, BS_ON_EXIT, dump_me_status, NULL); -- To view, visit https://review.coreboot.org/c/coreboot/+/32991 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd8b18a41c502c4ecfb84698a7669028394589fd Gerrit-Change-Number: 32991 Gerrit-PatchSet: 1 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: libpayload: Reset PS/2 keyboard
by Paul Menzel (Code Review) 04 Jun '19

04 Jun '19

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32951 Change subject: libpayload: Reset PS/2 keyboard ...................................................................... libpayload: Reset PS/2 keyboard Loading a libpayload based payload like coreinfo or FILO from SeaBIOS pressing keys does not give the expected results. For example, pressing F1 gives the character 24 translated to scan code 6a. ESC for example 43 (111). The problem is not reproducible using the payload directly, that means without SeaBIOS. The problem seems to be, that SeaBIOS already initializes the PS/2 controller and AT keyboard. Comparing it with coreboot’s PS/2 keyboard code, the keyboard needs to be reset. That seems to fix the issue, when the keyboard was initialized before. TEST=Build coreboot for QEMU Q35 with SeaBIOS, and coreinfo as secondary payload. Run qemu-system-i386 -M q35 -L /dev/shm -bios build/coreboot.rom -serial stdio press 3 to select the coreinfo payload, and verify that the keys F1 and F2 are working. Change-Id: I2732292ac316d4bc0029ecb5c95fa7d1e7d68947 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M payloads/libpayload/drivers/i8042/i8042.h M payloads/libpayload/drivers/i8042/keyboard.c 2 files changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/32951/1 diff --git a/payloads/libpayload/drivers/i8042/i8042.h b/payloads/libpayload/drivers/i8042/i8042.h index 643167e..e864ac9 100644 --- a/payloads/libpayload/drivers/i8042/i8042.h +++ b/payloads/libpayload/drivers/i8042/i8042.h @@ -63,6 +63,7 @@ #define I8042_KBCMD_EN 0xf4 #define I8042_KBCMD_DEFAULT_DIS 0xf5 #define I8042_KBCMD_SET_DEFAULT 0xf6 +#define I8042_KBCMD_ACK 0xfa #define I8042_KBCMD_RESEND 0xfe #define I8042_KBCMD_RESET 0xff diff --git a/payloads/libpayload/drivers/i8042/keyboard.c b/payloads/libpayload/drivers/i8042/keyboard.c index cded638..fea9e71 100644 --- a/payloads/libpayload/drivers/i8042/keyboard.c +++ b/payloads/libpayload/drivers/i8042/keyboard.c @@ -317,6 +317,13 @@ /* Enable first PS/2 port */ i8042_cmd(I8042_CMD_EN_KB); + /* Reset keyboard and self test (keyboard side) */ + ret = keyboard_cmd(I8042_KBCMD_RESET); + if (ret != I8042_KBCMD_ACK) { + printf("ERROR: Keyboard reset failed ACK: 0x%x\n", ret); + return; + } + /* Set scancode set 1 */ ret = keyboard_cmd(I8042_KBCMD_SET_SCANCODE); if (!ret && !CONFIG(LP_PC_KEYBOARD_IGNORE_INIT_FAILURE)) -- To view, visit https://review.coreboot.org/c/coreboot/+/32951 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2732292ac316d4bc0029ecb5c95fa7d1e7d68947 Gerrit-Change-Number: 32951 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/driver/vpd: Check decoded content length before invoking callback
by Hung-Te Lin (Code Review) 04 Jun '19

04 Jun '19

Hung-Te Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33016 Change subject: src/driver/vpd: Check decoded content length before invoking callback ...................................................................... src/driver/vpd: Check decoded content length before invoking callback When decoding, the content (key or value) part should be also checked before we jump into callback because the callback function has no idea if the contents are all valid. BUG=chromium:967209 TEST=make; boots on at least kukui boards. Change-Id: I3928e9c43cb87caf93fb44ee10434ce80f0a188a Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- M src/drivers/vpd/lib_vpd.c 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/33016/1 diff --git a/src/drivers/vpd/lib_vpd.c b/src/drivers/vpd/lib_vpd.c index 0744a71..f235a82 100644 --- a/src/drivers/vpd/lib_vpd.c +++ b/src/drivers/vpd/lib_vpd.c @@ -79,8 +79,8 @@ if (VPD_OK != decodeLen(max_len - *consumed, &input_buf[*consumed], &key_len, &decoded_len) || - *consumed + decoded_len >= max_len) { - return VPD_FAIL; + *consumed + decoded_len + key_len >= max_len) { + return VPD_FAIL; } *consumed += decoded_len; @@ -91,8 +91,8 @@ if (VPD_OK != decodeLen(max_len - *consumed, &input_buf[*consumed], &value_len, &decoded_len) || - *consumed + decoded_len > max_len) { - return VPD_FAIL; + *consumed + decoded_len + value_len > max_len) { + return VPD_FAIL; } *consumed += decoded_len; value = &input_buf[*consumed]; -- To view, visit https://review.coreboot.org/c/coreboot/+/33016 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3928e9c43cb87caf93fb44ee10434ce80f0a188a Gerrit-Change-Number: 33016 Gerrit-PatchSet: 1 Gerrit-Owner: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/cannonlake: Do not read SPD again if index hasn't changed
by Furquan Shaikh (Code Review) 04 Jun '19

04 Jun '19

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33137 Change subject: soc/intel/cannonlake: Do not read SPD again if index hasn't changed ...................................................................... soc/intel/cannonlake: Do not read SPD again if index hasn't changed With the recent refactoring of memory configuration in CB:32513 ("soc/intel/cannonlake: Support different SPD read type for each slot"), meminit_cbfs_spd_index ends up reading SPD from CBFS for each slot. However, for mainboards that use the same SPD index for each slot this is unneccessary. This change adds a check to see if spd_data_ptr is not NULL and current spd index is the same as the last call to decide if SPD read from CBFS should be skipped. TEST=Verified that SPD gets read only once on hatch. Change-Id: I91963b55cea534c92207b2cd9f0caa96df8f222b Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/intel/cannonlake/cnl_memcfg_init.c 1 file changed, 21 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/33137/1 diff --git a/src/soc/intel/cannonlake/cnl_memcfg_init.c b/src/soc/intel/cannonlake/cnl_memcfg_init.c index 4ebd997..d3e5e83 100644 --- a/src/soc/intel/cannonlake/cnl_memcfg_init.c +++ b/src/soc/intel/cannonlake/cnl_memcfg_init.c @@ -91,18 +91,29 @@ static void meminit_cbfs_spd_index(FSP_M_CONFIG *mem_cfg, int spd_index, uint8_t mem_slot) { - size_t spd_data_len; - uintptr_t spd_data_ptr; - struct region_device spd_rdev; + static size_t spd_data_len; + static uintptr_t spd_data_ptr; + static int last_spd_index; assert(mem_slot < NUM_DIMM_SLOT); - printk(BIOS_DEBUG, "SPD INDEX = %d\n", spd_index); - if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0) - die("spd.bin not found or incorrect index\n"); - spd_data_len = region_device_sz(&spd_rdev); - /* Memory leak is ok since we have memory mapped boot media */ - assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); - spd_data_ptr = (uintptr_t)rdev_mmap_full(&spd_rdev); + + if ((spd_data_ptr == 0) || (last_spd_index != spd_index)) { + struct region_device spd_rdev; + + printk(BIOS_DEBUG, "SPD INDEX = %d\n", spd_index); + + if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0) + die("spd.bin not found or incorrect index\n"); + + spd_data_len = region_device_sz(&spd_rdev); + + /* Memory leak is ok since we have memory mapped boot media */ + assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); + + spd_data_ptr = (uintptr_t)rdev_mmap_full(&spd_rdev); + last_spd_index = spd_index; + } + meminit_spd_data(mem_cfg, mem_slot, spd_data_len, spd_data_ptr); } -- To view, visit https://review.coreboot.org/c/coreboot/+/33137 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I91963b55cea534c92207b2cd9f0caa96df8f222b Gerrit-Change-Number: 33137 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: arch/riscv/Kconfig: Make correct default value for CONFIG_ARCH_RISCV_M
by Subrata Banik (Code Review) 04 Jun '19

04 Jun '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33144 Change subject: arch/riscv/Kconfig: Make correct default value for CONFIG_ARCH_RISCV_M ...................................................................... arch/riscv/Kconfig: Make correct default value for CONFIG_ARCH_RISCV_M Change-Id: Ib9329904060cab48d527de1b1ccdab5b6fe71b99 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/arch/riscv/Kconfig 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/33144/1 diff --git a/src/arch/riscv/Kconfig b/src/arch/riscv/Kconfig index 9d325af..25a3980 100644 --- a/src/arch/riscv/Kconfig +++ b/src/arch/riscv/Kconfig @@ -24,8 +24,8 @@ # one implementation that will not have it due # to security concerns. bool - default n if ARCH_RISCV_M_DISABLED - default y + default y if ARCH_RISCV && !ARCH_RISCV_M_DISABLED + default n config ARCH_RISCV_S # S (supervisor) mode is for kernels. It is optional. -- To view, visit https://review.coreboot.org/c/coreboot/+/33144 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9329904060cab48d527de1b1ccdab5b6fe71b99 Gerrit-Change-Number: 33144 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: TEST:superiotool: add SCH5544 support
by Arthur Heymans (Code Review) 04 Jun '19

04 Jun '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33179 Change subject: TEST:superiotool: add SCH5544 support ...................................................................... TEST:superiotool: add SCH5544 support Change-Id: I093e9b74c1c2d31ef28fb6aa8fcff407150bf5f5 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M util/superiotool/smsc.c 1 file changed, 27 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/33179/1 diff --git a/util/superiotool/smsc.c b/util/superiotool/smsc.c index 2fe940c..f0fb477 100644 --- a/util/superiotool/smsc.c +++ b/util/superiotool/smsc.c @@ -890,6 +890,33 @@ {0x30,0x60,0x61,0x70,0xf0,0xf1,EOT}, {0x00,0x00,0x00,0x00,0x00,RSVD,EOT}}, {EOT}}}, + {0xc4, "SCH5544", { /* From sensors-detect, dump from datasheet */ + {NOLDN, NULL, + {0x02,0x03,0x21,0x22,0x23,0x24,0x26,0x27, + 0x28,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, + {0x00,RSVD,MISC,0x00,0x00,0x44,MISC,0x00, + RSVD,0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, + {0x0, "Floppy", + {0x30,0x60,0x61,0x70,0x74,0xf0,0xf1,0xf2,0xf4, + 0xf5,EOT}, + {0x00,0x03,0xf0,0x06,0x02,0x0e,0x00,0xff,0x00, + 0x00,EOT}}, + {0x3, "Parallel port", + {0x30,0x60,0x61,0x70,0x74,0xf0,0xf1,EOT}, + {0x00,0x00,0x00,0x00,0x04,0x3c,0x00,EOT}}, + {0x4, "COM1", + {0x30,0x60,0x61,0x70,0xf0,EOT}, + {0x00,0x00,0x00,0x00,0x00,EOT}}, + {0x5, "COM2", + {0x30,0x60,0x61,0x70,0xf0,0xf1,0xf2,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x02,0x03,EOT}}, + {0x7, "Keyboard", + {0x30,0x70,0x72,0xf0,EOT}, + {0x00,0x00,0x00,0x00,EOT}}, + {0xa, "Runtime registers", + {0x30,0x60,0x61,0x70,0xf0,0xf1,EOT}, + {0x00,0x00,0x00,0x00,0x00,RSVD,EOT}}, + {EOT}}}, {0x89, "SCH5027", { /* From sensors-detect (no public datasheet) */ {EOT}}}, {0x8c, "SCH5317", { /* From sensors-detect */ -- To view, visit https://review.coreboot.org/c/coreboot/+/33179 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I093e9b74c1c2d31ef28fb6aa8fcff407150bf5f5 Gerrit-Change-Number: 33179 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mainboard/intel/saddlebrook: Remove unused functions
by Arthur Heymans (Code Review) 03 Jun '19

03 Jun '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32985 Change subject: mainboard/intel/saddlebrook: Remove unused functions ...................................................................... mainboard/intel/saddlebrook: Remove unused functions Setting up the SIO serial console is done in the bootblock. Change-Id: Ideaf8f3dc0ee067e96d3fb5046071551c6d45329 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/intel/saddlebrook/romstage.c 1 file changed, 0 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/32985/1 diff --git a/src/mainboard/intel/saddlebrook/romstage.c b/src/mainboard/intel/saddlebrook/romstage.c index 82b85fd..45f39d4 100644 --- a/src/mainboard/intel/saddlebrook/romstage.c +++ b/src/mainboard/intel/saddlebrook/romstage.c @@ -23,15 +23,7 @@ #include <soc/romstage.h> #include "spd/spd.h" #include <spd_bin.h> -#include <superio/nuvoton/common/nuvoton.h> -#include <superio/nuvoton/nct6776/nct6776.h> -#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) - -void car_mainboard_pre_console_init(void) -{ - nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); -} void mainboard_memory_init_params( struct romstage_params *params, -- To view, visit https://review.coreboot.org/c/coreboot/+/32985 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ideaf8f3dc0ee067e96d3fb5046071551c6d45329 Gerrit-Change-Number: 32985 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/skylake: Use PCI func0 if enabled in device tree
by Furquan Shaikh (Code Review) 03 Jun '19

03 Jun '19

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32846 ) Change subject: soc/intel/skylake: Use PCI func0 if enabled in device tree ...................................................................... Patch Set 1: Code-Review+2 (1 comment) https://review.coreboot.org/#/c/32846/1/src/soc/intel/skylake/chip_fsp20.c File src/soc/intel/skylake/chip_fsp20.c: https://review.coreboot.org/#/c/32846/1/src/soc/intel/skylake/chip_fsp20.c@… PS1, Line 113: enabled "... enabled in device tree, ..." to make it clear that is different than the disabled mentioned in L109 above? -- To view, visit https://review.coreboot.org/c/coreboot/+/32846 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c44ee5493eff1f9e04aa891030fde2a6f0c636f Gerrit-Change-Number: 32846 Gerrit-PatchSet: 1 Gerrit-Owner: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: caveh jalali <caveh(a)chromium.org> Gerrit-Comment-Date: Mon, 03 Jun 2019 18:38:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: src/soc/intel: Fix Coverity scan report
by John Zhao (Code Review) 03 Jun '19

03 Jun '19

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33152 Change subject: src/soc/intel: Fix Coverity scan report ...................................................................... src/soc/intel: Fix Coverity scan report Coverity detects pointer mem_info as NULL_RETURNS. Add sanity check for mem_info to prevent null pointer dereference. BUG=CID 1401394 TEST=Built and boot up to kernel. Change-Id: I9d78ab38b8b2dd3734e0143acfd88d9093f16ce6 Signed-off-by: John Zhao <john.zhao(a)intel.com> --- M src/soc/intel/broadwell/romstage/raminit.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/33152/1 diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c index fc8b7c6..ffa1feb 100644 --- a/src/soc/intel/broadwell/romstage/raminit.c +++ b/src/soc/intel/broadwell/romstage/raminit.c @@ -122,6 +122,10 @@ printk(BIOS_DEBUG, "create cbmem for dimm information\n"); mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(struct memory_info)); + + if (!mem_info) + return; + memset(mem_info, 0, sizeof(*mem_info)); /* Translate pei_memory_info struct data into memory_info struct */ mem_info->dimm_cnt = pei_data->meminfo.dimm_cnt; -- To view, visit https://review.coreboot.org/c/coreboot/+/33152 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d78ab38b8b2dd3734e0143acfd88d9093f16ce6 Gerrit-Change-Number: 33152 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

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coreboot-gerrit June 2019