Christoph Pomaska has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/20238 )
Change subject: [WIP]: add superio driver for sch5545
......................................................................
Patch Set 2:
The header information seems outdated.
It doesnt build when configured into the Optiplex 790 because of unknown type names.
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Felix Held has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32544 )
Change subject: drivers/fsp20: Fix spelling in help text
......................................................................
drivers/fsp20: Fix spelling in help text
Change-Id: Iab8d20a385bde31b29fa7766a87753fcc2d759b8
Signed-off-by: Felix Singer <felix.singer(a)9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32544
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de>
---
M src/drivers/intel/fsp2_0/Kconfig
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Felix Held: Looks good to me, approved
diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig
index 7fe81e5..3fb39d5 100644
--- a/src/drivers/intel/fsp2_0/Kconfig
+++ b/src/drivers/intel/fsp2_0/Kconfig
@@ -27,7 +27,7 @@
select FSP_PEIM_TO_PEIM_INTERFACE
help
Include FSP 2.1 wrappers and functionality.
- Features added into FSP 2.1 specification that impacts corerboot are:
+ Features added into FSP 2.1 specification that impacts coreboot are:
1. Remove FSP stack switch and use the same stack with boot firmware
2. FSP should support external PPI interface pulled in via FSP_PEIM_TO_PEIM_INTERFACE
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Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32544 )
Change subject: drivers/fsp20: Fix spelling in help text
......................................................................
Patch Set 1: Code-Review+2
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30414 )
Change subject: mainboard/facebook/fbg1701: Do initial mainboard commit
......................................................................
Patch Set 26:
(2 comments)
https://review.coreboot.org/#/c/30414/26/src/mainboard/facebook/fbg1701/irq…
File src/mainboard/facebook/fbg1701/irqroute.h:
https://review.coreboot.org/#/c/30414/26/src/mainboard/facebook/fbg1701/irq…
PS26, Line 40: #define PCI_DEV_PIRQ_ROUTES \
Macros with complex values should be enclosed in parentheses
https://review.coreboot.org/#/c/30414/26/src/mainboard/facebook/fbg1701/irq…
PS26, Line 62: #define PIRQ_PIC_ROUTES \
Macros with complex values should be enclosed in parentheses
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Hello Alex Thiessen, Patrick Rudolph, Patrick Rudolph, David Hendricks, build bot (Jenkins), Nico Huber, Michał Żygowski, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/30414
to look at the new patch set (#26).
Change subject: mainboard/facebook/fbg1701: Do initial mainboard commit
......................................................................
mainboard/facebook/fbg1701: Do initial mainboard commit
Initial support for Facebook FBG-1701 system.
coreboot implementation based on Intel Strago mainboard.
Configure 'Onboard memory manufacturer' which must match HW.
BUG=N/A
TEST=booting SeaBIOS and Linux 4.15+ kernel on Facebook FBG-1701
Change-Id: I28ac78a630ee705b1e546031f024bfe7f952ab39
Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com>
---
A Documentation/mainboard/facebook/fbg1701.md
M Documentation/mainboard/index.md
A src/mainboard/facebook/fbg1701/Kconfig
A src/mainboard/facebook/fbg1701/Kconfig.name
A src/mainboard/facebook/fbg1701/Makefile.inc
A src/mainboard/facebook/fbg1701/acpi/ec.asl
A src/mainboard/facebook/fbg1701/acpi/mainboard.asl
A src/mainboard/facebook/fbg1701/acpi/sleepstates.asl
A src/mainboard/facebook/fbg1701/acpi/superio.asl
A src/mainboard/facebook/fbg1701/acpi_tables.c
A src/mainboard/facebook/fbg1701/board_info.txt
A src/mainboard/facebook/fbg1701/cmos.layout
A src/mainboard/facebook/fbg1701/com_init.c
A src/mainboard/facebook/fbg1701/devicetree.cb
A src/mainboard/facebook/fbg1701/dsdt.asl
A src/mainboard/facebook/fbg1701/fadt.c
A src/mainboard/facebook/fbg1701/gpio.c
A src/mainboard/facebook/fbg1701/hda_verb.c
A src/mainboard/facebook/fbg1701/irqroute.c
A src/mainboard/facebook/fbg1701/irqroute.h
A src/mainboard/facebook/fbg1701/logo.c
A src/mainboard/facebook/fbg1701/mainboard.c
A src/mainboard/facebook/fbg1701/mainboard.h
A src/mainboard/facebook/fbg1701/onboard.h
A src/mainboard/facebook/fbg1701/ramstage.c
A src/mainboard/facebook/fbg1701/romstage.c
A src/mainboard/facebook/fbg1701/spd/MICRON_MT41K512M16HA-125A.spd.hex
A src/mainboard/facebook/fbg1701/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex
A src/mainboard/facebook/fbg1701/w25q64.c
29 files changed, 2,038 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/30414/26
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Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30414 )
Change subject: mainboard/facebook/fbg1701: Do initial mainboard commit
......................................................................
Patch Set 25:
(1 comment)
https://review.coreboot.org/#/c/30414/25/src/mainboard/facebook/fbg1701/rom…
File src/mainboard/facebook/fbg1701/romstage.c:
https://review.coreboot.org/#/c/30414/25/src/mainboard/facebook/fbg1701/rom…
PS25, Line 28: /* First call into mainboard. */
: void mainboard_romstage_entry(struct romstage_params *params)
: {
: romstage_common(params);
: }
:
> This seems to be leftover from earlier baytrail --> braswell porting, and is no longer needed. […]
After latest merge of car stage code this needs to be removed.
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29284 )
Change subject: soc/intel/braswell/chip.c: Configure LPSS devices in correct mode
......................................................................
Patch Set 11:
(1 comment)
https://review.coreboot.org/#/c/29284/11//COMMIT_MSG
Commit Message:
https://review.coreboot.org/#/c/29284/11//COMMIT_MSG@27
PS11, Line 27: devices/connections are available.
> Linux is reporting 'i2c /dev entries driver' but I could not check if the controllers are working. […]
As discussed, there are probably better ways to handle this.
Maybe remove the PcdEnable* settings from `chip.h` and use the
`pci device ... on/off` setting instead. Then, nobody could
accidentally put individual devices into ACPI mode.
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Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33112
Change subject: Kconfig: Make ramstage kconfigs dependent on CONFIG_ARCH_RAMSTAGE_X86_32/64
......................................................................
Kconfig: Make ramstage kconfigs dependent on CONFIG_ARCH_RAMSTAGE_X86_32/64
This patch ensures required ramstage configs like COMPRESS_RAMSTAGE
and RELOCATABLE_RAMSTAGE are not enable if CONFIG_ARCH_RAMSTAGE_X86_32/64
is not selected.
Change-Id: I5d0c31152ffa8faf62b10a6bda12c9ad2e786d94
Signed-off-by: Subrata Banik <subrata.banik(a)intel.com>
---
M src/Kconfig
1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/33112/1
diff --git a/src/Kconfig b/src/Kconfig
index d30aa99..ac7aad2 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -129,6 +129,7 @@
config COMPRESS_RAMSTAGE
bool "Compress ramstage with LZMA"
+ depends on ARCH_RAMSTAGE_X86_32 || ARCH_RAMSTAGE_X86_64
# Default value set at the end of the file
help
Compress ramstage to save memory in the flash image. Note
@@ -234,6 +235,7 @@
config RELOCATABLE_RAMSTAGE
bool
+ depends on ARCH_RAMSTAGE_X86_32 || ARCH_RAMSTAGE_X86_64
default !NO_RELOCATABLE_RAMSTAGE
select RELOCATABLE_MODULES
help
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