coreboot-gerrit September 2023

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[main]: soc/intel/cse: Implement APIs to access PSR backup status in CMOS
by Rizwan Qureshi (Code Review) 29 Sep '23

29 Sep '23

Attention is currently required from: Anil Kumar K, Jérémy Compostella, Krishna P Bhat D, Subrata Banik, sridhar siricilla. Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77069?usp=email ) Change subject: soc/intel/cse: Implement APIs to access PSR backup status in CMOS ...................................................................... Patch Set 10: (1 comment) File src/soc/intel/common/block/include/intelblocks/cse.h: https://review.coreboot.org/c/coreboot/+/77069/comment/a1586e79_e26a9168 : PS10, Line 172: PSR_BACKUP_DONE = 0, : PSR_BACKUP_PENDING = 1, > the very first time when there is no data initialized in cmos this function will not be true because […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/77069?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I270894e3e08dd50ca88e5402b59c211d7e693d14 Gerrit-Change-Number: 77069 Gerrit-PatchSet: 10 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-CC: sridhar siricilla <siricillasridhar(a)gmail.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: sridhar siricilla <siricillasridhar(a)gmail.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Comment-Date: Fri, 29 Sep 2023 14:37:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Anil Kumar K <anil.kumar.k(a)intel.com> Comment-In-Reply-To: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel/cse: Implement APIs to access PSR backup status in CMOS
by Anil Kumar K (Code Review) 29 Sep '23

29 Sep '23

Attention is currently required from: Jérémy Compostella, Krishna P Bhat D, Rizwan Qureshi, Subrata Banik, sridhar siricilla. Anil Kumar K has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77069?usp=email ) Change subject: soc/intel/cse: Implement APIs to access PSR backup status in CMOS ...................................................................... Patch Set 10: (1 comment) File src/soc/intel/common/block/include/intelblocks/cse.h: https://review.coreboot.org/c/coreboot/+/77069/comment/3b0d5b85_67ab80fc : PS10, Line 172: PSR_BACKUP_DONE = 0, : PSR_BACKUP_PENDING = 1, > I am wondering what is the default value of the CMOS bank after #RTCRST is toggled. […] the very first time when there is no data initialized in cmos this function will not be true because the signature will be invalid static bool is_psr_data_backed_up(void) { /* Track PSR backup status in CMOS */ return (get_psr_backup_status() == PSR_BACKUP_DONE); } get_psr_backup_status() will return -1 -- To view, visit https://review.coreboot.org/c/coreboot/+/77069?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I270894e3e08dd50ca88e5402b59c211d7e693d14 Gerrit-Change-Number: 77069 Gerrit-PatchSet: 10 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-CC: sridhar siricilla <siricillasridhar(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: sridhar siricilla <siricillasridhar(a)gmail.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Comment-Date: Fri, 29 Sep 2023 14:33:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel/cse: Implement APIs to access PSR backup status in CMOS
by Rizwan Qureshi (Code Review) 29 Sep '23

29 Sep '23

Attention is currently required from: Anil Kumar K, Jérémy Compostella, Krishna P Bhat D, Subrata Banik, sridhar siricilla. Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77069?usp=email ) Change subject: soc/intel/cse: Implement APIs to access PSR backup status in CMOS ...................................................................... Patch Set 10: (1 comment) File src/soc/intel/common/block/include/intelblocks/cse.h: https://review.coreboot.org/c/coreboot/+/77069/comment/ac027212_04a672d1 : PS10, Line 172: PSR_BACKUP_DONE = 0, : PSR_BACKUP_PENDING = 1, I am wondering what is the default value of the CMOS bank after #RTCRST is toggled. If it is 0 then we need to invert this state values. Because we need the state to be pending by default. -- To view, visit https://review.coreboot.org/c/coreboot/+/77069?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I270894e3e08dd50ca88e5402b59c211d7e693d14 Gerrit-Change-Number: 77069 Gerrit-PatchSet: 10 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-CC: sridhar siricilla <siricillasridhar(a)gmail.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: sridhar siricilla <siricillasridhar(a)gmail.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Comment-Date: Fri, 29 Sep 2023 13:23:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel/cse: Implement APIs to access PSR backup status in CMOS
by Rizwan Qureshi (Code Review) 29 Sep '23

29 Sep '23

Attention is currently required from: Anil Kumar K, Jérémy Compostella, Krishna P Bhat D, Subrata Banik, sridhar siricilla. Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77069?usp=email ) Change subject: soc/intel/cse: Implement APIs to access PSR backup status in CMOS ...................................................................... Patch Set 10: (1 comment) File src/soc/intel/common/block/include/intelblocks/cse.h: https://review.coreboot.org/c/coreboot/+/77069/comment/5fa4e908_d92601fc : PS9, Line 171: #define PSR_BACKUP_DONE 0 : #define PSR_BACKUP_PENDING 1 > care to use an enum ? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/77069?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I270894e3e08dd50ca88e5402b59c211d7e693d14 Gerrit-Change-Number: 77069 Gerrit-PatchSet: 10 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-CC: sridhar siricilla <siricillasridhar(a)gmail.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: sridhar siricilla <siricillasridhar(a)gmail.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Comment-Date: Fri, 29 Sep 2023 13:21:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/nissa/var/yavilla: Add elan and G2 i2c touchscreen
by Felix Held (Code Review) 29 Sep '23

29 Sep '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/77996?usp=email ) Change subject: mb/google/nissa/var/yavilla: Add elan and G2 i2c touchscreen ...................................................................... mb/google/nissa/var/yavilla: Add elan and G2 i2c touchscreen Implement support for elan i2c touchscreen and use fw_config to pick between i2c or HID-over-i2c touchscreen. Support G2 TS have different slave address by fw_config BUG=b:295272539 BRANCH=firmware-nissa-15217.B TEST=build and verified touchscreen work Change-Id: I5e3f85106606d84e1cfa204e62b7b2662db6546b Signed-off-by: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77996 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Derek Huang <derekhuang(a)google.com> --- M src/mainboard/google/brya/Kconfig.name M src/mainboard/google/brya/variants/yavilla/overridetree.cb 2 files changed, 45 insertions(+), 1 deletion(-) Approvals: Derek Huang: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 95acffd..03a8519 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -427,6 +427,7 @@ select DRIVERS_INTEL_MIPI_CAMERA select HAVE_WWAN_POWER_SEQUENCE select INTEL_GMA_HAVE_VBT + select EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG config BOARD_GOOGLE_ZYDRON bool "-> Zydron" diff --git a/src/mainboard/google/brya/variants/yavilla/overridetree.cb b/src/mainboard/google/brya/variants/yavilla/overridetree.cb index 8e8cf76..d31a8f9 100644 --- a/src/mainboard/google/brya/variants/yavilla/overridetree.cb +++ b/src/mainboard/google/brya/variants/yavilla/overridetree.cb @@ -40,6 +40,11 @@ option INTEL_YAVIJO_WIFI 5 option UNUSED 15 end + field TOUCH_PANEL 40 41 + option TOUCH_ELAN_I2C 0 + option TOUCH_ELAN_HID_I2C 1 + option TOUCH_G2_HID_I2c 2 + end end chip soc/intel/alderlake @@ -257,7 +262,9 @@ register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" register "enable_delay_ms" = "1" register "has_power_resource" = "1" - device i2c 10 on end + device i2c 10 on + probe TOUCH_PANEL TOUCH_ELAN_I2C + end end chip drivers/i2c/hid register "generic.hid" = ""ELAN2513"" @@ -274,6 +281,25 @@ register "generic.enable_delay_ms" = "1" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x01" + device i2c 10 on + probe TOUCH_PANEL TOUCH_ELAN_HID_I2C + end + end + chip drivers/i2c/hid + register "generic.hid" = ""ELAN2513"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "generic.detect" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + register "generic.reset_delay_ms" = "20" + register "generic.reset_off_delay_ms" = "2" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" + register "generic.stop_delay_ms" = "280" + register "generic.stop_off_delay_ms" = "2" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" device i2c 15 on end end chip drivers/i2c/hid @@ -283,6 +309,23 @@ register "generic.detect" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" register "generic.reset_delay_ms" = "50" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" + register "generic.stop_delay_ms" = "100" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 10 on + probe TOUCH_PANEL TOUCH_G2_HID_I2c + end + end + chip drivers/i2c/hid + register "generic.hid" = ""GTCH7503"" + register "generic.desc" = ""G2TOUCH Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "generic.detect" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + register "generic.reset_delay_ms" = "50" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" register "generic.enable_delay_ms" = "1" register "generic.has_power_resource" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/77996?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5e3f85106606d84e1cfa204e62b7b2662db6546b Gerrit-Change-Number: 77996 Gerrit-PatchSet: 7 Gerrit-Owner: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Chen-Tsung Hsieh <chentsung(a)chromium.org> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-CC: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: soc/intel/cse: Check PSR bit before issuing PSR backup command
by Rizwan Qureshi (Code Review) 29 Sep '23

29 Sep '23

Attention is currently required from: Anil Kumar K, Krishna P Bhat D, Subrata Banik. Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74874?usp=email ) Change subject: soc/intel/cse: Check PSR bit before issuing PSR backup command ...................................................................... Patch Set 9: (1 comment) Patchset: PS8: > can we pull this check early in the patch train ? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/74874?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6e92341a9dc799146eb8f1a70b3a4a16fd1aa0ae Gerrit-Change-Number: 74874 Gerrit-PatchSet: 9 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Comment-Date: Fri, 29 Sep 2023 12:43:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel/cse: Check PSR bit before issuing PSR backup command
by Rizwan Qureshi (Code Review) 29 Sep '23

29 Sep '23

Attention is currently required from: Anil Kumar K, Krishna P Bhat D, Rizwan Qureshi, Subrata Banik. Rizwan Qureshi has uploaded a new patch set (#9) to the change originally created by Anil Kumar K. ( https://review.coreboot.org/c/coreboot/+/74874?usp=email ) The following approvals got outdated and were removed: Code-Review+2 by Subrata Banik Change subject: soc/intel/cse: Check PSR bit before issuing PSR backup command ...................................................................... soc/intel/cse: Check PSR bit before issuing PSR backup command Get PSR bit state using MKHI_FWCAPS_GET_FW_FEATURE_STATE HECI command Use this bit info to check if SKU supports PSR and consequently issue PSR_HECI_FW_DOWNGRADE_BACKUP command for PSR data backup during downgrade. BUG=b:273207144 TEST=build CB image and boot on google/rex board. Check for "PSR is supported in this SKU" message in coreboot logs to confirm that PSR bit is set in SKU Signed-off-by: Anil Kumar <anil.kumar.k(a)intel.com> Change-Id: I6e92341a9dc799146eb8f1a70b3a4a16fd1aa0ae --- M src/soc/intel/common/block/cse/cse_lite.c M src/soc/intel/common/block/include/intelblocks/cse.h 2 files changed, 33 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/74874/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/74874?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6e92341a9dc799146eb8f1a70b3a4a16fd1aa0ae Gerrit-Change-Number: 74874 Gerrit-PatchSet: 9 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: soc/intel/cse: Implement APIs to access PSR backup status in CMOS
by Rizwan Qureshi (Code Review) 29 Sep '23

29 Sep '23

Attention is currently required from: Anil Kumar K, Jérémy Compostella, Krishna P Bhat D, Rizwan Qureshi, Subrata Banik, sridhar siricilla. Rizwan Qureshi has uploaded a new patch set (#10) to the change originally created by Krishna P Bhat D. ( https://review.coreboot.org/c/coreboot/+/77069?usp=email ) The following approvals got outdated and were removed: Code-Review+1 by Subrata Banik, Verified+1 by build bot (Jenkins) Change subject: soc/intel/cse: Implement APIs to access PSR backup status in CMOS ...................................................................... soc/intel/cse: Implement APIs to access PSR backup status in CMOS PSR data is created and stored in CSE data partition. In platforms that employ CSE Lite SKU firmware, a firmware downgrade involves clearing of CSE data partition which results in PSR data being lost. The PSR data needs to be preserved across the firmware downgrade flow. CSE Lite SKU firmware supports command to backup PSR data. Since firmware downgrade and PSR data backup flows involve global resets, there is a need to track the PSR data backup status across resets. So adding a CMOS variable for the same. This patch implements API to access PSR backup status stored in CMOS. The get API allows to retrieve the PSR backup status from CMOS memory. The update API allows to update the PSR backup status in CMOS. BRANCH=None BUG=b:273207144 TEST=Able to retrieve PSR backup status across resets. Change-Id: I270894e3e08dd50ca88e5402b59c211d7e693d14 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- M src/soc/intel/common/block/cse/cse_lite_cmos.c M src/soc/intel/common/block/cse/cse_lite_cmos.h M src/soc/intel/common/block/include/intelblocks/cse.h 3 files changed, 91 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/77069/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/77069?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I270894e3e08dd50ca88e5402b59c211d7e693d14 Gerrit-Change-Number: 77069 Gerrit-PatchSet: 10 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-CC: sridhar siricilla <siricillasridhar(a)gmail.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: sridhar siricilla <siricillasridhar(a)gmail.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: soc/intel/cse: Check PSR bit before issuing PSR backup command
by Subrata Banik (Code Review) 29 Sep '23

29 Sep '23

Attention is currently required from: Anil Kumar K, Krishna P Bhat D, Rizwan Qureshi. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74874?usp=email ) Change subject: soc/intel/cse: Check PSR bit before issuing PSR backup command ...................................................................... Patch Set 8: (1 comment) Patchset: PS8: can we pull this check early in the patch train ? -- To view, visit https://review.coreboot.org/c/coreboot/+/74874?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6e92341a9dc799146eb8f1a70b3a4a16fd1aa0ae Gerrit-Change-Number: 74874 Gerrit-PatchSet: 8 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Comment-Date: Fri, 29 Sep 2023 11:35:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel/cse: Check PSR bit before issuing PSR backup command
by Subrata Banik (Code Review) 29 Sep '23

29 Sep '23

Attention is currently required from: Anil Kumar K, Krishna P Bhat D, Rizwan Qureshi. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74874?usp=email ) Change subject: soc/intel/cse: Check PSR bit before issuing PSR backup command ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74874?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6e92341a9dc799146eb8f1a70b3a4a16fd1aa0ae Gerrit-Change-Number: 74874 Gerrit-PatchSet: 8 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Comment-Date: Fri, 29 Sep 2023 11:35:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit September 2023