coreboot-gerrit December 2019

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Change in ...coreboot[master]: mb/gigabyte: add GA-P67A-UD3R
by James (Code Review) 07 Aug '23

07 Aug '23

James has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31363 Change subject: mb/gigabyte: add GA-P67A-UD3R ...................................................................... mb/gigabyte: add GA-P67A-UD3R This is a Intel P67 chipset motherboard for Sandy Bridge processors. The P67 chipset has no graphics support. This board has redundant 4MB SOIC-8 flash chips, and flashrom is usable with the vendor BIOS. This is an original P67 chipset, and is affected by a SATA 2 hardware bug. There is a variant P67A-UD3R-B3 that is unaffected. The function of PCIe ports PCIEX4 and PCIEX1_* are configured in PCHSTRP9. By default, PCIEX4 is configured for 4 lanes and PCIEX1_* are disabled. This can be switched to 1 lane for all ports. Tested and working: - Intel Core i7 2600 - 4 DIMMs (4x4GB DDR3) - Booting Linux (SeaBIOS) - Native RAM init - PCIe graphics - Onboard Ethernet - Sensors (SuperIO) - S3 sleep - S4 hibernate - SATA 3 - USB 2.0 - USB 3.0 - Onboard audio (speakers, headphones) - CMOS - EHCI debug port - Serial port Not tested: - SATA 2 - PS/2 keyboard/mouse - Digital audio Change-Id: I4fbf50376be3184bf01a3bc8aae09bce54676707 Signed-off-by: James Ye <jye836(a)gmail.com> --- A src/mainboard/gigabyte/ga-p67a-ud3r/Kconfig A src/mainboard/gigabyte/ga-p67a-ud3r/Kconfig.name A src/mainboard/gigabyte/ga-p67a-ud3r/Makefile.inc A src/mainboard/gigabyte/ga-p67a-ud3r/acpi/ec.asl A src/mainboard/gigabyte/ga-p67a-ud3r/acpi/mainboard.asl A src/mainboard/gigabyte/ga-p67a-ud3r/acpi/platform.asl A src/mainboard/gigabyte/ga-p67a-ud3r/acpi/superio.asl A src/mainboard/gigabyte/ga-p67a-ud3r/acpi_tables.c A src/mainboard/gigabyte/ga-p67a-ud3r/board_info.txt A src/mainboard/gigabyte/ga-p67a-ud3r/cmos.default A src/mainboard/gigabyte/ga-p67a-ud3r/cmos.layout A src/mainboard/gigabyte/ga-p67a-ud3r/devicetree.cb A src/mainboard/gigabyte/ga-p67a-ud3r/dsdt.asl A src/mainboard/gigabyte/ga-p67a-ud3r/gpio.c A src/mainboard/gigabyte/ga-p67a-ud3r/hda_verb.c A src/mainboard/gigabyte/ga-p67a-ud3r/romstage.c 16 files changed, 781 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/31363/1 diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/Kconfig b/src/mainboard/gigabyte/ga-p67a-ud3r/Kconfig new file mode 100644 index 0000000..c1efe12 --- /dev/null +++ b/src/mainboard/gigabyte/ga-p67a-ud3r/Kconfig @@ -0,0 +1,40 @@ +if BOARD_GIGABYTE_GA_P67A_UD3R + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_4096 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_BD82X6X + select USE_NATIVE_RAMINIT + select SUPERIO_ITE_IT8728F + +config MAINBOARD_DIR + string + default "gigabyte/ga-p67a-ud3r" + +config MAINBOARD_PART_NUMBER + string + default "GA-P67A-UD3R" + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x5001 + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x1458 + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX + int + default 2 + +endif # BOARD_GIGABYTE_GA_P67A_UD3R diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/Kconfig.name b/src/mainboard/gigabyte/ga-p67a-ud3r/Kconfig.name new file mode 100644 index 0000000..15f0655 --- /dev/null +++ b/src/mainboard/gigabyte/ga-p67a-ud3r/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_GIGABYTE_GA_P67A_UD3R + bool "GA-P67A-UD3R" diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/Makefile.inc b/src/mainboard/gigabyte/ga-p67a-ud3r/Makefile.inc new file mode 100644 index 0000000..3dae61e --- /dev/null +++ b/src/mainboard/gigabyte/ga-p67a-ud3r/Makefile.inc @@ -0,0 +1 @@ +romstage-y += gpio.c diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/acpi/ec.asl b/src/mainboard/gigabyte/ga-p67a-ud3r/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/gigabyte/ga-p67a-ud3r/acpi/ec.asl diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/acpi/mainboard.asl b/src/mainboard/gigabyte/ga-p67a-ud3r/acpi/mainboard.asl new file mode 100644 index 0000000..34de86f --- /dev/null +++ b/src/mainboard/gigabyte/ga-p67a-ud3r/acpi/mainboard.asl @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB) +{ + Device (PWRB) + { + Name (_HID, EisaId("PNP0C0C")) + } +} diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/acpi/platform.asl b/src/mainboard/gigabyte/ga-p67a-ud3r/acpi/platform.asl new file mode 100644 index 0000000..d8d3320 --- /dev/null +++ b/src/mainboard/gigabyte/ga-p67a-ud3r/acpi/platform.asl @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + Return(Package(){0,0}) +} diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/acpi/superio.asl b/src/mainboard/gigabyte/ga-p67a-ud3r/acpi/superio.asl new file mode 100644 index 0000000..2b20c77 --- /dev/null +++ b/src/mainboard/gigabyte/ga-p67a-ud3r/acpi/superio.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 James Ye <jye836(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/acpi_tables.c b/src/mainboard/gigabyte/ga-p67a-ud3r/acpi_tables.c new file mode 100644 index 0000000..a2f383b --- /dev/null +++ b/src/mainboard/gigabyte/ga-p67a-ud3r/acpi_tables.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/bd82x6x/nvs.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; +} diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/board_info.txt b/src/mainboard/gigabyte/ga-p67a-ud3r/board_info.txt new file mode 100644 index 0000000..c6f16ae --- /dev/null +++ b/src/mainboard/gigabyte/ga-p67a-ud3r/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.gigabyte.com/Motherboard/GA-P67A-UD3R-rev-10 +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2011 diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/cmos.default b/src/mainboard/gigabyte/ga-p67a-ud3r/cmos.default new file mode 100644 index 0000000..60de212 --- /dev/null +++ b/src/mainboard/gigabyte/ga-p67a-ud3r/cmos.default @@ -0,0 +1,5 @@ +boot_option=Fallback +debug_level=Debug +nmi=Enable +power_on_after_fail=Disable +sata_mode=AHCI diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/cmos.layout b/src/mainboard/gigabyte/ga-p67a-ud3r/cmos.layout new file mode 100644 index 0000000..4e5c0a8 --- /dev/null +++ b/src/mainboard/gigabyte/ga-p67a-ud3r/cmos.layout @@ -0,0 +1,107 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2014 Vladimir Serbinenko +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +# Status Register A +# ----------------------------------------------------------------- +# Status Register B +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 3 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +#392 3 r 0 unused +395 4 e 4 debug_level +#399 1 r 0 unused + +#400 8 r 0 reserved for century byte + +# coreboot config options: southbridge +#400 1 e 0 unused +408 1 e 1 nmi +409 2 e 5 power_on_after_fail +411 1 e 6 sata_mode + +# coreboot config options: northbridge +#432 3 r 0 unused + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable + +2 0 Enable +2 1 Disable + +3 0 Fallback +3 1 Normal + +4 0 Emergency +4 1 Alert +4 2 Critical +4 3 Error +4 4 Warning +4 5 Notice +4 6 Info +4 7 Debug +4 8 Spew + +5 0 Disable +5 1 Enable +5 2 Keep + +6 0 AHCI +6 1 Compatible + +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/devicetree.cb b/src/mainboard/gigabyte/ga-p67a-ud3r/devicetree.cb new file mode 100644 index 0000000..4ed458d --- /dev/null +++ b/src/mainboard/gigabyte/ga-p67a-ud3r/devicetree.cb @@ -0,0 +1,124 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 James Ye <jye836(a)gmail.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +# +chip northbridge/intel/sandybridge + device cpu_cluster 0x0 on + chip cpu/intel/model_206ax + device lapic 0x0 on end + + # Magic APIC ID to locate this chip + device lapic 0xacac off end + + register "c1_acpower" = "1" + register "c2_acpower" = "3" + register "c3_acpower" = "5" + + register "c1_battery" = "1" + register "c2_battery" = "3" + register "c3_battery" = "5" + end + end + + device domain 0x0 on + subsystemid 0x1458 0x5001 inherit + + device pci 00.0 on end # Host bridge + device pci 01.0 on # PCIe bridge (PCIEX16) + subsystemid 0x1458 0x5000 + end + device pci 02.0 off end # Internal graphics + + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "sata_port_map" = "0x3f" + register "sata_interface_speed_support" = "0x3" + + register "gen1_dec" = "0x000c0801" + register "gen2_dec" = "0x000c0291" + + register "pcie_port_coalesce" = "0" + register "c2_latency" = "0x0065" + register "p_cnt_throttling_supported" = "1" + + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + + device pci 16.0 off end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 off end # Intel Gigabit Ethernet + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x1458 0x5006 + end + device pci 1b.0 on # High Definition Audio controller + subsystemid 0x1458 0xa102 + end + device pci 1c.0 on end # Unrouted, to disable coalescing + device pci 1c.1 on # PCIe Port #2 + device pci 00.0 on # USB 3.0 controller + subsystemid 0x1458 0x5007 + end + end + device pci 1c.2 on # PCIe Port #3 + device pci 00.0 on # Ethernet controller + subsystemid 0x1458 0xe000 + end + end + device pci 1c.3 on # PCIe Port #4 + device pci 00.0 on # PCI bridge + subsystemid 0x1458 0x5000 + end + end + device pci 1c.4 on end # PCIe Port #5 (PCIEX4) + device pci 1c.5 off end # PCIe Port #6 (PCIEX1_1) + device pci 1c.6 off end # PCIe Port #7 (PCIEX1_2) + device pci 1c.7 off end # PCIe Port #8 (PCIEX1_3) + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x1458 0x5006 + end + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on # LPC bridge + chip superio/ite/it8728f + device pnp 2e.0 off end # Floppy, not routed + device pnp 2e.1 on # COM1 + io 0x60 = 0x03f8 + irq 0x70 = 4 + end + device pnp 2e.2 off end # COM2, not routed + device pnp 2e.3 off end # Parallel port, not rounted + device pnp 2e.4 on # Environment Controller + io 0x60 = 0x0290 + io 0x62 = 0x0 + irq 0x70 = 0 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.6 off end # Mouse + device pnp 2e.7 off end # GPIO + device pnp 2e.a off end # CIR, not routed + end + end + device pci 1f.2 on # SATA Controller 1 + subsystemid 0x1458 0xb005 + end + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/dsdt.asl b/src/mainboard/gigabyte/ga-p67a-ud3r/dsdt.asl new file mode 100644 index 0000000..365a0fa --- /dev/null +++ b/src/mainboard/gigabyte/ga-p67a-ud3r/dsdt.asl @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 James Ye <jye836(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +DefinitionBlock ( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI 2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 // OEM revision +) +{ + // Some generic macros + #include "acpi/mainboard.asl" + #include "acpi/platform.asl" + #include "acpi/superio.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + + // Global NVS and variables + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + + // Chipset specific sleep states + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } +} diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/gpio.c b/src/mainboard/gigabyte/ga-p67a-ud3r/gpio.c new file mode 100644 index 0000000..c65f432 --- /dev/null +++ b/src/mainboard/gigabyte/ga-p67a-ud3r/gpio.c @@ -0,0 +1,204 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2019 James Ye <jye836(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio11 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_GPIO, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio47 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_LOW, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/hda_verb.c b/src/mainboard/gigabyte/ga-p67a-ud3r/hda_verb.c new file mode 100644 index 0000000..a843a2b --- /dev/null +++ b/src/mainboard/gigabyte/ga-p67a-ud3r/hda_verb.c @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2019 James Ye <jye836(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0892, /* Codec Vendor / Device ID: Realtek */ + 0x1458a022, /* Subsystem ID */ + + 15, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x2, 0x1458a022), + + /* NID 0x11. */ + AZALIA_PIN_CFG(0x2, 0x11, 0x99430140), + + /* NID 0x12. */ + AZALIA_PIN_CFG(0x2, 0x12, 0x411111f0), + + /* NID 0x14. */ + AZALIA_PIN_CFG(0x2, 0x14, 0x01014410), + + /* NID 0x15. */ + AZALIA_PIN_CFG(0x2, 0x15, 0x01011412), + + /* NID 0x16. */ + AZALIA_PIN_CFG(0x2, 0x16, 0x01016411), + + /* NID 0x17. */ + AZALIA_PIN_CFG(0x2, 0x17, 0x01012414), + + /* NID 0x18. */ + AZALIA_PIN_CFG(0x2, 0x18, 0x01a19c50), + + /* NID 0x19. */ + AZALIA_PIN_CFG(0x2, 0x19, 0x02a19c60), + + /* NID 0x1a. */ + AZALIA_PIN_CFG(0x2, 0x1a, 0x0181345f), + + /* NID 0x1b. */ + AZALIA_PIN_CFG(0x2, 0x1b, 0x02214c20), + + /* NID 0x1c. */ + AZALIA_PIN_CFG(0x2, 0x1c, 0x593301f0), + + /* NID 0x1d. */ + AZALIA_PIN_CFG(0x2, 0x1d, 0x4005e601), + + /* NID 0x1e. */ + AZALIA_PIN_CFG(0x2, 0x1e, 0x014b6130), + + /* NID 0x1f. */ + AZALIA_PIN_CFG(0x2, 0x1f, 0x411111f0), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/romstage.c b/src/mainboard/gigabyte/ga-p67a-ud3r/romstage.c new file mode 100644 index 0000000..3037b73 --- /dev/null +++ b/src/mainboard/gigabyte/ga-p67a-ud3r/romstage.c @@ -0,0 +1,75 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2019 James Ye <jye836(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <superio/ite/common/ite.h> +#include <superio/ite/it8728f/it8728f.h> + +#define SUPERIO_BASE 0x2e +#define SUPERIO_GPIO PNP_DEV(SUPERIO_BASE, IT8728F_GPIO) +#define SERIAL_DEV PNP_DEV(SUPERIO_BASE, 0x01) + +void pch_enable_lpc(void) +{ + pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | CNF1_LPC_EN | + CNF2_LPC_EN | COMA_LPC_EN); +} + +void mainboard_rcba_config(void) +{ +} + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 1, 0 }, + { 1, 1, 0 }, + { 1, 1, 1 }, + { 1, 1, 1 }, + { 1, 6, 2 }, + { 1, 6, 2 }, + { 1, 6, 3 }, + { 1, 5, 3 }, + { 1, 5, 4 }, + { 1, 5, 4 }, + { 1, 5, 5 }, + { 1, 5, 5 }, + { 1, 5, 6 }, + { 1, 5, 6 }, +}; + +void mainboard_early_init(int s3resume) +{ +} + +void mainboard_config_superio(void) +{ + /* Enable serial port */ + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + + /* Disable SIO WDT which kicks in DualBIOS */ + ite_reg_write(SUPERIO_GPIO, 0xEF, 0x7E); +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x51, id_only); + read_spd(&spd[2], 0x52, id_only); + read_spd(&spd[3], 0x53, id_only); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/31363 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4fbf50376be3184bf01a3bc8aae09bce54676707 Gerrit-Change-Number: 31363 Gerrit-PatchSet: 1 Gerrit-Owner: James <jye836(a)gmail.com> Gerrit-MessageType: newchange

5 22

Change in ...coreboot[master]: nb/intel/sandybridge: Introduce soc/iomap.h
by Patrick Rudolph (Code Review) 07 Aug '23

07 Aug '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32075 Change subject: nb/intel/sandybridge: Introduce soc/iomap.h ...................................................................... nb/intel/sandybridge: Introduce soc/iomap.h Defines the memory ranges used by the northbridge in a separate header. Include the new header and rename the defines to match the one found in soc/intel/common. Change-Id: I93aa0e78ff52e46256debd26601600a96404509f Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/northbridge/intel/sandybridge/Makefile.inc M src/northbridge/intel/sandybridge/acpi.c M src/northbridge/intel/sandybridge/early_init.c A src/northbridge/intel/sandybridge/include/soc/iomap.h M src/northbridge/intel/sandybridge/northbridge.c M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/raminit_mrc.c M src/northbridge/intel/sandybridge/sandybridge.h 8 files changed, 92 insertions(+), 54 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/32075/1 diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index 54a4057..c3d9079 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -15,6 +15,8 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE)$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE),y) +CFLAGS_common += -Isrc/northbridge/intel/sandybridge/include + ramstage-y += ram_calc.c ramstage-y += northbridge.c ramstage-y += pcie.c diff --git a/src/northbridge/intel/sandybridge/acpi.c b/src/northbridge/intel/sandybridge/acpi.c index 4afb546..af2f37b 100644 --- a/src/northbridge/intel/sandybridge/acpi.c +++ b/src/northbridge/intel/sandybridge/acpi.c @@ -92,7 +92,8 @@ unsigned long tmp; tmp = current; - current += acpi_create_dmar_drhd(current, 0, 0, IOMMU_BASE1); + current += acpi_create_dmar_drhd(current, 0, 0, + GFXVT_BASE_ADDRESS); current += acpi_create_dmar_ds_pci(current, 0, 2, 0); current += acpi_create_dmar_ds_pci(current, 0, 2, 1); acpi_dmar_drhd_fixup(tmp, current); @@ -107,8 +108,8 @@ } const unsigned long tmp = current; - current += acpi_create_dmar_drhd(current, - DRHD_INCLUDE_PCI_ALL, 0, IOMMU_BASE2); + current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, + VTVC0_BASE_ADDRESS); current += acpi_create_dmar_ds_ioapic(current, 2, PCH_IOAPIC_PCI_BUS, PCH_IOAPIC_PCI_SLOT, 0); size_t i; diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index 5307a2c..2e0f087 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -35,20 +35,20 @@ return; /* setup BARs */ - MCHBAR32(0x5404) = IOMMU_BASE1 >> 32; - MCHBAR32(0x5400) = IOMMU_BASE1 | 1; - MCHBAR32(0x5414) = IOMMU_BASE2 >> 32; - MCHBAR32(0x5410) = IOMMU_BASE2 | 1; + MCHBAR32(0x5404) = GFXVT_BASE_ADDRESS >> 32; + MCHBAR32(0x5400) = GFXVT_BASE_ADDRESS | 1; + MCHBAR32(0x5414) = VTVC0_BASE_ADDRESS >> 32; + MCHBAR32(0x5410) = VTVC0_BASE_ADDRESS | 1; /* lock policies */ - write32((void *)(IOMMU_BASE1 + 0xff0), 0x80000000); + write32((void *)(GFXVT_BASE_ADDRESS + 0xff0), 0x80000000); const struct device *const azalia = pcidev_on_root(0x1b, 0); if (azalia && azalia->enabled) { - write32((void *)(IOMMU_BASE2 + 0xff0), 0x20000000); - write32((void *)(IOMMU_BASE2 + 0xff0), 0xa0000000); + write32((void *)(VTVC0_BASE_ADDRESS + 0xff0), 0x20000000); + write32((void *)(VTVC0_BASE_ADDRESS + 0xff0), 0xa0000000); } else { - write32((void *)(IOMMU_BASE2 + 0xff0), 0x80000000); + write32((void *)(VTVC0_BASE_ADDRESS + 0xff0), 0x80000000); } } @@ -67,12 +67,12 @@ { printk(BIOS_DEBUG, "Setting up static northbridge registers..."); /* Set up all hardcoded northbridge BARs */ - pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1); - pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR + 4, (0LL+DEFAULT_EPBAR) >> 32); - pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1); - pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4, (0LL+(uintptr_t)DEFAULT_MCHBAR) >> 32); - pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1); - pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, (0LL+(uintptr_t)DEFAULT_DMIBAR) >> 32); + pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, EP_BASE_ADDRESS | 1); + pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR + 4, EP_BASE_ADDRESS >> 32); + pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, MCH_BASE_ADDRESS | 1); + pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4, MCH_BASE_ADDRESS >> 32); + pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, DMI_BASE_ADDRESS | 1); + pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, DMI_BASE_ADDRESS >> 32); printk(BIOS_DEBUG, " done\n"); } diff --git a/src/northbridge/intel/sandybridge/include/soc/iomap.h b/src/northbridge/intel/sandybridge/include/soc/iomap.h new file mode 100644 index 0000000..75fd9d9 --- /dev/null +++ b/src/northbridge/intel/sandybridge/include/soc/iomap.h @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_SANDYBRIDGE_IOMAP_H_ +#define _SOC_SANDYBRIDGE_IOMAP_H_ + +/* + * Memory-mapped I/O registers. + */ +#define MCFG_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS +#define MCFG_BASE_SIZE 0x4000000 + +/* Intel Enhanced Debug region must be 4MB */ + +#define IED_SIZE CONFIG_IED_REGION_SIZE + +#define ILB_BASE_ADDRESS 0xfed08000ULL +#define ILB_BASE_SIZE 0x400 + +#define DMI_BASE_ADDRESS 0xfed18000ULL +#define DMI_BASE_SIZE 0x1000 + +#define MCH_BASE_ADDRESS 0xfed10000ULL +#define MCH_BASE_SIZE 0x4000 + +#define EP_BASE_ADDRESS 0xfed19000ULL +#define EP_BASE_SIZE 0x1000 + +#define GFXVT_BASE_ADDRESS 0xfed90000ULL +#define GFXVT_BASE_SIZE 0x1000 + +#define VTVC0_BASE_ADDRESS 0xfed91000ULL +#define VTVC0_BASE_SIZE 0x1000 + +#define TPM_BASE_ADDRESS 0xfed40000ULL +#define TPM_BASE_SIZE 0x5000 + + +#endif diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 5aa06c8..71dea62 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -112,8 +112,8 @@ /* Reserve IOMMU BARs */ const u32 capid0_a = pci_read_config32(dev, 0xe4); if (!(capid0_a & (1 << 23))) { - mmio_resource(dev, index++, IOMMU_BASE1 >> 10, 4); - mmio_resource(dev, index++, IOMMU_BASE2 >> 10, 4); + mmio_resource(dev, index++, GFXVT_BASE_ADDRESS / KiB, 4); + mmio_resource(dev, index++, VTVC0_BASE_ADDRESS / KiB, 4); } } diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 55df03b..72ae5b0 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -41,23 +41,23 @@ * Channel X = [0, 1] * Command queue index Y = [0, 1, 2, 3] * - * DEFAULT_MCHBAR + 0x4220 + 0x400 * X + 4 * Y: command io register + * MCH_BASE_ADDRESS + 0x4220 + 0x400 * X + 4 * Y: command io register * Controls the DRAM command signals * Bit 0: !RAS * Bit 1: !CAS * Bit 2: !WE * - * DEFAULT_MCHBAR + 0x4200 + 0x400 * X + 4 * Y: addr bankslot io register + * MCH_BASE_ADDRESS + 0x4200 + 0x400 * X + 4 * Y: addr bankslot io register * Controls the address, bank address and slotrank signals * Bit 0-15 : Address * Bit 20-22: Bank Address * Bit 24-25: slotrank * - * DEFAULT_MCHBAR + 0x4230 + 0x400 * X + 4 * Y: idle register + * MCH_BASE_ADDRESS + 0x4230 + 0x400 * X + 4 * Y: idle register * Controls the idle time after issuing this DRAM command * Bit 16-32: number of clock-cylces to idle * - * DEFAULT_MCHBAR + 0x4284 + 0x400 * channel: execute command queue + * MCH_BASE_ADDRESS + 0x4284 + 0x400 * channel: execute command queue * Starts to execute all queued commands * Bit 0 : start DRAM command execution * Bit 18-19 : number of queued commands - 1 diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index c544a74..2382084 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -277,10 +277,10 @@ static void northbridge_fill_pei_data(struct pei_data *pei_data) { - pei_data->mchbar = (uintptr_t)DEFAULT_MCHBAR; - pei_data->dmibar = (uintptr_t)DEFAULT_DMIBAR; - pei_data->epbar = DEFAULT_EPBAR; - pei_data->pciexbar = CONFIG_MMCONF_BASE_ADDRESS; + pei_data->mchbar = MCH_BASE_ADDRESS; + pei_data->dmibar = DMI_BASE_ADDRESS; + pei_data->epbar = EP_BASE_ADDRESS; + pei_data->pciexbar = MCFG_BASE_ADDRESS; pei_data->smbusbar = SMBUS_IO_BASE; pei_data->wdbbar = 0x4000000; pei_data->wdbsize = 0x1000; diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index d7de843..dc9f889 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -17,6 +17,8 @@ #ifndef __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__ #define __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__ +#include <northbridge/intel/sandybridge/include/soc/iomap.h> + /* Device ID for SandyBridge and IvyBridge */ #define BASE_REV_SNB 0x00 #define BASE_REV_IVB 0x50 @@ -34,24 +36,6 @@ #define IVB_STEP_K0 (BASE_REV_IVB + 5) #define IVB_STEP_D0 (BASE_REV_IVB + 6) -/* Intel Enhanced Debug region must be 4MB */ - -#define IED_SIZE CONFIG_IED_REGION_SIZE - -/* Northbridge BARs */ -#ifndef __ACPI__ -#define DEFAULT_MCHBAR ((u8 *)0xfed10000) /* 16 KB */ -#define DEFAULT_DMIBAR ((u8 *)0xfed18000) /* 4 KB */ -#else -#define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */ -#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ -#endif -#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ -#define DEFAULT_RCBABASE ((u8 *)0xfed1c000) - -#define IOMMU_BASE1 0xfed90000ULL -#define IOMMU_BASE2 0xfed91000ULL - /* Everything below this line is ignored in the DSDT */ #ifndef __ACPI__ #include <cpu/intel/model_206ax/model_206ax.h> @@ -118,9 +102,9 @@ * MCHBAR */ -#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x)))) +#define MCHBAR8(x) (*((volatile u8 *)((uintptr_t)MCH_BASE_ADDRESS + (x)))) +#define MCHBAR16(x) (*((volatile u16 *)((uintptr_t)MCH_BASE_ADDRESS + (x)))) +#define MCHBAR32(x) (*((volatile u32 *)((uintptr_t)MCH_BASE_ADDRESS + (x)))) #define MCHBAR32_OR(x, or) (MCHBAR32(x) = (MCHBAR32(x) | (or))) #define MCHBAR32_AND(x, and) (MCHBAR32(x) = (MCHBAR32(x) & (and))) #define MCHBAR32_AND_OR(x, and, or) \ @@ -133,9 +117,9 @@ * EPBAR - Egress Port Root Complex Register Block */ -#define EPBAR8(x) (*((volatile u8 *)(DEFAULT_EPBAR + (x)))) -#define EPBAR16(x) (*((volatile u16 *)(DEFAULT_EPBAR + (x)))) -#define EPBAR32(x) (*((volatile u32 *)(DEFAULT_EPBAR + (x)))) +#define EPBAR8(x) (*((volatile u8 *)((uintptr_t)EP_BASE_ADDRESS + (x)))) +#define EPBAR16(x) (*((volatile u16 *)((uintptr_t)EP_BASE_ADDRESS + (x)))) +#define EPBAR32(x) (*((volatile u32 *)((uintptr_t)EP_BASE_ADDRESS + (x)))) #define EPPVCCAP1 0x004 /* 32bit */ #define EPPVCCAP2 0x008 /* 32bit */ @@ -164,9 +148,9 @@ * DMIBAR */ -#define DMIBAR8(x) (*((volatile u8 *)(DEFAULT_DMIBAR + (x)))) -#define DMIBAR16(x) (*((volatile u16 *)(DEFAULT_DMIBAR + (x)))) -#define DMIBAR32(x) (*((volatile u32 *)(DEFAULT_DMIBAR + (x)))) +#define DMIBAR8(x) (*((volatile u8 *)((uintptr_t)DMI_BASE_ADDRESS + (x)))) +#define DMIBAR16(x) (*((volatile u16 *)((uintptr_t)DMI_BASE_ADDRESS + (x)))) +#define DMIBAR32(x) (*((volatile u32 *)((uintptr_t)DMI_BASE_ADDRESS + (x)))) #define DMIVCECH 0x000 /* 32bit */ #define DMIPVCCAP1 0x004 /* 32bit */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32075 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93aa0e78ff52e46256debd26601600a96404509f Gerrit-Change-Number: 32075 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

6 9

Change in ...coreboot[master]: [WIP]x86: Introduce the blobolator
by Patrick Rudolph (Code Review) 07 Aug '23

07 Aug '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32020 Change subject: [WIP]x86: Introduce the blobolator ...................................................................... [WIP]x86: Introduce the blobolator This is a PoC to run arbitrary code and blobs inside an emulated virtual machine using libx86emu, thus the name blobolator. The libx86emu has been patched to the following: * redirect IO to the host machine it's running on * trace IO * start in protected mode * add mechanism to drop IO access * add Kconfig to debug code it is running Implemented features: * Run ramstage in libx86emu * Run postcar in libx86emu TODO: * Add support to trace only blobs, not stages. * Improve translation of known IO to human readable format ** COM ** PCI ** APIC ** PIT ** POST Tested on qemu. Sucessfully run ramstage in blobolator. Change-Id: I13e47f45e69376d046f35c04363fe3db1cfaa610 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/Kconfig M src/arch/x86/boot.c M src/mainboard/emulation/qemu-i440fx/romstage.c M src/mainboard/emulation/qemu-q35/romstage.c M src/vendorcode/Makefile.inc A src/vendorcode/libx86emu/Makefile.inc A src/vendorcode/libx86emu/blobolator.c A src/vendorcode/libx86emu/decode.c A src/vendorcode/libx86emu/include/decode.h A src/vendorcode/libx86emu/include/mem.h A src/vendorcode/libx86emu/include/ops.h A src/vendorcode/libx86emu/include/prim_ops.h A src/vendorcode/libx86emu/include/x86emu.h A src/vendorcode/libx86emu/include/x86emu_int.h A src/vendorcode/libx86emu/mem.c A src/vendorcode/libx86emu/ops.c A src/vendorcode/libx86emu/ops2.c A src/vendorcode/libx86emu/prim_ops.c 18 files changed, 14,512 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/32020/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/32020 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I13e47f45e69376d046f35c04363fe3db1cfaa610 Gerrit-Change-Number: 32020 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

10 31

Change in coreboot[master]: Documentation: Add guidelines for new mainboard ports
by Patrick Rudolph (Code Review) 07 Aug '23

07 Aug '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34632 ) Change subject: Documentation: Add guidelines for new mainboard ports ...................................................................... Documentation: Add guidelines for new mainboard ports This is WIP and partly copied from https://www.coreboot.org/Motherboard_Porting_Guide It also list what should be documented for new mainboard ports. Change-Id: I134dbf2341696ba0dd33c3d52bf787b8eaabbdab Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M Documentation/getting_started/index.md A Documentation/getting_started/new_mainboard_ports.md M Documentation/getting_started/writing_documentation.md 3 files changed, 95 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/34632/1 diff --git a/Documentation/getting_started/index.md b/Documentation/getting_started/index.md index 52d873e..7821ee1 100644 --- a/Documentation/getting_started/index.md +++ b/Documentation/getting_started/index.md @@ -7,3 +7,4 @@ * [Gerrit Guidelines](gerrit_guidelines.md) * [Documentation License](license.md) * [Writing Documentation](writing_documentation.md) +* [Adding new mainboards](new_mainboard_ports.md) diff --git a/Documentation/getting_started/new_mainboard_ports.md b/Documentation/getting_started/new_mainboard_ports.md new file mode 100644 index 0000000..cb7cd9b --- /dev/null +++ b/Documentation/getting_started/new_mainboard_ports.md @@ -0,0 +1,91 @@ +# Adding new mainboards + +Mainboard code is placed under `src/mainboards`. It glues the HW components +together by selecting appropiate northbridge, southbridge, on-board HW and +drivers. + +It provides the devicetree.cb, configures GPIOs, audio codecs, a static ACPI +board desciption and allows the romstage code to retrieve the SPD for +DRAM training. + +## Starting a new port from scratch + +1. Identify your platform + Try to find out as much as possible about the current hardware. + Dump information with existing tools: + * lspci + * lsusb + * superiotool + * inteltool + * ectool + * dmidecode + * acpidump + + Have a look at the mainboard schematics to see how those components are + connected. +2. Find a similar existing board + It a good idea to find a similar board and use it as reference. You should + then provide a proper GPIO configuration and devicetree.cb. +3. Find a similar SuperIo or BMC + To debug coreboot you should get the serial console working first. If your + board has a SuperIO or BMC try to find a compatible one. + Some boards have UART hardware on the SoC, makeing external components + obsolete. +4. Start with a minimal bootable configuration. That is: + * serial is working + * SPD reading/DRAM is working + * A payload that is able to boot an operating system +5. Be able to recover from a bad flash. You should use external flashing as + it's likely that you will brick your platform on the first attempts. + Make sure to backup the original firmware (if any). + +## Code submission + +Here's a checklist for new mainboard ports: + +1. Try to not duplicate code, use variants scheme instead. +2. Split changes logical into top level directories: + `src/mainboard` , `src/northbridge`, `src/ec`, ... +3. Provide good documentation, see point 4 +4. In the commit message describe as much as possible or point to the + documentation, satisfying the following questions: + * Where's the flash IC located? + * Can you flash incircuit? + * Are there pinheaders for flashing? + * Is the flash hardware write-protected? + * Which flash IC is usually equipped? + * If the board features an BMC, can it be used for developing and + debugging? + * What was tested and is working? + * What was tested and isn't working? + * What wasn't tested (due to lack of testing equipment)? + * Are blobs necessary? + * How can the board be debugged? + * Are there serial, EHCI debug, xHCI debug or BMC connections? + * Does it have a SuperIO? + + In addition please descibe: + * How to retrieve blobs, like dumping them from vendor firmware + + See [Writing Documentation] for more details. + +5. What you should **not** document: + * Steps or instructions how to flash the board + * Steps or instructions how to use a specific application for flashing + * Please do not provide pictures of the whole board or it's backplate + connectors +6. Recommand a flashing method as descibed in [Flashing tutorial] +7. If you are working at/for a hardware vendor, please provide free board + schematics as well. +8. Provide a picture of the flash IC or flash connector. + * The picture should be less than 800pc in width and compressed with + 70% compression to reduce size. + * You must own the Copyright + * Try to cut of uninteresting parts of the image, like tables, cables, ... + +Once done submit your board to Gerrit. Please follow the [Gerrit Guidelines] as +well. + +[Writing Documentation]: writing_documentation.md +[Flashing tutorial]: ../flash_tutorial/index.md +[Gerrit Guidelines]: gerrit_guidelines.md diff --git a/Documentation/getting_started/writing_documentation.md b/Documentation/getting_started/writing_documentation.md index fb942a4..0b820fc 100644 --- a/Documentation/getting_started/writing_documentation.md +++ b/Documentation/getting_started/writing_documentation.md @@ -49,6 +49,8 @@ the current theme doesn't allow bigger images. 12. Shouldn't cover implementation details; for details, the code is the reference. +13. New mainboard ports should also add documentation. See + [Adding new mainboards] for more details. ## Referencing markdown documents @@ -122,3 +124,4 @@ [Markdown Guide]: https://www.markdownguide.org/ [Gerrit Guidelines]: gerrit_guidelines.md [review.coreboot.org]: https://review.coreboot.org +[Adding new mainboards]: new_mainboard_ports.md -- To view, visit https://review.coreboot.org/c/coreboot/+/34632 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I134dbf2341696ba0dd33c3d52bf787b8eaabbdab Gerrit-Change-Number: 34632 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

9 19

Change in ...coreboot[master]: WIP: google/krane: Add Panel TV101WUM-NL6 support.
by Kaka Ni (Code Review) 07 Aug '23

07 Aug '23

Kaka Ni has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32512 Change subject: WIP: google/krane: Add Panel TV101WUM-NL6 support. ...................................................................... WIP: google/krane: Add Panel TV101WUM-NL6 support. Add panel TV101WUM-NL6 for Krane. The edid info and init command are from: https://crrev.com/c/1565758 Change-Id: Ieb6b2be6c2c571c09c781f4370d8c52612421823 Signed-off-by: Kaka Ni <nigang(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/kukui/Makefile.inc M src/mainboard/google/kukui/display.c M src/mainboard/google/kukui/display.h A src/mainboard/google/kukui/panel_krane.c 4 files changed, 423 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/32512/1 diff --git a/src/mainboard/google/kukui/Makefile.inc b/src/mainboard/google/kukui/Makefile.inc index ef52031..9576b7d 100644 --- a/src/mainboard/google/kukui/Makefile.inc +++ b/src/mainboard/google/kukui/Makefile.inc @@ -24,6 +24,7 @@ ramstage-y += chromeos.c ramstage-y += display.c ramstage-y += panel_kukui.c +ramstage-y += panel_krane.c ramstage-y += mainboard.c ramstage-y += memlayout.ld ramstage-y += reset.c diff --git a/src/mainboard/google/kukui/display.c b/src/mainboard/google/kukui/display.c index 5ec6ccd..b0a5026 100644 --- a/src/mainboard/google/kukui/display.c +++ b/src/mainboard/google/kukui/display.c @@ -97,6 +97,8 @@ { if (CONFIG(BOARD_GOOGLE_KUKUI)) return &kukui_display_intf; + else if (CONFIG(BOARD_GOOGLE_KRANE)) + return &krane_display_intf; else return NULL; } diff --git a/src/mainboard/google/kukui/display.h b/src/mainboard/google/kukui/display.h index 33cc997..52420db 100644 --- a/src/mainboard/google/kukui/display.h +++ b/src/mainboard/google/kukui/display.h @@ -33,9 +33,18 @@ PANEL_KUKUI_UNINITIALIZED }; +enum krane_panel_id { + PANEL_KRANE_FIRST = 0, + PANEL_KRANE_BOE_TV101WUM_NL6, + PANEL_KRANE_UNKNOWN, + PANEL_KRANE_COUNT, + PANEL_KRANE_UNINITIALIZED +}; + union panel_id { enum kukui_panel_id kukui_panel; + enum krane_panel_id krane_panel; int value; }; @@ -90,6 +99,7 @@ * Panel Interface for boards */ extern struct board_display_intf kukui_display_intf; +extern struct board_display_intf krane_display_intf; #endif diff --git a/src/mainboard/google/kukui/panel_krane.c b/src/mainboard/google/kukui/panel_krane.c new file mode 100644 index 0000000..5c338c8 --- /dev/null +++ b/src/mainboard/google/kukui/panel_krane.c @@ -0,0 +1,410 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Huaqin Telecom Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <delay.h> +#include <device/device.h> +#include <edid.h> +#include <gpio.h> +#include <soc/auxadc.h> +#include <soc/ddp.h> +#include <soc/dsi.h> +#include <soc/gpio.h> +#include <boardid.h> + +#include "display.h" +#include "gpio.h" + +static struct edid krane_boe_tv101wum_nl6_edid = { + .panel_bits_per_color = 8, + .panel_bits_per_pixel = 24, + .mode = { + .name = "1200x1920@60Hz", + .pixel_clock = 159420, + .lvds_dual_channel = 0, + .refresh = 60, + .ha = 1200, .hbl = 164, .hso = 80, .hspw = 24, .hborder = 0, + .va = 1920, .vbl = 28, .vso = 10, .vspw = 4, .vborder = 0, + .phsync = '-', .pvsync = '-', + .x_mm = 135, .y_mm = 216, + }, +}; + +struct lcm_init_table boe_tv101wum_nl6_init_cmd[] = { + {INIT_DCS_CMD, 1, { 0x10 } }, + {DELAY_CMD, 34, {} }, + {INIT_DCS_CMD, 2, { 0xB0, 0x05 } }, + {INIT_DCS_CMD, 2, { 0xB1, 0xE5 } }, + {INIT_DCS_CMD, 2, { 0xB3, 0x52 } }, + {INIT_DCS_CMD, 2, { 0xB0, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xB3, 0x88 } }, + {INIT_DCS_CMD, 2, { 0xB0, 0x04 } }, + {INIT_DCS_CMD, 2, { 0xB8, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xB0, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xB6, 0x03 } }, + {INIT_DCS_CMD, 2, { 0xBA, 0x8B } }, + {INIT_DCS_CMD, 2, { 0xBF, 0x1A } }, + {INIT_DCS_CMD, 2, { 0xC0, 0x0F } }, + {INIT_DCS_CMD, 2, { 0xC2, 0x0C } }, + {INIT_DCS_CMD, 2, { 0xC3, 0x02 } }, + {INIT_DCS_CMD, 2, { 0xC4, 0x0C } }, + {INIT_DCS_CMD, 2, { 0xC5, 0x02 } }, + {INIT_DCS_CMD, 2, { 0xB0, 0x01 } }, + {INIT_DCS_CMD, 2, { 0xE0, 0x26 } }, + {INIT_DCS_CMD, 2, { 0xE1, 0x26 } }, + {INIT_DCS_CMD, 2, { 0xDC, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xDD, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xCC, 0x26 } }, + {INIT_DCS_CMD, 2, { 0xCD, 0x26 } }, + {INIT_DCS_CMD, 2, { 0xC8, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xC9, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xD2, 0x03 } }, + {INIT_DCS_CMD, 2, { 0xD3, 0x03 } }, + {INIT_DCS_CMD, 2, { 0xE6, 0x04 } }, + {INIT_DCS_CMD, 2, { 0xE7, 0x04 } }, + {INIT_DCS_CMD, 2, { 0xC4, 0x09 } }, + {INIT_DCS_CMD, 2, { 0xC5, 0x09 } }, + {INIT_DCS_CMD, 2, { 0xD8, 0x0A } }, + {INIT_DCS_CMD, 2, { 0xD9, 0x0A } }, + {INIT_DCS_CMD, 2, { 0xC2, 0x0B } }, + {INIT_DCS_CMD, 2, { 0xC3, 0x0B } }, + {INIT_DCS_CMD, 2, { 0xD6, 0x0C } }, + {INIT_DCS_CMD, 2, { 0xD7, 0x0C } }, + {INIT_DCS_CMD, 2, { 0xC0, 0x05 } }, + {INIT_DCS_CMD, 2, { 0xC1, 0x05 } }, + {INIT_DCS_CMD, 2, { 0xD4, 0x06 } }, + {INIT_DCS_CMD, 2, { 0xD5, 0x06 } }, + {INIT_DCS_CMD, 2, { 0xCA, 0x07 } }, + {INIT_DCS_CMD, 2, { 0xCB, 0x07 } }, + {INIT_DCS_CMD, 2, { 0xDE, 0x08 } }, + {INIT_DCS_CMD, 2, { 0xDF, 0x08 } }, + {INIT_DCS_CMD, 2, { 0xB0, 0x02 } }, + {INIT_DCS_CMD, 2, { 0xC0, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xC1, 0x0D } }, + {INIT_DCS_CMD, 2, { 0xC2, 0x17 } }, + {INIT_DCS_CMD, 2, { 0xC3, 0x26 } }, + {INIT_DCS_CMD, 2, { 0xC4, 0x31 } }, + {INIT_DCS_CMD, 2, { 0xC5, 0x1C } }, + {INIT_DCS_CMD, 2, { 0xC6, 0x2C } }, + {INIT_DCS_CMD, 2, { 0xC7, 0x33 } }, + {INIT_DCS_CMD, 2, { 0xC8, 0x31 } }, + {INIT_DCS_CMD, 2, { 0xC9, 0x37 } }, + {INIT_DCS_CMD, 2, { 0xCA, 0x37 } }, + {INIT_DCS_CMD, 2, { 0xCB, 0x37 } }, + {INIT_DCS_CMD, 2, { 0xCC, 0x39 } }, + {INIT_DCS_CMD, 2, { 0xCD, 0x2E } }, + {INIT_DCS_CMD, 2, { 0xCE, 0x2F } }, + {INIT_DCS_CMD, 2, { 0xCF, 0x2F } }, + {INIT_DCS_CMD, 2, { 0xD0, 0x07 } }, + {INIT_DCS_CMD, 2, { 0xD2, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xD3, 0x0D } }, + {INIT_DCS_CMD, 2, { 0xD4, 0x17 } }, + {INIT_DCS_CMD, 2, { 0xD5, 0x26 } }, + {INIT_DCS_CMD, 2, { 0xD6, 0x31 } }, + {INIT_DCS_CMD, 2, { 0xD7, 0x3F } }, + {INIT_DCS_CMD, 2, { 0xD8, 0x3F } }, + {INIT_DCS_CMD, 2, { 0xD9, 0x3F } }, + {INIT_DCS_CMD, 2, { 0xDA, 0x3F } }, + {INIT_DCS_CMD, 2, { 0xDB, 0x37 } }, + {INIT_DCS_CMD, 2, { 0xDC, 0x37 } }, + {INIT_DCS_CMD, 2, { 0xDD, 0x37 } }, + {INIT_DCS_CMD, 2, { 0xDE, 0x39 } }, + {INIT_DCS_CMD, 2, { 0xDF, 0x2E } }, + {INIT_DCS_CMD, 2, { 0xE0, 0x2F } }, + {INIT_DCS_CMD, 2, { 0xE1, 0x2F } }, + {INIT_DCS_CMD, 2, { 0xE2, 0x07 } }, + {INIT_DCS_CMD, 2, { 0xB0, 0x03 } }, + {INIT_DCS_CMD, 2, { 0xC8, 0x0B } }, + {INIT_DCS_CMD, 2, { 0xC9, 0x07 } }, + {INIT_DCS_CMD, 2, { 0xC3, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xE7, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xC5, 0x2A } }, + {INIT_DCS_CMD, 2, { 0xDE, 0x2A } }, + {INIT_DCS_CMD, 2, { 0xCA, 0x43 } }, + {INIT_DCS_CMD, 2, { 0xC9, 0x07 } }, + {INIT_DCS_CMD, 2, { 0xE4, 0xC0 } }, + {INIT_DCS_CMD, 2, { 0xE5, 0x0D } }, + {INIT_DCS_CMD, 2, { 0xCB, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xB0, 0x06 } }, + {INIT_DCS_CMD, 2, { 0xB8, 0xA5 } }, + {INIT_DCS_CMD, 2, { 0xC0, 0xA5 } }, + {INIT_DCS_CMD, 2, { 0xC7, 0x0F } }, + {INIT_DCS_CMD, 2, { 0xD5, 0x32 } }, + {INIT_DCS_CMD, 2, { 0xB8, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xC0, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xBC, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xB0, 0x07 } }, + {INIT_DCS_CMD, 2, { 0xB1, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xB2, 0x02 } }, + {INIT_DCS_CMD, 2, { 0xB3, 0x0F } }, + {INIT_DCS_CMD, 2, { 0xB4, 0x25 } }, + {INIT_DCS_CMD, 2, { 0xB5, 0x39 } }, + {INIT_DCS_CMD, 2, { 0xB6, 0x4E } }, + {INIT_DCS_CMD, 2, { 0xB7, 0x72 } }, + {INIT_DCS_CMD, 2, { 0xB8, 0x97 } }, + {INIT_DCS_CMD, 2, { 0xB9, 0xDC } }, + {INIT_DCS_CMD, 2, { 0xBA, 0x22 } }, + {INIT_DCS_CMD, 2, { 0xBB, 0xA4 } }, + {INIT_DCS_CMD, 2, { 0xBC, 0x2B } }, + {INIT_DCS_CMD, 2, { 0xBD, 0x2F } }, + {INIT_DCS_CMD, 2, { 0xBE, 0xA9 } }, + {INIT_DCS_CMD, 2, { 0xBF, 0x25 } }, + {INIT_DCS_CMD, 2, { 0xC0, 0x61 } }, + {INIT_DCS_CMD, 2, { 0xC1, 0x97 } }, + {INIT_DCS_CMD, 2, { 0xC2, 0xB2 } }, + {INIT_DCS_CMD, 2, { 0xC3, 0xCD } }, + {INIT_DCS_CMD, 2, { 0xC4, 0xD9 } }, + {INIT_DCS_CMD, 2, { 0xC5, 0xE7 } }, + {INIT_DCS_CMD, 2, { 0xC6, 0xF4 } }, + {INIT_DCS_CMD, 2, { 0xC7, 0xFA } }, + {INIT_DCS_CMD, 2, { 0xC8, 0xFC } }, + {INIT_DCS_CMD, 2, { 0xC9, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xCA, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xCB, 0x16 } }, + {INIT_DCS_CMD, 2, { 0xCC, 0xAF } }, + {INIT_DCS_CMD, 2, { 0xCD, 0xFF } }, + {INIT_DCS_CMD, 2, { 0xCE, 0xFF } }, + {INIT_DCS_CMD, 2, { 0xB0, 0x08 } }, + {INIT_DCS_CMD, 2, { 0xB1, 0x04 } }, + {INIT_DCS_CMD, 2, { 0xB2, 0x05 } }, + {INIT_DCS_CMD, 2, { 0xB3, 0x11 } }, + {INIT_DCS_CMD, 2, { 0xB4, 0x24 } }, + {INIT_DCS_CMD, 2, { 0xB5, 0x39 } }, + {INIT_DCS_CMD, 2, { 0xB6, 0x4F } }, + {INIT_DCS_CMD, 2, { 0xB7, 0x72 } }, + {INIT_DCS_CMD, 2, { 0xB8, 0x98 } }, + {INIT_DCS_CMD, 2, { 0xB9, 0xDC } }, + {INIT_DCS_CMD, 2, { 0xBA, 0x23 } }, + {INIT_DCS_CMD, 2, { 0xBB, 0xA6 } }, + {INIT_DCS_CMD, 2, { 0xBC, 0x2C } }, + {INIT_DCS_CMD, 2, { 0xBD, 0x30 } }, + {INIT_DCS_CMD, 2, { 0xBE, 0xAA } }, + {INIT_DCS_CMD, 2, { 0xBF, 0x26 } }, + {INIT_DCS_CMD, 2, { 0xC0, 0x62 } }, + {INIT_DCS_CMD, 2, { 0xC1, 0x9B } }, + {INIT_DCS_CMD, 2, { 0xC2, 0xB5 } }, + {INIT_DCS_CMD, 2, { 0xC3, 0xCF } }, + {INIT_DCS_CMD, 2, { 0xC4, 0xDB } }, + {INIT_DCS_CMD, 2, { 0xC5, 0xE8 } }, + {INIT_DCS_CMD, 2, { 0xC6, 0xF5 } }, + {INIT_DCS_CMD, 2, { 0xC7, 0xFA } }, + {INIT_DCS_CMD, 2, { 0xC8, 0xFC } }, + {INIT_DCS_CMD, 2, { 0xC9, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xCA, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xCB, 0x16 } }, + {INIT_DCS_CMD, 2, { 0xCC, 0xAF } }, + {INIT_DCS_CMD, 2, { 0xCD, 0xFF } }, + {INIT_DCS_CMD, 2, { 0xCE, 0xFF } }, + {INIT_DCS_CMD, 2, { 0xB0, 0x09 } }, + {INIT_DCS_CMD, 2, { 0xB1, 0x04 } }, + {INIT_DCS_CMD, 2, { 0xB2, 0x02 } }, + {INIT_DCS_CMD, 2, { 0xB3, 0x16 } }, + {INIT_DCS_CMD, 2, { 0xB4, 0x24 } }, + {INIT_DCS_CMD, 2, { 0xB5, 0x3B } }, + {INIT_DCS_CMD, 2, { 0xB6, 0x4F } }, + {INIT_DCS_CMD, 2, { 0xB7, 0x73 } }, + {INIT_DCS_CMD, 2, { 0xB8, 0x99 } }, + {INIT_DCS_CMD, 2, { 0xB9, 0xE0 } }, + {INIT_DCS_CMD, 2, { 0xBA, 0x26 } }, + {INIT_DCS_CMD, 2, { 0xBB, 0xAD } }, + {INIT_DCS_CMD, 2, { 0xBC, 0x36 } }, + {INIT_DCS_CMD, 2, { 0xBD, 0x3A } }, + {INIT_DCS_CMD, 2, { 0xBE, 0xAE } }, + {INIT_DCS_CMD, 2, { 0xBF, 0x2A } }, + {INIT_DCS_CMD, 2, { 0xC0, 0x66 } }, + {INIT_DCS_CMD, 2, { 0xC1, 0x9E } }, + {INIT_DCS_CMD, 2, { 0xC2, 0xB8 } }, + {INIT_DCS_CMD, 2, { 0xC3, 0xD1 } }, + {INIT_DCS_CMD, 2, { 0xC4, 0xDD } }, + {INIT_DCS_CMD, 2, { 0xC5, 0xE9 } }, + {INIT_DCS_CMD, 2, { 0xC6, 0xF6 } }, + {INIT_DCS_CMD, 2, { 0xC7, 0xFA } }, + {INIT_DCS_CMD, 2, { 0xC8, 0xFC } }, + {INIT_DCS_CMD, 2, { 0xC9, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xCA, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xCB, 0x16 } }, + {INIT_DCS_CMD, 2, { 0xCC, 0xAF } }, + {INIT_DCS_CMD, 2, { 0xCD, 0xFF } }, + {INIT_DCS_CMD, 2, { 0xCE, 0xFF } }, + {INIT_DCS_CMD, 2, { 0xB0, 0x0A } }, + {INIT_DCS_CMD, 2, { 0xB1, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xB2, 0x02 } }, + {INIT_DCS_CMD, 2, { 0xB3, 0x0F } }, + {INIT_DCS_CMD, 2, { 0xB4, 0x25 } }, + {INIT_DCS_CMD, 2, { 0xB5, 0x39 } }, + {INIT_DCS_CMD, 2, { 0xB6, 0x4E } }, + {INIT_DCS_CMD, 2, { 0xB7, 0x72 } }, + {INIT_DCS_CMD, 2, { 0xB8, 0x97 } }, + {INIT_DCS_CMD, 2, { 0xB9, 0xDC } }, + {INIT_DCS_CMD, 2, { 0xBA, 0x22 } }, + {INIT_DCS_CMD, 2, { 0xBB, 0xA4 } }, + {INIT_DCS_CMD, 2, { 0xBC, 0x2B } }, + {INIT_DCS_CMD, 2, { 0xBD, 0x2F } }, + {INIT_DCS_CMD, 2, { 0xBE, 0xA9 } }, + {INIT_DCS_CMD, 2, { 0xBF, 0x25 } }, + {INIT_DCS_CMD, 2, { 0xC0, 0x61 } }, + {INIT_DCS_CMD, 2, { 0xC1, 0x97 } }, + {INIT_DCS_CMD, 2, { 0xC2, 0xB2 } }, + {INIT_DCS_CMD, 2, { 0xC3, 0xCD } }, + {INIT_DCS_CMD, 2, { 0xC4, 0xD9 } }, + {INIT_DCS_CMD, 2, { 0xC5, 0xE7 } }, + {INIT_DCS_CMD, 2, { 0xC6, 0xF4 } }, + {INIT_DCS_CMD, 2, { 0xC7, 0xFA } }, + {INIT_DCS_CMD, 2, { 0xC8, 0xFC } }, + {INIT_DCS_CMD, 2, { 0xC9, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xCA, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xCB, 0x16 } }, + {INIT_DCS_CMD, 2, { 0xCC, 0xAF } }, + {INIT_DCS_CMD, 2, { 0xCD, 0xFF } }, + {INIT_DCS_CMD, 2, { 0xCE, 0xFF } }, + {INIT_DCS_CMD, 2, { 0xB0, 0x0B } }, + {INIT_DCS_CMD, 2, { 0xB1, 0x04 } }, + {INIT_DCS_CMD, 2, { 0xB2, 0x05 } }, + {INIT_DCS_CMD, 2, { 0xB3, 0x11 } }, + {INIT_DCS_CMD, 2, { 0xB4, 0x24 } }, + {INIT_DCS_CMD, 2, { 0xB5, 0x39 } }, + {INIT_DCS_CMD, 2, { 0xB6, 0x4F } }, + {INIT_DCS_CMD, 2, { 0xB7, 0x72 } }, + {INIT_DCS_CMD, 2, { 0xB8, 0x98 } }, + {INIT_DCS_CMD, 2, { 0xB9, 0xDC } }, + {INIT_DCS_CMD, 2, { 0xBA, 0x23 } }, + {INIT_DCS_CMD, 2, { 0xBB, 0xA6 } }, + {INIT_DCS_CMD, 2, { 0xBC, 0x2C } }, + {INIT_DCS_CMD, 2, { 0xBD, 0x30 } }, + {INIT_DCS_CMD, 2, { 0xBE, 0xAA } }, + {INIT_DCS_CMD, 2, { 0xBF, 0x26 } }, + {INIT_DCS_CMD, 2, { 0xC0, 0x62 } }, + {INIT_DCS_CMD, 2, { 0xC1, 0x9B } }, + {INIT_DCS_CMD, 2, { 0xC2, 0xB5 } }, + {INIT_DCS_CMD, 2, { 0xC3, 0xCF } }, + {INIT_DCS_CMD, 2, { 0xC4, 0xDB } }, + {INIT_DCS_CMD, 2, { 0xC5, 0xE8 } }, + {INIT_DCS_CMD, 2, { 0xC6, 0xF5 } }, + {INIT_DCS_CMD, 2, { 0xC7, 0xFA } }, + {INIT_DCS_CMD, 2, { 0xC8, 0xFC } }, + {INIT_DCS_CMD, 2, { 0xC9, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xCA, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xCB, 0x16 } }, + {INIT_DCS_CMD, 2, { 0xCC, 0xAF } }, + {INIT_DCS_CMD, 2, { 0xCD, 0xFF } }, + {INIT_DCS_CMD, 2, { 0xCE, 0xFF } }, + {INIT_DCS_CMD, 2, { 0xB0, 0x0C } }, + {INIT_DCS_CMD, 2, { 0xB1, 0x04 } }, + {INIT_DCS_CMD, 2, { 0xB2, 0x02 } }, + {INIT_DCS_CMD, 2, { 0xB3, 0x16 } }, + {INIT_DCS_CMD, 2, { 0xB4, 0x24 } }, + {INIT_DCS_CMD, 2, { 0xB5, 0x3B } }, + {INIT_DCS_CMD, 2, { 0xB6, 0x4F } }, + {INIT_DCS_CMD, 2, { 0xB7, 0x73 } }, + {INIT_DCS_CMD, 2, { 0xB8, 0x99 } }, + {INIT_DCS_CMD, 2, { 0xB9, 0xE0 } }, + {INIT_DCS_CMD, 2, { 0xBA, 0x26 } }, + {INIT_DCS_CMD, 2, { 0xBB, 0xAD } }, + {INIT_DCS_CMD, 2, { 0xBC, 0x36 } }, + {INIT_DCS_CMD, 2, { 0xBD, 0x3A } }, + {INIT_DCS_CMD, 2, { 0xBE, 0xAE } }, + {INIT_DCS_CMD, 2, { 0xBF, 0x2A } }, + {INIT_DCS_CMD, 2, { 0xC0, 0x66 } }, + {INIT_DCS_CMD, 2, { 0xC1, 0x9E } }, + {INIT_DCS_CMD, 2, { 0xC2, 0xB8 } }, + {INIT_DCS_CMD, 2, { 0xC3, 0xD1 } }, + {INIT_DCS_CMD, 2, { 0xC4, 0xDD } }, + {INIT_DCS_CMD, 2, { 0xC5, 0xE9 } }, + {INIT_DCS_CMD, 2, { 0xC6, 0xF6 } }, + {INIT_DCS_CMD, 2, { 0xC7, 0xFA } }, + {INIT_DCS_CMD, 2, { 0xC8, 0xFC } }, + {INIT_DCS_CMD, 2, { 0xC9, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xCA, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xCB, 0x16 } }, + {INIT_DCS_CMD, 2, { 0xCC, 0xAF } }, + {INIT_DCS_CMD, 2, { 0xCD, 0xFF } }, + {INIT_DCS_CMD, 2, { 0xCE, 0xFF } }, + {INIT_DCS_CMD, 2, { 0xB0, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xB3, 0x08 } }, + {INIT_DCS_CMD, 2, { 0xB0, 0x04 } }, + {INIT_DCS_CMD, 2, { 0xB8, 0x68 } }, + {DELAY_CMD, 10, {} }, + {INIT_DCS_CMD, 1, { 0x11 } }, + {DELAY_CMD, 120, {} }, + {INIT_DCS_CMD, 1, { 0x29 } }, + {DELAY_CMD, 20, {} }, + +}; + +struct panel_info krane_panel_info[] = { + PANEL(PANEL_KRANE_BOE_TV101WUM_NL6, + 74000, + krane_boe_tv101wum_nl6_edid, + boe_tv101wum_nl6_init_cmd), + {{PANEL_KRANE_UNKNOWN}, "PANEL_KRANE_UNKNOWN", + 0, NULL, NULL, 0}, +}; + + +static union panel_id krane_get_panel_id(struct board_display_intf *intf) +{ + + return (union panel_id)PANEL_KRANE_BOE_TV101WUM_NL6; +}; + +static bool krane_is_panel_id_valid(union panel_id id) +{ + if (id.value < PANEL_KRANE_UNKNOWN) + return true; + return false; +}; + +static int krane_backlight(struct board_display_intf *intf) +{ + configure_backlight(); + return 0; +}; + +static int krane_power(struct board_display_intf *intf) +{ + + if (board_id() < 2) { + /* board from p1 */ + gpio_output(GPIO(LCM_RST), 0); + udelay(100); + gpio_output(GPIO(LCM_RST), 1); + mdelay(20); + } else { + /* board from p2 */ + gpio_output(GPIO(LCM_RST), 0); + udelay(1500); + gpio_output(GPIO(SIM2_SRST), 1); + mdelay(5); + gpio_output(GPIO(PERIPHERAL_EN9), 1); + gpio_output(GPIO(MISC_BSI_CK_3), 1); + mdelay(100); + gpio_output(GPIO(LCM_RST), 1); + mdelay(10); + } + + return 0; + +}; + +struct board_display_intf krane_display_intf = { + .board = "krane", + .all_panel_info = krane_panel_info, + .all_panel_info_size = ARRAY_SIZE(krane_panel_info), + .cur_panel_info = NULL, + .get_panel_id = &krane_get_panel_id, + .is_panel_id_valid = &krane_is_panel_id_valid, + .backlight = &krane_backlight, + .power = &krane_power, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/32512 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb6b2be6c2c571c09c781f4370d8c52612421823 Gerrit-Change-Number: 32512 Gerrit-PatchSet: 1 Gerrit-Owner: Kaka Ni <nigang(a)huaqin.corp-partner.google.com> Gerrit-MessageType: newchange

6 15

Change in ...coreboot[master]: util/lint: check correctness of Change-Id line
by Idwer Vollering (Code Review) 07 Aug '23

07 Aug '23

Idwer Vollering has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33884 Change subject: util/lint: check correctness of Change-Id line ...................................................................... util/lint: check correctness of Change-Id line Change-Id: I67b9f134500bb596ae5790b68fe9f27e2fa2cfb4 Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> --- A util/lint/lint-extended-024-change-id 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/33884/1 diff --git a/util/lint/lint-extended-024-change-id b/util/lint/lint-extended-024-change-id new file mode 100755 index 0000000..1989ed4 --- /dev/null +++ b/util/lint/lint-extended-024-change-id @@ -0,0 +1,10 @@ +#!/bin/sh +if [ "$(git log -n 1 | grep -c '[[:space:]]\+Change-Id: ')" -lt 1 ] +then + echo "Change-Id line is missing"; +fi + +if [ "$(git log -n 1 | grep -c '[[:space:]]\+Change-Id: ')" -gt 1 ] +then + echo "Found more than one Change-Id line"; +fi -- To view, visit https://review.coreboot.org/c/coreboot/+/33884 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67b9f134500bb596ae5790b68fe9f27e2fa2cfb4 Gerrit-Change-Number: 33884 Gerrit-PatchSet: 1 Gerrit-Owner: Idwer Vollering <vidwer(a)gmail.com> Gerrit-MessageType: newchange

7 18

Change in coreboot[master]: cpu/intel/speedstep: Add comment to clarify define
by Patrick Rudolph (Code Review) 07 Aug '23

07 Aug '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34360 ) Change subject: cpu/intel/speedstep: Add comment to clarify define ...................................................................... cpu/intel/speedstep: Add comment to clarify define Add a comment to clarify that the define must match the define in southbridge headers. Change-Id: Ie0e97b170c81e3bca38975d6a3fe9a368c70e622 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/include/cpu/intel/speedstep.h 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/34360/1 diff --git a/src/include/cpu/intel/speedstep.h b/src/include/cpu/intel/speedstep.h index 05d83ed..660e5ae 100644 --- a/src/include/cpu/intel/speedstep.h +++ b/src/include/cpu/intel/speedstep.h @@ -25,6 +25,7 @@ /* MWAIT coordination I/O base address. This must match * the \_PR_.CP00 PM base address. + * PMB0_BASE - 0x10 should match PMBASE for legacy C-state emulation. */ #define PMB0_BASE 0x510 -- To view, visit https://review.coreboot.org/c/coreboot/+/34360 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie0e97b170c81e3bca38975d6a3fe9a368c70e622 Gerrit-Change-Number: 34360 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

5 4

Change in coreboot[master]: mb/supermicro: Add X10SLM+-LN4F as X10SLM variant
by Christoph Pomaska (Code Review) 07 Aug '23

07 Aug '23

Christoph Pomaska has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35163 ) Change subject: mb/supermicro: Add X10SLM+-LN4F as X10SLM variant ...................................................................... mb/supermicro: Add X10SLM+-LN4F as X10SLM variant This commit modifies the source tree of the X10SLM-F board to support building a slightly different variant of the board, the X10SLM-LN4F. Change-Id: I686d8d4e2ec5b4eb2db214b6e0827ac9c33829d1 Signed-off-by: Christoph Pomaska <c.pomaska(a)hosting.de> --- D src/mainboard/supermicro/x10slm-f/Kconfig.name D src/mainboard/supermicro/x10slm-f/board_info.txt R src/mainboard/supermicro/x10slm/Kconfig A src/mainboard/supermicro/x10slm/Kconfig.name R src/mainboard/supermicro/x10slm/Makefile.inc R src/mainboard/supermicro/x10slm/acpi/ec.asl R src/mainboard/supermicro/x10slm/acpi/platform.asl R src/mainboard/supermicro/x10slm/acpi/superio.asl R src/mainboard/supermicro/x10slm/acpi_tables.c A src/mainboard/supermicro/x10slm/board_info.txt R src/mainboard/supermicro/x10slm/bootblock.c R src/mainboard/supermicro/x10slm/cmos.default R src/mainboard/supermicro/x10slm/cmos.layout R src/mainboard/supermicro/x10slm/dsdt.asl R src/mainboard/supermicro/x10slm/gpio.c R src/mainboard/supermicro/x10slm/mainboard.c R src/mainboard/supermicro/x10slm/romstage.c R src/mainboard/supermicro/x10slm/variants/x10slm-f/devicetree.cb R src/mainboard/supermicro/x10slm/variants/x10slm-f/hda_verb.c A src/mainboard/supermicro/x10slm/variants/x10slm-ln4f/devicetree.cb C src/mainboard/supermicro/x10slm/variants/x10slm-ln4f/hda_verb.c 21 files changed, 238 insertions(+), 78 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/35163/1 diff --git a/src/mainboard/supermicro/x10slm-f/Kconfig.name b/src/mainboard/supermicro/x10slm-f/Kconfig.name deleted file mode 100644 index a1965a3..0000000 --- a/src/mainboard/supermicro/x10slm-f/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_SUPERMICRO_X10SLM_PLUS_F - bool "X10SLM+-F" diff --git a/src/mainboard/supermicro/x10slm-f/board_info.txt b/src/mainboard/supermicro/x10slm-f/board_info.txt deleted file mode 100644 index e558429..0000000 --- a/src/mainboard/supermicro/x10slm-f/board_info.txt +++ /dev/null @@ -1,7 +0,0 @@ -Category: server -Board URL: https://www.supermicro.com/products/motherboard/xeon/c220/x10slm_-f.cfm -ROM package: SOIC-8 -ROM protocol: SPI -ROM socketed: n -Flashrom support: y -Release year: 2013 diff --git a/src/mainboard/supermicro/x10slm-f/Kconfig b/src/mainboard/supermicro/x10slm/Kconfig similarity index 60% rename from src/mainboard/supermicro/x10slm-f/Kconfig rename to src/mainboard/supermicro/x10slm/Kconfig index 3945c09..99a3099 100644 --- a/src/mainboard/supermicro/x10slm-f/Kconfig +++ b/src/mainboard/supermicro/x10slm/Kconfig @@ -2,6 +2,7 @@ ## This file is part of the coreboot project. ## ## Copyright (C) 2018 Tristan Corrick <tristan(a)corrick.kiwi> +## Copyright (C) 2019 Hosting.de GmbH <c.pomaska(a)hosting.de> ## ## This program is free software: you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -14,13 +15,12 @@ ## GNU General Public License for more details. ## -if BOARD_SUPERMICRO_X10SLM_PLUS_F +if BOARD_SUPERMICRO_X10SLM_PLUS_F || BOARD_SUPERMICRO_X10SLM_PLUS_LN4F config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_16384 select CPU_INTEL_HASWELL - select DRIVERS_ASPEED_AST2050 # Supports AST2400 too. select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE @@ -30,19 +30,33 @@ select SOUTHBRIDGE_INTEL_LYNXPOINT select SUPERIO_NUVOTON_NCT6776 select SUPERIO_NUVOTON_NCT6776_COM_A + select DRIVERS_ASPEED_AST2050 + select SUPERIO_ASPEED_AST2400 # The board's BMC + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_TPM2 + +config MAINBOARD_DIR + string + default "supermicro/x10slm" + +config VARIANT_DIR + string + default "x10slm-f" if BOARD_SUPERMICRO_X10SLM_PLUS_F + default "x10slm-ln4f" if BOARD_SUPERMICRO_X10SLM_PLUS_LN4F + +config MAINBOARD_PART_NUMBER + string + default "X10SLM+-F" if BOARD_SUPERMICRO_X10SLM_PLUS_F + default "X10SLM+-LN4F" if BOARD_SUPERMICRO_X10SLM_PLUS_LN4F + +config DEVICETREE + default "variants/x10slm-f/devicetree.cb" if BOARD_SUPERMICRO_X10SLM_PLUS_F + default "variants/x10slm-ln4f/devicetree.cb" if BOARD_SUPERMICRO_X10SLM_PLUS_LN4F config CBFS_SIZE hex default 0xb00000 -config MAINBOARD_DIR - string - default "supermicro/x10slm-f" - -config MAINBOARD_PART_NUMBER - string - default "X10SLM+-F" - config MAX_CPUS int default 8 diff --git a/src/mainboard/supermicro/x10slm/Kconfig.name b/src/mainboard/supermicro/x10slm/Kconfig.name new file mode 100644 index 0000000..6f95d97 --- /dev/null +++ b/src/mainboard/supermicro/x10slm/Kconfig.name @@ -0,0 +1,4 @@ +config BOARD_SUPERMICRO_X10SLM_PLUS_F + bool "X10SLM+-F" +config BOARD_SUPERMICRO_X10SLM_PLUS_LN4F + bool "X10SLM+-LN4F" diff --git a/src/mainboard/supermicro/x10slm-f/Makefile.inc b/src/mainboard/supermicro/x10slm/Makefile.inc similarity index 100% rename from src/mainboard/supermicro/x10slm-f/Makefile.inc rename to src/mainboard/supermicro/x10slm/Makefile.inc diff --git a/src/mainboard/supermicro/x10slm-f/acpi/ec.asl b/src/mainboard/supermicro/x10slm/acpi/ec.asl similarity index 100% rename from src/mainboard/supermicro/x10slm-f/acpi/ec.asl rename to src/mainboard/supermicro/x10slm/acpi/ec.asl diff --git a/src/mainboard/supermicro/x10slm-f/acpi/platform.asl b/src/mainboard/supermicro/x10slm/acpi/platform.asl similarity index 100% rename from src/mainboard/supermicro/x10slm-f/acpi/platform.asl rename to src/mainboard/supermicro/x10slm/acpi/platform.asl diff --git a/src/mainboard/supermicro/x10slm-f/acpi/superio.asl b/src/mainboard/supermicro/x10slm/acpi/superio.asl similarity index 100% rename from src/mainboard/supermicro/x10slm-f/acpi/superio.asl rename to src/mainboard/supermicro/x10slm/acpi/superio.asl diff --git a/src/mainboard/supermicro/x10slm-f/acpi_tables.c b/src/mainboard/supermicro/x10slm/acpi_tables.c similarity index 100% rename from src/mainboard/supermicro/x10slm-f/acpi_tables.c rename to src/mainboard/supermicro/x10slm/acpi_tables.c diff --git a/src/mainboard/supermicro/x10slm/board_info.txt b/src/mainboard/supermicro/x10slm/board_info.txt new file mode 100644 index 0000000..741cfa3 --- /dev/null +++ b/src/mainboard/supermicro/x10slm/board_info.txt @@ -0,0 +1,9 @@ +Category: server +Board URLs: +X10SLM-F: https://www.supermicro.com/products/motherboard/xeon/c220/x10slm_-f.cfm +X10SLM-LN4F: https://www.supermicro.com/en/products/motherboard/X10SLM+-LN4F +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2013 diff --git a/src/mainboard/supermicro/x10slm-f/bootblock.c b/src/mainboard/supermicro/x10slm/bootblock.c similarity index 100% rename from src/mainboard/supermicro/x10slm-f/bootblock.c rename to src/mainboard/supermicro/x10slm/bootblock.c diff --git a/src/mainboard/supermicro/x10slm-f/cmos.default b/src/mainboard/supermicro/x10slm/cmos.default similarity index 100% rename from src/mainboard/supermicro/x10slm-f/cmos.default rename to src/mainboard/supermicro/x10slm/cmos.default diff --git a/src/mainboard/supermicro/x10slm-f/cmos.layout b/src/mainboard/supermicro/x10slm/cmos.layout similarity index 100% rename from src/mainboard/supermicro/x10slm-f/cmos.layout rename to src/mainboard/supermicro/x10slm/cmos.layout diff --git a/src/mainboard/supermicro/x10slm-f/dsdt.asl b/src/mainboard/supermicro/x10slm/dsdt.asl similarity index 100% rename from src/mainboard/supermicro/x10slm-f/dsdt.asl rename to src/mainboard/supermicro/x10slm/dsdt.asl diff --git a/src/mainboard/supermicro/x10slm-f/gpio.c b/src/mainboard/supermicro/x10slm/gpio.c similarity index 86% rename from src/mainboard/supermicro/x10slm-f/gpio.c rename to src/mainboard/supermicro/x10slm/gpio.c index a1668f1..0ecdaca 100644 --- a/src/mainboard/supermicro/x10slm-f/gpio.c +++ b/src/mainboard/supermicro/x10slm/gpio.c @@ -87,16 +87,14 @@ .gpio28 = GPIO_LEVEL_HIGH, }; -static const struct pch_gpio_set1 pch_gpio_set1_reset = { -}; +static const struct pch_gpio_set1 pch_gpio_set1_reset = {}; static const struct pch_gpio_set1 pch_gpio_set1_invert = { .gpio3 = GPIO_INVERT, .gpio14 = GPIO_INVERT, }; -static const struct pch_gpio_set1 pch_gpio_set1_blink = { -}; +static const struct pch_gpio_set1 pch_gpio_set1_blink = {}; static const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio32 = GPIO_MODE_GPIO, @@ -156,8 +154,7 @@ .gpio54 = GPIO_LEVEL_HIGH, }; -static const struct pch_gpio_set2 pch_gpio_set2_reset = { -}; +static const struct pch_gpio_set2 pch_gpio_set2_reset = {}; static const struct pch_gpio_set3 pch_gpio_set3_mode = { .gpio64 = GPIO_MODE_GPIO, @@ -188,28 +185,30 @@ .gpio73 = GPIO_LEVEL_LOW, }; -static const struct pch_gpio_set3 pch_gpio_set3_reset = { -}; +static const struct pch_gpio_set3 pch_gpio_set3_reset = {}; const struct pch_gpio_map mainboard_gpio_map = { - .set1 = { - .mode = &pch_gpio_set1_mode, - .direction = &pch_gpio_set1_direction, - .level = &pch_gpio_set1_level, - .blink = &pch_gpio_set1_blink, - .invert = &pch_gpio_set1_invert, - .reset = &pch_gpio_set1_reset, - }, - .set2 = { - .mode = &pch_gpio_set2_mode, - .direction = &pch_gpio_set2_direction, - .level = &pch_gpio_set2_level, - .reset = &pch_gpio_set2_reset, - }, - .set3 = { - .mode = &pch_gpio_set3_mode, - .direction = &pch_gpio_set3_direction, - .level = &pch_gpio_set3_level, - .reset = &pch_gpio_set3_reset, - }, + .set1 = + { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = + { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = + { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, }; diff --git a/src/mainboard/supermicro/x10slm-f/mainboard.c b/src/mainboard/supermicro/x10slm/mainboard.c similarity index 96% rename from src/mainboard/supermicro/x10slm-f/mainboard.c rename to src/mainboard/supermicro/x10slm/mainboard.c index 4bd5d15..57b5cec 100644 --- a/src/mainboard/supermicro/x10slm-f/mainboard.c +++ b/src/mainboard/supermicro/x10slm/mainboard.c @@ -53,6 +53,5 @@ } struct chip_operations mainboard_ops = { - CHIP_NAME("X10SLM+-F") - .enable_dev = mainboard_enable, + CHIP_NAME("X10SLM+-F").enable_dev = mainboard_enable, }; diff --git a/src/mainboard/supermicro/x10slm-f/romstage.c b/src/mainboard/supermicro/x10slm/romstage.c similarity index 70% rename from src/mainboard/supermicro/x10slm-f/romstage.c rename to src/mainboard/supermicro/x10slm/romstage.c index 552ebd2..0ff9b69 100644 --- a/src/mainboard/supermicro/x10slm-f/romstage.c +++ b/src/mainboard/supermicro/x10slm/romstage.c @@ -16,7 +16,7 @@ */ #include <cpu/intel/haswell/haswell.h> -#include <arch/romstage.h> +#include <cpu/intel/romstage.h> #include <northbridge/intel/haswell/haswell.h> #include <northbridge/intel/haswell/pei_data.h> #include <southbridge/intel/common/gpio.h> @@ -38,7 +38,7 @@ RCBA_END_CONFIG, }; -void mainboard_romstage_entry(void) +void mainboard_romstage_entry(unsigned long bist) { struct pei_data pei_data = { .pei_version = PEI_VERSION, @@ -56,42 +56,45 @@ .temp_mmio_base = 0xfed08000, .system_type = 1, /* desktop/server */ .tseg_size = CONFIG_SMM_TSEG_SIZE, - .spd_addresses = { 0xa0, 0xa2, 0xa4, 0xa6 }, + .spd_addresses = {0xa0, 0xa2, 0xa4, 0xa6}, .ec_present = 0, .ddr_refresh_2x = 1, .max_ddr3_freq = 1600, - .usb2_ports = { - /* Length, Enable, OCn#, Location */ - { 0x0040, 1, 0, USB_PORT_INTERNAL }, - { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, - { 0x0110, 1, 1, USB_PORT_BACK_PANEL }, - { 0x0110, 1, 1, USB_PORT_BACK_PANEL }, - { 0x0110, 1, 2, USB_PORT_BACK_PANEL }, - { 0x0110, 1, 2, USB_PORT_BACK_PANEL }, - { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP }, - { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP }, - { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, - { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, - { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP }, - { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP }, - { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, - { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, - }, - .usb3_ports = { - /* Enable, OCn# */ - { 1, 1 }, - { 1, 1 }, - { 0, USB_OC_PIN_SKIP }, - { 0, USB_OC_PIN_SKIP }, - { 1, 3 }, - { 1, 3 }, - }, + .usb2_ports = + { + /* Length, Enable, OCn#, Location */ + {0x0040, 1, 0, USB_PORT_INTERNAL}, + {0x0040, 1, 0, USB_PORT_BACK_PANEL}, + {0x0110, 1, 1, USB_PORT_BACK_PANEL}, + {0x0110, 1, 1, USB_PORT_BACK_PANEL}, + {0x0110, 1, 2, USB_PORT_BACK_PANEL}, + {0x0110, 1, 2, USB_PORT_BACK_PANEL}, + {0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP}, + {0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP}, + {0x0040, 1, 4, USB_PORT_BACK_PANEL}, + {0x0040, 1, 4, USB_PORT_BACK_PANEL}, + {0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP}, + {0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP}, + {0x0040, 1, 6, USB_PORT_BACK_PANEL}, + {0x0040, 1, 6, USB_PORT_BACK_PANEL}, + }, + .usb3_ports = + { + /* Enable, OCn# */ + {1, 1}, + {1, 1}, + {0, USB_OC_PIN_SKIP}, + {0, USB_OC_PIN_SKIP}, + {1, 3}, + {1, 3}, + }, }; struct romstage_params romstage_params = { .pei_data = &pei_data, .gpio_map = &mainboard_gpio_map, .rcba_config = rcba_config, + .bist = bist, }; romstage_common(&romstage_params); diff --git a/src/mainboard/supermicro/x10slm-f/devicetree.cb b/src/mainboard/supermicro/x10slm/variants/x10slm-f/devicetree.cb similarity index 100% rename from src/mainboard/supermicro/x10slm-f/devicetree.cb rename to src/mainboard/supermicro/x10slm/variants/x10slm-f/devicetree.cb diff --git a/src/mainboard/supermicro/x10slm-f/hda_verb.c b/src/mainboard/supermicro/x10slm/variants/x10slm-f/hda_verb.c similarity index 100% rename from src/mainboard/supermicro/x10slm-f/hda_verb.c rename to src/mainboard/supermicro/x10slm/variants/x10slm-f/hda_verb.c diff --git a/src/mainboard/supermicro/x10slm/variants/x10slm-ln4f/devicetree.cb b/src/mainboard/supermicro/x10slm/variants/x10slm-ln4f/devicetree.cb new file mode 100644 index 0000000..5dce6b0 --- /dev/null +++ b/src/mainboard/supermicro/x10slm/variants/x10slm-ln4f/devicetree.cb @@ -0,0 +1,141 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2018 Tristan Corrick <tristan(a)corrick.kiwi> +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip northbridge/intel/haswell + + device cpu_cluster 0 on + chip cpu/intel/haswell + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + + device lapic 0 on end + device lapic 0xacac off end + end + end + + device domain 0 on + subsystemid 0x15d9 0x0803 inherit + + device pci 00.0 on end # Host bridge + device pci 01.0 on end # PEG 10 + device pci 01.1 on end # PEG 11 + device pci 02.0 off end # IGD + device pci 03.0 off end # Mini-HD audio + + chip southbridge/intel/lynxpoint + register "pirqa_routing" = "0x8b" + register "pirqb_routing" = "0x8a" + register "pirqc_routing" = "0x8b" + register "pirqd_routing" = "0x8a" + register "pirqe_routing" = "0x80" + register "pirqf_routing" = "0x80" + register "pirqg_routing" = "0x80" + register "pirqh_routing" = "0x85" + + register "sata_ahci" = "1" + register "sata_port_map" = "0x3f" + + register "gen1_dec" = "0x00000295" # Super I/O HWM + + device pci 14.0 on end # xHCI controller + device pci 16.0 on end # Management Engine interface 1 + device pci 16.1 on end # Management Engine interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 off end # Intel Gigabit Ethernet + device pci 1a.0 on end # EHCI controller 2 + device pci 1b.0 off end # HD audio controller + device pci 1c.0 on # PCIe root port 1 + device pci 00.0 on # ASPEED PCI-to-PCI bridge + device pci 00.0 on end # VGA controller + end + end + device pci 1c.1 off end # PCIe root port 2 + device pci 1c.2 on # PCIe root port 3 + device pci 00.0 on # Intel I210 Gigabit Ethernet + subsystemid 0x15d9 0x1533 + end + end + device pci 1c.3 on # PCIe root port 4 + device pci 00.0 on # Intel I210 Gigabit Ethernet + subsystemid 0x15d9 0x1533 + end + end + device pci 1c.4 on end # PCIe root port 5 + device pci 1c.5 off end # PCIe root port 6 + device pci 1c.6 on # PCIe root port 7 + device pci 00.0 on # Intel I210 Gigabit Ethernet + subsystemid 0x15d9 0x1533 + end + end + device pci 1c.7 on # PCIe root port 8 + device pci 00.0 on # Intel I210 Gigabit Ethernet + subsystemid 0x15d9 0x1533 + end + end + device pci 1d.0 on end # EHCI controller 1 + device pci 1f.0 on # LPC bridge + chip superio/nuvoton/nct6776 + device pnp 2e.0 off end # Floppy + device pnp 2e.1 off end # Parallel + device pnp 2e.2 on # UART A + io 0x60 = 0x03f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # UART B + io 0x60 = 0x02f8 + irq 0x70 = 3 + end + device pnp 2e.5 off end # PS/2 KBC + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO8 + device pnp 2e.107 off end # GPIO9 + device pnp 2e.8 off end # WDT + device pnp 2e.108 off end # GPIO0 + device pnp 2e.208 off end # GPIOA + device pnp 2e.308 off end # GPIO base + device pnp 2e.109 off end # GPIO1 + device pnp 2e.209 off end # GPIO2 + device pnp 2e.309 off end # GPIO3 + device pnp 2e.409 off end # GPIO4 + device pnp 2e.509 off end # GPIO5 + device pnp 2e.609 off end # GPIO6 + device pnp 2e.709 off end # GPIO7 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HWM, LED + io 0x60 = 0x0290 + io 0x62 = 0 + irq 0x70 = 0 + end + device pnp 2e.d off end # VID + device pnp 2e.e off end # CIR wake-up + device pnp 2e.f off end # GPIO PP/OD + device pnp 2e.14 off end # SVID + device pnp 2e.16 off end # Deep sleep + device pnp 2e.17 off end # GPIOA + end + end + device pci 1f.2 on end # SATA controller 1 + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA controller 2 + device pci 1f.6 on end # PCH thermal sensor + end + end +end diff --git a/src/mainboard/supermicro/x10slm-f/hda_verb.c b/src/mainboard/supermicro/x10slm/variants/x10slm-ln4f/hda_verb.c similarity index 100% copy from src/mainboard/supermicro/x10slm-f/hda_verb.c copy to src/mainboard/supermicro/x10slm/variants/x10slm-ln4f/hda_verb.c -- To view, visit https://review.coreboot.org/c/coreboot/+/35163 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I686d8d4e2ec5b4eb2db214b6e0827ac9c33829d1 Gerrit-Change-Number: 35163 Gerrit-PatchSet: 1 Gerrit-Owner: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-MessageType: newchange

6 15

Change in coreboot[master]: coreinfo/coreinfo.c: Provide information of time format
by Name of user not set (Code Review) 07 Aug '23

07 Aug '23

Name of user not set #1002476 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35847 ) Change subject: coreinfo/coreinfo.c: Provide information of time format ...................................................................... coreinfo/coreinfo.c: Provide information of time format Specify Coordinated Universal Time (UTC) time format while print date and time in the coreinfo payload. Change-Id: I359cef7697daf5d92d2c9fb58bf75c5b1345e982 Signed-off-by: Sourabh Kashyap <sourabhka(a)hcl.com> --- M payloads/coreinfo/coreinfo.c 1 file changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/35847/1 diff --git a/payloads/coreinfo/coreinfo.c b/payloads/coreinfo/coreinfo.c index 53985b2..ea4d424 100644 --- a/payloads/coreinfo/coreinfo.c +++ b/payloads/coreinfo/coreinfo.c @@ -124,8 +124,10 @@ rtc_read_clock(&tm); - mvwprintw(menuwin, 1, 57, "%02d/%02d/%04d - %02d:%02d:%02d", - tm.tm_mon + 1, tm.tm_mday, 1900 + tm.tm_year, tm.tm_hour, + mvwprintw(menuwin, 1, 53, "%02d/%02d/%04d", tm.tm_mon + 1, + tm.tm_mday, 1900 + tm.tm_year); + mvwprintw(menuwin, 1, 63, " - UTC "); + mvwprintw(menuwin, 1, 70, "%02d:%02d:%02d", tm.tm_hour, tm.tm_min, tm.tm_sec); } #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/35847 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I359cef7697daf5d92d2c9fb58bf75c5b1345e982 Gerrit-Change-Number: 35847 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1002476 Gerrit-MessageType: newchange

4 10

Change in coreboot[master]: soc/intel/(fsp_)baytrail: Initialize SPI before console init
by Arthur Heymans (Code Review) 07 Aug '23

07 Aug '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36407 ) Change subject: soc/intel/(fsp_)baytrail: Initialize SPI before console init ...................................................................... soc/intel/(fsp_)baytrail: Initialize SPI before console init This makes the spi flash console function during romstage. It was tested with the FSP baytrail codepath but it's a safe assumption that the same fix also applies for the google mrc.bin codepath. Tested on Intel Minnowboard Turbot. Change-Id: If6ef0eeea902ab76d398d0218ee943e482f69b43 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/baytrail/romstage/romstage.c M src/soc/intel/fsp_baytrail/romstage/romstage.c 2 files changed, 5 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/36407/1 diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 7c129e2..e06c39e 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -165,10 +165,10 @@ if (CONFIG(ENABLE_BUILTIN_COM1)) byt_config_com1_and_enable(); - console_init(); - spi_init(); + console_init(); + set_max_freq(); punit_init(); diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c index f347591..78aa9fc 100644 --- a/src/soc/intel/fsp_baytrail/romstage/romstage.c +++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c @@ -171,9 +171,11 @@ byt_config_com1_and_enable(); post_code(0x43); - console_init(); spi_init(); + + console_init(); + baytrail_rtc_init(); /* Call into mainboard. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/36407 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6ef0eeea902ab76d398d0218ee943e482f69b43 Gerrit-Change-Number: 36407 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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