Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35490 )
Change subject: drivers/i2c/at24rf08c: Cache devices associated with this driver
......................................................................
drivers/i2c/at24rf08c: Cache devices associated with this driver
To get rid of the fragile dev_find_slot_on_smbus(), we let the
chip driver register the individual devices (EEPROMs) instead.
They will be cached in an global array. So, the implementation
assumes that there is only one instance of this driver but that
should always be the case.
Change-Id: I11eade2cea924839f4b1e1eeee612931fdfd1299
Signed-off-by: Nico Huber <nico.huber(a)secunet.com>
---
M src/drivers/i2c/at24rf08c/at24rf08c.c
M src/drivers/i2c/at24rf08c/lenovo.h
M src/drivers/i2c/at24rf08c/lenovo_serials.c
3 files changed, 42 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/35490/1
diff --git a/src/drivers/i2c/at24rf08c/at24rf08c.c b/src/drivers/i2c/at24rf08c/at24rf08c.c
index 67760a0..7fbae84 100644
--- a/src/drivers/i2c/at24rf08c/at24rf08c.c
+++ b/src/drivers/i2c/at24rf08c/at24rf08c.c
@@ -18,6 +18,7 @@
#include <device/smbus.h>
#include <smbios.h>
#include <console/console.h>
+#include "lenovo.h"
static void at24rf08c_init(struct device *dev)
{
@@ -26,9 +27,14 @@
if (!dev->enabled)
return;
+ if (dev->path.type != DEVICE_PATH_I2C)
+ return;
+
+ lenovo_serials_register_bank(dev);
+
/* Ensure that EEPROM/RFID chip is not accessible through RFID.
Need to do it only on 5c. */
- if (dev->path.type != DEVICE_PATH_I2C || dev->path.i2c.device != 0x5c)
+ if (dev->path.i2c.device != 0x5c)
return;
printk (BIOS_DEBUG, "Locking EEPROM RFID\n");
diff --git a/src/drivers/i2c/at24rf08c/lenovo.h b/src/drivers/i2c/at24rf08c/lenovo.h
index 6824eb6..45d45cc 100644
--- a/src/drivers/i2c/at24rf08c/lenovo.h
+++ b/src/drivers/i2c/at24rf08c/lenovo.h
@@ -1 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef DRIVERS_I2C_AT24RF08C_LENOVO_H
+#define DRIVERS_I2C_AT24RF08C_LENOVO_H
+
+#include <device/device.h>
+
const char *lenovo_mainboard_partnumber(void);
+
+void lenovo_serials_register_bank(struct device *);
+
+#endif /* DRIVERS_I2C_AT24RF08C_LENOVO_H */
diff --git a/src/drivers/i2c/at24rf08c/lenovo_serials.c b/src/drivers/i2c/at24rf08c/lenovo_serials.c
index 0a6b343..584714e 100644
--- a/src/drivers/i2c/at24rf08c/lenovo_serials.c
+++ b/src/drivers/i2c/at24rf08c/lenovo_serials.c
@@ -24,10 +24,20 @@
#define ERROR_STRING "*INVALID*"
+static struct device *banks[4];
+
+void lenovo_serials_register_bank(struct device *const dev)
+{
+ if (0x54 > dev->path.i2c.device || dev->path.i2c.device > 0x57)
+ return;
+ banks[dev->path.i2c.device & 3] = dev;
+}
+
static struct device *at24rf08c_find_bank(u8 bank)
{
- struct device *dev;
- dev = dev_find_slot_on_smbus(1, 0x54 | bank);
+ struct device *const dev = banks[bank];
+ if (bank > ARRAY_SIZE(banks))
+ return NULL;
if (!dev)
printk(BIOS_WARNING, "EEPROM not found\n");
return dev;
@@ -72,7 +82,6 @@
dev = at24rf08c_find_bank(bank);
if (dev == NULL) {
- printk(BIOS_WARNING, "EEPROM not found\n");
memcpy(result, ERROR_STRING, sizeof (ERROR_STRING));
return;
}
@@ -134,9 +143,8 @@
memset(result, 0, sizeof (result));
- dev = dev_find_slot_on_smbus(1, 0x56);
+ dev = at24rf08c_find_bank(2);
if (dev == NULL) {
- printk(BIOS_WARNING, "EEPROM not found\n");
already_read = 1;
memset(uuid, 0, 16);
return;
--
To view, visit https://review.coreboot.org/c/coreboot/+/35490
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I11eade2cea924839f4b1e1eeee612931fdfd1299
Gerrit-Change-Number: 35490
Gerrit-PatchSet: 1
Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>
Gerrit-MessageType: newchange
Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32719
Change subject: drivers/apple: Add hybrid graphics driver
......................................................................
drivers/apple: Add hybrid graphics driver
Hybrid graphics driver for Apple MacBook Pro.
Change-Id: I22b66622cd2da0e9951ee726d650d204fbb8a5bc
Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io>
---
A src/drivers/apple/hybrid_graphics/Kconfig
A src/drivers/apple/hybrid_graphics/Makefile.inc
A src/drivers/apple/hybrid_graphics/chip.h
A src/drivers/apple/hybrid_graphics/gmux.c
A src/drivers/apple/hybrid_graphics/gmux.h
A src/drivers/apple/hybrid_graphics/hybrid_graphics.c
A src/drivers/apple/hybrid_graphics/hybrid_graphics.h
A src/drivers/apple/hybrid_graphics/romstage.c
8 files changed, 417 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/32719/1
diff --git a/src/drivers/apple/hybrid_graphics/Kconfig b/src/drivers/apple/hybrid_graphics/Kconfig
new file mode 100644
index 0000000..252373f
--- /dev/null
+++ b/src/drivers/apple/hybrid_graphics/Kconfig
@@ -0,0 +1,3 @@
+config DRIVERS_APPLE_HYBRID_GRAPHICS
+ bool
+ default n
diff --git a/src/drivers/apple/hybrid_graphics/Makefile.inc b/src/drivers/apple/hybrid_graphics/Makefile.inc
new file mode 100644
index 0000000..ea45b45
--- /dev/null
+++ b/src/drivers/apple/hybrid_graphics/Makefile.inc
@@ -0,0 +1,15 @@
+#
+# This file is part of the coreboot project.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+romstage-$(CONFIG_DRIVERS_APPLE_HYBRID_GRAPHICS) += gmux.c romstage.c
+ramstage-$(CONFIG_DRIVERS_APPLE_HYBRID_GRAPHICS) += gmux.c hybrid_graphics.c
diff --git a/src/drivers/apple/hybrid_graphics/chip.h b/src/drivers/apple/hybrid_graphics/chip.h
new file mode 100644
index 0000000..39434f8
--- /dev/null
+++ b/src/drivers/apple/hybrid_graphics/chip.h
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Evgeny Zinoviev <me(a)ch1p.io>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _APPLE_HYBRID_GRAPHICS_CHIP_H_
+#define _APPLE_HYBRID_GRAPHICS_CHIP_H_
+
+enum hybrid_graphics_req {
+ HYBRID_GRAPHICS_INTEGRATED = 0,
+ HYBRID_GRAPHICS_DISCRETE = 1
+};
+
+#define HYBRID_GRAPHICS_DEFAULT_GPU HYBRID_GRAPHICS_INTEGRATED
+
+struct drivers_apple_hybrid_graphics_config {
+ unsigned int gmux_indexed;
+};
+
+#endif /* _APPLE_HYBRID_GRAPHICS_CHIP_H_ */
diff --git a/src/drivers/apple/hybrid_graphics/gmux.c b/src/drivers/apple/hybrid_graphics/gmux.c
new file mode 100644
index 0000000..e1f763a
--- /dev/null
+++ b/src/drivers/apple/hybrid_graphics/gmux.c
@@ -0,0 +1,158 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) Canonical Ltd. <seth.forshee(a)canonical.com>
+ * Copyright (C) 2010-2012 Andreas Heider <andreas(a)meetr.de>
+ * Copyright (C) 2015 Lukas Wunner <lukas(a)wunner.de>
+ * Copyright (C) 2019 Evgeny Zinoviev <me(a)ch1p.io>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <delay.h>
+#include <arch/io.h>
+#include <device/device.h>
+#include "gmux.h"
+#include "chip.h"
+
+static int gmux_index_wait_ready(void)
+{
+ int i = 200;
+ u8 gwr = inb(GMUX_IOSTART + GMUX_PORT_WRITE);
+
+ while (i && (gwr & 0x01)) {
+ inb(GMUX_IOSTART + GMUX_PORT_READ);
+ gwr = inb(GMUX_IOSTART + GMUX_PORT_WRITE);
+ udelay(100);
+ i--;
+ }
+
+ return !!i;
+}
+
+static int gmux_index_wait_complete(void)
+{
+ int i = 200;
+ u8 gwr = inb(GMUX_IOSTART + GMUX_PORT_WRITE);
+
+ while (i && !(gwr & 0x01)) {
+ gwr = inb(GMUX_IOSTART + GMUX_PORT_WRITE);
+ udelay(100);
+ i--;
+ }
+
+ if (gwr & 0x01)
+ inb(GMUX_IOSTART + GMUX_PORT_READ);
+
+ return !!i;
+}
+
+u8 gmux_pio_read8(int port)
+{
+ return inb(GMUX_IOSTART + port);
+}
+
+u8 gmux_index_read8(int port)
+{
+ u8 val;
+
+ gmux_index_wait_ready();
+ outb((port & 0xff), GMUX_IOSTART + GMUX_PORT_READ);
+ gmux_index_wait_complete();
+ val = inb(GMUX_IOSTART + GMUX_PORT_VALUE);
+
+ return val;
+}
+
+void gmux_pio_write8(int port, u8 val)
+{
+ outb(val, GMUX_IOSTART + port);
+}
+
+
+void gmux_index_write8(int port, u8 val)
+{
+ outb(val, GMUX_IOSTART + GMUX_PORT_VALUE);
+ gmux_index_wait_ready();
+ outb(port & 0xff, GMUX_IOSTART + GMUX_PORT_WRITE);
+ gmux_index_wait_complete();
+}
+
+u32 gmux_pio_read32(int port)
+{
+ return inl(GMUX_IOSTART + port);
+}
+
+u32 gmux_index_read32(int port)
+{
+ u32 val;
+
+ gmux_index_wait_ready();
+ outb((port & 0xff), GMUX_IOSTART + GMUX_PORT_READ);
+ gmux_index_wait_complete();
+ val = inl(GMUX_IOSTART + GMUX_PORT_VALUE);
+
+ return val;
+}
+
+u8 gmux_read8(const struct device *dev, int port)
+{
+ const struct drivers_apple_hybrid_graphics_config *config = dev->chip_info;
+ if (config->gmux_indexed) {
+ return gmux_index_read8(port);
+ } else {
+ return gmux_pio_read8(port);
+ }
+}
+
+void gmux_write8(const struct device *dev, int port, u8 val)
+{
+ const struct drivers_apple_hybrid_graphics_config *config = dev->chip_info;
+ if (config->gmux_indexed) {
+ gmux_index_write8(port, val);
+ } else {
+ gmux_pio_write8(port, val);
+ }
+}
+
+u32 gmux_read32(const struct device *dev, int port)
+{
+ const struct drivers_apple_hybrid_graphics_config *config = dev->chip_info;
+ if (config->gmux_indexed) {
+ return gmux_index_read32(port);
+ } else {
+ return gmux_pio_read32(port);
+ }
+}
+
+void gmux_dgpu_power_enable(const struct device *dev, bool enable)
+{
+ if (enable) {
+ gmux_write8(dev, GMUX_PORT_DISCRETE_POWER, 1);
+ gmux_write8(dev, GMUX_PORT_DISCRETE_POWER, 3);
+ } else {
+ gmux_write8(dev, GMUX_PORT_DISCRETE_POWER, 1);
+ gmux_write8(dev, GMUX_PORT_DISCRETE_POWER, 0);
+ }
+}
+
+void gmux_switch(const struct device *dev, bool dgpu)
+{
+ if (dgpu) {
+ gmux_write8(dev, GMUX_PORT_SWITCH_DDC, 2);
+ gmux_write8(dev, GMUX_PORT_SWITCH_DISPLAY, 3);
+ } else {
+ gmux_write8(dev, GMUX_PORT_SWITCH_DDC, 1);
+ gmux_write8(dev, GMUX_PORT_SWITCH_DISPLAY, 2);
+ }
+}
+
+
diff --git a/src/drivers/apple/hybrid_graphics/gmux.h b/src/drivers/apple/hybrid_graphics/gmux.h
new file mode 100644
index 0000000..18f6722
--- /dev/null
+++ b/src/drivers/apple/hybrid_graphics/gmux.h
@@ -0,0 +1,60 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) Canonical Ltd. <seth.forshee(a)canonical.com>
+ * Copyright (C) 2010-2012 Andreas Heider <andreas(a)meetr.de>
+ * Copyright (C) 2015 Lukas Wunner <lukas(a)wunner.de>
+ * Copyright (C) 2019 Evgeny Zinoviev <me(a)ch1p.io>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef EC_APPLE_GMUX_H
+#define EC_APPLE_GMUX_H
+
+#define GMUX_PORT_VERSION_MAJOR 0x04
+#define GMUX_PORT_VERSION_MINOR 0x05
+#define GMUX_PORT_VERSION_RELEASE 0x06
+
+#define GMUX_PORT_SWITCH_DISPLAY 0x10
+#define GMUX_PORT_SWITCH_DDC 0x28
+#define GMUX_PORT_DISCRETE_POWER 0x50
+#define GMUX_PORT_MAX_BRIGHTNESS 0x70
+#define GMUX_PORT_BRIGHTNESS 0x74
+#define GMUX_PORT_VALUE 0xc2
+#define GMUX_PORT_READ 0xd0
+#define GMUX_PORT_WRITE 0xd4
+
+#define GMUX_PORT_INTERRUPT_ENABLE 0x14
+#define GMUX_INTERRUPT_ENABLE 0xff
+#define GMUX_INTERRUPT_DISABLE 0x00
+
+#define GMUX_BRIGHTNESS_MASK 0x00ffffff
+#define GMUX_MAX_BRIGHTNESS GMUX_BRIGHTNESS_MASK
+
+#define GMUX_IOSTART 0x700
+
+u8 gmux_index_read8(int port);
+u8 gmux_pio_read8(int port);
+u8 gmux_read8(const struct device *dev, int port);
+
+void gmux_index_write8(int port, u8 val);
+void gmux_pio_write8(int port, u8 val);
+void gmux_write8(const struct device *dev, int port, u8 val);
+
+u32 gmux_index_read32(int port);
+u32 gmux_pio_read32(int port);
+u32 gmux_read32(const struct device *dev, int port);
+
+void gmux_switch(const struct device *dev, bool dgpu);
+void gmux_dgpu_power_enable(const struct device *dev, bool enable);
+
+#endif /* EC_APPLE_GMUX_H */
diff --git a/src/drivers/apple/hybrid_graphics/hybrid_graphics.c b/src/drivers/apple/hybrid_graphics/hybrid_graphics.c
new file mode 100644
index 0000000..804eb76
--- /dev/null
+++ b/src/drivers/apple/hybrid_graphics/hybrid_graphics.c
@@ -0,0 +1,64 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Evgeny Zinoviev <me(a)ch1p.io>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <types.h>
+#include <option.h>
+#include <device/device.h>
+
+#include <southbridge/intel/common/gpio.h>
+#include <console/console.h>
+#include "chip.h"
+#include "gmux.h"
+
+static void enable_dev(struct device *dev)
+{
+ printk(BIOS_INFO, "Hybrid graphics enable_dev\n");
+
+ const struct drivers_lenovo_hybrid_graphics_config *config;
+ enum hybrid_graphics_req mode;
+ u8 ver_major, ver_minor, ver_release;
+ u32 version, max_brightness, brightness;
+
+ /* Don't confuse anyone else and disable the fake device */
+ dev->enabled = 0;
+
+ config = dev->chip_info;
+ if (!config) {
+ printk(BIOS_INFO, "Hybrid graphics: Not installed\n");
+ return;
+ }
+
+ version = gmux_index_read32(GMUX_PORT_VERSION_MAJOR);
+ ver_major = (version >> 24) & 0xff;
+ ver_minor = (version >> 16) & 0xff;
+ ver_release = (version >> 8) & 0xff;
+ max_brightness = gmux_index_read32(GMUX_PORT_MAX_BRIGHTNESS);
+ brightness = gmux_index_read32(GMUX_PORT_BRIGHTNESS) & GMUX_BRIGHTNESS_MASK;
+
+ printk(BIOS_INFO, "gmux version: %d.%d.%d\n",
+ ver_major, ver_minor, ver_release);
+ printk(BIOS_INFO, "gmux max brightness: %d\n", max_brightness);
+ printk(BIOS_INFO, "gmux brightness: %d\n", brightness);
+
+ mode = HYBRID_GRAPHICS_DEFAULT_GPU;
+ get_option(&mode, "hybrid_graphics_mode");
+
+ gmux_switch(dev, mode == HYBRID_GRAPHICS_DISCRETE);
+}
+
+struct chip_operations drivers_apple_hybrid_graphics_ops = {
+ CHIP_NAME("Apple hybrid graphics driver")
+ .enable_dev = enable_dev
+};
diff --git a/src/drivers/apple/hybrid_graphics/hybrid_graphics.h b/src/drivers/apple/hybrid_graphics/hybrid_graphics.h
new file mode 100644
index 0000000..782be44
--- /dev/null
+++ b/src/drivers/apple/hybrid_graphics/hybrid_graphics.h
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Evgeny Zinoviev <me(a)ch1p.io>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DRIVERS_APPLE_HYBRID_GRAPHICS_H_
+#define _DRIVERS_APPLE_HYBRID_GRAPHICS_H_
+
+#define HYBRID_GRAPHICS_PORT 0xff
+#define HYBRID_GRAPHICS_DEVICE 0xf
+
+void early_hybrid_graphics(bool *enable_igd, bool *enable_peg);
+
+#endif /* _DRIVERS_APPLE_HYBRID_GRAPHICS_CHIP_H_ */
diff --git a/src/drivers/apple/hybrid_graphics/romstage.c b/src/drivers/apple/hybrid_graphics/romstage.c
new file mode 100644
index 0000000..9cd5098
--- /dev/null
+++ b/src/drivers/apple/hybrid_graphics/romstage.c
@@ -0,0 +1,63 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Patrick Rudolph <siro(a)das-labor.org>
+ * Copyright (C) 2019 Evgeny Zinoviev <me(a)ch1p.io>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <types.h>
+#include <option.h>
+#include <device/device.h>
+#include <console/console.h>
+#include "hybrid_graphics.h"
+#include "chip.h"
+#include "gmux.h"
+
+void early_hybrid_graphics(bool *enable_igd, bool *enable_peg)
+{
+ const struct drivers_apple_hybrid_graphics_config *config;
+ const struct device *dev;
+
+ enum hybrid_graphics_req mode = HYBRID_GRAPHICS_DEFAULT_GPU;
+
+ printk(BIOS_INFO, "Hybrid graphics early_hybrid_graphics\n");
+
+ /* TODO: Use generic device instead of dummy PNP device */
+ dev = dev_find_slot_pnp(HYBRID_GRAPHICS_PORT, HYBRID_GRAPHICS_DEVICE);
+
+ if (!dev || !dev->chip_info) {
+ printk(BIOS_ERR, "Hybrid graphics: ERROR\n");
+ *enable_igd = true;
+ *enable_peg = false;
+ return;
+ }
+
+ config = dev->chip_info;
+
+ get_option(&mode, "hybrid_graphics_mode");
+
+ if (mode == HYBRID_GRAPHICS_DISCRETE) {
+ printk(BIOS_DEBUG, "Hybrid graphics:"
+ " Disabling integrated GPU.\n");
+
+ *enable_igd = false;
+ *enable_peg = true;
+ } else if (mode == HYBRID_GRAPHICS_INTEGRATED) {
+ printk(BIOS_DEBUG, "Hybrid graphics:"
+ " Disabling discrete GPU.\n");
+
+ *enable_igd = true;
+ *enable_peg = false;
+ }
+
+ gmux_dgpu_power_enable(dev, *enable_peg);
+}
--
To view, visit https://review.coreboot.org/c/coreboot/+/32719
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I22b66622cd2da0e9951ee726d650d204fbb8a5bc
Gerrit-Change-Number: 32719
Gerrit-PatchSet: 1
Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.com>
Gerrit-MessageType: newchange
James has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31363
Change subject: mb/gigabyte: add GA-P67A-UD3R
......................................................................
mb/gigabyte: add GA-P67A-UD3R
This is a Intel P67 chipset motherboard for Sandy Bridge processors.
The P67 chipset has no graphics support.
This board has redundant 4MB SOIC-8 flash chips, and flashrom is usable with the
vendor BIOS.
This is an original P67 chipset, and is affected by a SATA 2 hardware bug.
There is a variant P67A-UD3R-B3 that is unaffected.
The function of PCIe ports PCIEX4 and PCIEX1_* are configured in PCHSTRP9.
By default, PCIEX4 is configured for 4 lanes and PCIEX1_* are disabled.
This can be switched to 1 lane for all ports.
Tested and working:
- Intel Core i7 2600
- 4 DIMMs (4x4GB DDR3)
- Booting Linux (SeaBIOS)
- Native RAM init
- PCIe graphics
- Onboard Ethernet
- Sensors (SuperIO)
- S3 sleep
- S4 hibernate
- SATA 3
- USB 2.0
- USB 3.0
- Onboard audio (speakers, headphones)
- CMOS
- EHCI debug port
- Serial port
Not tested:
- SATA 2
- PS/2 keyboard/mouse
- Digital audio
Change-Id: I4fbf50376be3184bf01a3bc8aae09bce54676707
Signed-off-by: James Ye <jye836(a)gmail.com>
---
A src/mainboard/gigabyte/ga-p67a-ud3r/Kconfig
A src/mainboard/gigabyte/ga-p67a-ud3r/Kconfig.name
A src/mainboard/gigabyte/ga-p67a-ud3r/Makefile.inc
A src/mainboard/gigabyte/ga-p67a-ud3r/acpi/ec.asl
A src/mainboard/gigabyte/ga-p67a-ud3r/acpi/mainboard.asl
A src/mainboard/gigabyte/ga-p67a-ud3r/acpi/platform.asl
A src/mainboard/gigabyte/ga-p67a-ud3r/acpi/superio.asl
A src/mainboard/gigabyte/ga-p67a-ud3r/acpi_tables.c
A src/mainboard/gigabyte/ga-p67a-ud3r/board_info.txt
A src/mainboard/gigabyte/ga-p67a-ud3r/cmos.default
A src/mainboard/gigabyte/ga-p67a-ud3r/cmos.layout
A src/mainboard/gigabyte/ga-p67a-ud3r/devicetree.cb
A src/mainboard/gigabyte/ga-p67a-ud3r/dsdt.asl
A src/mainboard/gigabyte/ga-p67a-ud3r/gpio.c
A src/mainboard/gigabyte/ga-p67a-ud3r/hda_verb.c
A src/mainboard/gigabyte/ga-p67a-ud3r/romstage.c
16 files changed, 781 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/31363/1
diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/Kconfig b/src/mainboard/gigabyte/ga-p67a-ud3r/Kconfig
new file mode 100644
index 0000000..c1efe12
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-p67a-ud3r/Kconfig
@@ -0,0 +1,40 @@
+if BOARD_GIGABYTE_GA_P67A_UD3R
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select BOARD_ROMSIZE_KB_4096
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select HAVE_OPTION_TABLE
+ select HAVE_CMOS_DEFAULT
+ select NORTHBRIDGE_INTEL_SANDYBRIDGE
+ select SERIRQ_CONTINUOUS_MODE
+ select SOUTHBRIDGE_INTEL_BD82X6X
+ select USE_NATIVE_RAMINIT
+ select SUPERIO_ITE_IT8728F
+
+config MAINBOARD_DIR
+ string
+ default "gigabyte/ga-p67a-ud3r"
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "GA-P67A-UD3R"
+
+config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+ hex
+ default 0x5001
+
+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+ hex
+ default 0x1458
+
+config MAX_CPUS
+ int
+ default 8
+
+config USBDEBUG_HCD_INDEX
+ int
+ default 2
+
+endif # BOARD_GIGABYTE_GA_P67A_UD3R
diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/Kconfig.name b/src/mainboard/gigabyte/ga-p67a-ud3r/Kconfig.name
new file mode 100644
index 0000000..15f0655
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-p67a-ud3r/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_GIGABYTE_GA_P67A_UD3R
+ bool "GA-P67A-UD3R"
diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/Makefile.inc b/src/mainboard/gigabyte/ga-p67a-ud3r/Makefile.inc
new file mode 100644
index 0000000..3dae61e
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-p67a-ud3r/Makefile.inc
@@ -0,0 +1 @@
+romstage-y += gpio.c
diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/acpi/ec.asl b/src/mainboard/gigabyte/ga-p67a-ud3r/acpi/ec.asl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-p67a-ud3r/acpi/ec.asl
diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/acpi/mainboard.asl b/src/mainboard/gigabyte/ga-p67a-ud3r/acpi/mainboard.asl
new file mode 100644
index 0000000..34de86f
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-p67a-ud3r/acpi/mainboard.asl
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Scope (\_SB)
+{
+ Device (PWRB)
+ {
+ Name (_HID, EisaId("PNP0C0C"))
+ }
+}
diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/acpi/platform.asl b/src/mainboard/gigabyte/ga-p67a-ud3r/acpi/platform.asl
new file mode 100644
index 0000000..d8d3320
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-p67a-ud3r/acpi/platform.asl
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method(_PTS,1)
+{
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method(_WAK,1)
+{
+ Return(Package(){0,0})
+}
diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/acpi/superio.asl b/src/mainboard/gigabyte/ga-p67a-ud3r/acpi/superio.asl
new file mode 100644
index 0000000..2b20c77
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-p67a-ud3r/acpi/superio.asl
@@ -0,0 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 James Ye <jye836(a)gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <drivers/pc80/pc/ps2_controller.asl>
diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/acpi_tables.c b/src/mainboard/gigabyte/ga-p67a-ud3r/acpi_tables.c
new file mode 100644
index 0000000..a2f383b
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-p67a-ud3r/acpi_tables.c
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/bd82x6x/nvs.h>
+
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+ /* Disable USB ports in S3 by default */
+ gnvs->s3u0 = 0;
+ gnvs->s3u1 = 0;
+
+ /* Disable USB ports in S5 by default */
+ gnvs->s5u0 = 0;
+ gnvs->s5u1 = 0;
+}
diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/board_info.txt b/src/mainboard/gigabyte/ga-p67a-ud3r/board_info.txt
new file mode 100644
index 0000000..c6f16ae
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-p67a-ud3r/board_info.txt
@@ -0,0 +1,7 @@
+Category: desktop
+Board URL: https://www.gigabyte.com/Motherboard/GA-P67A-UD3R-rev-10
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
+Release year: 2011
diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/cmos.default b/src/mainboard/gigabyte/ga-p67a-ud3r/cmos.default
new file mode 100644
index 0000000..60de212
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-p67a-ud3r/cmos.default
@@ -0,0 +1,5 @@
+boot_option=Fallback
+debug_level=Debug
+nmi=Enable
+power_on_after_fail=Disable
+sata_mode=AHCI
diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/cmos.layout b/src/mainboard/gigabyte/ga-p67a-ud3r/cmos.layout
new file mode 100644
index 0000000..4e5c0a8
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-p67a-ud3r/cmos.layout
@@ -0,0 +1,107 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+## Copyright (C) 2014 Vladimir Serbinenko
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+# -----------------------------------------------------------------
+entries
+
+# -----------------------------------------------------------------
+# Status Register A
+# -----------------------------------------------------------------
+# Status Register B
+# -----------------------------------------------------------------
+# Status Register C
+#96 4 r 0 status_c_rsvd
+#100 1 r 0 uf_flag
+#101 1 r 0 af_flag
+#102 1 r 0 pf_flag
+#103 1 r 0 irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104 7 r 0 status_d_rsvd
+#111 1 r 0 valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112 8 r 0 diag_rsvd1
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+#120 264 r 0 unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 3 boot_option
+388 4 h 0 reboot_counter
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+#392 3 r 0 unused
+395 4 e 4 debug_level
+#399 1 r 0 unused
+
+#400 8 r 0 reserved for century byte
+
+# coreboot config options: southbridge
+#400 1 e 0 unused
+408 1 e 1 nmi
+409 2 e 5 power_on_after_fail
+411 1 e 6 sata_mode
+
+# coreboot config options: northbridge
+#432 3 r 0 unused
+
+# SandyBridge MRC Scrambler Seed values
+896 32 r 0 mrc_scrambler_seed
+928 32 r 0 mrc_scrambler_seed_s3
+960 16 r 0 mrc_scrambler_seed_chk
+
+# coreboot config options: check sums
+984 16 h 0 check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+
+2 0 Enable
+2 1 Disable
+
+3 0 Fallback
+3 1 Normal
+
+4 0 Emergency
+4 1 Alert
+4 2 Critical
+4 3 Error
+4 4 Warning
+4 5 Notice
+4 6 Info
+4 7 Debug
+4 8 Spew
+
+5 0 Disable
+5 1 Enable
+5 2 Keep
+
+6 0 AHCI
+6 1 Compatible
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 415 984
diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/devicetree.cb b/src/mainboard/gigabyte/ga-p67a-ud3r/devicetree.cb
new file mode 100644
index 0000000..4ed458d
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-p67a-ud3r/devicetree.cb
@@ -0,0 +1,124 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2019 James Ye <jye836(a)gmail.com>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+#
+chip northbridge/intel/sandybridge
+ device cpu_cluster 0x0 on
+ chip cpu/intel/model_206ax
+ device lapic 0x0 on end
+
+ # Magic APIC ID to locate this chip
+ device lapic 0xacac off end
+
+ register "c1_acpower" = "1"
+ register "c2_acpower" = "3"
+ register "c3_acpower" = "5"
+
+ register "c1_battery" = "1"
+ register "c2_battery" = "3"
+ register "c3_battery" = "5"
+ end
+ end
+
+ device domain 0x0 on
+ subsystemid 0x1458 0x5001 inherit
+
+ device pci 00.0 on end # Host bridge
+ device pci 01.0 on # PCIe bridge (PCIEX16)
+ subsystemid 0x1458 0x5000
+ end
+ device pci 02.0 off end # Internal graphics
+
+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+ register "sata_port_map" = "0x3f"
+ register "sata_interface_speed_support" = "0x3"
+
+ register "gen1_dec" = "0x000c0801"
+ register "gen2_dec" = "0x000c0291"
+
+ register "pcie_port_coalesce" = "0"
+ register "c2_latency" = "0x0065"
+ register "p_cnt_throttling_supported" = "1"
+
+ register "spi_lvscc" = "0x2005"
+ register "spi_uvscc" = "0x2005"
+
+ device pci 16.0 off end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT
+ device pci 19.0 off end # Intel Gigabit Ethernet
+ device pci 1a.0 on # USB2 EHCI #2
+ subsystemid 0x1458 0x5006
+ end
+ device pci 1b.0 on # High Definition Audio controller
+ subsystemid 0x1458 0xa102
+ end
+ device pci 1c.0 on end # Unrouted, to disable coalescing
+ device pci 1c.1 on # PCIe Port #2
+ device pci 00.0 on # USB 3.0 controller
+ subsystemid 0x1458 0x5007
+ end
+ end
+ device pci 1c.2 on # PCIe Port #3
+ device pci 00.0 on # Ethernet controller
+ subsystemid 0x1458 0xe000
+ end
+ end
+ device pci 1c.3 on # PCIe Port #4
+ device pci 00.0 on # PCI bridge
+ subsystemid 0x1458 0x5000
+ end
+ end
+ device pci 1c.4 on end # PCIe Port #5 (PCIEX4)
+ device pci 1c.5 off end # PCIe Port #6 (PCIEX1_1)
+ device pci 1c.6 off end # PCIe Port #7 (PCIEX1_2)
+ device pci 1c.7 off end # PCIe Port #8 (PCIEX1_3)
+ device pci 1d.0 on # USB2 EHCI #1
+ subsystemid 0x1458 0x5006
+ end
+ device pci 1e.0 off end # PCI bridge
+ device pci 1f.0 on # LPC bridge
+ chip superio/ite/it8728f
+ device pnp 2e.0 off end # Floppy, not routed
+ device pnp 2e.1 on # COM1
+ io 0x60 = 0x03f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.2 off end # COM2, not routed
+ device pnp 2e.3 off end # Parallel port, not rounted
+ device pnp 2e.4 on # Environment Controller
+ io 0x60 = 0x0290
+ io 0x62 = 0x0
+ irq 0x70 = 0
+ end
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ end
+ device pnp 2e.6 off end # Mouse
+ device pnp 2e.7 off end # GPIO
+ device pnp 2e.a off end # CIR, not routed
+ end
+ end
+ device pci 1f.2 on # SATA Controller 1
+ subsystemid 0x1458 0xb005
+ end
+ device pci 1f.3 on end # SMBus
+ device pci 1f.5 off end # SATA Controller 2
+ device pci 1f.6 off end # Thermal
+ end
+ end
+end
diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/dsdt.asl b/src/mainboard/gigabyte/ga-p67a-ud3r/dsdt.asl
new file mode 100644
index 0000000..365a0fa
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-p67a-ud3r/dsdt.asl
@@ -0,0 +1,45 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 James Ye <jye836(a)gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+DefinitionBlock (
+ "dsdt.aml",
+ "DSDT",
+ 0x02, // DSDT revision: ACPI 2.0 and up
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20141018 // OEM revision
+)
+{
+ // Some generic macros
+ #include "acpi/mainboard.asl"
+ #include "acpi/platform.asl"
+ #include "acpi/superio.asl"
+ #include <cpu/intel/common/acpi/cpu.asl>
+ #include <southbridge/intel/bd82x6x/acpi/platform.asl>
+
+ // Global NVS and variables
+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+
+ // Chipset specific sleep states
+ #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>
+
+ Device (\_SB.PCI0)
+ {
+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+ #include <southbridge/intel/bd82x6x/acpi/pch.asl>
+ }
+}
diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/gpio.c b/src/mainboard/gigabyte/ga-p67a-ud3r/gpio.c
new file mode 100644
index 0000000..c65f432
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-p67a-ud3r/gpio.c
@@ -0,0 +1,204 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ * Copyright (C) 2019 James Ye <jye836(a)gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO,
+ .gpio1 = GPIO_MODE_GPIO,
+ .gpio2 = GPIO_MODE_NATIVE,
+ .gpio3 = GPIO_MODE_NATIVE,
+ .gpio4 = GPIO_MODE_NATIVE,
+ .gpio5 = GPIO_MODE_NATIVE,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio9 = GPIO_MODE_NATIVE,
+ .gpio10 = GPIO_MODE_NATIVE,
+ .gpio11 = GPIO_MODE_GPIO,
+ .gpio12 = GPIO_MODE_GPIO,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_NATIVE,
+ .gpio15 = GPIO_MODE_GPIO,
+ .gpio16 = GPIO_MODE_GPIO,
+ .gpio17 = GPIO_MODE_GPIO,
+ .gpio18 = GPIO_MODE_NATIVE,
+ .gpio19 = GPIO_MODE_GPIO,
+ .gpio20 = GPIO_MODE_NATIVE,
+ .gpio21 = GPIO_MODE_GPIO,
+ .gpio22 = GPIO_MODE_GPIO,
+ .gpio23 = GPIO_MODE_NATIVE,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_NATIVE,
+ .gpio26 = GPIO_MODE_NATIVE,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+ .gpio29 = GPIO_MODE_GPIO,
+ .gpio30 = GPIO_MODE_NATIVE,
+ .gpio31 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_INPUT,
+ .gpio1 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_OUTPUT,
+ .gpio11 = GPIO_DIR_INPUT,
+ .gpio12 = GPIO_DIR_OUTPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio15 = GPIO_DIR_INPUT,
+ .gpio16 = GPIO_DIR_INPUT,
+ .gpio17 = GPIO_DIR_INPUT,
+ .gpio19 = GPIO_DIR_INPUT,
+ .gpio21 = GPIO_DIR_INPUT,
+ .gpio22 = GPIO_DIR_INPUT,
+ .gpio24 = GPIO_DIR_OUTPUT,
+ .gpio27 = GPIO_DIR_INPUT,
+ .gpio28 = GPIO_DIR_OUTPUT,
+ .gpio29 = GPIO_DIR_INPUT,
+ .gpio31 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio8 = GPIO_LEVEL_HIGH,
+ .gpio12 = GPIO_LEVEL_LOW,
+ .gpio24 = GPIO_LEVEL_LOW,
+ .gpio28 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+ .gpio24 = GPIO_RESET_RSMRST,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio11 = GPIO_INVERT,
+ .gpio13 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_GPIO,
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio35 = GPIO_MODE_GPIO,
+ .gpio36 = GPIO_MODE_GPIO,
+ .gpio37 = GPIO_MODE_GPIO,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO,
+ .gpio40 = GPIO_MODE_NATIVE,
+ .gpio41 = GPIO_MODE_NATIVE,
+ .gpio42 = GPIO_MODE_NATIVE,
+ .gpio43 = GPIO_MODE_NATIVE,
+ .gpio44 = GPIO_MODE_NATIVE,
+ .gpio45 = GPIO_MODE_NATIVE,
+ .gpio46 = GPIO_MODE_NATIVE,
+ .gpio47 = GPIO_MODE_GPIO,
+ .gpio48 = GPIO_MODE_GPIO,
+ .gpio49 = GPIO_MODE_GPIO,
+ .gpio50 = GPIO_MODE_NATIVE,
+ .gpio51 = GPIO_MODE_NATIVE,
+ .gpio52 = GPIO_MODE_NATIVE,
+ .gpio53 = GPIO_MODE_NATIVE,
+ .gpio54 = GPIO_MODE_NATIVE,
+ .gpio55 = GPIO_MODE_NATIVE,
+ .gpio56 = GPIO_MODE_NATIVE,
+ .gpio57 = GPIO_MODE_GPIO,
+ .gpio58 = GPIO_MODE_NATIVE,
+ .gpio59 = GPIO_MODE_NATIVE,
+ .gpio60 = GPIO_MODE_NATIVE,
+ .gpio61 = GPIO_MODE_NATIVE,
+ .gpio62 = GPIO_MODE_NATIVE,
+ .gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio32 = GPIO_DIR_OUTPUT,
+ .gpio33 = GPIO_DIR_OUTPUT,
+ .gpio34 = GPIO_DIR_INPUT,
+ .gpio35 = GPIO_DIR_OUTPUT,
+ .gpio36 = GPIO_DIR_INPUT,
+ .gpio37 = GPIO_DIR_INPUT,
+ .gpio38 = GPIO_DIR_INPUT,
+ .gpio39 = GPIO_DIR_INPUT,
+ .gpio47 = GPIO_DIR_INPUT,
+ .gpio48 = GPIO_DIR_INPUT,
+ .gpio49 = GPIO_DIR_INPUT,
+ .gpio57 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio32 = GPIO_LEVEL_LOW,
+ .gpio33 = GPIO_LEVEL_HIGH,
+ .gpio35 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio64 = GPIO_MODE_NATIVE,
+ .gpio65 = GPIO_MODE_NATIVE,
+ .gpio66 = GPIO_MODE_NATIVE,
+ .gpio67 = GPIO_MODE_NATIVE,
+ .gpio68 = GPIO_MODE_GPIO,
+ .gpio69 = GPIO_MODE_GPIO,
+ .gpio70 = GPIO_MODE_NATIVE,
+ .gpio71 = GPIO_MODE_NATIVE,
+ .gpio72 = GPIO_MODE_GPIO,
+ .gpio73 = GPIO_MODE_NATIVE,
+ .gpio74 = GPIO_MODE_NATIVE,
+ .gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio68 = GPIO_DIR_INPUT,
+ .gpio69 = GPIO_DIR_INPUT,
+ .gpio72 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ .reset = &pch_gpio_set3_reset,
+ },
+};
diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/hda_verb.c b/src/mainboard/gigabyte/ga-p67a-ud3r/hda_verb.c
new file mode 100644
index 0000000..a843a2b
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-p67a-ud3r/hda_verb.c
@@ -0,0 +1,74 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ * Copyright (C) 2019 James Ye <jye836(a)gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ 0x10ec0892, /* Codec Vendor / Device ID: Realtek */
+ 0x1458a022, /* Subsystem ID */
+
+ 15, /* Number of 4 dword sets */
+ /* NID 0x01: Subsystem ID. */
+ AZALIA_SUBVENDOR(0x2, 0x1458a022),
+
+ /* NID 0x11. */
+ AZALIA_PIN_CFG(0x2, 0x11, 0x99430140),
+
+ /* NID 0x12. */
+ AZALIA_PIN_CFG(0x2, 0x12, 0x411111f0),
+
+ /* NID 0x14. */
+ AZALIA_PIN_CFG(0x2, 0x14, 0x01014410),
+
+ /* NID 0x15. */
+ AZALIA_PIN_CFG(0x2, 0x15, 0x01011412),
+
+ /* NID 0x16. */
+ AZALIA_PIN_CFG(0x2, 0x16, 0x01016411),
+
+ /* NID 0x17. */
+ AZALIA_PIN_CFG(0x2, 0x17, 0x01012414),
+
+ /* NID 0x18. */
+ AZALIA_PIN_CFG(0x2, 0x18, 0x01a19c50),
+
+ /* NID 0x19. */
+ AZALIA_PIN_CFG(0x2, 0x19, 0x02a19c60),
+
+ /* NID 0x1a. */
+ AZALIA_PIN_CFG(0x2, 0x1a, 0x0181345f),
+
+ /* NID 0x1b. */
+ AZALIA_PIN_CFG(0x2, 0x1b, 0x02214c20),
+
+ /* NID 0x1c. */
+ AZALIA_PIN_CFG(0x2, 0x1c, 0x593301f0),
+
+ /* NID 0x1d. */
+ AZALIA_PIN_CFG(0x2, 0x1d, 0x4005e601),
+
+ /* NID 0x1e. */
+ AZALIA_PIN_CFG(0x2, 0x1e, 0x014b6130),
+
+ /* NID 0x1f. */
+ AZALIA_PIN_CFG(0x2, 0x1f, 0x411111f0),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/romstage.c b/src/mainboard/gigabyte/ga-p67a-ud3r/romstage.c
new file mode 100644
index 0000000..3037b73
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-p67a-ud3r/romstage.c
@@ -0,0 +1,75 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ * Copyright (C) 2019 James Ye <jye836(a)gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <northbridge/intel/sandybridge/raminit_native.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <superio/ite/common/ite.h>
+#include <superio/ite/it8728f/it8728f.h>
+
+#define SUPERIO_BASE 0x2e
+#define SUPERIO_GPIO PNP_DEV(SUPERIO_BASE, IT8728F_GPIO)
+#define SERIAL_DEV PNP_DEV(SUPERIO_BASE, 0x01)
+
+void pch_enable_lpc(void)
+{
+ pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | CNF1_LPC_EN |
+ CNF2_LPC_EN | COMA_LPC_EN);
+}
+
+void mainboard_rcba_config(void)
+{
+}
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+ { 1, 1, 0 },
+ { 1, 1, 0 },
+ { 1, 1, 1 },
+ { 1, 1, 1 },
+ { 1, 6, 2 },
+ { 1, 6, 2 },
+ { 1, 6, 3 },
+ { 1, 5, 3 },
+ { 1, 5, 4 },
+ { 1, 5, 4 },
+ { 1, 5, 5 },
+ { 1, 5, 5 },
+ { 1, 5, 6 },
+ { 1, 5, 6 },
+};
+
+void mainboard_early_init(int s3resume)
+{
+}
+
+void mainboard_config_superio(void)
+{
+ /* Enable serial port */
+ ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+
+ /* Disable SIO WDT which kicks in DualBIOS */
+ ite_reg_write(SUPERIO_GPIO, 0xEF, 0x7E);
+}
+
+void mainboard_get_spd(spd_raw_data *spd, bool id_only)
+{
+ read_spd(&spd[0], 0x50, id_only);
+ read_spd(&spd[1], 0x51, id_only);
+ read_spd(&spd[2], 0x52, id_only);
+ read_spd(&spd[3], 0x53, id_only);
+}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I4fbf50376be3184bf01a3bc8aae09bce54676707
Gerrit-Change-Number: 31363
Gerrit-PatchSet: 1
Gerrit-Owner: James <jye836(a)gmail.com>
Gerrit-MessageType: newchange