coreboot-gerrit September 2013

coreboot-gerrit@coreboot.org

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191 discussions

Patch set updated for coreboot: 35bf7d9 beaglebone: Update bootblock.c to take advantage of the new structs/code.
by Gabe Black 24 Sep '13

24 Sep '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3944 -gerrit commit 35bf7d9caad5a49190abee07e191f149370c0274 Author: Gabe Black <gabeblack(a)chromium.org> Date: Tue Sep 24 01:42:30 2013 -0700 beaglebone: Update bootblock.c to take advantage of the new structs/code. New structures and functions have been added to make it easier and clearer to talk to GPIOs, configure the clock module, and toggle the LEDs. Use that code in bootblock.c instead of doing those things manually with hardcoded addresses. Change-Id: If41db0220de4bc95a6c99945ec402e3026cb4eeb Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/mainboard/ti/beaglebone/bootblock.c | 40 ++++++++++++++++----------------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/src/mainboard/ti/beaglebone/bootblock.c b/src/mainboard/ti/beaglebone/bootblock.c index dd46040..ce7beab 100644 --- a/src/mainboard/ti/beaglebone/bootblock.c +++ b/src/mainboard/ti/beaglebone/bootblock.c @@ -21,48 +21,48 @@ #include <types.h> #include <uart.h> #include <console/console.h> +#include <cpu/ti/am335x/clock.h> +#include <cpu/ti/am335x/gpio.h> #include <cpu/ti/am335x/pinmux.h> +#include "leds.h" + void bootblock_mainboard_init(void); void bootblock_mainboard_init(void) { - void *uart_clock_ctrl = NULL; - - /* Enable the GPIO module */ - writel((0x2 << 0) | (1 << 18), (uint32_t *)(0x44e00000 + 0xac)); - - /* Disable interrupts from these GPIOs */ - setbits_le32((uint32_t *)(0x4804c000 + 0x3c), 0xf << 21); + writel(CM_ST_SW_WKUP | CM_FCLK_EN, &am335x_cm_wkup->wkup_gpio0); + writel(CM_ST_SW_WKUP | CM_FCLK_EN, &am335x_cm_per->gpio1); + writel(CM_ST_SW_WKUP | CM_FCLK_EN, &am335x_cm_per->gpio2); + writel(CM_ST_SW_WKUP | CM_FCLK_EN, &am335x_cm_per->gpio3); - /* Enable output */ - clrbits_le32((uint32_t *)(0x4804c000 + 0x134), 0xf << 21); + am335x_disable_gpio_irqs(); - /* Set every other light */ - clrbits_le32((uint32_t *)(0x4804c000 + 0x13c), 0xf << 21); - setbits_le32((uint32_t *)(0x4804c000 + 0x13c), 0x5 << 21); + beaglebone_leds_init(); + beaglebone_leds_set(BEAGLEBONE_LED_USR0, 1); + beaglebone_leds_set(BEAGLEBONE_LED_USR1, 0); + beaglebone_leds_set(BEAGLEBONE_LED_USR2, 1); + beaglebone_leds_set(BEAGLEBONE_LED_USR3, 0); /* Set up the UART we're going to use */ if (CONFIG_CONSOLE_SERIAL_UART0) { am335x_pinmux_uart0(); - uart_clock_ctrl = (void *)(uintptr_t)(0x44e00400 + 0xb4); + writel(CM_ST_SW_WKUP, &am335x_cm_wkup->wkup_uart0); } else if (CONFIG_CONSOLE_SERIAL_UART1) { am335x_pinmux_uart1(); - uart_clock_ctrl = (void *)(uintptr_t)(0x44e00000 + 0x6c); + writel(CM_ST_SW_WKUP, &am335x_cm_per->uart1); } else if (CONFIG_CONSOLE_SERIAL_UART2) { am335x_pinmux_uart2(); - uart_clock_ctrl = (void *)(uintptr_t)(0x44e00000 + 0x70); + writel(CM_ST_SW_WKUP, &am335x_cm_per->uart2); } else if (CONFIG_CONSOLE_SERIAL_UART3) { am335x_pinmux_uart3(); - uart_clock_ctrl = (void *)(uintptr_t)(0x44e00000 + 0x74); + writel(CM_ST_SW_WKUP, &am335x_cm_per->uart3); } else if (CONFIG_CONSOLE_SERIAL_UART4) { am335x_pinmux_uart4(); - uart_clock_ctrl = (void *)(uintptr_t)(0x44e00000 + 0x78); + writel(CM_ST_SW_WKUP, &am335x_cm_per->uart4); } else if (CONFIG_CONSOLE_SERIAL_UART5) { am335x_pinmux_uart5(); - uart_clock_ctrl = (void *)(uintptr_t)(0x44e00000 + 0x38); + writel(CM_ST_SW_WKUP, &am335x_cm_per->uart5); } - if (uart_clock_ctrl) - writel(0x2, uart_clock_ctrl); /* Start monotonic timer */ //rtc_start();

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New patch to review for coreboot: fb9f814 beaglebone: Update bootblock.c to take advantage of the new structs/code.
by Gabe Black 24 Sep '13

24 Sep '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3944 -gerrit commit fb9f81446b0602915b6e25d078465c7e8ebe9941 Author: Gabe Black <gabeblack(a)chromium.org> Date: Tue Sep 24 01:42:30 2013 -0700 beaglebone: Update bootblock.c to take advantage of the new structs/code. New structures and functions have been added to make it easier and clearer to talk to GPIOs, configure the clock module, and toggle the LEDs. Use that code in bootblock.c instead of doing those things manually with hardcoded addresses. Change-Id: If41db0220de4bc95a6c99945ec402e3026cb4eeb Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/mainboard/ti/beaglebone/bootblock.c | 40 ++++++++++++++++----------------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/src/mainboard/ti/beaglebone/bootblock.c b/src/mainboard/ti/beaglebone/bootblock.c index dd46040..ce7beab 100644 --- a/src/mainboard/ti/beaglebone/bootblock.c +++ b/src/mainboard/ti/beaglebone/bootblock.c @@ -21,48 +21,48 @@ #include <types.h> #include <uart.h> #include <console/console.h> +#include <cpu/ti/am335x/clock.h> +#include <cpu/ti/am335x/gpio.h> #include <cpu/ti/am335x/pinmux.h> +#include "leds.h" + void bootblock_mainboard_init(void); void bootblock_mainboard_init(void) { - void *uart_clock_ctrl = NULL; - - /* Enable the GPIO module */ - writel((0x2 << 0) | (1 << 18), (uint32_t *)(0x44e00000 + 0xac)); - - /* Disable interrupts from these GPIOs */ - setbits_le32((uint32_t *)(0x4804c000 + 0x3c), 0xf << 21); + writel(CM_ST_SW_WKUP | CM_FCLK_EN, &am335x_cm_wkup->wkup_gpio0); + writel(CM_ST_SW_WKUP | CM_FCLK_EN, &am335x_cm_per->gpio1); + writel(CM_ST_SW_WKUP | CM_FCLK_EN, &am335x_cm_per->gpio2); + writel(CM_ST_SW_WKUP | CM_FCLK_EN, &am335x_cm_per->gpio3); - /* Enable output */ - clrbits_le32((uint32_t *)(0x4804c000 + 0x134), 0xf << 21); + am335x_disable_gpio_irqs(); - /* Set every other light */ - clrbits_le32((uint32_t *)(0x4804c000 + 0x13c), 0xf << 21); - setbits_le32((uint32_t *)(0x4804c000 + 0x13c), 0x5 << 21); + beaglebone_leds_init(); + beaglebone_leds_set(BEAGLEBONE_LED_USR0, 1); + beaglebone_leds_set(BEAGLEBONE_LED_USR1, 0); + beaglebone_leds_set(BEAGLEBONE_LED_USR2, 1); + beaglebone_leds_set(BEAGLEBONE_LED_USR3, 0); /* Set up the UART we're going to use */ if (CONFIG_CONSOLE_SERIAL_UART0) { am335x_pinmux_uart0(); - uart_clock_ctrl = (void *)(uintptr_t)(0x44e00400 + 0xb4); + writel(CM_ST_SW_WKUP, &am335x_cm_wkup->wkup_uart0); } else if (CONFIG_CONSOLE_SERIAL_UART1) { am335x_pinmux_uart1(); - uart_clock_ctrl = (void *)(uintptr_t)(0x44e00000 + 0x6c); + writel(CM_ST_SW_WKUP, &am335x_cm_per->uart1); } else if (CONFIG_CONSOLE_SERIAL_UART2) { am335x_pinmux_uart2(); - uart_clock_ctrl = (void *)(uintptr_t)(0x44e00000 + 0x70); + writel(CM_ST_SW_WKUP, &am335x_cm_per->uart2); } else if (CONFIG_CONSOLE_SERIAL_UART3) { am335x_pinmux_uart3(); - uart_clock_ctrl = (void *)(uintptr_t)(0x44e00000 + 0x74); + writel(CM_ST_SW_WKUP, &am335x_cm_per->uart3); } else if (CONFIG_CONSOLE_SERIAL_UART4) { am335x_pinmux_uart4(); - uart_clock_ctrl = (void *)(uintptr_t)(0x44e00000 + 0x78); + writel(CM_ST_SW_WKUP, &am335x_cm_per->uart4); } else if (CONFIG_CONSOLE_SERIAL_UART5) { am335x_pinmux_uart5(); - uart_clock_ctrl = (void *)(uintptr_t)(0x44e00000 + 0x38); + writel(CM_ST_SW_WKUP, &am335x_cm_per->uart5); } - if (uart_clock_ctrl) - writel(0x2, uart_clock_ctrl); /* Start monotonic timer */ //rtc_start();

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New patch to review for coreboot: 9dc55d5 beaglebone: Add code to set the value of the LEDs.
by Gabe Black 24 Sep '13

24 Sep '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3943 -gerrit commit 9dc55d596a92e95c7c00a16595aab33c23b61599 Author: Gabe Black <gabeblack(a)chromium.org> Date: Tue Sep 24 01:40:07 2013 -0700 beaglebone: Add code to set the value of the LEDs. The LEDs on the beaglebone are connected to GPIOs called USR0-USR3. This change adds some functions to make it easy to set their value and clear what the calling code is trying to do. Change-Id: I0bb83bbc2e195ce1a0104afcd120089efaa22916 Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/mainboard/ti/beaglebone/Makefile.inc | 2 ++ src/mainboard/ti/beaglebone/leds.c | 47 ++++++++++++++++++++++++++++++++ src/mainboard/ti/beaglebone/leds.h | 34 +++++++++++++++++++++++ 3 files changed, 83 insertions(+) diff --git a/src/mainboard/ti/beaglebone/Makefile.inc b/src/mainboard/ti/beaglebone/Makefile.inc index c76cb37..fc4051c 100644 --- a/src/mainboard/ti/beaglebone/Makefile.inc +++ b/src/mainboard/ti/beaglebone/Makefile.inc @@ -17,6 +17,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +bootblock-y += leds.c + romstage-y += romstage.c #ramstage-y += ramstage.c diff --git a/src/mainboard/ti/beaglebone/leds.c b/src/mainboard/ti/beaglebone/leds.c new file mode 100644 index 0000000..0e3a1f4 --- /dev/null +++ b/src/mainboard/ti/beaglebone/leds.c @@ -0,0 +1,47 @@ +/* + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <assert.h> +#include <console/console.h> +#include <cpu/ti/am335x/gpio.h> +#include <stdlib.h> + +#include "leds.h" + +static const int led_gpios[BEAGLEBONE_LED_COUNT] = { + [BEAGLEBONE_LED_USR0] = AM335X_GPIO_BITS_PER_BANK + 21, + [BEAGLEBONE_LED_USR1] = AM335X_GPIO_BITS_PER_BANK + 22, + [BEAGLEBONE_LED_USR2] = AM335X_GPIO_BITS_PER_BANK + 23, + [BEAGLEBONE_LED_USR3] = AM335X_GPIO_BITS_PER_BANK + 24 +}; + +void beaglebone_leds_init(void) +{ + int i; + for (i = 0; i < ARRAY_SIZE(led_gpios); i++) + gpio_direction_output(led_gpios[i], 0); +} + +void beaglebone_leds_set(unsigned led, int on) +{ + int res; + ASSERT(led < ARRAY_SIZE(led_gpios) && led_gpios[led]); + res = gpio_set_value(led_gpios[led], on); + ASSERT(res != -1); +} diff --git a/src/mainboard/ti/beaglebone/leds.h b/src/mainboard/ti/beaglebone/leds.h new file mode 100644 index 0000000..f28d50b --- /dev/null +++ b/src/mainboard/ti/beaglebone/leds.h @@ -0,0 +1,34 @@ +/* + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __MAINBOARD_TI_BEAGLEBONE_LEDS_H__ +#define __MAINBOARD_TI_BEAGLEBONE_LEDS_H__ + +enum beaglebone_led { + BEAGLEBONE_LED_USR0, + BEAGLEBONE_LED_USR1, + BEAGLEBONE_LED_USR2, + BEAGLEBONE_LED_USR3, + BEAGLEBONE_LED_COUNT +}; + +void beaglebone_leds_init(void); +void beaglebone_leds_set(enum beaglebone_led, int on); + +#endif /* __MAINBOARD_TI_BEAGLEBONE_LEDS_H__ */

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New patch to review for coreboot: 634dca0 am335x: Add some code for manipulating GPIOs.
by Gabe Black 24 Sep '13

24 Sep '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3942 -gerrit commit 634dca04afb42afca600d859018db8ef7f95dcb3 Author: Gabe Black <gabeblack(a)chromium.org> Date: Tue Sep 24 01:36:08 2013 -0700 am335x: Add some code for manipulating GPIOs. Add code for manipulating the GPIOs on the am335x. The API is patterned after the one used for the Exynos SOCs. Change-Id: I275317304bd0682f348f72f1c77ed5613065af3f Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/ti/am335x/Makefile.inc | 3 +- src/cpu/ti/am335x/gpio.c | 88 ++++++++++++++++++++++++++++++++++++++++++ src/cpu/ti/am335x/gpio.h | 75 +++++++++++++++++++++++++++++++++++ 3 files changed, 165 insertions(+), 1 deletion(-) diff --git a/src/cpu/ti/am335x/Makefile.inc b/src/cpu/ti/am335x/Makefile.inc index ff00733..690b2cf 100644 --- a/src/cpu/ti/am335x/Makefile.inc +++ b/src/cpu/ti/am335x/Makefile.inc @@ -1,5 +1,6 @@ -bootblock-y += dmtimer.c bootblock-y += bootblock_media.c +bootblock-y += dmtimer.c +bootblock-y += gpio.c bootblock-y += pinmux.c bootblock-$(CONFIG_EARLY_CONSOLE) += uart.c diff --git a/src/cpu/ti/am335x/gpio.c b/src/cpu/ti/am335x/gpio.c new file mode 100644 index 0000000..d8264ae --- /dev/null +++ b/src/cpu/ti/am335x/gpio.c @@ -0,0 +1,88 @@ +/* + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <cpu/ti/am335x/gpio.h> +#include <stdint.h> +#include <stdlib.h> + +static struct am335x_gpio_regs *gpio_regs_and_bit(unsigned gpio, uint32_t *bit) +{ + unsigned bank = gpio / AM335X_GPIO_BITS_PER_BANK; + if (bank > ARRAY_SIZE(am335x_gpio_banks)) { + printk(BIOS_ERR, "Bad gpio index %d.\n", gpio); + return NULL; + } + *bit = 1 << (gpio % 32); + return am335x_gpio_banks[bank]; +} + +void am335x_disable_gpio_irqs(void) +{ + int i; + for (i = 0; i < ARRAY_SIZE(am335x_gpio_banks); i++) + writel(0xffffffff, &am335x_gpio_banks[i]->irqstatus_clr_0); +} + +int gpio_direction_input(unsigned gpio) +{ + uint32_t bit; + struct am335x_gpio_regs *regs = gpio_regs_and_bit(gpio, &bit); + if (!regs) + return -1; + setbits_le32(&regs->oe, bit); + return 0; +} + +int gpio_direction_output(unsigned gpio, int value) +{ + uint32_t bit; + struct am335x_gpio_regs *regs = gpio_regs_and_bit(gpio, &bit); + if (!regs) + return -1; + if (value) + writel(bit, &regs->setdataout); + else + writel(bit, &regs->cleardataout); + clrbits_le32(&regs->oe, bit); + return 0; +} + +int gpio_get_value(unsigned gpio) +{ + uint32_t bit; + struct am335x_gpio_regs *regs = gpio_regs_and_bit(gpio, &bit); + if (!regs) + return -1; + return (readl(&regs->datain) & bit) ? 1 : 0; +} + +int gpio_set_value(unsigned gpio, int value) +{ + uint32_t bit; + struct am335x_gpio_regs *regs = gpio_regs_and_bit(gpio, &bit); + if (!regs) + return -1; + if (value) + writel(bit, &regs->setdataout); + else + writel(bit, &regs->cleardataout); + return 0; +} diff --git a/src/cpu/ti/am335x/gpio.h b/src/cpu/ti/am335x/gpio.h new file mode 100644 index 0000000..a828b96 --- /dev/null +++ b/src/cpu/ti/am335x/gpio.h @@ -0,0 +1,75 @@ +/* + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CPU_TI_AM335X_GPIO_H__ +#define __CPU_TI_AM335X_GPIO_H__ + +#include <stdint.h> + +enum { + AM335X_GPIO_BITS_PER_BANK = 32 +}; + +struct am335x_gpio_regs { + uint32_t revision; // 0x0 + uint8_t _rsv0[0xc]; // 0x4-0xf + uint32_t sysconfig; // 0x10 + uint8_t _rsv1[0xc]; // 0x14-0x1f + uint32_t eoi; // 0x20 + uint32_t irqstatus_raw_0; // 0x24 + uint32_t irqstatus_raw_1; // 0x28 + uint32_t irqstatus_0; // 0x2c + uint32_t irqstatus_1; // 0x30 + uint32_t irqstatus_set_0; // 0x34 + uint32_t irqstatus_set_1; // 0x38 + uint32_t irqstatus_clr_0; // 0x3c + uint32_t irqstatus_clk_1; // 0x40 + uint32_t irqwaken_0; // 0x44 + uint32_t irqwaken_1; // 0x48 + uint8_t _rsv2[0xc8]; // 0x4c-0x113 + uint32_t sysstatus; // 0x114 + uint8_t _rsv3[0x18]; // 0x118-0x12f + uint32_t ctrl; // 0x130 + uint32_t oe; // 0x134 + uint32_t datain; // 0x138 + uint32_t dataout; // 0x13c + uint32_t leveldetect0; // 0x140 + uint32_t leveldetect1; // 0x144 + uint32_t risingdetect; // 0x148 + uint32_t fallingdetect; // 0x14c + uint32_t debouncenable; // 0x150 + uint32_t debouncingtime; // 0x154 + uint8_t _rsv4[0x38]; // 0x158-0x18f + uint32_t cleardataout; // 0x190 + uint32_t setdataout; // 0x194 +} __attribute__((packed)); + +static struct am335x_gpio_regs * const am335x_gpio_banks[] = { + (void *)0x44e07000, (void *)0x4804c000, + (void *)0x481ac000, (void *)0x481ae000 +}; + +void am335x_disable_gpio_irqs(void); + +int gpio_direction_input(unsigned gpio); +int gpio_direction_output(unsigned gpio, int value); +int gpio_get_value(unsigned gpio); +int gpio_set_value(unsigned gpio, int value); + +#endif /* __CPU_TI_AM335X_CLOCK_H__ */

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New patch to review for coreboot: ebcc3f5 am335x: Add data structures for the clock module registers.
by Gabe Black 24 Sep '13

24 Sep '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3941 -gerrit commit ebcc3f57a4ff0b307dd0ef7b26b6b32392052707 Author: Gabe Black <gabeblack(a)chromium.org> Date: Tue Sep 24 01:25:02 2013 -0700 am335x: Add data structures for the clock module registers. To avoid having to read/write raw addresses with magic constants, this change adds data structures which represent the clock module registers and some constants for how the clock module is used currently. Change-Id: I955dae39bbdabccf048a086e706a48c58f620ad4 Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/ti/am335x/clock.h | 239 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 239 insertions(+) diff --git a/src/cpu/ti/am335x/clock.h b/src/cpu/ti/am335x/clock.h new file mode 100644 index 0000000..7af53c4 --- /dev/null +++ b/src/cpu/ti/am335x/clock.h @@ -0,0 +1,239 @@ +/* + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CPU_TI_AM335X_CLOCK_H__ +#define __CPU_TI_AM335X_CLOCK_H__ + +#include <stdint.h> + +enum { + CM_ST_NO_SLEEP = 0x0, + CM_ST_SW_SLEEP = 0x1, + CM_ST_SW_WKUP = 0x2 +}; + +enum { + CM_MODULEMODE_DISABLED = 0x0, + CM_MODULEMODE_ENABLED = 0x2 +}; + +enum { + CM_FCLK_DIS = 0x0 << 18, + CM_FCLK_EN = 0x1 << 18 +}; + +/* Clock module peripheral registers */ +struct am335x_cm_per_regs { + uint32_t l4ls_st; // 0x0 + uint32_t l3s_st; // 0x4 + uint8_t _rsv0[4]; // 0x8-0xb + uint32_t l3_st; // 0xc + uint8_t _rsv1[4]; // 0x10-0x13 + uint32_t cpgmac0; // 0x14 + uint32_t lcdc; // 0x18 + uint32_t usb0; // 0x1c + uint8_t _rsv2[4]; // 0x20-0x23 + uint32_t tptc0; // 0x24 + uint32_t emif; // 0x28 + uint32_t ocmcram; // 0x2c + uint32_t gpmc; // 0x30 + uint32_t mcasp0; // 0x34 + uint32_t uart5; // 0x38 + uint32_t mmc0; // 0x3c + uint32_t elm; // 0x40 + uint32_t i2c2; // 0x44 + uint32_t i2c1; // 0x48 + uint32_t spi0; // 0x4c + uint32_t spi1; // 0x50 + uint8_t _rsv3[0xc]; // 0x54-0x5f + uint32_t l4ls; // 0x60 + uint8_t _rsv4[4]; // 0x64-0x67 + uint32_t mcasp1; // 0x68 + uint32_t uart1; // 0x6c + uint32_t uart2; // 0x70 + uint32_t uart3; // 0x74 + uint32_t uart4; // 0x78 + uint32_t timer7; // 0x7c + uint32_t timer2; // 0x80 + uint32_t timer3; // 0x84 + uint32_t timer4; // 0x88 + uint8_t _rsv5[0x20]; // 0x90-0xab + uint32_t gpio1; // 0xac + uint32_t gpio2; // 0xb0 + uint32_t gpio3; // 0xb4 + uint8_t _rsv6[4]; // 0xb8-0xbb + uint32_t tpcc; // 0xbc + uint32_t dcan0; // 0xc0 + uint32_t dcan1; // 0xc4 + uint8_t _rsv7[4]; // 0xc8-0xcb + uint32_t epwmss1; // 0xcc + uint8_t _rsv8[4]; // 0xd0-0xd3 + uint32_t epwmss0; // 0xd4 + uint32_t epwmss2; // 0xd8 + uint32_t l3_instr; // 0xdc + uint32_t l3; // 0xe0 + uint32_t ieee5000; // 0xe4 + uint32_t pru_icss; // 0xe8 + uint32_t timer5; // 0xec + uint32_t timer6; // 0xf0 + uint32_t mmc1; // 0xf4 + uint32_t mmc2; // 0xf8 + uint32_t tptc1; // 0xfc + uint32_t tptc2; // 0x100 + uint8_t _rsv9[8]; // 0x104-0x10b + uint32_t spinlock; // 0x10c + uint32_t mailbox0; // 0x110 + uint8_t _rsv10[8]; // 0x114-0x11b + uint32_t l4hs_st; // 0x11c + uint32_t l4hs; // 0x120 + uint8_t _rsv11[8]; // 0x124-0x12b + uint32_t ocpwp_l3_st; // 0x12c + uint32_t ocpwp; // 0x130 + uint8_t _rsv12[0xb]; // 0x134-0x13f + uint32_t pru_icss_st; // 0x140 + uint32_t cpsw_st; // 0x144 + uint32_t lcdc_st; // 0x148 + uint32_t clkdiv32k; // 0x14c + uint32_t clk_24mhz_st; // 0x150 +} __attribute__((packed)); +static struct am335x_cm_per_regs * const am335x_cm_per = (void *)0x44e00000; + +/* Clock module wakeup registers */ +struct am335x_cm_wkup_regs { + uint32_t wkup_st; // 0x0 + uint32_t wkup_control; // 0x4 + uint32_t wkup_gpio0; // 0x8 + uint32_t wkup_l4wkup; // 0xc + uint32_t wkup_timer0; // 0x10 + uint32_t wkup_debugss; // 0x14 + uint32_t l3_aon_st; // 0x18 + uint32_t autoidle_dpll_mpu; // 0x1c + uint32_t idlest_dpll_mpu; // 0x20 + uint32_t ssc_deltamstep_dpll_mpu; // 0x24 + uint32_t ssc_modfreqdiv_dpll_mpu; // 0x28 + uint32_t clksel_dpll_mpu; // 0x2c + uint32_t autoidle_dpll_ddr; // 0x30 + uint32_t idlest_dpll_ddr; // 0x34 + uint32_t ssc_deltamstep_dpll_ddr; // 0x38 + uint32_t ssc_modfreqdiv_dpll_ddr; // 0x3c + uint32_t clksel_dpll_ddr; // 0x40 + uint32_t autoidle_dpll_disp; // 0x44 + uint32_t idlest_dpll_disp; // 0x48 + uint32_t ssc_deltamstep_dpll_disp; // 0x4c + uint32_t ssc_modfreqdiv_dpll_disp; // 0x50 + uint32_t clksel_dpll_disp; // 0x54 + uint32_t autoidle_dpll_core; // 0x58 + uint32_t idlest_dpll_core; // 0x5c + uint32_t ssc_deltamstep_dpll_core; // 0x60 + uint32_t ssc_modfreqdiv_dpll_core; // 0x64 + uint32_t clksel_dpll_core; // 0x68 + uint32_t autoidle_dpll_per; // 0x6c + uint32_t idlest_dpll_per; // 0x70 + uint32_t ssc_deltamstep_dpll_per; // 0x74 + uint32_t ssc_modfreqdiv_dpll_per; // 0x78 + uint32_t clkdcoldo_dpll_per; // 0x7c + uint32_t div_m4_dpll_core; // 0x80 + uint32_t div_m5_dpll_core; // 0x84 + uint32_t clkmode_dpll_mpu; // 0x88 + uint32_t clkmode_dpll_per; // 0x8c + uint32_t clkmode_dpll_core; // 0x90 + uint32_t clkmode_dpll_ddr; // 0x94 + uint32_t clkmode_dpll_disp; // 0x98 + uint32_t clksel_dpll_periph; // 0x9c + uint32_t div_m2_dpll_ddr; // 0xa0 + uint32_t div_m2_dpll_disp; // 0xa4 + uint32_t div_m2_dpll_mpu; // 0xa8 + uint32_t div_m2_dpll_per; // 0xac + uint32_t wkup_wkup_m3; // 0xb0 + uint32_t wkup_uart0; // 0xb4 + uint32_t wkup_i2c0; // 0xb8 + uint32_t wkup_adc_tsc; // 0xbc + uint32_t wkup_smartreflex0; // 0xc0 + uint32_t wkup_timer1; // 0xc4 + uint32_t wkup_smartreflex1; // 0xc8 + uint32_t l4_wkup_aon_st; // 0xcc + uint8_t _rsv0[4]; // 0xd0-0xd3 + uint32_t wkup_wdt1; // 0xd4 + uint32_t div_m6_dpll_core; // 0xd8 +} __attribute__((packed)); +static struct am335x_cm_wkup_regs * const am335x_cm_wkup = (void *)0x44e00400; + +/* Clock module pll registers */ +struct am335x_cm_dpll_regs { + uint8_t _rsv0[4]; // 0x0-0x3 + uint32_t clksel_timer7_clk; // 0x4 + uint32_t clksel_timer2_clk; // 0x8 + uint32_t clksel_timer3_clk; // 0xc + uint32_t clksel_timer4_clk; // 0x10 + uint32_t cm_mac_clksel; // 0x14 + uint32_t clksel_timer5_clk; // 0x18 + uint32_t clksel_timer6_clk; // 0x1c + uint32_t cm_cpts_rft_Clksel; // 0x20 + uint8_t _rsv1[4]; // 0x24-0x27 + uint32_t clksel_timer1ms_clk; // 0x28 + uint32_t clksel_gfx_fclk; // 0x2c + uint32_t clksel_pru_icss_ocp_clk; // 0x30 + uint32_t clksel_lcdc_pixel_clk; // 0x34 + uint32_t clksel_wdt1_clk; // 0x38 + uint32_t clksel_gpio0_dbclk; // 0x3c +} __attribute__((packed)); +static struct am335x_cm_dpll_regs * const am335x_cm_dpll = (void *)0x44e00500; + +/* Clock module mpu registers */ +struct am335x_cm_mpu_regs { + uint32_t st; // 0x0 + uint32_t mpu; // 0x4 +} __attribute__((packed)); +static struct am335x_cm_mpu_regs * const am335x_cm_mpu = (void *)0x44e00600; + +/* Clock module device registers */ +struct am335x_cm_device_regs { + uint32_t cm_clkout_ctrl; // 0x0 +} __attribute__((packed)); +static struct am335x_cm_device_regs * const am335x_cm_device = + (void *)0x44e00700; + +/* Clock module RTC registers */ +struct am335x_cm_rtc_regs { + uint32_t rtc; // 0x0 + uint32_t st; // 0x4 +} __attribute__((packed)); +static struct am335x_cm_rtc_regs * const am335x_cm_rtc = (void *)0x44e00800; + +/* Clock module graphics controller registers */ +struct am335x_cm_gfx_regs { + uint32_t l3_st; // 0x0 + uint32_t gfx; // 0x4 + uint8_t _rsv0[4]; // 0x8-0xb + uint32_t l4ls_gfx_st; // 0xc + uint32_t mmucfg; // 0x10 + uint32_t mmudata; // 0x14 +} __attribute__((packed)); +static struct am335x_cm_gfx_regs * const am335x_cm_gfx = (void *)0x44e00900; + +/* Clock module efuse registers */ +struct am335x_cm_cefuse_regs { + uint32_t st; // 0x0 + uint8_t _rsv0[0x1c]; // 0x4-0x1f + uint32_t cefuse; // 0x20 +} __attribute__((packed)); +static struct am335x_cm_cefuse_regs * const am335x_cm_cefuse = + (void *)0x44e00a00; + +#endif /* __CPU_TI_AM335X_CLOCK_H__ */

1 0

Patch set updated for coreboot: 2605d98 AMD Olive Hill: Disable NoSnoopEnable to fix HDMI audio corruptions with Ubuntu
by Siyuan Wang 24 Sep '13

24 Sep '13

Siyuan Wang (wangsiyuanbuaa(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3934 -gerrit commit 2605d98575e1e90ac4b2797bc90ec9adffceab4a Author: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Date: Sun Sep 22 15:20:37 2013 +0800 AMD Olive Hill: Disable NoSnoopEnable to fix HDMI audio corruptions with Ubuntu Ubuntu's HDMI audio has noise and echo. Disable NoSnoopEnable can resolve this issue. I have tested on Ubuntu 13.04 with AMD Catalyst 13.4 Proprietary Linux Display Driver[1]. [1]. http://support.amd.com/us/gpudownload/linux/Pages/radeon_linux.aspx Change-Id: I5d2dddb1b7469d56cd64e3c1e0f4c6c6f095b4ab Signed-off-by: WANG Siyuan <SiYuan.Wang(a)amd.com> Signed-off-by: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> --- src/mainboard/amd/olivehill/get_bus_conf.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/mainboard/amd/olivehill/get_bus_conf.c b/src/mainboard/amd/olivehill/get_bus_conf.c index 0d379d5..892471a 100644 --- a/src/mainboard/amd/olivehill/get_bus_conf.c +++ b/src/mainboard/amd/olivehill/get_bus_conf.c @@ -54,6 +54,7 @@ void get_bus_conf(void) { u32 apicid_base; u32 status; + u32 value; device_t dev; int i, j; @@ -98,6 +99,12 @@ void get_bus_conf(void) pci_write_config32(dev, 0xF8, 0); pci_write_config32(dev, 0xFC, 5); /* TODO: move it to dsdt.asl */ + /* disable No Snoop */ + dev = dev_find_slot(0, PCI_DEVFN(1, 1)); + value = pci_read_config32(dev, 0x60); + value &= ~(1 << 11); + pci_write_config32(dev, 0x60, value); + sbdn_yangtze = 0; for (i = 0; i < 3; i++) {

1 0

Patch set updated for coreboot: 774bb81 AMD Olive Hill: Disable NoSnoopEnable to fix HDMI audio corruptions with Ubuntu
by Siyuan Wang 24 Sep '13

24 Sep '13

Siyuan Wang (wangsiyuanbuaa(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3934 -gerrit commit 774bb8197beb08dbf9eb0ada49ee035956c567d2 Author: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Date: Sun Sep 22 15:20:37 2013 +0800 AMD Olive Hill: Disable NoSnoopEnable to fix HDMI audio corruptions with Ubuntu Ubuntu's HDMI audio has noise and echo. Disable NoSnoopEnable can resolve this issue. I have tested on Ubuntu 13.04 with AMD Catalyst 13.4 Proprietary Linux Display Driver. Change-Id: I5d2dddb1b7469d56cd64e3c1e0f4c6c6f095b4ab Signed-off-by: WANG Siyuan <SiYuan.Wang(a)amd.com> Signed-off-by: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> --- src/mainboard/amd/olivehill/get_bus_conf.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/mainboard/amd/olivehill/get_bus_conf.c b/src/mainboard/amd/olivehill/get_bus_conf.c index 0d379d5..892471a 100644 --- a/src/mainboard/amd/olivehill/get_bus_conf.c +++ b/src/mainboard/amd/olivehill/get_bus_conf.c @@ -54,6 +54,7 @@ void get_bus_conf(void) { u32 apicid_base; u32 status; + u32 value; device_t dev; int i, j; @@ -98,6 +99,12 @@ void get_bus_conf(void) pci_write_config32(dev, 0xF8, 0); pci_write_config32(dev, 0xFC, 5); /* TODO: move it to dsdt.asl */ + /* disable No Snoop */ + dev = dev_find_slot(0, PCI_DEVFN(1, 1)); + value = pci_read_config32(dev, 0x60); + value &= ~(1 << 11); + pci_write_config32(dev, 0x60, value); + sbdn_yangtze = 0; for (i = 0; i < 3; i++) {

1 0

Patch merged into coreboot/master: dd6c4ec libpayload: Remove unnecessary keyboard mode setting code
by gerrit＠coreboot.org 24 Sep '13

24 Sep '13

the following patch was just integrated into master: commit dd6c4ec1ed64f3d9803cca6eb53fa5049cacdd09 Author: Shawn Nematbakhsh <shawnn(a)chromium.org> Date: Fri Aug 23 14:12:24 2013 -0700 libpayload: Remove unnecessary keyboard mode setting code keyboard_init attempts to read the existing mode register, set the 'XLATE' bit, and write it back. The implementation is buggy because the keyboard may be active at the time we read the mode, and we can misinterpret scancode data as the reply to our command. It leads to problems where the KB gets disabled in firmware. In fact, setting the 'XLATE' bit is completely unnecessary, even if we desire QEMU keyboard support. We already set this bit when we initialize the keyboard in pc_keyboard_init. Basically, this code does nothing (or worse), so just remove it. Change-Id: Iab23f03fa8bced74842c33a7d263de5f449bb983 Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Reviewed-on: http://review.coreboot.org/3883 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/3883 for details. -gerrit

1 0

Patch merged into coreboot/master: 5a7e127 southbridge/cimx/sb900: Rename headers to match sb700 & sb800
by gerrit＠coreboot.org 24 Sep '13

24 Sep '13

the following patch was just integrated into master: commit 5a7e127cd429b101814cae0a1ca3fb5de912777c Author: Corey Osgood <corey.osgood(a)gmail.com> Date: Sun Jul 28 05:36:45 2013 -0400 southbridge/cimx/sb900: Rename headers to match sb700 & sb800 Northbridge code includes these headers, so they all need to have the same name to allow different combinations of northbridge and southbridge. This changes the sb900 names to match sb700 & sb800, and points agesa/family12 and amd/torpedo to the new file names. Change-Id: I7a654ce9ae591a636a56177f64fb8cb953b4b04f Signed-off-by: Corey Osgood <corey.osgood(a)gmail.com> Reviewed-on: http://review.coreboot.org/3825 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/3825 for details. -gerrit

1 0

New patch to review for coreboot: d74affb Make CACHE_AS_RAM independent of arch
by Kyösti Mälkki 24 Sep '13

24 Sep '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3940 -gerrit commit d74affb6ab319b99bf662caaf45f3cbd48b6d2f7 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Sep 24 01:35:24 2013 +0300 Make CACHE_AS_RAM independent of arch This generally controls existence of global variables in romstage. Change-Id: I22b8f7c61dfa67c971a8f00e867845738608deae Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/armv7/Makefile.inc | 2 + src/arch/armv7/cbmem.c | 27 ++++++++++++ src/arch/armv7/romstage.ld | 17 +++++++ src/arch/armv7/tables.c | 7 --- src/cpu/Kconfig | 8 ++-- src/cpu/x86/Makefile.inc | 1 - src/cpu/x86/car.c | 105 -------------------------------------------- src/lib/Makefile.inc | 1 + src/lib/car.c | 105 ++++++++++++++++++++++++++++++++++++++++++++ 9 files changed, 156 insertions(+), 117 deletions(-) diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc index 4b1c591..4a2ccc3 100644 --- a/src/arch/armv7/Makefile.inc +++ b/src/arch/armv7/Makefile.inc @@ -167,12 +167,14 @@ bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += early_console.c bootblock-y += cache.c romstage-y += cache.c +romstage-y += cbmem.c romstage-y += div0.c romstage-$(CONFIG_EARLY_CONSOLE) += early_console.c ramstage-y += div0.c #ramstage-y += interrupts.c ramstage-y += cache.c +ramstage-y += cbmem.c ramstage-y += mmu.c romstage-y += eabi_compat.c diff --git a/src/arch/armv7/cbmem.c b/src/arch/armv7/cbmem.c new file mode 100644 index 0000000..979bc7c --- /dev/null +++ b/src/arch/armv7/cbmem.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + +#include <console/console.h> +#include <cbmem.h> + +void __attribute__((weak)) get_cbmem_table(uint64_t *base, uint64_t *size) +{ + printk(BIOS_WARNING, "WARNING: you need to define get_cbmem_table for your board\n"); + *base = 0; + *size = 0; +} + diff --git a/src/arch/armv7/romstage.ld b/src/arch/armv7/romstage.ld index 0555fc4..26c24e8 100644 --- a/src/arch/armv7/romstage.ld +++ b/src/arch/armv7/romstage.ld @@ -53,6 +53,10 @@ SECTIONS *(.machine_param); *(.data); . = ALIGN(8); + _car_migrate_start = .; + *(.car.migrate); + _car_migrate_end = .; + . = ALIGN(8); _erom = .; } @@ -69,6 +73,19 @@ SECTIONS *(.sbss) *(COMMON) } + + .car.data . (NOLOAD) : { + _car_data_start = .; + *(.car.global_data); + /* The cbmem_console section comes last to take advantage of + * a zero-sized array to hold the memconsole contents that + * grows to a bound of CONFIG_CONSOLE_CAR_BUFFER_SIZE. However, + * collisions within the cache-as-ram region cannot be + * statically checked because the cache-as-ram region usage is + * cpu/chipset dependent. */ + *(.car.cbmem_console); + _car_data_end = .; + } _ebss = .; _end = .; diff --git a/src/arch/armv7/tables.c b/src/arch/armv7/tables.c index b566ff6..de6b6fa 100644 --- a/src/arch/armv7/tables.c +++ b/src/arch/armv7/tables.c @@ -29,13 +29,6 @@ #define MAX_COREBOOT_TABLE_SIZE (8 * 1024) -void __attribute__((weak)) get_cbmem_table(uint64_t *base, uint64_t *size) -{ - printk(BIOS_WARNING, "WARNING: you need to define get_cbmem_table for your board\n"); - *base = 0; - *size = 0; -} - void cbmem_arch_init(void) { } diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index e48fe87..fa0a858 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -18,10 +18,6 @@ source src/cpu/via/Kconfig source src/cpu/qemu-x86/Kconfig source src/cpu/x86/Kconfig -config CACHE_AS_RAM - bool - default !ROMCC - config DCACHE_RAM_BASE hex @@ -73,6 +69,10 @@ config SSE2 endif # ARCH_X86 +config CACHE_AS_RAM + bool + default !ROMCC + config CPU_MICROCODE_IN_CBFS bool default n diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc index 311dcc1..e69de29 100644 --- a/src/cpu/x86/Makefile.inc +++ b/src/cpu/x86/Makefile.inc @@ -1 +0,0 @@ -romstage-$(CONFIG_CACHE_AS_RAM) += car.c diff --git a/src/cpu/x86/car.c b/src/cpu/x86/car.c deleted file mode 100644 index 481153d..0000000 --- a/src/cpu/x86/car.c +++ /dev/null @@ -1,105 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <string.h> -#include <stddef.h> -#include <console/console.h> -#include <cbmem.h> -#include <arch/early_variables.h> - -typedef void (* const car_migration_func_t)(void); - -extern car_migration_func_t _car_migrate_start; -extern car_migration_func_t _car_migrate_end; - -extern char _car_data_start[]; -extern char _car_data_end[]; - -/* - * The car_migrated global variable determines if the cache-as-ram space has - * been migrated to real RAM. It does this by assuming the following things: - * 1. cache-as-ram space is zero'd out once it is set up. - * 2. Either the cache-as-ram space is memory-backed after getting torn down - * or the space returns 0xff's for each byte read. - * Based on these 2 attributes there is the ability to tell when the - * cache-as-ram region has been migrated. - */ -static int car_migrated CAR_GLOBAL; - - -void *car_get_var_ptr(void *var) -{ - char *migrated_base; - int offset; - void * _car_start = &_car_data_start; - void * _car_end = &_car_data_end; - - /* If the cache-as-ram has not been migrated return the pointer - * passed in. */ - if (!car_migrated) - return var; - - if (var < _car_start || var >= _car_end) { - printk(BIOS_ERR, - "Requesting CAR variable outside of CAR region: %p\n", - var); - return var; - } - - migrated_base = cbmem_find(CBMEM_ID_CAR_GLOBALS); - - if (migrated_base == NULL) { - printk(BIOS_ERR, "CAR: Could not find migration base!\n"); - return var; - } - - offset = (char *)var - (char *)_car_start; - - return &migrated_base[offset]; -} - -void car_migrate_variables(void) -{ - void *migrated_base; - car_migration_func_t *migrate_func; - size_t car_data_size = &_car_data_end[0] - &_car_data_start[0]; - - /* Check if already migrated. */ - if (car_migrated) - return; - - migrated_base = cbmem_add(CBMEM_ID_CAR_GLOBALS, car_data_size); - - if (migrated_base == NULL) { - printk(BIOS_ERR, "Could not migrate CAR data!\n"); - return; - } - - memcpy(migrated_base, &_car_data_start[0], car_data_size); - - /* Mark that the data has been moved. */ - car_migrated = ~0; - - /* Call all the migration functions. */ - migrate_func = &_car_migrate_start; - while (migrate_func != &_car_migrate_end) { - (*migrate_func)(); - migrate_func++; - } -} diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 1455e4c..3e11896 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -111,6 +111,7 @@ ramstage-y += cbmem.c romstage-$(CONFIG_CACHE_AS_RAM) += cbmem.c endif # CONFIG_DYNAMIC_CBMEM ramstage-y += cbmem_info.c +romstage-$(CONFIG_CACHE_AS_RAM) += car.c ramstage-$(CONFIG_CONSOLE_NE2K) += ne2k.c diff --git a/src/lib/car.c b/src/lib/car.c new file mode 100644 index 0000000..481153d --- /dev/null +++ b/src/lib/car.c @@ -0,0 +1,105 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <string.h> +#include <stddef.h> +#include <console/console.h> +#include <cbmem.h> +#include <arch/early_variables.h> + +typedef void (* const car_migration_func_t)(void); + +extern car_migration_func_t _car_migrate_start; +extern car_migration_func_t _car_migrate_end; + +extern char _car_data_start[]; +extern char _car_data_end[]; + +/* + * The car_migrated global variable determines if the cache-as-ram space has + * been migrated to real RAM. It does this by assuming the following things: + * 1. cache-as-ram space is zero'd out once it is set up. + * 2. Either the cache-as-ram space is memory-backed after getting torn down + * or the space returns 0xff's for each byte read. + * Based on these 2 attributes there is the ability to tell when the + * cache-as-ram region has been migrated. + */ +static int car_migrated CAR_GLOBAL; + + +void *car_get_var_ptr(void *var) +{ + char *migrated_base; + int offset; + void * _car_start = &_car_data_start; + void * _car_end = &_car_data_end; + + /* If the cache-as-ram has not been migrated return the pointer + * passed in. */ + if (!car_migrated) + return var; + + if (var < _car_start || var >= _car_end) { + printk(BIOS_ERR, + "Requesting CAR variable outside of CAR region: %p\n", + var); + return var; + } + + migrated_base = cbmem_find(CBMEM_ID_CAR_GLOBALS); + + if (migrated_base == NULL) { + printk(BIOS_ERR, "CAR: Could not find migration base!\n"); + return var; + } + + offset = (char *)var - (char *)_car_start; + + return &migrated_base[offset]; +} + +void car_migrate_variables(void) +{ + void *migrated_base; + car_migration_func_t *migrate_func; + size_t car_data_size = &_car_data_end[0] - &_car_data_start[0]; + + /* Check if already migrated. */ + if (car_migrated) + return; + + migrated_base = cbmem_add(CBMEM_ID_CAR_GLOBALS, car_data_size); + + if (migrated_base == NULL) { + printk(BIOS_ERR, "Could not migrate CAR data!\n"); + return; + } + + memcpy(migrated_base, &_car_data_start[0], car_data_size); + + /* Mark that the data has been moved. */ + car_migrated = ~0; + + /* Call all the migration functions. */ + migrate_func = &_car_migrate_start; + while (migrate_func != &_car_migrate_end) { + (*migrate_func)(); + migrate_func++; + } +}

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coreboot-gerrit September 2013