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Change in ...coreboot[master]: mainboard/samsung/350v5c: add initial board files
by Kacper Słomiński (Code Review) 08 Jun '24

08 Jun '24

Kacper Słomiński has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30942 Change subject: mainboard/samsung/350v5c: add initial board files ...................................................................... mainboard/samsung/350v5c: add initial board files Signed-off-by: Kacper Słomiński <kacper.slominski72(a)gmail.com> Change-Id: I64fcf931938fb3b158b9576b787f452bf6077843 --- A src/mainboard/samsung/350v5c/Kconfig A src/mainboard/samsung/350v5c/Kconfig.name A src/mainboard/samsung/350v5c/Makefile.inc A src/mainboard/samsung/350v5c/acpi/ec.asl A src/mainboard/samsung/350v5c/acpi/platform.asl A src/mainboard/samsung/350v5c/acpi/superio.asl A src/mainboard/samsung/350v5c/acpi_tables.c A src/mainboard/samsung/350v5c/board_info.txt A src/mainboard/samsung/350v5c/devicetree.cb A src/mainboard/samsung/350v5c/dsdt.asl A src/mainboard/samsung/350v5c/gnvs.c A src/mainboard/samsung/350v5c/gpio.c A src/mainboard/samsung/350v5c/hda_verb.c A src/mainboard/samsung/350v5c/mainboard.c A src/mainboard/samsung/350v5c/romstage.c 15 files changed, 705 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/30942/1 diff --git a/src/mainboard/samsung/350v5c/Kconfig b/src/mainboard/samsung/350v5c/Kconfig new file mode 100644 index 0000000..5ec7139 --- /dev/null +++ b/src/mainboard/samsung/350v5c/Kconfig @@ -0,0 +1,53 @@ +if BOARD_SAMSUNG_350V5C + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_6144 + select CPU_INTEL_SOCKET_RPGA989 + select EC_ACPI + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select NORTHBRIDGE_INTEL_IVYBRIDGE + select SANDYBRIDGE_IVYBRIDGE_LVDS + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_C216 + select SYSTEM_TYPE_LAPTOP + select USE_NATIVE_RAMINIT + +config MAINBOARD_DIR + string + default samsung/350v5c + +config MAINBOARD_PART_NUMBER + string + default "350V5C" + +config VGA_BIOS_FILE + string + default "pci8086,0166.rom" + +config VGA_BIOS_ID + string + default "8086,0166" + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0xc0d8 + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x144d + +config DRAM_RESET_GATE_GPIO # FIXME: check this + int + default 60 + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX # FIXME: check this + int + default 2 +endif diff --git a/src/mainboard/samsung/350v5c/Kconfig.name b/src/mainboard/samsung/350v5c/Kconfig.name new file mode 100644 index 0000000..9a2e96a --- /dev/null +++ b/src/mainboard/samsung/350v5c/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_SAMSUNG_350V5C + bool "350V5C" diff --git a/src/mainboard/samsung/350v5c/Makefile.inc b/src/mainboard/samsung/350v5c/Makefile.inc new file mode 100644 index 0000000..c55eebe --- /dev/null +++ b/src/mainboard/samsung/350v5c/Makefile.inc @@ -0,0 +1,2 @@ +romstage-y += gpio.c +ramstage-y += gnvs.c diff --git a/src/mainboard/samsung/350v5c/acpi/ec.asl b/src/mainboard/samsung/350v5c/acpi/ec.asl new file mode 100644 index 0000000..f2f4269 --- /dev/null +++ b/src/mainboard/samsung/350v5c/acpi/ec.asl @@ -0,0 +1,7 @@ +Device(EC) +{ + Name (_HID, EISAID("PNP0C09")) + Name (_UID, 0) + Name (_GPE, 23) +/* FIXME: EC support */ +} diff --git a/src/mainboard/samsung/350v5c/acpi/platform.asl b/src/mainboard/samsung/350v5c/acpi/platform.asl new file mode 100644 index 0000000..c2862c9 --- /dev/null +++ b/src/mainboard/samsung/350v5c/acpi/platform.asl @@ -0,0 +1,10 @@ +Method(_WAK,1) +{ + /* FIXME: EC support */ + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ + /* FIXME: EC support */ +} diff --git a/src/mainboard/samsung/350v5c/acpi/superio.asl b/src/mainboard/samsung/350v5c/acpi/superio.asl new file mode 100644 index 0000000..f2b35ba --- /dev/null +++ b/src/mainboard/samsung/350v5c/acpi/superio.asl @@ -0,0 +1 @@ +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/samsung/350v5c/acpi_tables.c b/src/mainboard/samsung/350v5c/acpi_tables.c new file mode 100644 index 0000000..2997587 --- /dev/null +++ b/src/mainboard/samsung/350v5c/acpi_tables.c @@ -0,0 +1 @@ +/* dummy */ diff --git a/src/mainboard/samsung/350v5c/board_info.txt b/src/mainboard/samsung/350v5c/board_info.txt new file mode 100644 index 0000000..cdbf8b8 --- /dev/null +++ b/src/mainboard/samsung/350v5c/board_info.txt @@ -0,0 +1,4 @@ +Category: laptop +ROM protocol: SPI +Flashrom support: n +FIXME: put ROM package, ROM socketed, Release year diff --git a/src/mainboard/samsung/350v5c/devicetree.cb b/src/mainboard/samsung/350v5c/devicetree.cb new file mode 100644 index 0000000..91093c0 --- /dev/null +++ b/src/mainboard/samsung/350v5c/devicetree.cb @@ -0,0 +1,119 @@ +chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + register "gfx.link_frequency_270_mhz" = "0" + register "gfx.ndid" = "3" + register "gfx.use_spread_spectrum_clock" = "0" + register "gpu_cpu_backlight" = "0x00000000" + register "gpu_dp_b_hotplug" = "0" + register "gpu_dp_c_hotplug" = "0" + register "gpu_dp_d_hotplug" = "0" + register "gpu_panel_port_select" = "0" + register "gpu_panel_power_backlight_off_delay" = "0" + register "gpu_panel_power_backlight_on_delay" = "0" + register "gpu_panel_power_cycle_delay" = "0" + register "gpu_panel_power_down_delay" = "0" + register "gpu_panel_power_up_delay" = "0" + register "gpu_pch_backlight" = "0x00000000" + device cpu_cluster 0x0 on + chip cpu/intel/socket_rPGA989 + device lapic 0x0 on + end + end + chip cpu/intel/model_206ax # FIXME: check all registers + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0xacac off + end + end + end + device domain 0x0 on + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "1" + register "gen1_dec" = "0x00040069" + register "gen2_dec" = "0x0004fd61" + register "gen3_dec" = "0x00000000" + register "gen4_dec" = "0x00000000" + register "gpi7_routing" = "2" + register "p_cnt_throttling_supported" = "0" + register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x11" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + register "superspeed_capable_ports" = "0x0000000f" + register "xhci_overcurrent_mapping" = "0x00000c03" + register "xhci_switchable_ports" = "0x0000000f" + device pci 14.0 on # USB 3.0 Controller + subsystemid 0x144d 0xc0d8 + end + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x144d 0xc0d8 + end + device pci 16.1 off # Management Engine Interface 2 + end + device pci 16.2 off # Management Engine IDE-R + end + device pci 16.3 off # Management Engine KT + end + device pci 19.0 off # Intel Gigabit Ethernet + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x144d 0xc0d8 + end + device pci 1b.0 on # High Definition Audio Audio controller + subsystemid 0x144d 0xc0d8 + end + device pci 1c.0 on # PCIe Port #1 + subsystemid 0x144d 0xc0d8 + end + device pci 1c.1 on # PCIe Port #2 + subsystemid 0x144d 0xc0d8 + end + device pci 1c.2 off # PCIe Port #3 + end + device pci 1c.3 off # PCIe Port #4 + end + device pci 1c.4 off # PCIe Port #5 + end + device pci 1c.5 off # PCIe Port #6 + end + device pci 1c.6 off # PCIe Port #7 + end + device pci 1c.7 off # PCIe Port #8 + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x144d 0xc0d8 + end + device pci 1e.0 off # PCI bridge + end + device pci 1f.0 on # LPC bridge PCI-LPC bridge + subsystemid 0x144d 0xc0d8 + end + device pci 1f.2 on # SATA Controller 1 + subsystemid 0x144d 0xc0d8 + end + device pci 1f.3 on # SMBus + subsystemid 0x144d 0xc0d8 + end + device pci 1f.5 off # SATA Controller 2 + end + device pci 1f.6 off # Thermal + end + end + device pci 00.0 on # Host bridge Host bridge + subsystemid 0x144d 0xc0d8 + end + device pci 01.0 on # PCIe Bridge for discrete graphics + subsystemid 0x144d 0xc0d8 + end + device pci 02.0 on # Internal graphics VGA controller + subsystemid 0x144d 0xc0d8 + end + end +end diff --git a/src/mainboard/samsung/350v5c/dsdt.asl b/src/mainboard/samsung/350v5c/dsdt.asl new file mode 100644 index 0000000..fb55547 --- /dev/null +++ b/src/mainboard/samsung/350v5c/dsdt.asl @@ -0,0 +1,30 @@ +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI 2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" + #include <cpu/intel/model_206ax/acpi/cpu.asl> + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + /* global NVS and variables. */ + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } + } +} diff --git a/src/mainboard/samsung/350v5c/gnvs.c b/src/mainboard/samsung/350v5c/gnvs.c new file mode 100644 index 0000000..6b731cc --- /dev/null +++ b/src/mainboard/samsung/350v5c/gnvs.c @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/bd82x6x/nvs.h> + +/* FIXME: check this function. */ +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + // the lid is open by default. + gnvs->lids = 1; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/samsung/350v5c/gpio.c b/src/mainboard/samsung/350v5c/gpio.c new file mode 100644 index 0000000..6bf860f --- /dev/null +++ b/src/mainboard/samsung/350v5c/gpio.c @@ -0,0 +1,232 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_NATIVE, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_NATIVE, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_OUTPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio4 = GPIO_LEVEL_LOW, + .gpio12 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_LOW, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, + .gpio30 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio3 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio8 = GPIO_INVERT, + .gpio15 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_NATIVE, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_GPIO, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_GPIO, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio37 = GPIO_DIR_OUTPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_OUTPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio50 = GPIO_DIR_OUTPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_OUTPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_OUTPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_OUTPUT, + .gpio61 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio34 = GPIO_LEVEL_LOW, + .gpio35 = GPIO_LEVEL_HIGH, + .gpio37 = GPIO_LEVEL_LOW, + .gpio42 = GPIO_LEVEL_LOW, + .gpio49 = GPIO_LEVEL_LOW, + .gpio50 = GPIO_LEVEL_HIGH, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio52 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio54 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_HIGH, + .gpio61 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_GPIO, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_NATIVE, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio66 = GPIO_DIR_OUTPUT, + .gpio67 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_OUTPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio74 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio66 = GPIO_LEVEL_LOW, + .gpio68 = GPIO_LEVEL_LOW, + .gpio74 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/samsung/350v5c/hda_verb.c b/src/mainboard/samsung/350v5c/hda_verb.c new file mode 100644 index 0000000..d05fc02 --- /dev/null +++ b/src/mainboard/samsung/350v5c/hda_verb.c @@ -0,0 +1,76 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0269, /* Codec Vendor / Device ID: Realtek */ + 0x144dc0d8, /* Subsystem ID */ + + 0x0000000b, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x0, 0x144dc0d8), + + /* NID 0x12. */ + AZALIA_PIN_CFG(0x0, 0x12, 0x411111f0), + + /* NID 0x14. */ + AZALIA_PIN_CFG(0x0, 0x14, 0x90170110), + + /* NID 0x15. */ + AZALIA_PIN_CFG(0x0, 0x15, 0x0421101f), + + /* NID 0x17. */ + AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0), + + /* NID 0x18. */ + AZALIA_PIN_CFG(0x0, 0x18, 0x04a11820), + + /* NID 0x19. */ + AZALIA_PIN_CFG(0x0, 0x19, 0x90a7092f), + + /* NID 0x1a. */ + AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0), + + /* NID 0x1b. */ + AZALIA_PIN_CFG(0x0, 0x1b, 0x411111f0), + + /* NID 0x1d. */ + AZALIA_PIN_CFG(0x0, 0x1d, 0x4005822d), + + /* NID 0x1e. */ + AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0), + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x144dc0d8, /* Subsystem ID */ + + 0x00000004, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x3, 0x144dc0d8), + + /* NID 0x05. */ + AZALIA_PIN_CFG(0x3, 0x05, 0x18560010), + + /* NID 0x06. */ + AZALIA_PIN_CFG(0x3, 0x06, 0x58560020), + + /* NID 0x07. */ + AZALIA_PIN_CFG(0x3, 0x07, 0x58560030), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/samsung/350v5c/mainboard.c b/src/mainboard/samsung/350v5c/mainboard.c new file mode 100644 index 0000000..44f4fa4 --- /dev/null +++ b/src/mainboard/samsung/350v5c/mainboard.c @@ -0,0 +1,50 @@ +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <ec/acpi/ec.h> +#include <console/console.h> +#include <pc80/keyboard.h> + +static void mainboard_init(struct device *dev) +{ + /* FIXME: trim this down or remove if necessary */ + { + int i; + const u8 dmp[256] = { + /* 00 */ 0x00, 0x00, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 10 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 20 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 30 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 40 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 50 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 60 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 70 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 80 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 90 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* a0 */ 0x00, 0x04, 0x00, 0x84, 0xc1, 0x00, 0x00, 0x61, 0x64, 0x00, 0x00, 0x08, 0x64, 0x19, 0x00, 0xd8, + /* b0 */ 0x00, 0x00, 0xff, 0x33, 0x01, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0x0f, 0x00, 0x4b, 0x00, 0x00, + /* c0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* d0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* e0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* f0 */ 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + }; + + printk(BIOS_DEBUG, "Replaying EC dump ..."); + for (i = 0; i < 256; i++) + ec_write (i, dmp[i]); + printk(BIOS_DEBUG, "done\n"); + } + pc_keyboard_init(NO_AUX_DEVICE); +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = mainboard_init; + + /* FIXME: fix those values*/ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/samsung/350v5c/romstage.c b/src/mainboard/samsung/350v5c/romstage.c new file mode 100644 index 0000000..860b045 --- /dev/null +++ b/src/mainboard/samsung/350v5c/romstage.c @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <lib.h> +#include <timestamp.h> +#include <arch/byteorder.h> +#include <arch/io.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +#include <arch/acpi.h> +#include <console/console.h> +#include "northbridge/intel/sandybridge/sandybridge.h" +#include "northbridge/intel/sandybridge/raminit_native.h" +#include "southbridge/intel/bd82x6x/pch.h" +#include <southbridge/intel/common/gpio.h> +#include <arch/cpu.h> +#include <cpu/x86/msr.h> + +void pch_enable_lpc(void) +{ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3c00); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x00040069); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x0004fd61); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00000000); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000000); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000); +} + +void mainboard_rcba_config(void) +{ +} + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 1, 0 }, + { 1, 1, 0 }, + { 1, 1, 1 }, + { 1, 1, 1 }, + { 0, 0, 2 }, + { 0, 0, 2 }, + { 0, 0, 3 }, + { 0, 0, 3 }, + { 1, 1, 4 }, + { 1, 1, 4 }, + { 0, 0, 5 }, + { 1, 0, 5 }, + { 0, 0, 6 }, + { 0, 0, 6 }, +}; + +void mainboard_early_init(int s3resume) +{ +} + +void mainboard_config_superio(void) +{ +} + +/* FIXME: Put proper SPD map here. */ +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x51, id_only); + read_spd(&spd[2], 0x52, id_only); + read_spd(&spd[3], 0x53, id_only); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/30942 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I64fcf931938fb3b158b9576b787f452bf6077843 Gerrit-Change-Number: 30942 Gerrit-PatchSet: 1 Gerrit-Owner: Kacper Słomiński <kacper.slominski72(a)gmail.com> Gerrit-MessageType: newchange

6 25

Change in ...coreboot[master]: mb/gigabyte: add GA-P67A-UD3R
by James (Code Review) 08 Jun '24

08 Jun '24

James has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31363 Change subject: mb/gigabyte: add GA-P67A-UD3R ...................................................................... mb/gigabyte: add GA-P67A-UD3R This is a Intel P67 chipset motherboard for Sandy Bridge processors. The P67 chipset has no graphics support. This board has redundant 4MB SOIC-8 flash chips, and flashrom is usable with the vendor BIOS. This is an original P67 chipset, and is affected by a SATA 2 hardware bug. There is a variant P67A-UD3R-B3 that is unaffected. The function of PCIe ports PCIEX4 and PCIEX1_* are configured in PCHSTRP9. By default, PCIEX4 is configured for 4 lanes and PCIEX1_* are disabled. This can be switched to 1 lane for all ports. Tested and working: - Intel Core i7 2600 - 4 DIMMs (4x4GB DDR3) - Booting Linux (SeaBIOS) - Native RAM init - PCIe graphics - Onboard Ethernet - Sensors (SuperIO) - S3 sleep - S4 hibernate - SATA 3 - USB 2.0 - USB 3.0 - Onboard audio (speakers, headphones) - CMOS - EHCI debug port - Serial port Not tested: - SATA 2 - PS/2 keyboard/mouse - Digital audio Change-Id: I4fbf50376be3184bf01a3bc8aae09bce54676707 Signed-off-by: James Ye <jye836(a)gmail.com> --- A src/mainboard/gigabyte/ga-p67a-ud3r/Kconfig A src/mainboard/gigabyte/ga-p67a-ud3r/Kconfig.name A src/mainboard/gigabyte/ga-p67a-ud3r/Makefile.inc A src/mainboard/gigabyte/ga-p67a-ud3r/acpi/ec.asl A src/mainboard/gigabyte/ga-p67a-ud3r/acpi/mainboard.asl A src/mainboard/gigabyte/ga-p67a-ud3r/acpi/platform.asl A src/mainboard/gigabyte/ga-p67a-ud3r/acpi/superio.asl A src/mainboard/gigabyte/ga-p67a-ud3r/acpi_tables.c A src/mainboard/gigabyte/ga-p67a-ud3r/board_info.txt A src/mainboard/gigabyte/ga-p67a-ud3r/cmos.default A src/mainboard/gigabyte/ga-p67a-ud3r/cmos.layout A src/mainboard/gigabyte/ga-p67a-ud3r/devicetree.cb A src/mainboard/gigabyte/ga-p67a-ud3r/dsdt.asl A src/mainboard/gigabyte/ga-p67a-ud3r/gpio.c A src/mainboard/gigabyte/ga-p67a-ud3r/hda_verb.c A src/mainboard/gigabyte/ga-p67a-ud3r/romstage.c 16 files changed, 781 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/31363/1 diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/Kconfig b/src/mainboard/gigabyte/ga-p67a-ud3r/Kconfig new file mode 100644 index 0000000..c1efe12 --- /dev/null +++ b/src/mainboard/gigabyte/ga-p67a-ud3r/Kconfig @@ -0,0 +1,40 @@ +if BOARD_GIGABYTE_GA_P67A_UD3R + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_4096 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_BD82X6X + select USE_NATIVE_RAMINIT + select SUPERIO_ITE_IT8728F + +config MAINBOARD_DIR + string + default "gigabyte/ga-p67a-ud3r" + +config MAINBOARD_PART_NUMBER + string + default "GA-P67A-UD3R" + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x5001 + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x1458 + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX + int + default 2 + +endif # BOARD_GIGABYTE_GA_P67A_UD3R diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/Kconfig.name b/src/mainboard/gigabyte/ga-p67a-ud3r/Kconfig.name new file mode 100644 index 0000000..15f0655 --- /dev/null +++ b/src/mainboard/gigabyte/ga-p67a-ud3r/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_GIGABYTE_GA_P67A_UD3R + bool "GA-P67A-UD3R" diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/Makefile.inc b/src/mainboard/gigabyte/ga-p67a-ud3r/Makefile.inc new file mode 100644 index 0000000..3dae61e --- /dev/null +++ b/src/mainboard/gigabyte/ga-p67a-ud3r/Makefile.inc @@ -0,0 +1 @@ +romstage-y += gpio.c diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/acpi/ec.asl b/src/mainboard/gigabyte/ga-p67a-ud3r/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/gigabyte/ga-p67a-ud3r/acpi/ec.asl diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/acpi/mainboard.asl b/src/mainboard/gigabyte/ga-p67a-ud3r/acpi/mainboard.asl new file mode 100644 index 0000000..34de86f --- /dev/null +++ b/src/mainboard/gigabyte/ga-p67a-ud3r/acpi/mainboard.asl @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB) +{ + Device (PWRB) + { + Name (_HID, EisaId("PNP0C0C")) + } +} diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/acpi/platform.asl b/src/mainboard/gigabyte/ga-p67a-ud3r/acpi/platform.asl new file mode 100644 index 0000000..d8d3320 --- /dev/null +++ b/src/mainboard/gigabyte/ga-p67a-ud3r/acpi/platform.asl @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + Return(Package(){0,0}) +} diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/acpi/superio.asl b/src/mainboard/gigabyte/ga-p67a-ud3r/acpi/superio.asl new file mode 100644 index 0000000..2b20c77 --- /dev/null +++ b/src/mainboard/gigabyte/ga-p67a-ud3r/acpi/superio.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 James Ye <jye836(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/acpi_tables.c b/src/mainboard/gigabyte/ga-p67a-ud3r/acpi_tables.c new file mode 100644 index 0000000..a2f383b --- /dev/null +++ b/src/mainboard/gigabyte/ga-p67a-ud3r/acpi_tables.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/bd82x6x/nvs.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; +} diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/board_info.txt b/src/mainboard/gigabyte/ga-p67a-ud3r/board_info.txt new file mode 100644 index 0000000..c6f16ae --- /dev/null +++ b/src/mainboard/gigabyte/ga-p67a-ud3r/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.gigabyte.com/Motherboard/GA-P67A-UD3R-rev-10 +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2011 diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/cmos.default b/src/mainboard/gigabyte/ga-p67a-ud3r/cmos.default new file mode 100644 index 0000000..60de212 --- /dev/null +++ b/src/mainboard/gigabyte/ga-p67a-ud3r/cmos.default @@ -0,0 +1,5 @@ +boot_option=Fallback +debug_level=Debug +nmi=Enable +power_on_after_fail=Disable +sata_mode=AHCI diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/cmos.layout b/src/mainboard/gigabyte/ga-p67a-ud3r/cmos.layout new file mode 100644 index 0000000..4e5c0a8 --- /dev/null +++ b/src/mainboard/gigabyte/ga-p67a-ud3r/cmos.layout @@ -0,0 +1,107 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2014 Vladimir Serbinenko +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +# Status Register A +# ----------------------------------------------------------------- +# Status Register B +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 3 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +#392 3 r 0 unused +395 4 e 4 debug_level +#399 1 r 0 unused + +#400 8 r 0 reserved for century byte + +# coreboot config options: southbridge +#400 1 e 0 unused +408 1 e 1 nmi +409 2 e 5 power_on_after_fail +411 1 e 6 sata_mode + +# coreboot config options: northbridge +#432 3 r 0 unused + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable + +2 0 Enable +2 1 Disable + +3 0 Fallback +3 1 Normal + +4 0 Emergency +4 1 Alert +4 2 Critical +4 3 Error +4 4 Warning +4 5 Notice +4 6 Info +4 7 Debug +4 8 Spew + +5 0 Disable +5 1 Enable +5 2 Keep + +6 0 AHCI +6 1 Compatible + +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/devicetree.cb b/src/mainboard/gigabyte/ga-p67a-ud3r/devicetree.cb new file mode 100644 index 0000000..4ed458d --- /dev/null +++ b/src/mainboard/gigabyte/ga-p67a-ud3r/devicetree.cb @@ -0,0 +1,124 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 James Ye <jye836(a)gmail.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +# +chip northbridge/intel/sandybridge + device cpu_cluster 0x0 on + chip cpu/intel/model_206ax + device lapic 0x0 on end + + # Magic APIC ID to locate this chip + device lapic 0xacac off end + + register "c1_acpower" = "1" + register "c2_acpower" = "3" + register "c3_acpower" = "5" + + register "c1_battery" = "1" + register "c2_battery" = "3" + register "c3_battery" = "5" + end + end + + device domain 0x0 on + subsystemid 0x1458 0x5001 inherit + + device pci 00.0 on end # Host bridge + device pci 01.0 on # PCIe bridge (PCIEX16) + subsystemid 0x1458 0x5000 + end + device pci 02.0 off end # Internal graphics + + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "sata_port_map" = "0x3f" + register "sata_interface_speed_support" = "0x3" + + register "gen1_dec" = "0x000c0801" + register "gen2_dec" = "0x000c0291" + + register "pcie_port_coalesce" = "0" + register "c2_latency" = "0x0065" + register "p_cnt_throttling_supported" = "1" + + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + + device pci 16.0 off end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 off end # Intel Gigabit Ethernet + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x1458 0x5006 + end + device pci 1b.0 on # High Definition Audio controller + subsystemid 0x1458 0xa102 + end + device pci 1c.0 on end # Unrouted, to disable coalescing + device pci 1c.1 on # PCIe Port #2 + device pci 00.0 on # USB 3.0 controller + subsystemid 0x1458 0x5007 + end + end + device pci 1c.2 on # PCIe Port #3 + device pci 00.0 on # Ethernet controller + subsystemid 0x1458 0xe000 + end + end + device pci 1c.3 on # PCIe Port #4 + device pci 00.0 on # PCI bridge + subsystemid 0x1458 0x5000 + end + end + device pci 1c.4 on end # PCIe Port #5 (PCIEX4) + device pci 1c.5 off end # PCIe Port #6 (PCIEX1_1) + device pci 1c.6 off end # PCIe Port #7 (PCIEX1_2) + device pci 1c.7 off end # PCIe Port #8 (PCIEX1_3) + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x1458 0x5006 + end + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on # LPC bridge + chip superio/ite/it8728f + device pnp 2e.0 off end # Floppy, not routed + device pnp 2e.1 on # COM1 + io 0x60 = 0x03f8 + irq 0x70 = 4 + end + device pnp 2e.2 off end # COM2, not routed + device pnp 2e.3 off end # Parallel port, not rounted + device pnp 2e.4 on # Environment Controller + io 0x60 = 0x0290 + io 0x62 = 0x0 + irq 0x70 = 0 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.6 off end # Mouse + device pnp 2e.7 off end # GPIO + device pnp 2e.a off end # CIR, not routed + end + end + device pci 1f.2 on # SATA Controller 1 + subsystemid 0x1458 0xb005 + end + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/dsdt.asl b/src/mainboard/gigabyte/ga-p67a-ud3r/dsdt.asl new file mode 100644 index 0000000..365a0fa --- /dev/null +++ b/src/mainboard/gigabyte/ga-p67a-ud3r/dsdt.asl @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 James Ye <jye836(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +DefinitionBlock ( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI 2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 // OEM revision +) +{ + // Some generic macros + #include "acpi/mainboard.asl" + #include "acpi/platform.asl" + #include "acpi/superio.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + + // Global NVS and variables + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + + // Chipset specific sleep states + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } +} diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/gpio.c b/src/mainboard/gigabyte/ga-p67a-ud3r/gpio.c new file mode 100644 index 0000000..c65f432 --- /dev/null +++ b/src/mainboard/gigabyte/ga-p67a-ud3r/gpio.c @@ -0,0 +1,204 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2019 James Ye <jye836(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio11 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_GPIO, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio47 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_LOW, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/hda_verb.c b/src/mainboard/gigabyte/ga-p67a-ud3r/hda_verb.c new file mode 100644 index 0000000..a843a2b --- /dev/null +++ b/src/mainboard/gigabyte/ga-p67a-ud3r/hda_verb.c @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2019 James Ye <jye836(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0892, /* Codec Vendor / Device ID: Realtek */ + 0x1458a022, /* Subsystem ID */ + + 15, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x2, 0x1458a022), + + /* NID 0x11. */ + AZALIA_PIN_CFG(0x2, 0x11, 0x99430140), + + /* NID 0x12. */ + AZALIA_PIN_CFG(0x2, 0x12, 0x411111f0), + + /* NID 0x14. */ + AZALIA_PIN_CFG(0x2, 0x14, 0x01014410), + + /* NID 0x15. */ + AZALIA_PIN_CFG(0x2, 0x15, 0x01011412), + + /* NID 0x16. */ + AZALIA_PIN_CFG(0x2, 0x16, 0x01016411), + + /* NID 0x17. */ + AZALIA_PIN_CFG(0x2, 0x17, 0x01012414), + + /* NID 0x18. */ + AZALIA_PIN_CFG(0x2, 0x18, 0x01a19c50), + + /* NID 0x19. */ + AZALIA_PIN_CFG(0x2, 0x19, 0x02a19c60), + + /* NID 0x1a. */ + AZALIA_PIN_CFG(0x2, 0x1a, 0x0181345f), + + /* NID 0x1b. */ + AZALIA_PIN_CFG(0x2, 0x1b, 0x02214c20), + + /* NID 0x1c. */ + AZALIA_PIN_CFG(0x2, 0x1c, 0x593301f0), + + /* NID 0x1d. */ + AZALIA_PIN_CFG(0x2, 0x1d, 0x4005e601), + + /* NID 0x1e. */ + AZALIA_PIN_CFG(0x2, 0x1e, 0x014b6130), + + /* NID 0x1f. */ + AZALIA_PIN_CFG(0x2, 0x1f, 0x411111f0), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/gigabyte/ga-p67a-ud3r/romstage.c b/src/mainboard/gigabyte/ga-p67a-ud3r/romstage.c new file mode 100644 index 0000000..3037b73 --- /dev/null +++ b/src/mainboard/gigabyte/ga-p67a-ud3r/romstage.c @@ -0,0 +1,75 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2019 James Ye <jye836(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <superio/ite/common/ite.h> +#include <superio/ite/it8728f/it8728f.h> + +#define SUPERIO_BASE 0x2e +#define SUPERIO_GPIO PNP_DEV(SUPERIO_BASE, IT8728F_GPIO) +#define SERIAL_DEV PNP_DEV(SUPERIO_BASE, 0x01) + +void pch_enable_lpc(void) +{ + pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | CNF1_LPC_EN | + CNF2_LPC_EN | COMA_LPC_EN); +} + +void mainboard_rcba_config(void) +{ +} + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 1, 0 }, + { 1, 1, 0 }, + { 1, 1, 1 }, + { 1, 1, 1 }, + { 1, 6, 2 }, + { 1, 6, 2 }, + { 1, 6, 3 }, + { 1, 5, 3 }, + { 1, 5, 4 }, + { 1, 5, 4 }, + { 1, 5, 5 }, + { 1, 5, 5 }, + { 1, 5, 6 }, + { 1, 5, 6 }, +}; + +void mainboard_early_init(int s3resume) +{ +} + +void mainboard_config_superio(void) +{ + /* Enable serial port */ + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + + /* Disable SIO WDT which kicks in DualBIOS */ + ite_reg_write(SUPERIO_GPIO, 0xEF, 0x7E); +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x51, id_only); + read_spd(&spd[2], 0x52, id_only); + read_spd(&spd[3], 0x53, id_only); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/31363 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4fbf50376be3184bf01a3bc8aae09bce54676707 Gerrit-Change-Number: 31363 Gerrit-PatchSet: 1 Gerrit-Owner: James <jye836(a)gmail.com> Gerrit-MessageType: newchange

6 24

Change in coreboot[master]: src/mainboard: Port for Chuwi Minibook (m3/8GB)
by Sergey Larin (Code Review) 08 Jun '24

08 Jun '24

Sergey Larin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38249 ) Change subject: src/mainboard: Port for Chuwi Minibook (m3/8GB) ...................................................................... src/mainboard: Port for Chuwi Minibook (m3/8GB) Hardware: - Intel Core m3-8100Y (Amber Lake aka Kabylake) - Sunrise Point-LP C iHDCP 2.2 Premium - ITE IT8987E EC - Unknown soldered 8GB memory - SPD was extracted from BIOS image (BIOS says it's Micron/2 ranks/13-15-15-34) - 1200x1920 eDP display (yep it's rotated) - mini-HDMI port - 1 USB 3.0, 1 USB 2.0, 1 USB Type-C port (as charger but working) - eMMC storage (unknown) - SD card slot - M.2 2242 slot - Intel WiFi chip Currently hangs after postcar stage. Change-Id: I7cfa4588802b9c07b504f03471265574608519c8 --- M src/drivers/spi/flashconsole.c A src/mainboard/chuwi/Kconfig A src/mainboard/chuwi/Kconfig.name A src/mainboard/chuwi/minibook/Kconfig A src/mainboard/chuwi/minibook/Kconfig.name A src/mainboard/chuwi/minibook/Makefile.inc A src/mainboard/chuwi/minibook/acpi/ec.asl A src/mainboard/chuwi/minibook/acpi/mainboard.asl A src/mainboard/chuwi/minibook/acpi/superio.asl A src/mainboard/chuwi/minibook/acpi_tables.c A src/mainboard/chuwi/minibook/board_info.txt A src/mainboard/chuwi/minibook/data.vbt A src/mainboard/chuwi/minibook/devicetree.cb A src/mainboard/chuwi/minibook/dsdt.asl A src/mainboard/chuwi/minibook/gma-mainboard.ads A src/mainboard/chuwi/minibook/gpio.h A src/mainboard/chuwi/minibook/hda_verb.c A src/mainboard/chuwi/minibook/mainboard.c A src/mainboard/chuwi/minibook/ramstage.c A src/mainboard/chuwi/minibook/romstage.c A src/mainboard/chuwi/minibook/spd/Makefile.inc A src/mainboard/chuwi/minibook/spd/micron.spd.hex A src/mainboard/chuwi/minibook/spd/spd.h A src/mainboard/chuwi/minibook/spd/spd_util.c A src/superio/ite/it8987e/Kconfig A src/superio/ite/it8987e/Makefile.inc A src/superio/ite/it8987e/it8987e.h A src/superio/ite/it8987e/superio.c 28 files changed, 1,360 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/38249/1 diff --git a/src/drivers/spi/flashconsole.c b/src/drivers/spi/flashconsole.c index 80c63e0..149a84e 100644 --- a/src/drivers/spi/flashconsole.c +++ b/src/drivers/spi/flashconsole.c @@ -22,11 +22,11 @@ #define LINE_BUFFER_SIZE 128 #define READ_BUFFER_SIZE 0x100 -static const struct region_device *rdev_ptr; -static struct region_device rdev; -static uint8_t line_buffer[LINE_BUFFER_SIZE]; -static size_t offset; -static size_t line_offset; +static const struct region_device *g_rdev_ptr; +static struct region_device g_rdev; +static uint8_t g_line_buffer[LINE_BUFFER_SIZE]; +static size_t g_offset; +static size_t g_line_offset; void flashconsole_init(void) { @@ -36,11 +36,11 @@ size_t len = READ_BUFFER_SIZE; size_t i; - if (fmap_locate_area_as_rdev_rw("CONSOLE", &rdev)) { + if (fmap_locate_area_as_rdev_rw("CONSOLE", &g_rdev)) { printk(BIOS_INFO, "Can't find 'CONSOLE' area in FMAP\n"); return; } - size = region_device_sz(&rdev); + size = region_device_sz(&g_rdev); /* * We need to check the region until we find a 0xff indicating @@ -56,7 +56,7 @@ // Fill the buffer on first iteration if (i == 0) { len = MIN(READ_BUFFER_SIZE, size - offset); - if (rdev_readat(&rdev, buffer, offset, len) != len) + if (rdev_readat(&g_rdev, buffer, offset, len) != len) return; } if (buffer[i] == 0xff) { @@ -75,29 +75,29 @@ return; } - offset = offset; - rdev_ptr = &rdev; + g_offset = offset; + g_rdev_ptr = &g_rdev; } void flashconsole_tx_byte(unsigned char c) { - if (!rdev_ptr) + if (!g_rdev_ptr) return; - size_t region_size = region_device_sz(rdev_ptr); + size_t region_size = region_device_sz(g_rdev_ptr); - line_buffer[line_offset++] = c; + g_line_buffer[g_line_offset++] = c; - if (line_offset >= LINE_BUFFER_SIZE || - offset + line_offset >= region_size || c == '\n') { + if (g_line_offset >= LINE_BUFFER_SIZE || + g_offset + g_line_offset >= region_size || c == '\n') { flashconsole_tx_flush(); } } void flashconsole_tx_flush(void) { - size_t offset = offset; - size_t len = line_offset; + size_t offset = g_offset; + size_t len = g_line_offset; size_t region_size; static int busy; @@ -107,23 +107,23 @@ if (busy) return; - if (!rdev_ptr) + if (!g_rdev_ptr) return; busy = 1; - region_size = region_device_sz(rdev_ptr); + region_size = region_device_sz(g_rdev_ptr); if (offset + len >= region_size) len = region_size - offset; - if (rdev_writeat(&rdev, line_buffer, offset, len) != len) + if (rdev_writeat(&g_rdev, g_line_buffer, offset, len) != len) return; // If the region is full, stop future write attempts if (offset + len >= region_size) return; - offset = offset + len; - line_offset = 0; + g_offset = offset + len; + g_line_offset = 0; busy = 0; } diff --git a/src/mainboard/chuwi/Kconfig b/src/mainboard/chuwi/Kconfig new file mode 100644 index 0000000..234d863 --- /dev/null +++ b/src/mainboard/chuwi/Kconfig @@ -0,0 +1,16 @@ +if VENDOR_CHUWI + +choice + prompt "Mainboard model" + +source "src/mainboard/chuwi/*/Kconfig.name" + +endchoice + +source "src/mainboard/chuwi/*/Kconfig" + +config MAINBOARD_VENDOR + string + default "CHUWI Innovation And Technology(ShenZhen)co.,Ltd" + +endif # VENDOR_CHUWI diff --git a/src/mainboard/chuwi/Kconfig.name b/src/mainboard/chuwi/Kconfig.name new file mode 100644 index 0000000..2582c97 --- /dev/null +++ b/src/mainboard/chuwi/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_CHUWI + bool "CHUWI Innovation And Technology(ShenZhen)co.,Ltd" diff --git a/src/mainboard/chuwi/minibook/Kconfig b/src/mainboard/chuwi/minibook/Kconfig new file mode 100644 index 0000000..32881b8 --- /dev/null +++ b/src/mainboard/chuwi/minibook/Kconfig @@ -0,0 +1,73 @@ +if BOARD_CHUWI_MINIBOOK + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SYSTEM_TYPE_CONVERTIBLE + select BOARD_ROMSIZE_KB_8192 + select SUPERIO_ITE_IT8987E + select SOC_INTEL_KABYLAKE + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select GFX_GMA_INTERNAL_IS_EDP + select GENERIC_SPD_BIN + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select ADD_FSP_BINARIES + select FSP_USE_REPO + +config SPI_FLASH_INCLUDE_ALL_DRIVERS + bool + default n + +config SPI_FLASH + bool + default y + +config SPI_FLASH_WINBOND + bool + default y + +config DIMM_SPD_SIZE + int + default 512 + +config VGA_BIOS_ID + string + default "8086,591c" + +config IRQ_SLOT_COUNT + int + default 18 + +config MINIBOOK_EC_BIN_PATH + string + default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/ec.bin" + +config FSP_FD_PATH + string + #default "3rdparty/fsp/AmberLakeFspBinPkg/Fsp.fd" + default "3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd" + +config FSP_HEADER_PATH + string + #default "3rdparty/fsp/AmberLakeFspBinPkg/Include/" + default "3rdparty/fsp/KabylakeFspBinPkg/Include/" + +config MAX_CPUS + int + default 4 + +config CBFS_SIZE + hex + default 0x600000 + +config MAINBOARD_DIR + string + default "chuwi/minibook" + +config MAINBOARD_PART_NUMBER + string + default "MiniBook" + +endif diff --git a/src/mainboard/chuwi/minibook/Kconfig.name b/src/mainboard/chuwi/minibook/Kconfig.name new file mode 100644 index 0000000..a8cb30a --- /dev/null +++ b/src/mainboard/chuwi/minibook/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_CHUWI_MINIBOOK + bool "MiniBook" diff --git a/src/mainboard/chuwi/minibook/Makefile.inc b/src/mainboard/chuwi/minibook/Makefile.inc new file mode 100644 index 0000000..7c7ca2a --- /dev/null +++ b/src/mainboard/chuwi/minibook/Makefile.inc @@ -0,0 +1,26 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2015 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +subdirs-y += spd + +#ramstage-y += mainboard.c +ramstage-y += ramstage.c +ramstage-y += hda_verb.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +cbfs-files-y += ec.bin +ec.bin-file := $(call strip_quotes,$(CONFIG_MINIBOOK_EC_BIN_PATH)) +ec.bin-type := raw +ec.bin-position := 0xffa40000 diff --git a/src/mainboard/chuwi/minibook/acpi/ec.asl b/src/mainboard/chuwi/minibook/acpi/ec.asl new file mode 100644 index 0000000..ecc384e --- /dev/null +++ b/src/mainboard/chuwi/minibook/acpi/ec.asl @@ -0,0 +1,176 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Johanna Schander <coreboot(a)mimoja.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (EC) +{ + Name (_HID, EisaId ("PNP0C09")) + Name (_UID, 0) + + Name (_CRS, ResourceTemplate () { + IO (Decode16, 0x62, 0x62, 0, 1) + IO (Decode16, 0x66, 0x66, 0, 1) + }) + + Name (ACEX, 0) + + OperationRegion (ERAM, EmbeddedControl, 0x00, 0xFF) + Field (ERAM, ByteAcc, NoLock, Preserve) + { + XXX0, 8, + XXX1, 8, + XXX2, 8, + Offset (0x11), + KBCD, 8, + Offset (0x20), + RCMD, 8, + RCST, 8, + TESR, 8, + Offset (0x60), + TSR1, 8, + TSR2, 8, + TSR3, 8, + TSI, 4, + HYST, 4, + TSHT, 8, + TSLT, 8, + TSSR, 8, + CHGR, 16, + Offset (0x72), + CHGT, 8, + Offset (0x7F), + LSTE, 1, + Offset (0x80), + ECWR, 8, + XX10, 8, + XX11, 16, + B1DC, 16, + B1FV, 16, + B1FC, 16, + XX15, 16, + B1ST, 8, + B1CR, 16, + B1RC, 16, + B1VT, 16, + BPCN, 8, + Offset (0xC0), + VER1, 8, + VER2, 8, + RSV1, 8, + RSV2, 8, + CCI0, 8, + CCI1, 8, + CCI2, 8, + CCI3, 8, + CTL0, 8, + CTL1, 8, + CTL2, 8, + CTL3, 8, + CTL4, 8, + CTL5, 8, + CTL6, 8, + CTL7, 8, + MGI0, 8, + MGI1, 8, + MGI2, 8, + MGI3, 8, + MGI4, 8, + MGI5, 8, + MGI6, 8, + MGI7, 8, + MGI8, 8, + MGI9, 8, + MGIA, 8, + MGIB, 8, + MGIC, 8, + MGID, 8, + MGIE, 8, + MGIF, 8, + MGO0, 8, + MGO1, 8, + MGO2, 8, + MGO3, 8, + MGO4, 8, + MGO5, 8, + MGO6, 8, + MGO7, 8, + MGO8, 8, + MGO9, 8, + MGOA, 8, + MGOB, 8, + MGOC, 8, + MGOD, 8, + MGOE, 8, + MGOF, 8, + , 3, + TPCC, 1, + , 2, + DRMD, 1, + Offset (0xF1) + } + + Method (_REG, 2, NotSerialized) + { + } + + // KEY_RFKILL??? + Method (_Q01, 0, NotSerialized) + { + } + + // AC plugged? + Method (_Q0A, 0, NotSerialized) + { + } + + // AC unplugged? + Method (_Q0B, 0, NotSerialized) + { + } + + // Lid open/closed + Method (_Q0C, 0, NotSerialized) + { + } + + // Lid open/closed + Method (_Q0D, 0, NotSerialized) + { + } + + // Brigtness up + Method (_Q06, 0, NotSerialized) + { + } + + // Brigtness down + Method (_Q07, 0, NotSerialized) + { + } + + // Power down event + Method (_Q54, 0, NotSerialized) + { + } + + // ??? USB Type C/UCSI Something? + Method (_Q79, 0, NotSerialized) + { + } + + // ??? DCI (OTG?) + Method (_QDD, 0, NotSerialized) + { + } +} diff --git a/src/mainboard/chuwi/minibook/acpi/mainboard.asl b/src/mainboard/chuwi/minibook/acpi/mainboard.asl new file mode 100644 index 0000000..20d993a --- /dev/null +++ b/src/mainboard/chuwi/minibook/acpi/mainboard.asl @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB) +{ + Device (LID0) + { + Name (_HID, EisaId ("PNP0C0D")) + + Method (_LID) + { + if (LEqual(\_SB.PCI0.LPCB.EC.LSTE,0)) + { + Return (One) + } + else + { + Return (Zero) + } + } + + Method (_STA) + { + Return (_LID) + } + } + + Device (PWRB) + { + Name (_HID, EisaId ("PNP0C0C")) + + Method (_STA) + { + Return (0xF) + } + + Name (_PRW, Package () { 27, 4 }) + } + +} diff --git a/src/mainboard/chuwi/minibook/acpi/superio.asl b/src/mainboard/chuwi/minibook/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/chuwi/minibook/acpi/superio.asl diff --git a/src/mainboard/chuwi/minibook/acpi_tables.c b/src/mainboard/chuwi/minibook/acpi_tables.c new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/chuwi/minibook/acpi_tables.c diff --git a/src/mainboard/chuwi/minibook/board_info.txt b/src/mainboard/chuwi/minibook/board_info.txt new file mode 100644 index 0000000..ebb9053 --- /dev/null +++ b/src/mainboard/chuwi/minibook/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Chuwi +Board name: Minibook +Category: laptop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/chuwi/minibook/data.vbt b/src/mainboard/chuwi/minibook/data.vbt new file mode 100644 index 0000000..16eac95 --- /dev/null +++ b/src/mainboard/chuwi/minibook/data.vbt Binary files differ diff --git a/src/mainboard/chuwi/minibook/devicetree.cb b/src/mainboard/chuwi/minibook/devicetree.cb new file mode 100644 index 0000000..20ec6d9 --- /dev/null +++ b/src/mainboard/chuwi/minibook/devicetree.cb @@ -0,0 +1,264 @@ +chip soc/intel/skylake + # Enable deep Sx states + register "deep_s3_enable_ac" = "0" + register "deep_s3_enable_dc" = "0" + register "deep_s5_enable_ac" = "0" + register "deep_s5_enable_dc" = "0" + register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" + + register "eist_enable" = "1" + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_C" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + register "gen1_dec" = "0x000c0681" + register "gen2_dec" = "0x000c1641" + register "gen3_dec" = "0x00000069" + register "gen4_dec" = "0x0000006d" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # Enable DPTF + register "dptf_enable" = "1" + + # FSP Configuration + register "ProbelessTrace" = "0" + register "EnableLan" = "0" + register "EnableSata" = "1" + register "SataSalpSupport" = "0" + register "SataMode" = "0" + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + register "SataPortsEnable[2]" = "1" + register "SataPortsDevSlp[1]" = "1" + register "EnableAzalia" = "1" + register "DspEnable" = "1" + register "IoBufferOwnership" = "0" + register "EnableTraceHub" = "0" + register "SsicPortEnable" = "0" + register "SmbusEnable" = "1" + register "Cio2Enable" = "0" + register "ScsEmmcEnabled" = "1" + register "ScsEmmcHs400Enabled" = "1" + register "ScsSdCardEnabled" = "2" # IDK why 2 really + register "PttSwitch" = "0" + register "SkipExtGfxScan" = "1" + register "PrimaryDisplay" = "Display_iGFX" + register "Device4Enable" = "1" + register "HeciEnabled" = "1" + register "SaGv" = "SaGv_Enabled" + register "PmConfigSlpS3MinAssert" = "2" # 50ms + register "PmConfigSlpS4MinAssert" = "1" # 1s + register "PmConfigSlpSusMinAssert" = "3" # 500ms + register "PmConfigSlpAMinAssert" = "3" # 2s + register "PmTimerDisabled" = "0" + + register "serirq_mode" = "SERIRQ_CONTINUOUS" + + register "pirqa_routing" = "PCH_IRQ11" + register "pirqb_routing" = "PCH_IRQ10" + register "pirqc_routing" = "PCH_IRQ11" + register "pirqd_routing" = "PCH_IRQ11" + register "pirqe_routing" = "PCH_IRQ11" + register "pirqf_routing" = "PCH_IRQ11" + register "pirqg_routing" = "PCH_IRQ11" + register "pirqh_routing" = "PCH_IRQ11" + + # VR Settings Configuration for 4 Domains + #+----------------+-----------+-----------+-------------+----------+ + #| Domain/Setting | SA | IA | GT Unsliced | GT | + #+----------------+-----------+-----------+-------------+----------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 5A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| IccMax | 4A | 28A | 24A | 24A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #+----------------+-----------+-----------+-------------+----------+ + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ \ + .vr_config_enable = 1, \ + .psi1threshold = VR_CFG_AMP(20), \ + .psi2threshold = VR_CFG_AMP(5), \ + .psi3threshold = VR_CFG_AMP(1), \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = VR_CFG_AMP(4), \ + .voltage_limit = 1520, \ + .ac_loadline = 1800, \ + .dc_loadline = 1800, \ + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ \ + .vr_config_enable = 1, \ + .psi1threshold = VR_CFG_AMP(20), \ + .psi2threshold = VR_CFG_AMP(5), \ + .psi3threshold = VR_CFG_AMP(1), \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = VR_CFG_AMP(28), \ + .voltage_limit = 1520, \ + .ac_loadline = 400, \ + .dc_loadline = 400, \ + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ \ + .vr_config_enable = 1, \ + .psi1threshold = VR_CFG_AMP(20), \ + .psi2threshold = VR_CFG_AMP(5), \ + .psi3threshold = VR_CFG_AMP(1), \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = VR_CFG_AMP(24), \ + .voltage_limit = 1520, \ + .ac_loadline = 570, \ + .dc_loadline = 570, \ + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ \ + .vr_config_enable = 1, \ + .psi1threshold = VR_CFG_AMP(20), \ + .psi2threshold = VR_CFG_AMP(5), \ + .psi3threshold = VR_CFG_AMP(1), \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = VR_CFG_AMP(24), \ + .voltage_limit = 1520, \ + .ac_loadline = 570, \ + .dc_loadline = 570, \ + }" + + # Enable Root Port 6 (WiFi) + register "PcieRpEnable[5]" = "1" + + register "PcieRpLtrEnable[5]" = "1" + + # USB + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port (left) + register "usb2_ports[2]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port (right) + register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Wireless + register "usb2_ports[8]" = "USB2_PORT_FLEX(OC_SKIP)" # Touchpad + + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port (left) + + register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" + register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3" + register "i2c_voltage[2]" = "I2C_VOLTAGE_1V8" + + # PL1 override 8W + register "tdp_pl1_override" = "8" + + # PL2 override 18W + register "tdp_pl2_override" = "18" + + # Send an extra VR mailbox command + register "SendVrMbxCmd" = "1" + + # Lock Down + register "common_soc_config" = "{ \ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, \ + }" + + # I2C4 is marked as "IoExpander" in BIOS + register "SerialIoDevMode" = "{ \ + [PchSerialIoIndexI2C0] = PchSerialIoPci, \ + [PchSerialIoIndexI2C1] = PchSerialIoPci, \ + [PchSerialIoIndexI2C2] = PchSerialIoPci, \ + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C4] = PchSerialIoAcpiHidden, \ + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \ + [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \ + [PchSerialIoIndexSpi1] = PchSerialIoPci, \ + [PchSerialIoIndexUart0] = PchSerialIoPci, \ + [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart2] = PchSerialIoDisabled, \ + }" + + register "sdcard_cd_gpio_default" = "GPP_B17" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # Thermal Subsystem + device pci 07.0 on end # ??? + device pci 08.0 on end # Gaussian Mixture Model + device pci 14.0 on end # USB xHCI + device pci 14.2 on end # Thermal Subsystem + # TODO fill I2C + device pci 15.0 on end # I2C Controller #0 + device pci 15.1 on end # I2C Controller #0 + device pci 15.2 on end # I2C Controller #0 + device pci 16.0 on end # Management Engine Interface 1 + device pci 17.0 on end # SATA + device pci 1c.0 on end # PCI Express Port 1 + device pci 1e.0 on end # Serial IO UART0 + device pci 1e.3 on end # SPI Controller #0 + device pci 1e.4 on end # SD Host Controller + device pci 1e.6 on end # SD Host Controller + device pci 1f.0 on # LPC + chip superio/ite/it8987e + device pnp 4e.4 off end # System Wake Up Control + device pnp 4e.5 on # KBC/Mouse Interface + irq 0x70 = 12 + end + device pnp 4e.6 on # KBC/Keyboard Interface + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 4e.a off end # Consumer IR + device pnp 4e.f on # Shared Memory/Flash Interface + io 0x60 = 0x200 + irq 0x70 = 0 + irq 0x71 = 2 + irq 0xf4 = 9 + end + device pnp 4e.10 on # Real Time Clock + io 0x60 = 0x912 + io 0x62 = 0x910 + irq 0x70 = 8 + end + device pnp 4e.11 on # Power Management I/F Channel 1 (PMC1) + io 0x60 = 0x62 + io 0x62 = 0x66 + irq 0x70 = 0 + end + device pnp 4e.12 on # Power Management I/F Channel 2 (PMC2) + io 0x60 = 0x68 + io 0x62 = 0x6c + irq 0x70 = 0 + irq 0xf0 = 0 + end + device pnp 4e.13 off end # Serial Peripheral Interface (SSPI) + device pnp 4e.14 off end # Platform Environment Control Interface (PECI) + device pnp 4e.17 off end # Power Management I/F Channel 3 (PMC3) + device pnp 4e.18 off end # Power Management I/F Channel 3 (PMC4) + device pnp 4e.19 off end # Power Management I/F Channel 3 (PMC5) + end + end # LPC Bridge + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + end +end diff --git a/src/mainboard/chuwi/minibook/dsdt.asl b/src/mainboard/chuwi/minibook/dsdt.asl new file mode 100644 index 0000000..ef48745 --- /dev/null +++ b/src/mainboard/chuwi/minibook/dsdt.asl @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x05, // DSDT revision: ACPI v5.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +){ + //Platform + #include <soc/intel/skylake/acpi/platform.asl> + + // global NVS and variables + #include <soc/intel/skylake/acpi/globalnvs.asl> + + // CPU + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/skylake/acpi/systemagent.asl> + #include <soc/intel/skylake/acpi/pch.asl> + } + + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> + + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/chuwi/minibook/gma-mainboard.ads b/src/mainboard/chuwi/minibook/gma-mainboard.ads new file mode 100644 index 0000000..452cf26 --- /dev/null +++ b/src/mainboard/chuwi/minibook/gma-mainboard.ads @@ -0,0 +1,33 @@ +-- +-- This file is part of the coreboot project. +-- +-- Copyright (C) 2018 Tristan Corrick <tristan(a)corrick.kiwi> +-- Copyright (C) 2019 Maxim Polyakov <max.senia.poliak(a)gmail.com> +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (Internal, + DP1, + HDMI1, + Analog, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/chuwi/minibook/gpio.h b/src/mainboard/chuwi/minibook/gpio.h new file mode 100644 index 0000000..e8460a7 --- /dev/null +++ b/src/mainboard/chuwi/minibook/gpio.h @@ -0,0 +1,194 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Sergey Larin <cerg2010cerg2010(a)mail.ru> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <soc/gpe.h> +#include <soc/gpio.h> + +#ifndef __ACPI__ + +/* Pad configuration in ramstage. */ +static const struct pad_config gpio_table[] = { + /* GPIO */ _PAD_CFG_STRUCT(GPP_A0, 0x4000100, 0x1000), + /* LAD0 */ _PAD_CFG_STRUCT(GPP_A1, 0x44000702, 0x3c00), + /* LAD1 */ _PAD_CFG_STRUCT(GPP_A2, 0x44000702, 0x3c00), + /* LAD2 */ _PAD_CFG_STRUCT(GPP_A3, 0x44000702, 0x3c00), + /* LAD3 */ _PAD_CFG_STRUCT(GPP_A4, 0x44000702, 0x3c00), + /* LFRAME# */ _PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x0), + /* SERIRQ */ _PAD_CFG_STRUCT(GPP_A6, 0x44000702, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_A7, 0x44000100, 0x1000), + /* CLKRUN# */ _PAD_CFG_STRUCT(GPP_A8, 0x44000700, 0x0), + /* CLKOUT_LPC0 */ _PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x1000), + /* CLKOUT_LPC1 */ _PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_A11, 0x44000102, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_A12, 0x44000100, 0x1000), + /* SUSWARN#/SUSPWRDNACK */ _PAD_CFG_STRUCT(GPP_A13, 0x44000700, 0x0), + /* SUS_STAT# */ _PAD_CFG_STRUCT(GPP_A14, 0x44000700, 0x0), + /* SUS_ACK# */ _PAD_CFG_STRUCT(GPP_A15, 0x44000702, 0x3000), + /* SD_1P8_SEL */ _PAD_CFG_STRUCT(GPP_A16, 0x44000500, 0x0), + /* SD_PWR_EN# */ _PAD_CFG_STRUCT(GPP_A17, 0x44000700, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_A18, 0x40800102, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_A19, 0x40000100, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_A20, 0x42000100, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_A21, 0x44000201, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_A22, 0x44000100, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_A23, 0x44000100, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_B0, 0x44000100, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_B1, 0x44000100, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_B2, 0x44000201, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_B3, 0x44000100, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_B4, 0x44000201, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_B5, 0x44000100, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_B6, 0x44000102, 0x3000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_B7, 0x44000102, 0x3000), + /* SRCCLKREQ3# */ _PAD_CFG_STRUCT(GPP_B8, 0x44000702, 0x3000), + /* SRCCLKREQ4# */ _PAD_CFG_STRUCT(GPP_B9, 0x44000702, 0x0), + /* SRCCLKREQ5# */ _PAD_CFG_STRUCT(GPP_B10, 0x44000702, 0x0), + /* EXT_PWR_GATE# */ _PAD_CFG_STRUCT(GPP_B11, 0x44000700, 0x0), + /* SLP_S0# */ _PAD_CFG_STRUCT(GPP_B12, 0x44000700, 0x0), + /* PLTRST# */ _PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_B14, 0x44000100, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_B15, 0x44000201, 0x800), + /* GPIO */ _PAD_CFG_STRUCT(GPP_B16, 0x42000100, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_B17, 0x46000100, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_B18, 0x44000100, 0x1000), + /* GSPI1_CS# */ _PAD_CFG_STRUCT(GPP_B19, 0x44000700, 0x0), + /* GSPI1_CLK */ _PAD_CFG_STRUCT(GPP_B20, 0x44000700, 0x1000), + /* GSPI1_MISO */ _PAD_CFG_STRUCT(GPP_B21, 0x44000700, 0x1000), + /* GSPI1_MOSI */ _PAD_CFG_STRUCT(GPP_B22, 0x44000700, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_B23, 0x44000100, 0x1000), + /* SMBCLK */ _PAD_CFG_STRUCT(GPP_C0, 0x44000702, 0x2800), + /* SMBDATA */ _PAD_CFG_STRUCT(GPP_C1, 0x44000702, 0x2800), + /* GPIO */ _PAD_CFG_STRUCT(GPP_C2, 0x44000100, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_C3, 0x44000100, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_C4, 0x44000100, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_C5, 0x44000100, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_C6, 0x44000100, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_C7, 0x44000100, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_C8, 0x44000102, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_C9, 0x86080102, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_C10, 0x4000201, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_C11, 0x44000102, 0x3000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_C12, 0x44000200, 0x2400), + /* GPIO */ _PAD_CFG_STRUCT(GPP_C13, 0x44000100, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_C14, 0x44000201, 0x800), + /* GPIO */ _PAD_CFG_STRUCT(GPP_C15, 0x82180102, 0x0), + /* I2C0_SDA */ _PAD_CFG_STRUCT(GPP_C16, 0x44000702, 0x0), + /* I2C0_SCL */ _PAD_CFG_STRUCT(GPP_C17, 0x44000702, 0x0), + /* I2C1_SDA */ _PAD_CFG_STRUCT(GPP_C18, 0x44000702, 0x0), + /* I2C1_SCL */ _PAD_CFG_STRUCT(GPP_C19, 0x44000702, 0x0), + /* UART2_RXD */ _PAD_CFG_STRUCT(GPP_C20, 0x44000702, 0x0), + /* UART2_TXD */ _PAD_CFG_STRUCT(GPP_C21, 0x44000700, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_C22, 0x44000200, 0x2400), + /* GPIO */ _PAD_CFG_STRUCT(GPP_C23, 0x44000100, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_D0, 0x44000100, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_D1, 0x44000100, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_D2, 0x44000100, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_D3, 0x44000100, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_D4, 0x44000100, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_D5, 0x44000102, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_D6, 0x44000102, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_D7, 0x44000102, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_D8, 0x44000102, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_D9, 0x44000100, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_D10, 0x44000100, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_D11, 0x40000102, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_D12, 0x40000102, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_D13, 0x44000100, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_D14, 0x44000100, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_D15, 0x44000100, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_D16, 0x44000100, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_D17, 0x44000200, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_D18, 0x44000201, 0x3000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_D19, 0x44000201, 0x3000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_D20, 0x4000201, 0x3000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_D21, 0x44000100, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_D22, 0x44000100, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_D23, 0x44000100, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_E0, 0x44000100, 0x1000), + /* SATAXPCIE1 */ _PAD_CFG_STRUCT(GPP_E1, 0x44000700, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_E2, 0x44000100, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_E3, 0x44000100, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_E4, 0x44000100, 0x1000), + /* SATA_DEVSLP1 */ _PAD_CFG_STRUCT(GPP_E5, 0x4000700, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_E6, 0x44000100, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_E7, 0x80180102, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_E8, 0x44000201, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_E9, 0x44000200, 0x3000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_E10, 0x44000200, 0x3000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_E11, 0x44000201, 0x3000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_E12, 0x44000200, 0x3000), + /* DDPB_HPD0 */ _PAD_CFG_STRUCT(GPP_E13, 0x44000700, 0x0), + /* DDPC_HPD1 */ _PAD_CFG_STRUCT(GPP_E14, 0x44000700, 0x0), + /* DDPD_HPD2 */ _PAD_CFG_STRUCT(GPP_E15, 0x44000702, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_E16, 0x80880102, 0x3000), + /* EDP_HPD */ _PAD_CFG_STRUCT(GPP_E17, 0x44000702, 0x0), + /* DDPB_CTRLCLK */ _PAD_CFG_STRUCT(GPP_E18, 0x44000700, 0x0), + /* DDPB_CTRLDATA */ _PAD_CFG_STRUCT(GPP_E19, 0x44000700, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_E20, 0x44000100, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_E21, 0x44000102, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_E22, 0x44000100, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_E23, 0x44000201, 0x1000), + /* BATLOW# */ _PAD_CFG_STRUCT(GPD0, 0x4000702, 0x0), + /* ACPRESENT */ _PAD_CFG_STRUCT(GPD1, 0x4000700, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPD2, 0x4000100, 0x1000), + /* PWRBTN# */ _PAD_CFG_STRUCT(GPD3, 0x4000702, 0x3000), + /* SLP_S3# */ _PAD_CFG_STRUCT(GPD4, 0x4000700, 0x0), + /* SLP_S4# */ _PAD_CFG_STRUCT(GPD5, 0x4000700, 0x0), + /* SLP_A# */ _PAD_CFG_STRUCT(GPD6, 0x4000600, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPD7, 0x4000201, 0x0), + /* SUSCLK */ _PAD_CFG_STRUCT(GPD8, 0x4000700, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPD9, 0x4000200, 0x0), + /* SLP_S5# */ _PAD_CFG_STRUCT(GPD10, 0x4000700, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPD11, 0x4000200, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_F0, 0x44000200, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_F1, 0x44000200, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_F2, 0x44000200, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_F3, 0x44000200, 0x1000), + /* I2C2_SDA */ _PAD_CFG_STRUCT(GPP_F4, 0x44000702, 0x2000000), + /* I2C2_SCL */ _PAD_CFG_STRUCT(GPP_F5, 0x44000702, 0x2000000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_F6, 0x44000201, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_F7, 0x80180102, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_F8, 0x40080100, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_F9, 0x44000201, 0x3000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_F10, 0x44000200, 0x1000), + /* GPIO */ _PAD_CFG_STRUCT(GPP_F11, 0x44000201, 0x0), + /* EMMC_CMD */ _PAD_CFG_STRUCT(GPP_F12, 0x44000702, 0x0), + /* EMMC_DATA0 */ _PAD_CFG_STRUCT(GPP_F13, 0x44000702, 0x0), + /* EMMC_DATA1 */ _PAD_CFG_STRUCT(GPP_F14, 0x44000702, 0x0), + /* EMMC_DATA2 */ _PAD_CFG_STRUCT(GPP_F15, 0x44000702, 0x0), + /* EMMC_DATA3 */ _PAD_CFG_STRUCT(GPP_F16, 0x44000702, 0x0), + /* EMMC_DATA4 */ _PAD_CFG_STRUCT(GPP_F17, 0x44000702, 0x0), + /* EMMC_DATA5 */ _PAD_CFG_STRUCT(GPP_F18, 0x44000702, 0x0), + /* EMMC_DATA6 */ _PAD_CFG_STRUCT(GPP_F19, 0x44000702, 0x0), + /* EMMC_DATA7 */ _PAD_CFG_STRUCT(GPP_F20, 0x44000702, 0x0), + /* EMMC_RCLK */ _PAD_CFG_STRUCT(GPP_F21, 0x44000700, 0x0), + /* EMMC_CLK */ _PAD_CFG_STRUCT(GPP_F22, 0x44000700, 0x0), + /* GPIO */ _PAD_CFG_STRUCT(GPP_F23, 0x44000200, 0x1000), + /* SD_CMD */ _PAD_CFG_STRUCT(GPP_G0, 0x44000702, 0x0), + /* SD_DATA0 */ _PAD_CFG_STRUCT(GPP_G1, 0x44000702, 0x0), + /* SD_DATA1 */ _PAD_CFG_STRUCT(GPP_G2, 0x44000702, 0x0), + /* SD_DATA2 */ _PAD_CFG_STRUCT(GPP_G3, 0x44000702, 0x0), + /* SD_DATA3 */ _PAD_CFG_STRUCT(GPP_G4, 0x44000702, 0x0), + /* SD_CD# */ _PAD_CFG_STRUCT(GPP_G5, 0x44000700, 0x3000), + /* SD_CLK */ _PAD_CFG_STRUCT(GPP_G6, 0x44000702, 0x0), + /* SD_WP */ _PAD_CFG_STRUCT(GPP_G7, 0x44000700, 0x0), +}; + +#endif + +#endif diff --git a/src/mainboard/chuwi/minibook/hda_verb.c b/src/mainboard/chuwi/minibook/hda_verb.c new file mode 100644 index 0000000..c654e70 --- /dev/null +++ b/src/mainboard/chuwi/minibook/hda_verb.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * Copyright (C) 2019 Sergey Larin <cerg2010cerg2010(a)mail.ru> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* Realtek, ALC269VC */ + 0x10ec0269, /* Vendor ID */ + 0x10ec0000, /* Subsystem ID */ + 11, /* Number of entries */ + AZALIA_SUBVENDOR(0, 0x10ec0000), + AZALIA_PIN_CFG(0, 0x12, 0xb7a60140), + AZALIA_PIN_CFG(0, 0x14, 0x90170120), + AZALIA_PIN_CFG(0, 0x15, 0x04211010), + AZALIA_PIN_CFG(0, 0x17, 0x40000000), + AZALIA_PIN_CFG(0, 0x18, 0x04a11030), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x40e4a205), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + + /* Intel, KabylakeHDMI */ + 0x8086280b, /* Vendor ID */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of entries */ + AZALIA_SUBVENDOR(2, 0x80860101), + AZALIA_PIN_CFG(2, 0x05, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560010), + AZALIA_PIN_CFG(2, 0x07, 0x18560010), +}; + +const u32 pc_beep_verbs[] = {}; +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/chuwi/minibook/mainboard.c b/src/mainboard/chuwi/minibook/mainboard.c new file mode 100644 index 0000000..7f1f114 --- /dev/null +++ b/src/mainboard/chuwi/minibook/mainboard.c @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Purism SPC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <smbios.h> +#include <string.h> +#include <cbfs.h> + +#define MAX_SERIAL_LENGTH 0x100 + +const char *smbios_mainboard_serial_number(void) +{ + static char serial_number[MAX_SERIAL_LENGTH + 1] = {0}; + struct cbfsf file; + + if (serial_number[0] != 0) + return serial_number; + + if (cbfs_boot_locate(&file, "serial_number", NULL) == 0) { + struct region_device cbfs_region; + size_t ser_len; + + cbfs_file_data(&cbfs_region, &file); + + ser_len = region_device_sz(&cbfs_region); + if (ser_len <= MAX_SERIAL_LENGTH) { + if (rdev_readat(&cbfs_region, serial_number, 0, ser_len) == ser_len) { + serial_number[ser_len] = 0; + return serial_number; + } + } + } + + strncpy(serial_number, CONFIG_MAINBOARD_SERIAL_NUMBER, MAX_SERIAL_LENGTH); + + return serial_number; +} diff --git a/src/mainboard/chuwi/minibook/ramstage.c b/src/mainboard/chuwi/minibook/ramstage.c new file mode 100644 index 0000000..94f8071 --- /dev/null +++ b/src/mainboard/chuwi/minibook/ramstage.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corporation + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/ramstage.h> +#include "gpio.h" + +void mainboard_silicon_init_params(FSP_SIL_UPD *params) +{ + /* Configure pads prior to SiliconInit() in case there's any + * dependencies during hardware initialization. */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/chuwi/minibook/romstage.c b/src/mainboard/chuwi/minibook/romstage.c new file mode 100644 index 0000000..d57adc5 --- /dev/null +++ b/src/mainboard/chuwi/minibook/romstage.c @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation + * Copyright (C) 2017 Purism SPC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <assert.h> +#include <console/console.h> +#include <soc/romstage.h> +#include <spd_bin.h> +#include "spd/spd.h" +#include <ec/acpi/ec.h> +#include <stdint.h> +#include <stddef.h> + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *mem_cfg; + mem_cfg = &mupd->FspmConfig; + + printk(BIOS_INFO, "SPD index %d\n", 0); + + mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0); + mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0); + mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); + mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); + + struct region_device spd_rdev; + + mem_cfg->DqPinsInterleaved = 0; + if (get_spd_cbfs_rdev(&spd_rdev, 0) < 0) + die("spd.bin not found\n"); + mem_cfg->MemorySpdDataLen = region_device_sz(&spd_rdev); + /* Memory leak is ok since we have memory mapped boot media */ + // TODO evaluate google/eve way of loading + mem_cfg->MemorySpdPtr00 = (uintptr_t)rdev_mmap_full(&spd_rdev); + //mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; + print_spd_info((uint8_t*)mem_cfg->MemorySpdPtr00); + + mupd->FspmTestConfig.DmiVc1 = 1; +} diff --git a/src/mainboard/chuwi/minibook/spd/Makefile.inc b/src/mainboard/chuwi/minibook/spd/Makefile.inc new file mode 100644 index 0000000..3f2fde0 --- /dev/null +++ b/src/mainboard/chuwi/minibook/spd/Makefile.inc @@ -0,0 +1,21 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 Johanna Schander <coreboot(a)mimoja.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +romstage-y += spd_util.c + +SPD_BIN = $(obj)/spd.bin + +# It's probably the same SPD used for 16GB version +SPD_SOURCES += micron # 0b0000 8GB diff --git a/src/mainboard/chuwi/minibook/spd/micron.spd.hex b/src/mainboard/chuwi/minibook/spd/micron.spd.hex new file mode 100644 index 0000000..0f1c25f --- /dev/null +++ b/src/mainboard/chuwi/minibook/spd/micron.spd.hex @@ -0,0 +1,32 @@ +91 20 f1 03 05 1a 05 0a 03 11 01 08 0a 00 00 01 +78 78 90 50 90 11 50 e0 90 06 3c 3c 01 90 00 00 +00 b1 00 00 00 00 00 a8 00 88 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 2c 00 00 00 00 00 00 00 da b0 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/chuwi/minibook/spd/spd.h b/src/mainboard/chuwi/minibook/spd/spd.h new file mode 100644 index 0000000..36363cc --- /dev/null +++ b/src/mainboard/chuwi/minibook/spd/spd.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * Copyright (C) 2019 Johanna Schander <coreboot(a)mimoja.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_SPD_H +#define MAINBOARD_SPD_H + +#include <gpio.h> +#include "../gpio.h" + +void mainboard_fill_dq_map_data(void *dq_map_ptr); +void mainboard_fill_dqs_map_data(void *dqs_map_ptr); +void mainboard_fill_rcomp_res_data(void *rcomp_ptr); +void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr); +#endif diff --git a/src/mainboard/chuwi/minibook/spd/spd_util.c b/src/mainboard/chuwi/minibook/spd/spd_util.c new file mode 100644 index 0000000..babd8ef --- /dev/null +++ b/src/mainboard/chuwi/minibook/spd/spd_util.c @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> + +#include "spd.h" + +void mainboard_fill_dq_map_data(void *dq_map_ptr) +{ + /* DQ byte map */ + const u8 dq_map[2][12] = { + {0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00}, + {0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00}}; + memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); +} + +void mainboard_fill_dqs_map_data(void *dqs_map_ptr) +{ + /* DQS CPU<>DRAM map */ + //const u8 dqs_map[2][8] = {{0, 1, 3, 2, 4, 5, 6, 7}, {1, 0, 4, 5, 2, 3, 6, 7}}; + const u8 dqs_map[2][8] = {{6, 4, 7, 5, 1, 3, 2, 0}, + {3, 1, 6, 4, 2, 0, 5, 7}}; + memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map)); +} + +void mainboard_fill_rcomp_res_data(void *rcomp_ptr) +{ + /* Rcomp resistor */ + /* Cannot find these in original BIOS, so use defaults */ + /* They are valid, probably */ + const u16 RcompResistor[3] = {200, 81, 162}; + memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor)); +} + +void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) +{ + /* Rcomp target */ + /* Cannot find these in original BIOS, so use defaults */ + /* They are valid, probably */ + static const u16 RcompTarget[5] = {100, 40, 40, 23, 40}; + + memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); +} diff --git a/src/superio/ite/it8987e/Kconfig b/src/superio/ite/it8987e/Kconfig new file mode 100644 index 0000000..b8e3258 --- /dev/null +++ b/src/superio/ite/it8987e/Kconfig @@ -0,0 +1,18 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 Sergey Larin <cerg2010cerg2010(a)mail.ru> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config SUPERIO_ITE_IT8987E + bool + select SUPERIO_ITE_COMMON_PRE_RAM diff --git a/src/superio/ite/it8987e/Makefile.inc b/src/superio/ite/it8987e/Makefile.inc new file mode 100644 index 0000000..01e4d3e --- /dev/null +++ b/src/superio/ite/it8987e/Makefile.inc @@ -0,0 +1,17 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 Sergey Larin <cerg2010cerg2010(a)mail.ru> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-$(CONFIG_SUPERIO_ITE_IT8987E) += superio.c diff --git a/src/superio/ite/it8987e/it8987e.h b/src/superio/ite/it8987e/it8987e.h new file mode 100644 index 0000000..4e265df --- /dev/null +++ b/src/superio/ite/it8987e/it8987e.h @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Sergey Larin <cerg2010cerg2010(a)mail.ru> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SUPERIO_ITE_IT8987E_H +#define SUPERIO_ITE_IT8987E_H + +#define IT8987E_SWUC 0x04 /* System Wake-Up */ +#define IT8987E_KBCM 0x05 /* PS/2 mouse */ +#define IT8987E_KBCK 0x06 /* PS/2 keyboard */ +#define IT8987E_IR 0x0a /* Consumer IR */ +#define IT8987E_SMFI 0x0f /* Shared Memory/Flash Interface */ +#define IT8987E_RTCT 0x10 /* RTC-like Timer */ +#define IT8987E_PMC1 0x11 /* Power Management Channel 1 */ +#define IT8987E_PMC2 0x12 /* Power Management Channel 2 */ +#define IT8987E_SSPI 0x13 /* Serial Peripheral Interface */ +#define IT8987E_PECI 0x14 /* Platform EC Interface */ +#define IT8987E_PMC3 0x17 /* Power Management Channel 3 */ +#define IT8987E_PMC4 0x18 /* Power Management Channel 4 */ +#define IT8987E_PMC5 0x19 /* Power Management Channel 5 */ + + +#endif /* SUPERIO_ITE_IT8987E_H */ diff --git a/src/superio/ite/it8987e/superio.c b/src/superio/ite/it8987e/superio.c new file mode 100644 index 0000000..dce7a6f --- /dev/null +++ b/src/superio/ite/it8987e/superio.c @@ -0,0 +1,65 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Sergey Larin <cerg2010cerg2010(a)mail.ru> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <device/pnp.h> +#include <superio/conf_mode.h> + +#include "it8987e.h" + +static void it8987e_init(struct device *dev) +{ +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = it8987e_init, + .ops_pnp_mode = &pnp_conf_mode_870155_aa, +}; + +static struct pnp_info pnp_dev_info[] = { + { NULL, IT8987E_SWUC, PNP_IO0 | PNP_IRQ0, 0xfff0, }, + { NULL, IT8987E_KBCM, PNP_IRQ0, }, + { NULL, IT8987E_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07ff, }, + { NULL, IT8987E_IR, PNP_IO0 | PNP_IRQ0, 0xfff8, }, + { NULL, IT8987E_SMFI, PNP_IO0 | PNP_IRQ0 | PNP_MSC4, 0xfff0, }, + { NULL, IT8987E_RTCT, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IO3 | PNP_IRQ0 + | PNP_MSC0 | PNP_MSC1 | PNP_MSC2, + 0xfffe, 0xfffe, 0xfffe, 0xfffe}, + { NULL, IT8987E_PMC1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07ff }, + { NULL, IT8987E_PMC2, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IRQ0 | PNP_MSC0, + 0x07fc, 0x07fc, 0xfff0 }, + { NULL, IT8987E_SSPI, PNP_IO0 | PNP_IRQ0, 0xfff8 }, + { NULL, IT8987E_PECI, PNP_IO0, 0xfff8 }, + { NULL, IT8987E_PMC3, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07ff }, + { NULL, IT8987E_PMC4, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC0, + 0x07ff, 0x07ff }, + { NULL, IT8987E_PMC5, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC0, + 0x07ff, 0x07ff }, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_ite_it8987e_ops = { + CHIP_NAME("ITE IT8987E Super I/O") + .enable_dev = enable_dev, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/38249 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7cfa4588802b9c07b504f03471265574608519c8 Gerrit-Change-Number: 38249 Gerrit-PatchSet: 1 Gerrit-Owner: Sergey Larin <cerg2010cerg2010(a)mail.ru> Gerrit-MessageType: newchange

6 9

Change in coreboot[master]: mb/intel/dq45ek: Add new mainboard
by Samuel Holland (Code Review) 08 Jun '24

08 Jun '24

Samuel Holland has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44696 ) Change subject: mb/intel/dq45ek: Add new mainboard ...................................................................... mb/intel/dq45ek: Add new mainboard The Intel DQ45EK is a mini-ITX motherboard featuring the Q45 chipset. The flash chip is soldered in the center of the bottom of the board, and cannot be flashed in-system, so flashing the board requires overriding the IFD permissions (grounding GPIO33 when powering the board on) or desoldering the chip. At that point, the ME firmware region can be completely removed (this will break fan control). Tested, working: * SeaBIOS, Tianocore * libgfxinit (both DVI ports, plus VGA on DVI-I) * PCIe x1 slot * COM1 * Audio, Ethernet, SATA (AHCI/IDE), USB (1.1/2.0) * S3 suspend/resume * power_on_after_fail option Change-Id: I565690c4ed7b4ae60760b8fa6b1e2d783f8e094b Signed-off-by: Samuel Holland <samuel(a)sholland.org> --- A src/mainboard/intel/dq45ek/Kconfig A src/mainboard/intel/dq45ek/Kconfig.name A src/mainboard/intel/dq45ek/Makefile.inc A src/mainboard/intel/dq45ek/acpi/ec.asl A src/mainboard/intel/dq45ek/acpi/ich10_pci_irqs.asl A src/mainboard/intel/dq45ek/acpi/superio.asl A src/mainboard/intel/dq45ek/acpi_tables.c A src/mainboard/intel/dq45ek/board_info.txt A src/mainboard/intel/dq45ek/cmos.default A src/mainboard/intel/dq45ek/cmos.layout A src/mainboard/intel/dq45ek/cstates.c A src/mainboard/intel/dq45ek/data.vbt A src/mainboard/intel/dq45ek/devicetree.cb A src/mainboard/intel/dq45ek/dsdt.asl A src/mainboard/intel/dq45ek/early_init.c A src/mainboard/intel/dq45ek/gma-mainboard.ads A src/mainboard/intel/dq45ek/gpio.c A src/mainboard/intel/dq45ek/hda_verb.c 18 files changed, 487 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/44696/1 diff --git a/src/mainboard/intel/dq45ek/Kconfig b/src/mainboard/intel/dq45ek/Kconfig new file mode 100644 index 0000000..593c878 --- /dev/null +++ b/src/mainboard/intel/dq45ek/Kconfig @@ -0,0 +1,34 @@ +# SPDX-License-Identifier: GPL-2.0-only + +if BOARD_INTEL_DQ45EK + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select CPU_INTEL_SOCKET_LGA775 + select NORTHBRIDGE_INTEL_X4X + select SOUTHBRIDGE_INTEL_I82801JX + select SUPERIO_WINBOND_WPCD376I + select BOARD_ROMSIZE_KB_4096 + select DRIVERS_I2C_CK505 + select GFX_GMA_ANALOG_I2C_HDMI_C + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_USES_IFD_GBE_REGION + +config VGA_BIOS_ID + string + default "8086,2e02" + +config MAINBOARD_DIR + string + default "intel/dq45ek" + +config MAINBOARD_PART_NUMBER + string + default "DQ45EK" + +endif # BOARD_INTEL_DQ45EK diff --git a/src/mainboard/intel/dq45ek/Kconfig.name b/src/mainboard/intel/dq45ek/Kconfig.name new file mode 100644 index 0000000..aa065e8 --- /dev/null +++ b/src/mainboard/intel/dq45ek/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_INTEL_DQ45EK + bool "DQ45EK" diff --git a/src/mainboard/intel/dq45ek/Makefile.inc b/src/mainboard/intel/dq45ek/Makefile.inc new file mode 100644 index 0000000..ede8d87 --- /dev/null +++ b/src/mainboard/intel/dq45ek/Makefile.inc @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ramstage-y += cstates.c +romstage-y += gpio.c + +bootblock-y += early_init.c +romstage-y += early_init.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/intel/dq45ek/acpi/ec.asl b/src/mainboard/intel/dq45ek/acpi/ec.asl new file mode 100644 index 0000000..2997587 --- /dev/null +++ b/src/mainboard/intel/dq45ek/acpi/ec.asl @@ -0,0 +1 @@ +/* dummy */ diff --git a/src/mainboard/intel/dq45ek/acpi/ich10_pci_irqs.asl b/src/mainboard/intel/dq45ek/acpi/ich10_pci_irqs.asl new file mode 100644 index 0000000..836523f --- /dev/null +++ b/src/mainboard/intel/dq45ek/acpi/ich10_pci_irqs.asl @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* This is board specific information: + * IRQ routing for the 0:1e.0 PCI bridge of the ICH10 + */ + +If (PICM) { + Return (Package() { + }) +} Else { + Return (Package() { + }) +} diff --git a/src/mainboard/intel/dq45ek/acpi/superio.asl b/src/mainboard/intel/dq45ek/acpi/superio.asl new file mode 100644 index 0000000..2997587 --- /dev/null +++ b/src/mainboard/intel/dq45ek/acpi/superio.asl @@ -0,0 +1 @@ +/* dummy */ diff --git a/src/mainboard/intel/dq45ek/acpi_tables.c b/src/mainboard/intel/dq45ek/acpi_tables.c new file mode 100644 index 0000000..f745951 --- /dev/null +++ b/src/mainboard/intel/dq45ek/acpi_tables.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi_gnvs.h> +#include <southbridge/intel/i82801jx/nvs.h> + +void acpi_create_gnvs(struct global_nvs *gnvs) +{ + gnvs->pwrs = 1; /* Power state (AC = 1) */ + gnvs->apic = 1; /* Enable APIC */ + gnvs->mpen = 1; /* Enable Multi Processing */ + gnvs->cmap = 1; /* Enable COM1 port */ +} diff --git a/src/mainboard/intel/dq45ek/board_info.txt b/src/mainboard/intel/dq45ek/board_info.txt new file mode 100644 index 0000000..eb1f4bf --- /dev/null +++ b/src/mainboard/intel/dq45ek/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://ark.intel.com/products/34688 +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2008 diff --git a/src/mainboard/intel/dq45ek/cmos.default b/src/mainboard/intel/dq45ek/cmos.default new file mode 100644 index 0000000..706f5dd --- /dev/null +++ b/src/mainboard/intel/dq45ek/cmos.default @@ -0,0 +1,6 @@ +boot_option=Fallback +debug_level=Debug +power_on_after_fail=Disable +nmi=Enable +sata_mode=AHCI +gfx_uma_size=64M diff --git a/src/mainboard/intel/dq45ek/cmos.layout b/src/mainboard/intel/dq45ek/cmos.layout new file mode 100644 index 0000000..2174ecd --- /dev/null +++ b/src/mainboard/intel/dq45ek/cmos.layout @@ -0,0 +1,96 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +# Status Register A +# ----------------------------------------------------------------- +# Status Register B +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#390 5 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 6 debug_level + +# coreboot config options: southbridge +408 1 e 10 sata_mode +409 2 e 7 power_on_after_fail +411 1 e 1 nmi + +# coreboot config options: cpu +#424 8 r 0 unused + +# coreboot config options: northbridge +432 4 e 11 gfx_uma_size +#435 549 r 0 unused + + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +10 0 AHCI +10 1 Compatible +11 1 4M +11 2 8M +11 3 16M +11 4 32M +11 5 48M +11 6 64M +11 7 128M +11 8 256M +11 9 96M +11 10 160M +11 11 224M +11 12 352M + +# ----------------------------------------------------------------- +checksums + +checksum 392 983 984 diff --git a/src/mainboard/intel/dq45ek/cstates.c b/src/mainboard/intel/dq45ek/cstates.c new file mode 100644 index 0000000..21b18b9 --- /dev/null +++ b/src/mainboard/intel/dq45ek/cstates.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpigen.h> + +int get_cst_entries(acpi_cstate_t **entries) +{ + return 0; +} diff --git a/src/mainboard/intel/dq45ek/data.vbt b/src/mainboard/intel/dq45ek/data.vbt new file mode 100644 index 0000000..c4a94cb --- /dev/null +++ b/src/mainboard/intel/dq45ek/data.vbt Binary files differ diff --git a/src/mainboard/intel/dq45ek/devicetree.cb b/src/mainboard/intel/dq45ek/devicetree.cb new file mode 100644 index 0000000..d574498 --- /dev/null +++ b/src/mainboard/intel/dq45ek/devicetree.cb @@ -0,0 +1,88 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +chip northbridge/intel/x4x # Northbridge + device cpu_cluster 0 on # APIC cluster + chip cpu/intel/socket_LGA775 + device lapic 0 on end + end + chip cpu/intel/model_1067x # CPU + device lapic 0xacac off end + end + end + device domain 0 on # PCI domain + subsystemid 0x8086 0x1004 inherit + device pci 0.0 on end # Host Bridge + device pci 2.0 on end # Integrated graphics controller + device pci 2.1 on end # Integrated graphics controller 2 + chip southbridge/intel/i82801jx # Southbridge + register "gpe0_en" = "0x28000140" + + register "sata_port_map" = "0x1f" + + register "pcie_slot_implemented" = "0x8" + + register "gen1_dec" = "0x00fc0a01" + + device pci 19.0 on end # GBE + device pci 1a.0 on end # USB + device pci 1a.1 on end # USB + device pci 1a.2 on end # USB + device pci 1a.7 on end # USB + device pci 1b.0 on end # Audio + device pci 1c.0 on end # PCIe 1 + device pci 1c.1 off end # PCIe 2 + device pci 1c.2 off end # PCIe 3 + device pci 1c.3 on end # PCIe 4 + device pci 1c.4 off end # PCIe 5 + device pci 1c.5 off end # PCIe 6 + device pci 1d.0 on end # USB + device pci 1d.1 on end # USB + device pci 1d.2 on end # USB + device pci 1d.7 on end # USB + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on # LPC bridge + chip superio/winbond/wpcd376i # Super I/O + device pnp 2e.0 off end # Floppy + device pnp 2e.1 off end # Parallel port + device pnp 2e.3 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 0x4 + irq 0xf0 = 0x2 + end + device pnp 2e.4 on # SWC + io 0x60 = 0xa00 + io 0x62 = 0xa10 + irq 0x70 = 0x0 + end + device pnp 2e.5 off end # Mouse + device pnp 2e.6 off end # Keyboard + device pnp 2e.7 on # GPIO + io 0x60 = 0xa20 + irq 0x70 = 0x0 + irq 0xf0 = 0x17 + irq 0xf1 = 0x03 + irq 0xf2 = 0x00 + irq 0xf3 = 0x00 + irq 0xf8 = 0x01 + end + device pnp 2e.15 off end # ECIR + device pnp 2e.16 off end # COM3 / IR + end + end + device pci 1f.2 on end # SATA + device pci 1f.3 on # SMBus + chip drivers/i2c/ck505 # SLG8XP549T + register "mask" = "{ 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff }" + register "regs" = "{ 0x91, 0xd9, 0xff, 0xff, + 0xff, 0x00, 0x00, 0x06, + 0x03, 0x25, 0x01, 0x80, 0x0d }" + device i2c 69 on end + end + end + device pci 1f.5 off end # IDE + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/intel/dq45ek/dsdt.asl b/src/mainboard/intel/dq45ek/dsdt.asl new file mode 100644 index 0000000..de548d1 --- /dev/null +++ b/src/mainboard/intel/dq45ek/dsdt.asl @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20090419 // OEM revision +) +{ + // global NVS and variables + #include <southbridge/intel/common/acpi/platform.asl> + #include <southbridge/intel/i82801jx/acpi/globalnvs.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/x4x/acpi/x4x.asl> + #include <southbridge/intel/i82801jx/acpi/ich10.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + } + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> +} diff --git a/src/mainboard/intel/dq45ek/early_init.c b/src/mainboard/intel/dq45ek/early_init.c new file mode 100644 index 0000000..dffde0a --- /dev/null +++ b/src/mainboard/intel/dq45ek/early_init.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <bootblock_common.h> +#include <northbridge/intel/x4x/x4x.h> +#include <southbridge/intel/i82801jx/i82801jx.h> +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/wpcd376i/wpcd376i.h> + +#define SERIAL_DEV PNP_DEV(0x2e, WPCD376I_SP1) + +void bootblock_mainboard_early_init(void) +{ + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} + +void mb_get_spd_map(u8 spd_map[4]) +{ + spd_map[0] = 0x50; + spd_map[2] = 0x52; +} diff --git a/src/mainboard/intel/dq45ek/gma-mainboard.ads b/src/mainboard/intel/dq45ek/gma-mainboard.ads new file mode 100644 index 0000000..8b07c07 --- /dev/null +++ b/src/mainboard/intel/dq45ek/gma-mainboard.ads @@ -0,0 +1,17 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, + HDMI2, + Analog, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/intel/dq45ek/gpio.c b/src/mainboard/intel/dq45ek/gpio.c new file mode 100644 index 0000000..1c64b2f --- /dev/null +++ b/src/mainboard/intel/dq45ek/gpio.c @@ -0,0 +1,117 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio18 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_OUTPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio20 = GPIO_LEVEL_HIGH, + .gpio21 = GPIO_LEVEL_LOW, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { + .gpio18 = GPIO_BLINK, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, + .gpio60 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_LOW, + .gpio49 = GPIO_LEVEL_LOW, + .gpio60 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio72 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { }; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + }, + +}; diff --git a/src/mainboard/intel/dq45ek/hda_verb.c b/src/mainboard/intel/dq45ek/hda_verb.c new file mode 100644 index 0000000..6a29631 --- /dev/null +++ b/src/mainboard/intel/dq45ek/hda_verb.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x11d41882, // Vendor ID + 0x80861004, // Subsystem ID + 11, // Number of entries + + /* Pin Widget Verb Table */ + + AZALIA_PIN_CFG(0, 0x11, 0x02214030), + AZALIA_PIN_CFG(0, 0x12, 0x01014010), + AZALIA_PIN_CFG(0, 0x13, 0x511711f0), + AZALIA_PIN_CFG(0, 0x14, 0x02a19040), + AZALIA_PIN_CFG(0, 0x15, 0x0181302e), + AZALIA_PIN_CFG(0, 0x16, 0x41011012), + AZALIA_PIN_CFG(0, 0x17, 0x01a19020), + AZALIA_PIN_CFG(0, 0x18, 0x59331122), + AZALIA_PIN_CFG(0, 0x1a, 0x91f711f0), + AZALIA_PIN_CFG(0, 0x1b, 0x4145f1a0), + AZALIA_PIN_CFG(0, 0x24, 0x41016011), +}; + +const u32 pc_beep_verbs[0] = {}; + +const u32 pc_beep_verbs_size = ARRAY_SIZE(pc_beep_verbs); +const u32 cim_verb_data_size = ARRAY_SIZE(cim_verb_data); -- To view, visit https://review.coreboot.org/c/coreboot/+/44696 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I565690c4ed7b4ae60760b8fa6b1e2d783f8e094b Gerrit-Change-Number: 44696 Gerrit-PatchSet: 1 Gerrit-Owner: Samuel Holland <samuel(a)sholland.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/lenovo/thinkcentre_m91p add ThinkCentre M91p
by Name of user not set (Code Review) 08 Jun '24

08 Jun '24

Name of user not set #1003058 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44302 ) Change subject: mb/lenovo/thinkcentre_m91p add ThinkCentre M91p ...................................................................... mb/lenovo/thinkcentre_m91p add ThinkCentre M91p Add mainboard for ThinkCentre M91p, this port was generated with autoport. This is an OEM board with a Macronix MX25L6406E flash chip Working: - All DIMM slots - libgfxinit - VGA - Flashing with flashrom Untested: - All USB Ports - All PCIe Ports - SATA Ports - Audio output - S3 suspend/resume - Intel GbE Issues: - Randomly hangs before and after a payload has chance to be loaded Signed-off-by: bengris32 <bengrisdale123(a)gmail.com> Change-Id: I48bf9093099abdece3b52d7169c000e25b400feb --- A src/mainboard/lenovo/thinkcentre_m91p/Kconfig A src/mainboard/lenovo/thinkcentre_m91p/Kconfig.name A src/mainboard/lenovo/thinkcentre_m91p/Makefile.inc A src/mainboard/lenovo/thinkcentre_m91p/acpi/ec.asl A src/mainboard/lenovo/thinkcentre_m91p/acpi/platform.asl A src/mainboard/lenovo/thinkcentre_m91p/acpi/superio.asl A src/mainboard/lenovo/thinkcentre_m91p/acpi_tables.c A src/mainboard/lenovo/thinkcentre_m91p/board_info.txt A src/mainboard/lenovo/thinkcentre_m91p/data.vbt A src/mainboard/lenovo/thinkcentre_m91p/devicetree.cb A src/mainboard/lenovo/thinkcentre_m91p/dsdt.asl A src/mainboard/lenovo/thinkcentre_m91p/early_init.c A src/mainboard/lenovo/thinkcentre_m91p/gma-mainboard.ads A src/mainboard/lenovo/thinkcentre_m91p/gpio.c A src/mainboard/lenovo/thinkcentre_m91p/hda_verb.c A src/mainboard/lenovo/thinkcentre_m91p/mainboard.c 16 files changed, 481 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/44302/1 diff --git a/src/mainboard/lenovo/thinkcentre_m91p/Kconfig b/src/mainboard/lenovo/thinkcentre_m91p/Kconfig new file mode 100644 index 0000000..07fc6cf --- /dev/null +++ b/src/mainboard/lenovo/thinkcentre_m91p/Kconfig @@ -0,0 +1,32 @@ +if BOARD_LENOVO_THINKCENTRE_M91P + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select MAINBOARD_HAS_LIBGFXINIT + select INTEL_GMA_HAVE_VBT + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select MAINBOARD_USES_IFD_GBE_REGION + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_BD82X6X + select USE_NATIVE_RAMINIT + +config MAINBOARD_DIR + string + default lenovo/thinkcentre_m91p + +config MAINBOARD_PART_NUMBER + string + default "ThinkCentre M91p" + +config DRAM_RESET_GATE_GPIO # FIXME: check this + int + default 10 + +config USBDEBUG_HCD_INDEX # FIXME: check this + int + default 2 +endif diff --git a/src/mainboard/lenovo/thinkcentre_m91p/Kconfig.name b/src/mainboard/lenovo/thinkcentre_m91p/Kconfig.name new file mode 100644 index 0000000..01956a6 --- /dev/null +++ b/src/mainboard/lenovo/thinkcentre_m91p/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_LENOVO_THINKCENTRE_M91P + bool "ThinkCentre M91p" diff --git a/src/mainboard/lenovo/thinkcentre_m91p/Makefile.inc b/src/mainboard/lenovo/thinkcentre_m91p/Makefile.inc new file mode 100644 index 0000000..18391d8 --- /dev/null +++ b/src/mainboard/lenovo/thinkcentre_m91p/Makefile.inc @@ -0,0 +1,5 @@ +bootblock-y += early_init.c +bootblock-y += gpio.c +romstage-y += early_init.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/lenovo/thinkcentre_m91p/acpi/ec.asl b/src/mainboard/lenovo/thinkcentre_m91p/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/lenovo/thinkcentre_m91p/acpi/ec.asl diff --git a/src/mainboard/lenovo/thinkcentre_m91p/acpi/platform.asl b/src/mainboard/lenovo/thinkcentre_m91p/acpi/platform.asl new file mode 100644 index 0000000..afb8abb --- /dev/null +++ b/src/mainboard/lenovo/thinkcentre_m91p/acpi/platform.asl @@ -0,0 +1,8 @@ +Method(_WAK, 1) +{ + Return(Package() {0, 0}) +} + +Method(_PTS, 1) +{ +} diff --git a/src/mainboard/lenovo/thinkcentre_m91p/acpi/superio.asl b/src/mainboard/lenovo/thinkcentre_m91p/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/lenovo/thinkcentre_m91p/acpi/superio.asl diff --git a/src/mainboard/lenovo/thinkcentre_m91p/acpi_tables.c b/src/mainboard/lenovo/thinkcentre_m91p/acpi_tables.c new file mode 100644 index 0000000..f8364ab --- /dev/null +++ b/src/mainboard/lenovo/thinkcentre_m91p/acpi_tables.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi_gnvs.h> +#include <southbridge/intel/bd82x6x/nvs.h> + +/* FIXME: check this function. */ +void acpi_create_gnvs(struct global_nvs *gnvs) +{ + /* The lid is open by default. */ + gnvs->lids = 1; + + /* Temperature at which OS will shutdown */ + gnvs->tcrt = 100; + /* Temperature at which OS will throttle CPU */ + gnvs->tpsv = 90; +} diff --git a/src/mainboard/lenovo/thinkcentre_m91p/board_info.txt b/src/mainboard/lenovo/thinkcentre_m91p/board_info.txt new file mode 100644 index 0000000..3353f8d --- /dev/null +++ b/src/mainboard/lenovo/thinkcentre_m91p/board_info.txt @@ -0,0 +1,2 @@ +Category: desktop +FIXME: check category, , put ROM package, ROM socketed, ROM protocol, Flashrom support, Release year diff --git a/src/mainboard/lenovo/thinkcentre_m91p/data.vbt b/src/mainboard/lenovo/thinkcentre_m91p/data.vbt new file mode 100644 index 0000000..73336f72 --- /dev/null +++ b/src/mainboard/lenovo/thinkcentre_m91p/data.vbt Binary files differ diff --git a/src/mainboard/lenovo/thinkcentre_m91p/devicetree.cb b/src/mainboard/lenovo/thinkcentre_m91p/devicetree.cb new file mode 100644 index 0000000..7a7da62 --- /dev/null +++ b/src/mainboard/lenovo/thinkcentre_m91p/devicetree.cb @@ -0,0 +1,105 @@ +chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply. + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + register "gpu_cpu_backlight" = "0x00000000" + register "gpu_dp_b_hotplug" = "0" + register "gpu_dp_c_hotplug" = "0" + register "gpu_dp_d_hotplug" = "0" + register "gpu_panel_port_select" = "0" + register "gpu_panel_power_backlight_off_delay" = "0" + register "gpu_panel_power_backlight_on_delay" = "0" + register "gpu_panel_power_cycle_delay" = "0" + register "gpu_panel_power_down_delay" = "0" + register "gpu_panel_power_up_delay" = "0" + register "gpu_pch_backlight" = "0x00000000" + device cpu_cluster 0x0 on + chip cpu/intel/model_206ax # FIXME: check all registers + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0x0 on + end + device lapic 0xacac off + end + end + end + device domain 0x0 on + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "0" + register "gen1_dec" = "0x003c0a01" + register "gen2_dec" = "0x00000000" + register "gen3_dec" = "0x00000000" + register "gen4_dec" = "0x00000000" + register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x8" + register "spi_lvscc" = "0x0" + register "spi_uvscc" = "0x0" + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x17aa 0x3070 + end + device pci 16.1 off # Management Engine Interface 2 + end + device pci 16.2 off # Management Engine IDE-R + end + device pci 16.3 off # Management Engine KT + end + device pci 19.0 on # Intel Gigabit Ethernet + subsystemid 0x17aa 0x3070 + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x17aa 0x3070 + end + device pci 1b.0 on # High Definition Audio + subsystemid 0x17aa 0x3070 + end + device pci 1c.0 off # PCIe Port #1 + end + device pci 1c.1 off # PCIe Port #2 + end + device pci 1c.2 off # PCIe Port #3 + end + device pci 1c.3 off # PCIe Port #4 + end + device pci 1c.4 off # PCIe Port #5 + end + device pci 1c.5 off # PCIe Port #6 + end + device pci 1c.6 off # PCIe Port #7 + end + device pci 1c.7 off # PCIe Port #8 + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x17aa 0x3070 + end + device pci 1e.0 on # PCI bridge + subsystemid 0x17aa 0x3070 + end + device pci 1f.0 on # LPC bridge + subsystemid 0x17aa 0x3070 + end + device pci 1f.2 on # SATA Controller 1 + subsystemid 0x17aa 0x3070 + end + device pci 1f.3 on # SMBus + subsystemid 0x17aa 0x3070 + end + device pci 1f.5 off # SATA Controller 2 + end + device pci 1f.6 off # Thermal + end + end + device pci 00.0 on # Host bridge Host bridge + subsystemid 0x17aa 0x3070 + end + device pci 01.0 off # PEG + end + device pci 02.0 on # iGPU + subsystemid 0x17aa 0x3070 + end + end +end diff --git a/src/mainboard/lenovo/thinkcentre_m91p/dsdt.asl b/src/mainboard/lenovo/thinkcentre_m91p/dsdt.asl new file mode 100644 index 0000000..e648a99 --- /dev/null +++ b/src/mainboard/lenovo/thinkcentre_m91p/dsdt.asl @@ -0,0 +1,28 @@ +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB + + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI 2.0 and up */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 /* OEM revision */ +) +{ + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } +} diff --git a/src/mainboard/lenovo/thinkcentre_m91p/early_init.c b/src/mainboard/lenovo/thinkcentre_m91p/early_init.c new file mode 100644 index 0000000..e3facd4 --- /dev/null +++ b/src/mainboard/lenovo/thinkcentre_m91p/early_init.c @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + + +#include <bootblock_common.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <device/pci.h> +#include <device/pci_def.h> + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, +}; + +void bootblock_mainboard_early_init(void) +{ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f01); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); +} + +/* FIXME: Put proper SPD map here. */ +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x52, id_only); + read_spd(&spd[2], 0x51, id_only); + read_spd(&spd[3], 0x53, id_only); +} diff --git a/src/mainboard/lenovo/thinkcentre_m91p/gma-mainboard.ads b/src/mainboard/lenovo/thinkcentre_m91p/gma-mainboard.ads new file mode 100644 index 0000000..df757d1 --- /dev/null +++ b/src/mainboard/lenovo/thinkcentre_m91p/gma-mainboard.ads @@ -0,0 +1,16 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, + Analog, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/lenovo/thinkcentre_m91p/gpio.c b/src/mainboard/lenovo/thinkcentre_m91p/gpio.c new file mode 100644 index 0000000..fc6b035 --- /dev/null +++ b/src/mainboard/lenovo/thinkcentre_m91p/gpio.c @@ -0,0 +1,179 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio11 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_NATIVE, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, + .gpio40 = GPIO_MODE_GPIO, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio40 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/lenovo/thinkcentre_m91p/hda_verb.c b/src/mainboard/lenovo/thinkcentre_m91p/hda_verb.c new file mode 100644 index 0000000..6786be0 --- /dev/null +++ b/src/mainboard/lenovo/thinkcentre_m91p/hda_verb.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0662, /* Codec Vendor / Device ID: Realtek */ + 0x17aa3070, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x17aa3070), + AZALIA_PIN_CFG(0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0, 0x15, 0x99130120), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x01a19840), + AZALIA_PIN_CFG(0, 0x19, 0x02a19850), + AZALIA_PIN_CFG(0, 0x1a, 0x0181304f), + AZALIA_PIN_CFG(0, 0x1b, 0x0221401f), + AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x4004c601), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + + 0x80862805, /* Codec Vendor / Device ID: Intel */ + 0x17aa3070, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(3, 0x17aa3070), + AZALIA_PIN_CFG(3, 0x05, 0x58560010), + AZALIA_PIN_CFG(3, 0x06, 0x18560020), + AZALIA_PIN_CFG(3, 0x07, 0x58560030), + +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/lenovo/thinkcentre_m91p/mainboard.c b/src/mainboard/lenovo/thinkcentre_m91p/mainboard.c new file mode 100644 index 0000000..e5cfebf --- /dev/null +++ b/src/mainboard/lenovo/thinkcentre_m91p/mainboard.c @@ -0,0 +1,15 @@ +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <southbridge/intel/bd82x6x/pch.h> + +static void mainboard_enable(struct device *dev) +{ + /* FIXME: fix these values. */ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/44302 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I48bf9093099abdece3b52d7169c000e25b400feb Gerrit-Change-Number: 44302 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1003058 Gerrit-MessageType: newchange

6 25

Change in coreboot[master]: adding new mainboard (no official website as it is a noname board but...
by Skoll RC (Code Review) 08 Jun '24

08 Jun '24

Skoll RC has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40813 ) Change subject: adding new mainboard (no official website as it is a noname board but easy to find) see https://github.com/skollrc/coreboot_noname_h61S1_port for more details ...................................................................... adding new mainboard (no official website as it is a noname board but easy to find) see https://github.com/skollrc/coreboot_noname_h61S1_port for more details Signed-off-by: Robin CASSET <amisbievre(a)posteo.net> Change-Id: I1f42ffdbbfb59a1b699ba49650919c1d538c8e6c --- A src/mainboard/ongy/Kconfig A src/mainboard/ongy/Kconfig.name A src/mainboard/ongy/h61m-s1/Kconfig A src/mainboard/ongy/h61m-s1/Kconfig.name A src/mainboard/ongy/h61m-s1/Makefile.inc A src/mainboard/ongy/h61m-s1/acpi/ec.asl A src/mainboard/ongy/h61m-s1/acpi/platform.asl A src/mainboard/ongy/h61m-s1/acpi/superio.asl A src/mainboard/ongy/h61m-s1/acpi_tables.c A src/mainboard/ongy/h61m-s1/board_info.txt A src/mainboard/ongy/h61m-s1/devicetree.cb A src/mainboard/ongy/h61m-s1/dsdt.asl A src/mainboard/ongy/h61m-s1/early_init.c A src/mainboard/ongy/h61m-s1/gma-mainboard.ads A src/mainboard/ongy/h61m-s1/gpio.c A src/mainboard/ongy/h61m-s1/hda_verb.c A src/mainboard/ongy/h61m-s1/mainboard.c 17 files changed, 559 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/40813/1 diff --git a/src/mainboard/ongy/Kconfig b/src/mainboard/ongy/Kconfig new file mode 100644 index 0000000..30ea9f3 --- /dev/null +++ b/src/mainboard/ongy/Kconfig @@ -0,0 +1,14 @@ +if VENDOR_ONGY +choice + prompt "Mainboard model" + +source "src/mainboard/ongy/*/Kconfig.name" + +endchoice + +source "src/mainboard/ongy/*/Kconfig" + +config MAINBOARD_VENDOR + default "H61M-S1" + +endif # VENDOR_ONGY diff --git a/src/mainboard/ongy/Kconfig.name b/src/mainboard/ongy/Kconfig.name new file mode 100644 index 0000000..d0e84b5 --- /dev/null +++ b/src/mainboard/ongy/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_ONGY + bool "ongy" diff --git a/src/mainboard/ongy/h61m-s1/Kconfig b/src/mainboard/ongy/h61m-s1/Kconfig new file mode 100644 index 0000000..65bda16 --- /dev/null +++ b/src/mainboard/ongy/h61m-s1/Kconfig @@ -0,0 +1,56 @@ +## +## This file is part of the coreboot project. +## +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +if BOARD_H61M_S1 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_4096 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select MAINBOARD_HAS_LIBGFXINIT + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_BD82X6X + select USE_NATIVE_RAMINIT + +config MAINBOARD_DIR + string + default ongy/h61m-s1 + +config MAINBOARD_PART_NUMBER + string + default "h61m-s1" + +config VGA_BIOS_FILE + string + default "pci8086,0112.rom" + +config VGA_BIOS_ID + string + default "8086,0112" + +config DRAM_RESET_GATE_GPIO + int + default 60 + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX + int + default 2 +endif diff --git a/src/mainboard/ongy/h61m-s1/Kconfig.name b/src/mainboard/ongy/h61m-s1/Kconfig.name new file mode 100644 index 0000000..36eed8c --- /dev/null +++ b/src/mainboard/ongy/h61m-s1/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_H61M_S1 + bool "h61m-s1" diff --git a/src/mainboard/ongy/h61m-s1/Makefile.inc b/src/mainboard/ongy/h61m-s1/Makefile.inc new file mode 100644 index 0000000..18391d8 --- /dev/null +++ b/src/mainboard/ongy/h61m-s1/Makefile.inc @@ -0,0 +1,5 @@ +bootblock-y += early_init.c +bootblock-y += gpio.c +romstage-y += early_init.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/ongy/h61m-s1/acpi/ec.asl b/src/mainboard/ongy/h61m-s1/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/ongy/h61m-s1/acpi/ec.asl diff --git a/src/mainboard/ongy/h61m-s1/acpi/platform.asl b/src/mainboard/ongy/h61m-s1/acpi/platform.asl new file mode 100644 index 0000000..ac9ff88 --- /dev/null +++ b/src/mainboard/ongy/h61m-s1/acpi/platform.asl @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ +/* The _PTS method (Prepare To Sleep) is called before the OS is +* entering a sleep state. The sleep state number is passed in Arg0 +*/ + +Method(_PTS,1) +{ +} + +/*The _WAK method is called on system wakeup*/ + +Method(_WAK,1) +{ + Return(Package(){0,0}) +} diff --git a/src/mainboard/ongy/h61m-s1/acpi/superio.asl b/src/mainboard/ongy/h61m-s1/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/ongy/h61m-s1/acpi/superio.asl diff --git a/src/mainboard/ongy/h61m-s1/acpi_tables.c b/src/mainboard/ongy/h61m-s1/acpi_tables.c new file mode 100644 index 0000000..3319c25 --- /dev/null +++ b/src/mainboard/ongy/h61m-s1/acpi_tables.c @@ -0,0 +1,22 @@ +/* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; version 2 of the License. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +*/ + +#include <southbridge/intel/bd82x6x/nvs.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; +} diff --git a/src/mainboard/ongy/h61m-s1/board_info.txt b/src/mainboard/ongy/h61m-s1/board_info.txt new file mode 100644 index 0000000..0fc073c --- /dev/null +++ b/src/mainboard/ongy/h61m-s1/board_info.txt @@ -0,0 +1,6 @@ +Category: desktop +Board URL: none +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y \ No newline at end of file diff --git a/src/mainboard/ongy/h61m-s1/devicetree.cb b/src/mainboard/ongy/h61m-s1/devicetree.cb new file mode 100644 index 0000000..38b740f --- /dev/null +++ b/src/mainboard/ongy/h61m-s1/devicetree.cb @@ -0,0 +1,95 @@ +## SPDX-License-Identifier: GPL-2.0-only +## This file is part of the coreboot project. + +chip northbridge/intel/sandybridge + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + register "gpu_cpu_backlight" = "0x00000000" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "gpu_panel_port_select" = "0" + register "gpu_panel_power_backlight_off_delay" = "0" + register "gpu_panel_power_backlight_on_delay" = "0" + register "gpu_panel_power_cycle_delay" = "4" + register "gpu_panel_power_down_delay" = "0" + register "gpu_panel_power_up_delay" = "0" + register "gpu_pch_backlight" = "0x00000000" + device cpu_cluster 0x0 on + chip cpu/intel/model_206ax + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0x0 on end + device lapic 0xacac off end + end + end + device domain 0x0 on + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "0" + register "gen1_dec" = "0x00fc0a01" + register "gen2_dec" = "0x00000000" + register "gen3_dec" = "0x00000000" + register "gen4_dec" = "0x00000000" + register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x33" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x8086 0x1c3a + end + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 off end # Intel Gigabit Ethernet + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x8086 0x1c2d + end + device pci 1b.0 on # High Definition Audio + subsystemid 0x8086 0x1c20 + end + device pci 1c.0 on # PCIe Port #1 + subsystemid 0x8086 0x1c10 + end + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 off end # PCIe Port #3 + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 on # PCIe Port #6 + subsystemid 0x8086 0x1c1a + end + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x8086 0x1c26 + end + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on # LPC bridge + subsystemid 0x8086 0x1c5c + end + device pci 1f.2 on # SATA Controller 1 + subsystemid 0x8086 0x1c02 + end + device pci 1f.3 on # SMBus + subsystemid 0x8086 0x1c22 + end + device pci 1f.5 off end # SATA Controller 2 + + device pci 1f.6 off end # Thermal + end + device pci 00.0 on # Host bridge Host bridge + subsystemid 0x8086 0x0100 + end + device pci 01.0 on # PEG + subsystemid 0x8086 0x0101 + end + device pci 02.0 on # iGPU + subsystemid 0x8086 0x2010 + end + end +end diff --git a/src/mainboard/ongy/h61m-s1/dsdt.asl b/src/mainboard/ongy/h61m-s1/dsdt.asl new file mode 100644 index 0000000..8c67659 --- /dev/null +++ b/src/mainboard/ongy/h61m-s1/dsdt.asl @@ -0,0 +1,43 @@ +/* +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; version 2 of the License. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +*/ + +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 + +#include <arch/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 // OEM revision +) +{ + #include "acpi/mainboard.asl" + #include "acpi/platform.asl" + #include "acpi/superio.asl" + #include "acpi/thermal.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + + /* global NVS and variables. */ + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } +} diff --git a/src/mainboard/ongy/h61m-s1/early_init.c b/src/mainboard/ongy/h61m-s1/early_init.c new file mode 100644 index 0000000..6cb36f1 --- /dev/null +++ b/src/mainboard/ongy/h61m-s1/early_init.c @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <stdint.h> +#include <string.h> +#include <timestamp.h> +#include <arch/byteorder.h> +#include <device/mmio.h> +#include <device/pci_ops.h> +#include <device/pnp_ops.h> +#include <console/console.h> +#include <bootblock_common.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/gpio.h> + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, 0 }, + { 1, 0, 0 }, + { 1, 0, 1 }, + { 1, 0, 1 }, + { 1, 0, 2 }, + { 1, 0, 2 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 0, 4 }, + { 1, 0, 4 }, + { 1, 0, 6 }, + { 1, 0, 5 }, + { 1, 0, 5 }, + { 1, 0, 6 }, +}; + +void bootblock_mainboard_early_init(void) +{ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1401); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000); +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[2], 0x52, id_only); +} diff --git a/src/mainboard/ongy/h61m-s1/gma-mainboard.ads b/src/mainboard/ongy/h61m-s1/gma-mainboard.ads new file mode 100644 index 0000000..e2c84c6 --- /dev/null +++ b/src/mainboard/ongy/h61m-s1/gma-mainboard.ads @@ -0,0 +1,15 @@ +-- SPDX-License-Identifier: GPL-2.0-only +-- This file is part of the coreboot project. + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + ports : constant Port_List := + (HDMI1, + Analog, + others => Disabled); +end GMA.Mainboard; diff --git a/src/mainboard/ongy/h61m-s1/gpio.c b/src/mainboard/ongy/h61m-s1/gpio.c new file mode 100644 index 0000000..22f4838 --- /dev/null +++ b/src/mainboard/ongy/h61m-s1/gpio.c @@ -0,0 +1,178 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_NATIVE, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/ongy/h61m-s1/hda_verb.c b/src/mainboard/ongy/h61m-s1/hda_verb.c new file mode 100644 index 0000000..09748c0 --- /dev/null +++ b/src/mainboard/ongy/h61m-s1/hda_verb.c @@ -0,0 +1,43 @@ +/* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; version 2 of +* the License. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +*/ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0662, /* Codec Vendor / Device ID: Realtek*/ + 0x10ec0000, /* Subsystem ID*/ + 12, /* Number of 4 dword sets*/ + AZALIA_SUBVENDOR(2, 0x10ec0000), + AZALIA_PIN_CFG(2, 0x12, 0x40130000), + AZALIA_PIN_CFG(2, 0x14, 0x01014010), + AZALIA_PIN_CFG(2, 0x15, 0x411111f0), + AZALIA_PIN_CFG(2, 0x16, 0x411111f0), + AZALIA_PIN_CFG(2, 0x18, 0x01a19040), + AZALIA_PIN_CFG(2, 0x19, 0x02a19050), + AZALIA_PIN_CFG(2, 0x1a, 0x0181304f), + AZALIA_PIN_CFG(2, 0x1b, 0x02214020), + AZALIA_PIN_CFG(2, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(2, 0x1d, 0x4044c601), + AZALIA_PIN_CFG(2, 0x1e, 0x01441130), + + 0x80862805, /* Codec Vendor / Device ID: Intel*/ + 0x80860101, /* Subsystem ID*/ + 4, /* Number of 4 dword sets*/ + AZALIA_SUBVENDOR(3, 0x80860101), + AZALIA_PIN_CFG(3, 0x05, 0x18560010), + AZALIA_PIN_CFG(3, 0x06, 0x18560020), + AZALIA_PIN_CFG(3, 0x07, 0x18560030), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/ongy/h61m-s1/mainboard.c b/src/mainboard/ongy/h61m-s1/mainboard.c new file mode 100644 index 0000000..3f9c24e --- /dev/null +++ b/src/mainboard/ongy/h61m-s1/mainboard.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <southbridge/intel/bd82x6x/pch.h> + +static void mainboard_enable(struct device *dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/40813 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1f42ffdbbfb59a1b699ba49650919c1d538c8e6c Gerrit-Change-Number: 40813 Gerrit-PatchSet: 1 Gerrit-Owner: Skoll RC Gerrit-MessageType: newchange

8 117

Change in coreboot[master]: soc/intel/braswell: Increase dcache size
by Shelley Chen (Code Review) 08 May '24

08 May '24

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45827 ) Change subject: soc/intel/braswell: Increase dcache size ...................................................................... soc/intel/braswell: Increase dcache size Need to increase the DRAM cache size for braswell as the was getting the compilation error "Cache as RAM area is too full" when moving the mrc_cache writeback to romstage. We need to increase this first before landing the CL moving mrc_cache writeback to romstage. BUG=b:150502246 BRANCH=None TEST=Able to successfully compile braswell boards Change-Id: I1538d504ddad8654c79a789e58ffe6b11b5d544c Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/soc/intel/braswell/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/45827/1 diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 5c9988c..077b5a1 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -96,7 +96,7 @@ config DCACHE_RAM_SIZE hex - default 0x4000 + default 0x5000 help The size of the cache-as-ram region required during bootblock and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE -- To view, visit https://review.coreboot.org/c/coreboot/+/45827 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1538d504ddad8654c79a789e58ffe6b11b5d544c Gerrit-Change-Number: 45827 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: newchange

5 9

Change in coreboot[master]: nb/intel/sandybridge: Improve channel disable logic
by Angel Pons (Code Review) 11 Apr '24

11 Apr '24

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45500 ) Change subject: nb/intel/sandybridge: Improve channel disable logic ...................................................................... nb/intel/sandybridge: Improve channel disable logic Do not consider the failed channel's SPDs in emergency mode. Also, force a full training if not resuming from S3 and the saved data indicates a channel has failed. Special care needs to be taken as the selected memory frequency could be raised after a channel has been disabled. Tested on Asus P8Z77-V LX2, with a good DIMM on channel 0 and a bad DIMM on channel 1. The failing channel causes errors when discovering timB, and emergency mode raminit for the other channel is good enough to boot. With this commit: a. Regular boots always result in full training. b. The board still boots, as emergency raminit trained the good DIMM. c. S3 resume still works in all tested configurations. d. If pretending the bad DIMM is slower: 1. The MPLL gets locked at the slow frequency of the bad DIMM. 2. The first raminit attempt still fails miserably on the bad DIMM. 3. Emergency mode uses the frequency the MPLL is locked at. 4. The board boots with the good DIMM running at the slow frequency. With good DIMMs on both channels, everything works the same as before. Change-Id: I3d34594561680906cb0b15a9c6a5fa7a773c0496 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/raminit_common.h M src/northbridge/intel/sandybridge/raminit_native.c 3 files changed, 38 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/45500/1 diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 319fea3..51c57c6 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -43,15 +43,7 @@ /* Disable a channel in ramctr_timing */ static void disable_channel(ramctr_timing *ctrl, int channel) { - ctrl->rankmap[channel] = 0; - - memset(&ctrl->rank_mirror[channel][0], 0, sizeof(ctrl->rank_mirror[0])); - - ctrl->channel_size_mb[channel] = 0; - ctrl->cmd_stretch[channel] = 0; - ctrl->mad_dimm[channel] = 0; - memset(&ctrl->timings[channel][0], 0, sizeof(ctrl->timings[0])); - memset(&ctrl->info.dimm[channel][0], 0, sizeof(ctrl->info.dimm[0])); + ctrl->failed_channels |= BIT(channel); } static bool nb_supports_ecc(const uint32_t capid0_a) @@ -163,6 +155,10 @@ FOR_ALL_CHANNELS { ctrl->channel_size_mb[channel] = 0; + /* Skip decoding the SPDs of failed channels */ + if (ctrl->failed_channels & BIT(channel)) + continue; + ch_dimms = 0; /* Count dimms on channel */ for (slot = 0; slot < NUM_SLOTS; slot++) { @@ -345,8 +341,21 @@ system_reset(); } + /* + * Discard the saved data if it is from raminit emergency mode. + * Ideally, we would not advertise support for ACPI S3 in such + * cases, because there is evidence that the RAM has stability + * problems. Until then, skip this sanity check on S3 resumes. + */ + if (!s3resume && ctrl_cached && ctrl_cached->failed_channels) { + printk(BIOS_ERR, "Stored timings indicate channels have failed.\n"); + + ctrl_cached = NULL; + } + /* Verify MRC cache for fast boot */ if (!s3resume && ctrl_cached) { + /* Load SPD unique information data. */ memset(spds, 0, sizeof(spds)); mainboard_get_spd(spds, 1); @@ -391,6 +400,13 @@ } if (err) { + /* + * We can't reinitialize the DRAM MPLL at a different frequency. + * As we want to ignore the SPDs on the failed channel, we have + * to use the same tCK in emergency mode to avoid some troubles. + */ + const u32 old_tCK = ctrl.tCK; + /* Fallback: disable failing channel */ printk(BIOS_ERR, "RAM training failed, trying fallback.\n"); printram("Disable failing channel.\n"); @@ -398,12 +414,15 @@ /* Reset internal state */ reinit_ctrl(&ctrl, cpuid); - /* Reset DDR3 frequency */ - dram_find_spds_ddr3(spds, &ctrl); - /* Disable failing channel */ disable_channel(&ctrl, GET_ERR_CHANNEL(err)); + /* Restore tCK */ + ctrl.tCK = old_tCK; + + /* Recalculate DDR3 frequency */ + dram_find_spds_ddr3(spds, &ctrl); + err = try_init_dram_ddr3(&ctrl, fast_boot, s3resume, me_uma_size); } diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index 32f2b44..cf3d6a9 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -105,7 +105,7 @@ /* * WARNING: Do not forget to increase MRC_CACHE_VERSION when the saved data is changed! */ -#define MRC_CACHE_VERSION 5 +#define MRC_CACHE_VERSION 6 typedef struct odtmap_st { u16 rttwr; @@ -185,6 +185,9 @@ /* Bits [0..11] of PM_DLL_CONFIG: Master DLL wakeup delay timer */ u16 mdll_wake_delay; + /* Bitmap of channels that have failed */ + u8 failed_channels; + u8 rankmap[NUM_CHANNELS]; int ref_card_offset[NUM_CHANNELS]; u32 mad_dimm[NUM_CHANNELS]; diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index c23a5ac..a469910 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -265,7 +265,9 @@ printk(BIOS_DEBUG, "PLL_REF100_CFG value: 0x%x\n", ref_100mhz_support); - ctrl->tCK = get_mem_min_tck(); + /* In emergency mode, use provided tCK if non-zero. Otherwise, calculate it. */ + if (!ctrl->failed_channels || !ctrl->tCK) + ctrl->tCK = get_mem_min_tck(); /* Find CAS latency */ while (1) { -- To view, visit https://review.coreboot.org/c/coreboot/+/45500 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d34594561680906cb0b15a9c6a5fa7a773c0496 Gerrit-Change-Number: 45500 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 8

Change in libgfxinit[master]: Add Bay Trail options
by Angel Pons (Code Review) 11 Apr '24

11 Apr '24

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/libgfxinit/+/44790 ) Change subject: Add Bay Trail options ...................................................................... Add Bay Trail options This will build the G45 code, though. Actual Bay Trail code will be added in subsequent commits. Change-Id: Ib30ea668da9641ccf1f94f8f25cfb897faa54aaa Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M common/Makefile.inc M common/hw-gfx-gma-config.ads.template M common/hw-gfx-gma-config_helpers.adb M common/hw-gfx-gma-panel.adb M common/hw-gfx-gma-registers.adb M common/hw-gfx-gma-registers.ads M common/hw-gfx-gma.adb M common/hw-gfx-gma.ads A common/valleyview/Makefile.inc A configs/baytrail 10 files changed, 154 insertions(+), 50 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/90/44790/1 diff --git a/common/Makefile.inc b/common/Makefile.inc index f2a2fbb..8935dda 100644 --- a/common/Makefile.inc +++ b/common/Makefile.inc @@ -57,13 +57,14 @@ CONFIG_GFX_GMA_ANALOG_I2C_PORT := $(call strip_quotes,$(CONFIG_GFX_GMA_ANALOG_I2C_PORT)) CONFIG_GFX_GMA_IGNORE_PRESENCE_STRAPS := $(if $(filter y,$(CONFIG_GFX_GMA_IGNORE_PRESENCE_STRAPS)),True,False) -_GEN_TLA_SUBSTITUTIONS := $g45\|ilk\|hsw\|skl$ +_GEN_TLA_SUBSTITUTIONS := $g45\|vlv\|ilk\|hsw\|skl$ _GEN_NONCONST := $(strip \ $(if $(filter G45,$(CONFIG_GFX_GMA_GENERATION)),g45, \ + $(if $(filter Valleyview,$(CONFIG_GFX_GMA_GENERATION)),vlv, \ $(if $(filter Ironlake,$(CONFIG_GFX_GMA_GENERATION)),ilk, \ $(if $(filter Haswell,$(CONFIG_GFX_GMA_GENERATION)),hsw, \ - $(if $(filter Skylake,$(CONFIG_GFX_GMA_GENERATION)),skl))))) + $(if $(filter Skylake,$(CONFIG_GFX_GMA_GENERATION)),skl)))))) # GNATprove (GPL 2017) doesn't realize when a boolean expression # that depends both on static values and variables can be evalu- # ated at compile time (e.g. `False and then Variable` is always @@ -113,6 +114,8 @@ ifneq ($(filter G45,$(CONFIG_GFX_GMA_GENERATION)),) subdirs-y += g45 +else ifneq ($(filter Valleyview,$(CONFIG_GFX_GMA_GENERATION)),) +subdirs-y += valleyview else ifneq ($(filter Ironlake,$(CONFIG_GFX_GMA_GENERATION)),) subdirs-y += ironlake else ifneq ($(filter Haswell,$(CONFIG_GFX_GMA_GENERATION)),) diff --git a/common/hw-gfx-gma-config.ads.template b/common/hw-gfx-gma-config.ads.template index a39ecd9..b260e76 100644 --- a/common/hw-gfx-gma-config.ads.template +++ b/common/hw-gfx-gma-config.ads.template @@ -20,18 +20,20 @@ CPU_First : constant CPU_Type := (case Gen is - when G45 => G45, - when Ironlake => Ironlake, - when Haswell => Haswell, - when Broxton => Broxton, - when Skylake => Skylake); + when G45 => G45, + when Valleyview => Baytrail, + when Ironlake => Ironlake, + when Haswell => Haswell, + when Broxton => Broxton, + when Skylake => Skylake); CPU_Last : constant CPU_Type := (case Gen is - when G45 => GM45, - when Ironlake => Ivybridge, - when Haswell => Broadwell, - when Broxton => Broxton, - when Skylake => Kabylake); + when G45 => GM45, + when Valleyview => Baytrail, + when Ironlake => Ivybridge, + when Haswell => Broadwell, + when Broxton => Broxton, + when Skylake => Kabylake); CPU_Var_Last : constant CPU_Variant := (case Gen is when Haswell | Skylake => ULX, @@ -118,6 +120,7 @@ -- values start after a line break. Gen_G45 : <genbool> := Gen = G45; + Gen_Valleyview : <genbool> := Gen = Valleyview; Gen_Ironlake : <genbool> := Gen = Ironlake; Gen_Haswell : <genbool> := Gen = Haswell; Gen_Broxton : <genbool> := Gen = Broxton; @@ -160,8 +163,9 @@ Is_LP : <hswsklbool> := Is_ULT or Is_ULX; ---------- CPU pipe: --------- - Has_Tertiary_Pipe : <ilkbool> := Ivybridge_On; - Disable_Trickle_Feed : <genbool> := not Gen_Haswell; + Has_Tertiary_Pipe : <ilkbool> := Ivybridge_On; -- VLV: False -- c.f. EDS or similar +-- Disable_Trickle_Feed : <genbool> := not Gen_Haswell; -- VLV: True -- intel_display_power.c: vlv_init_display_clock_gating() + Disable_Trickle_Feed : <genbool> := not Gen_Haswell and not Gen_Valleyview; -- VLV: False -- wise icon says: intel_display.c: i9xx_plane_ctl() conditions around 'DISPPLANE_TRICKLE_FEED_DISABLE' Pipe_Enabled_Workaround : <hswbool> := CPU_Broadwell; Has_EDP_Transcoder : <genbool> := Haswell_On; Use_PDW_For_EDP_Scaling : <hswbool> := CPU_Haswell; @@ -176,9 +180,15 @@ Has_Ivybridge_Cursors : <ilkbool> := Ivybridge_On; VGA_Plane_Workaround : <ilkbool> := CPU_Ivybridge; Has_GMCH_DP_Transcoder : <genbool> := Gen_G45; - Has_GMCH_VGACNTRL : <genbool> := Gen_G45; - Has_GMCH_PFIT_CONTROL : <genbool> := Gen_G45; + Has_GMCH_VGACNTRL : <genbool> := Gen_G45 or Gen_Valleyview; + Has_GMCH_PFIT_CONTROL : <genbool> := Gen_G45 or Gen_Valleyview; + -- wise icon checks bay trail and says: + -- + -- Looks like there are two sets of PP controls and they are tied to the + -- chosen display pipe (instead of the set of physical pins as usual). + -- This will screw us eventually, but nothing to worry about now. + -- --------- Panel power: ------- Has_PP_Write_Protection : <genbool> := Up_To_Ironlake; Has_PP_Port_Select : <genbool> := Up_To_Ironlake; @@ -188,7 +198,7 @@ Has_New_Backlight_Control : <genbool> := Gen_Broxton; ----------- PCH/FDI: --------- - Has_PCH : <genbool> := not Gen_Broxton and not Gen_G45; + Has_PCH : <genbool> := not (Gen_Broxton or Gen_Valleyview or Gen_G45); Has_PCH_DAC : <hswbool> := (Gen_Ironlake or (Gen_Haswell and then not Is_LP)); @@ -209,7 +219,7 @@ Has_FDI_RX_Power_Down : <genbool> := Gen_Haswell; ---------- Clocks: ----------- - Has_GMCH_RawClk : <genbool> := Gen_G45; + Has_GMCH_RawClk : <genbool> := Gen_G45 or Gen_Valleyview; Has_GMCH_Mobile_VCO : <g45bool> := GMCH_GM45; Has_Broadwell_CDClk : <hswbool> := CPU_Broadwell; Can_Switch_CDClk : <hswbool> := Broadwell_On; @@ -298,6 +308,7 @@ Default_CDClk_Freq : <ilkhswvar> CDClk_Range := (if Gen_G45 then 320_000_000 -- unused + elsif Gen_Valleyview then 320_000_000 -- runtime configurable elsif CPU_Ironlake then 450_000_000 elsif CPU_Sandybridge or CPU_Ivybridge then 400_000_000 elsif Gen_Haswell and then Is_ULX then 337_500_000 @@ -308,6 +319,7 @@ Default_RawClk_Freq : <hswvar> Frequency_Type := (if Gen_G45 then 100_000_000 -- unused, depends on FSB + elsif Gen_Valleyview then 100_000_000 -- not constant, must be looked at runtime elsif Gen_Ironlake then 125_000_000 elsif Gen_Haswell then (if Is_LP then 24_000_000 else 125_000_000) elsif Gen_Broxton then Frequency_Type'First -- none needed @@ -326,7 +338,7 @@ (Primary => 4096, Secondary => 2048, Tertiary => Pos32'First) - elsif Gen_Ironlake or CPU_Haswell then + elsif Gen_Valleyview or Gen_Ironlake or CPU_Haswell then (Primary => 4096, Secondary => 2048, Tertiary => 2048) @@ -349,12 +361,12 @@ HDMI_Max_Clock_24bpp : constant Frequency_Type := (case Gen is when Generation'First .. G45 => 165_000_000, - when Ironlake => 225_000_000, + when Valleyview .. Ironlake => 225_000_000, when Haswell .. Generation'Last => 300_000_000); ---------------------------------------------------------------------------- - Display_Base_Offset : constant := 0; + Display_Base_Offset : constant := (if Gen_Valleyview then 16#18_0000# else 0); GTT_PTE_Size : <hswvar> Natural := (if Has_64bit_GTT then 8 else 4); @@ -379,6 +391,10 @@ -- From Haswell on, we have to distinguish between -- Normal, ULT (U CPU lines) and ULX (Y CPU lines). + function Is_Baytrail (Device_Id : Word16) return Boolean is -- VLV: i915_pciids.h: INTEL_VLV_IDS + ((Device_Id and 16#fffc#) = 16#0f30# or + (Device_Id and 16#fffd#) = 16#0155#); + function Is_Haswell_Y (Device_Id : Word16) return Boolean is ((Device_Id and 16#ffef#) = 16#0a0e#); function Is_Haswell_U (Device_Id : Word16) return Boolean is @@ -450,6 +466,7 @@ (case CPU is when G45 => (Device_Id and 16#ff02#) = 16#2e02#, when GM45 => (Device_Id and 16#fffe#) = 16#2a42#, + when Baytrail => Is_Baytrail (Device_Id), when Ironlake => (Device_Id and 16#fff3#) = 16#0042#, when Sandybridge => (Device_Id and 16#ffc2#) = 16#0102#, when Ivybridge => (Device_Id and 16#ffc3#) = 16#0142#, diff --git a/common/hw-gfx-gma-config_helpers.adb b/common/hw-gfx-gma-config_helpers.adb index 2a09305..4141e15 100644 --- a/common/hw-gfx-gma-config_helpers.adb +++ b/common/hw-gfx-gma-config_helpers.adb @@ -29,7 +29,7 @@ begin return (case Config.Gen is - when G45 => -- everything on GMCH + when G45 | Valleyview => -- everything on GMCH or SoC (case Port is when LVDS => LVDS, when eDP => DIGI_A, -- n/a, actually diff --git a/common/hw-gfx-gma-panel.adb b/common/hw-gfx-gma-panel.adb index e343deb..e5670ae 100644 --- a/common/hw-gfx-gma-panel.adb +++ b/common/hw-gfx-gma-panel.adb @@ -114,12 +114,18 @@ DIVISOR => Registers.PCH_PP_DIVISOR)) -- won't be used else - (Panel_1 .. Panel_2 => + (Panel_1 => (STATUS => Registers.GMCH_PP_STATUS, CONTROL => Registers.GMCH_PP_CONTROL, ON_DELAYS => Registers.GMCH_PP_ON_DELAYS, OFF_DELAYS => Registers.GMCH_PP_OFF_DELAYS, - DIVISOR => Registers.GMCH_PP_DIVISOR))); + DIVISOR => Registers.GMCH_PP_DIVISOR), + Panel_2 => + (STATUS => Registers.VLV_PIPE_B_PP_STATUS, + CONTROL => Registers.VLV_PIPE_B_PP_CONTROL, + ON_DELAYS => Registers.VLV_PIPE_B_PP_ON_DLY, + OFF_DELAYS => Registers.VLV_PIPE_B_PP_OFF_DLY, + DIVISOR => Registers.VLV_PIPE_B_PP_DIVISOR))); function PCH_PP_ON_DELAYS_PWR_UP (US : Natural) return Word32 is begin @@ -256,11 +262,14 @@ end if; if Override_Delays then - if Config.Has_PP_Port_Select then + if Config.Gen_Valleyview then + Port_Select := PCH_PP_ON_DELAYS_PORT_SELECT_DP_C; + elsif Config.Has_PP_Port_Select then Port_Select := (case Config.Panel_Ports (Panel_1) is when LVDS => PCH_PP_ON_DELAYS_PORT_SELECT_LVDS, when eDP => PCH_PP_ON_DELAYS_PORT_SELECT_DP_A, + when DP1 | HDMI1 => PCH_PP_ON_DELAYS_PORT_SELECT_DP_A, -- FIXME: VLV HACK when DP2 | HDMI2 => PCH_PP_ON_DELAYS_PORT_SELECT_DP_C, when DP3 | HDMI3 => PCH_PP_ON_DELAYS_PORT_SELECT_DP_D, when others => 0); diff --git a/common/hw-gfx-gma-registers.adb b/common/hw-gfx-gma-registers.adb index 641f192..66d16e8 100644 --- a/common/hw-gfx-gma-registers.adb +++ b/common/hw-gfx-gma-registers.adb @@ -252,15 +252,18 @@ ---------------------------------------------------------------------------- -- Write a specific register - procedure Write (Register : Registers_Index; Value : Word32) + procedure Write + (Register : Registers_Index; + Value : Word32; + Verbose : Boolean := True) is begin - pragma Debug (Debug.Put (GNAT.Source_Info.Enclosing_Entity & ": ")); - pragma Debug (Debug.Put_Word32 (Value)); - pragma Debug (Debug.Put (" -> ")); - pragma Debug (Debug.Put_Word32 (Register'Enum_Rep * Register_Width)); - pragma Debug (Debug.Put (":")); - pragma Debug (Debug.Put_Line (Registers_Index'Image (Register))); + pragma Debug (Verbose, Debug.Put (GNAT.Source_Info.Enclosing_Entity & ": ")); + pragma Debug (Verbose, Debug.Put_Word32 (Value)); + pragma Debug (Verbose, Debug.Put (" -> ")); + pragma Debug (Verbose, Debug.Put_Word32 (Register'Enum_Rep * Register_Width)); + pragma Debug (Verbose, Debug.Put (":")); + pragma Debug (Verbose, Debug.Put_Line (Registers_Index'Image (Register))); Regs.Write (Rep.Index (Register), Value); pragma Debug (Debug.Register_Write_Wait); @@ -289,7 +292,7 @@ pragma Warnings (GNATprove, Off, "unused assignment to ""Ignored_Success"""); -- Wait for the bits in @Register@ indicated by @Mask@ to be of @Value@ - procedure Wait + procedure Wait_Quietly (Register : in Registers_Index; Mask : in Word32; Value : in Word32; @@ -301,14 +304,6 @@ Timeout : Time.T; Timed_Out : Boolean := False; begin - pragma Debug (Debug.Put (GNAT.Source_Info.Enclosing_Entity & ": ")); - pragma Debug (Debug.Put_Word32 (Value)); - pragma Debug (Debug.Put (" <- ")); - pragma Debug (Debug.Put_Word32 (Mask)); - pragma Debug (Debug.Put (" & ")); - pragma Debug (Debug.Put_Word32 (Register'Enum_Rep * Register_Width)); - pragma Debug (Debug.Put (":")); - pragma Debug (Debug.Put_Line (Registers_Index'Image (Register))); Timeout := Time.MS_From_Now (TOut_MS); loop @@ -318,14 +313,36 @@ Timed_Out := False; exit; end if; - pragma Debug (Timed_Out, Debug.Put (GNAT.Source_Info.Enclosing_Entity)); - pragma Debug (Timed_Out, Debug.Put_Line (": Timed Out!")); exit when Timed_Out; Timed_Out := Time.Timed_Out (Timeout); end loop; Success := not Timed_Out; + end Wait_Quietly; + + procedure Wait + (Register : in Registers_Index; + Mask : in Word32; + Value : in Word32; + TOut_MS : in Natural := Default_Timeout_MS; + Verbose : in Boolean := False; + Success : out Boolean) + is + begin + pragma Debug (Debug.Put (GNAT.Source_Info.Enclosing_Entity & ": ")); + pragma Debug (Debug.Put_Word32 (Value)); + pragma Debug (Debug.Put (" <- ")); + pragma Debug (Debug.Put_Word32 (Mask)); + pragma Debug (Debug.Put (" & ")); + pragma Debug (Debug.Put_Word32 (Register'Enum_Rep * Register_Width)); + pragma Debug (Debug.Put (":")); + pragma Debug (Debug.Put_Line (Registers_Index'Image (Register))); + + Wait_Quietly (Register, Mask, Value, TOut_MS, Verbose, Success); + + pragma Debug (not Success, Debug.Put (GNAT.Source_Info.Enclosing_Entity)); + pragma Debug (not Success, Debug.Put_Line (": Timed Out!")); end Wait; procedure Wait diff --git a/common/hw-gfx-gma-registers.ads b/common/hw-gfx-gma-registers.ads index 68e5664..b158300 100644 --- a/common/hw-gfx-gma-registers.ads +++ b/common/hw-gfx-gma-registers.ads @@ -46,6 +46,10 @@ MI_MODE, INSTPM, GT_MODE, + VLV_IOSF_DOORBELL_REQ, + VLV_IOSF_DATA, + VLV_IOSF_ADDR, + VLV_DPIO_CTL, CACHE_MODE_0, CTX_SIZE, PP_DCLV_HIGH, @@ -188,6 +192,11 @@ GMCH_PP_OFF_DELAYS, GMCH_PP_DIVISOR, GMCH_PFIT_CONTROL, + VLV_PIPE_B_PP_STATUS, + VLV_PIPE_B_PP_CONTROL, + VLV_PIPE_B_PP_ON_DLY, + VLV_PIPE_B_PP_OFF_DLY, + VLV_PIPE_B_PP_DIVISOR, PIPEB_DDI_FUNC_CTL, PIPEB_MSA_MISC, SRD_CTL_B, @@ -757,7 +766,8 @@ BXT_PORT_PCS_DW12_GRP_A, BXT_PORT_TX_DW2_GRP_A, BXT_PORT_TX_DW3_GRP_A, - BXT_PORT_TX_DW4_GRP_A); + BXT_PORT_TX_DW4_GRP_A + ); pragma Warnings (GNATprove, Off, "pragma ""KEEP_NAMES"" ignored *(not yet supported)", @@ -772,6 +782,16 @@ (Invalid_Register => 0, --------------------------------------------------------------------------- + -- Valleyview registers + --------------------------------------------------------------------------- + + VLV_IOSF_DOORBELL_REQ => 16#00_2100# / Register_Width, + VLV_IOSF_DATA => 16#00_2104# / Register_Width, + VLV_IOSF_ADDR => 16#00_2108# / Register_Width, + + VLV_DPIO_CTL => 16#00_2110# / Register_Width, + + --------------------------------------------------------------------------- -- Pipe A registers --------------------------------------------------------------------------- @@ -800,8 +820,8 @@ PIPEA_DATA_N1 => 16#06_0034# / Register_Width, PIPEA_LINK_M1 => 16#06_0040# / Register_Width, PIPEA_LINK_N1 => 16#06_0044# / Register_Width, - PIPEA_GMCH_DATA_M => 16#07_0050# / Register_Width, - PIPEA_GMCH_DATA_N => 16#07_0054# / Register_Width, + PIPEA_GMCH_DATA_M => 16#07_0050# / Register_Width, -- aliased by VLV_DDL1 + PIPEA_GMCH_DATA_N => 16#07_0054# / Register_Width, -- aliased by VLV_DDL2 PIPEA_GMCH_LINK_M => 16#07_0060# / Register_Width, PIPEA_GMCH_LINK_N => 16#07_0064# / Register_Width, PIPEA_DDI_FUNC_CTL => 16#06_0400# / Register_Width, @@ -1436,6 +1456,11 @@ GMCH_PP_OFF_DELAYS => 16#06_120c# / Register_Width, GMCH_PP_DIVISOR => 16#06_1210# / Register_Width, GMCH_PFIT_CONTROL => 16#06_1230# / Register_Width, + VLV_PIPE_B_PP_STATUS => 16#06_1300# / Register_Width, + VLV_PIPE_B_PP_CONTROL => 16#06_1304# / Register_Width, + VLV_PIPE_B_PP_ON_DLY => 16#06_1308# / Register_Width, + VLV_PIPE_B_PP_OFF_DLY => 16#06_130c# / Register_Width, + VLV_PIPE_B_PP_DIVISOR => 16#06_1310# / Register_Width, PCH_PP_STATUS => 16#0c_7200# / Register_Width, -- aliased with BXT_PP_STATUS_1 PCH_PP_CONTROL => 16#0c_7204# / Register_Width, -- aliased with BXT_PP_CONTROL_1 PCH_PP_ON_DELAYS => 16#0c_7208# / Register_Width, -- aliased with BXT_PP_ON_DELAYS_1 @@ -1668,6 +1693,8 @@ GMCH_ADPA : constant Registers_Index := FDI_TX_CTL_B; GMCH_HDMIB : constant Registers_Index := GMCH_SDVOB; GMCH_HDMIC : constant Registers_Index := GMCH_SDVOC; + VLV_DDL1 : constant Registers_Index := PIPEA_GMCH_DATA_M; + VLV_DDL2 : constant Registers_Index := PIPEA_GMCH_DATA_N; CURACNTR : constant Registers_Index := CUR_CTL_A; CURABASE : constant Registers_Index := CUR_BASE_A; CURAPOS : constant Registers_Index := CUR_POS_A; @@ -1704,10 +1731,11 @@ procedure Write (Register : Registers_Index; - Value : Word32) + Value : Word32; + Verbose : Boolean := True) with Global => (In_Out => Register_State), - Depends => (Register_State => (Register, Register_State, Value)), + Depends => (Register_State => (Register, Register_State, Value), null => Verbose), Pre => True, Post => True; @@ -1718,6 +1746,14 @@ pragma Warnings (GNATprove, Off, "unused initial value of ""Verbose""", Reason => "Only used on debugging path"); + + procedure Wait_Quietly + (Register : in Registers_Index; + Mask : in Word32; + Value : in Word32; + TOut_MS : in Natural := Default_Timeout_MS; + Verbose : in Boolean := False; + Success : out Boolean); procedure Wait (Register : in Registers_Index; Mask : in Word32; diff --git a/common/hw-gfx-gma.adb b/common/hw-gfx-gma.adb index 9157bbe..a363738 100644 --- a/common/hw-gfx-gma.adb +++ b/common/hw-gfx-gma.adb @@ -422,7 +422,7 @@ Audio_VID_DID : Word32; begin case Config.Gen is - when G45 => + when G45 .. Valleyview => Registers.Read (Registers.G4X_AUD_VID_DID, Audio_VID_DID); when Ironlake => Registers.Read (Registers.PCH_AUD_VID_DID, Audio_VID_DID); diff --git a/common/hw-gfx-gma.ads b/common/hw-gfx-gma.ads index 1215fc5..d7f7ab8 100644 --- a/common/hw-gfx-gma.ads +++ b/common/hw-gfx-gma.ads @@ -33,11 +33,12 @@ subtype GTT_Range is Natural range 0 .. 16#8_0000# - 1; GTT_Rotation_Offset : constant GTT_Range := GTT_Range'Last / 2 + 1; - type Generation is (G45, Ironlake, Haswell, Broxton, Skylake); + type Generation is (G45, Valleyview, Ironlake, Haswell, Broxton, Skylake); type CPU_Type is (G45, GM45, + Baytrail, Ironlake, Sandybridge, Ivybridge, diff --git a/common/valleyview/Makefile.inc b/common/valleyview/Makefile.inc new file mode 100644 index 0000000..766ade0 --- /dev/null +++ b/common/valleyview/Makefile.inc @@ -0,0 +1,15 @@ +gfxinit-y += ../g45/hw-gfx-gma-connectors.adb +gfxinit-y += ../g45/hw-gfx-gma-gmch-dp.adb +gfxinit-y += ../g45/hw-gfx-gma-gmch-dp.ads +gfxinit-y += ../g45/hw-gfx-gma-gmch-hdmi.adb +gfxinit-y += ../g45/hw-gfx-gma-gmch-hdmi.ads +gfxinit-y += ../g45/hw-gfx-gma-gmch-lvds.adb +gfxinit-y += ../g45/hw-gfx-gma-gmch-lvds.ads +gfxinit-y += ../g45/hw-gfx-gma-gmch-vga.adb +gfxinit-y += ../g45/hw-gfx-gma-gmch-vga.ads +gfxinit-y += ../g45/hw-gfx-gma-plls.adb +gfxinit-y += ../g45/hw-gfx-gma-plls.ads +gfxinit-y += ../g45/hw-gfx-gma-port_detect.adb +gfxinit-y += ../g45/hw-gfx-gma-gmch.ads +gfxinit-y += ../g45/hw-gfx-gma-power_and_clocks.ads +gfxinit-y += ../g45/hw-gfx-gma-power_and_clocks.adb diff --git a/configs/baytrail b/configs/baytrail new file mode 100644 index 0000000..9df28fd --- /dev/null +++ b/configs/baytrail @@ -0,0 +1,6 @@ +CONFIG_GFX_GMA_DYN_CPU = y +CONFIG_GFX_GMA_GENERATION = Valleyview +CONFIG_GFX_GMA_PANEL_1_PORT = DP1 +CONFIG_GFX_GMA_PANEL_2_PORT = DP2 +CONFIG_GFX_GMA_ANALOG_I2C_PORT = PCH_DAC +CONFIG_GFX_GMA_DEFAULT_MMIO = 16\#e000_0000\# -- To view, visit https://review.coreboot.org/c/libgfxinit/+/44790 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: Ib30ea668da9641ccf1f94f8f25cfb897faa54aaa Gerrit-Change-Number: 44790 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in libgfxinit[master]: gma: Use a full `case` statement in Decode_Stolen
by Angel Pons (Code Review) 11 Apr '24

11 Apr '24

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/libgfxinit/+/44934 ) Change subject: gma: Use a full `case` statement in Decode_Stolen ...................................................................... gma: Use a full `case` statement in Decode_Stolen Hopefully, this will cause a `missing case` warning when adding support for a new platform, instead of silently using the wrong functions. Change-Id: I39f37e931977f4f437b619188436c37752f6b915 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M common/hw-gfx-gma.adb 1 file changed, 13 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/34/44934/1 diff --git a/common/hw-gfx-gma.adb b/common/hw-gfx-gma.adb index 9157bbe..f36470e 100644 --- a/common/hw-gfx-gma.adb +++ b/common/hw-gfx-gma.adb @@ -739,20 +739,19 @@ GGC : Word16; begin Dev.Read16 (GGC, GGC_Reg); - if Config.Gen_G45 or Config.CPU_Ironlake then - GTT_Size := GTT_Size_Gen4 (GGC); - Stolen_Size := Stolen_Size_Gen4 (GGC); - elsif Config.CPU_Sandybridge or Config.CPU_Ivybridge or Config.CPU_Haswell - then - GTT_Size := GTT_Size_Gen6 (GGC); - Stolen_Size := Stolen_Size_Gen6 (GGC); - elsif Config.CPU_Broadwell then - GTT_Size := GTT_Size_Gen8 (GGC); - Stolen_Size := Stolen_Size_Gen8 (GGC); - else - GTT_Size := GTT_Size_Gen8 (GGC); - Stolen_Size := Stolen_Size_Gen9 (GGC); - end if; + + -- Upcasting is necessary to cover all cases + GTT_Size := + (case CPU_Type (Config.CPU) is + when G45 .. Ironlake => GTT_Size_Gen4 (GGC), + when Sandybridge .. Haswell => GTT_Size_Gen6 (GGC), + when Broadwell .. Kabylake => GTT_Size_Gen8 (GGC)); + Stolen_Size := + (case CPU_Type (Config.CPU) is + when G45 .. Ironlake => Stolen_Size_Gen4 (GGC), + when Sandybridge .. Haswell => Stolen_Size_Gen6 (GGC), + when Broadwell => Stolen_Size_Gen8 (GGC), + when Broxton .. Kabylake => Stolen_Size_Gen9 (GGC)); end Decode_Stolen; -- Additional runtime validation that FB fits stolen memory and aperture. -- To view, visit https://review.coreboot.org/c/libgfxinit/+/44934 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I39f37e931977f4f437b619188436c37752f6b915 Gerrit-Change-Number: 44934 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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