coreboot-gerrit September 2020

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Change in coreboot[master]: mainboard: add Dell Latitude E7240
by Iru Cai (vimacs) (Code Review) 01 Sep '20

01 Sep '20

Iru Cai (vimacs) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40300 ) Change subject: mainboard: add Dell Latitude E7240 ...................................................................... Patch Set 2: (10 comments) Recreate the code with the logs dumped from an i5 laptop (previously it's using an i3 CPU). The GPIO and USB settings have changed. https://review.coreboot.org/c/coreboot/+/40300/1//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/40300/1//COMMIT_MSG@12 PS1, Line 12: It just boots from USB with SeaBIOS and runs for more than one hour. > Wow. […] Ack https://review.coreboot.org/c/coreboot/+/40300/1/src/mainboard/dell/latitud… File src/mainboard/dell/latitude_e7240/acpi_tables.c: https://review.coreboot.org/c/coreboot/+/40300/1/src/mainboard/dell/latitud… PS1, Line 9: /* Disable USB ports in S3 by default */ : gnvs->s3u0 = 0; : gnvs->s3u1 = 0; : : /* Disable USB ports in S5 by default */ : gnvs->s5u0 = 0; : gnvs->s5u1 = 0; > Already zero Done https://review.coreboot.org/c/coreboot/+/40300/1/src/mainboard/dell/latitud… PS1, Line 17: // the lid is open by default. > That looks like old autoport: […] Done https://review.coreboot.org/c/coreboot/+/40300/1/src/mainboard/dell/latitud… File src/mainboard/dell/latitude_e7240/devicetree.cb: https://review.coreboot.org/c/coreboot/+/40300/1/src/mainboard/dell/latitud… PS1, Line 23: end > Pick these up and place them on the previous line? Done https://review.coreboot.org/c/coreboot/+/40300/1/src/mainboard/dell/latitud… PS1, Line 33: register "gen4_dec" = "0x00000000" > Already zero, can be dropped Done https://review.coreboot.org/c/coreboot/+/40300/1/src/mainboard/dell/latitud… PS1, Line 46: subsystemid 0x1028 0x05ca > Inherit this? Done https://review.coreboot.org/c/coreboot/+/40300/1/src/mainboard/dell/latitud… PS1, Line 100: : device pci 00.0 on # Host bridge Host bridge : subsystemid 0x1028 0x05ca : end : device pci 01.0 off # PCIe Bridge for discrete graphics : end : device pci 02.0 on # Internal graphics VGA controller : subsystemid 0x1028 0x05ca : end : device pci 03.0 on # Mini-HD audio Unsupported PCI device 8086:0a0c : subsystemid 0x1028 0x05ca : end > Move these above the "chip southbridge/intel/lynxpoint" entry? Done https://review.coreboot.org/c/coreboot/+/40300/1/src/mainboard/dell/latitud… File src/mainboard/dell/latitude_e7240/dsdt.asl: https://review.coreboot.org/c/coreboot/+/40300/1/src/mainboard/dell/latitud… PS1, Line 1: #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB > Missing license header, and these are likely not being used Done https://review.coreboot.org/c/coreboot/+/40300/1/src/mainboard/dell/latitud… File src/mainboard/dell/latitude_e7240/ec.c: https://review.coreboot.org/c/coreboot/+/40300/1/src/mainboard/dell/latitud… PS1, Line 77: static int write_send(u8 *sdata, u8 c, unsigned count) > Please address Now this file is moved to ec/ in another patch. https://review.coreboot.org/c/coreboot/+/40300/2/src/superio/smsc/Makefile.… File src/superio/smsc/Makefile.inc: https://review.coreboot.org/c/coreboot/+/40300/2/src/superio/smsc/Makefile.… PS2, Line 16: subdirs-y += ece5048 gosh, I'm not going to add this yet... -- To view, visit https://review.coreboot.org/c/coreboot/+/40300 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6933bdbcc8d0bbb85d62657624740266284ac71c Gerrit-Change-Number: 40300 Gerrit-PatchSet: 2 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 01 Sep 2020 07:30:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: build bot (Jenkins) <no-reply(a)coreboot.org> Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mainboard: add Dell Latitude E7240
by build bot (Jenkins) (Code Review) 01 Sep '20

01 Sep '20

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40300 ) Change subject: mainboard: add Dell Latitude E7240 ...................................................................... Patch Set 2: (8 comments) https://review.coreboot.org/c/coreboot/+/40300/2/src/mainboard/dell/latitud… File src/mainboard/dell/latitude_e7240/gpio.c: https://review.coreboot.org/c/coreboot/+/40300/2/src/mainboard/dell/latitud… PS2, Line 14: { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL, .pirq = GPIO_PIRQ_APIC_ROUTE }, /* 8 */ line over 96 characters https://review.coreboot.org/c/coreboot/+/40300/2/src/mainboard/dell/latitud… PS2, Line 15: { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, .pirq = GPIO_PIRQ_APIC_ROUTE }, /* 9 */ line over 96 characters https://review.coreboot.org/c/coreboot/+/40300/2/src/mainboard/dell/latitud… PS2, Line 19: { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL, .pirq = GPIO_PIRQ_APIC_ROUTE }, /* 13 */ line over 96 characters https://review.coreboot.org/c/coreboot/+/40300/2/src/mainboard/dell/latitud… PS2, Line 51: { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL, .route = GPIO_ROUTE_SMI, .pirq = GPIO_PIRQ_APIC_ROUTE }, /* 45 */ line over 96 characters https://review.coreboot.org/c/coreboot/+/40300/2/src/mainboard/dell/latitud… PS2, Line 53: { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT, .pirq = GPIO_PIRQ_APIC_ROUTE }, /* 47 */ line over 96 characters https://review.coreboot.org/c/coreboot/+/40300/2/src/mainboard/dell/latitud… PS2, Line 58: { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, .pirq = GPIO_PIRQ_APIC_ROUTE }, /* 52 */ line over 96 characters https://review.coreboot.org/c/coreboot/+/40300/2/src/mainboard/dell/latitud… PS2, Line 61: { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT, .pirq = GPIO_PIRQ_APIC_ROUTE }, /* 55 */ line over 96 characters https://review.coreboot.org/c/coreboot/+/40300/2/src/mainboard/dell/latitud… PS2, Line 102: }; adding a line without newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/40300 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6933bdbcc8d0bbb85d62657624740266284ac71c Gerrit-Change-Number: 40300 Gerrit-PatchSet: 2 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 01 Sep 2020 07:21:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mainboard: add Dell Latitude E7240
by Iru Cai (vimacs) (Code Review) 01 Sep '20

01 Sep '20

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Iru Cai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/40300 to look at the new patch set (#2). Change subject: mainboard: add Dell Latitude E7240 ...................................................................... mainboard: add Dell Latitude E7240 Based on autoport output. It boots from USB and mSATA with SeaBIOS. Change-Id: I6933bdbcc8d0bbb85d62657624740266284ac71c Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- A src/mainboard/dell/latitude_e7240/Kconfig A src/mainboard/dell/latitude_e7240/Kconfig.name A src/mainboard/dell/latitude_e7240/Makefile.inc A src/mainboard/dell/latitude_e7240/acpi/ec.asl A src/mainboard/dell/latitude_e7240/acpi/platform.asl A src/mainboard/dell/latitude_e7240/acpi/superio.asl A src/mainboard/dell/latitude_e7240/acpi_tables.c A src/mainboard/dell/latitude_e7240/board_info.txt A src/mainboard/dell/latitude_e7240/bootblock.c A src/mainboard/dell/latitude_e7240/devicetree.cb A src/mainboard/dell/latitude_e7240/dsdt.asl A src/mainboard/dell/latitude_e7240/gma-mainboard.ads A src/mainboard/dell/latitude_e7240/gpio.c A src/mainboard/dell/latitude_e7240/hda_verb.c A src/mainboard/dell/latitude_e7240/mainboard.c A src/mainboard/dell/latitude_e7240/romstage.c M src/superio/smsc/Makefile.inc 17 files changed, 423 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/40300/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/40300 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6933bdbcc8d0bbb85d62657624740266284ac71c Gerrit-Change-Number: 40300 Gerrit-PatchSet: 2 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/cpu: Update COS mask calculation for NEM enhanced mode
by Karthik Ramasubramanian (Code Review) 01 Sep '20

01 Sep '20

Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43494 ) Change subject: soc/intel/common/cpu: Update COS mask calculation for NEM enhanced mode ...................................................................... Patch Set 4: > Patch Set 4: > > Aamir, have you had a chance to test on other chipsets besides TGL ? I was able to boot up the JSL SoC with this change. I am yet to verify the mask contents in MSR. -- To view, visit https://review.coreboot.org/c/coreboot/+/43494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54e047161853bfc70516c1d607aa479e68836d04 Gerrit-Change-Number: 43494 Gerrit-PatchSet: 4 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Comment-Date: Tue, 01 Sep 2020 06:55:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/*/Kconfig: Drop redundant 'select CONSOLE_SERIAL'
by HAOUAS Elyes (Code Review) 01 Sep '20

01 Sep '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44906 ) Change subject: mb/*/Kconfig: Drop redundant 'select CONSOLE_SERIAL' ...................................................................... mb/*/Kconfig: Drop redundant 'select CONSOLE_SERIAL' 'CONSOLE_SERIAL' is already set to 'y' at src/console/Kconfig. Change-Id: I350cf12a115c6ebe54a2b0821edc94c29db8d137 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/emulation/qemu-aarch64/Kconfig M src/mainboard/emulation/qemu-armv7/Kconfig M src/mainboard/intel/saddlebrook/Kconfig 3 files changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/44906/1 diff --git a/src/mainboard/emulation/qemu-aarch64/Kconfig b/src/mainboard/emulation/qemu-aarch64/Kconfig index 368f7f3..54141b4 100644 --- a/src/mainboard/emulation/qemu-aarch64/Kconfig +++ b/src/mainboard/emulation/qemu-aarch64/Kconfig @@ -16,7 +16,6 @@ select BOOTBLOCK_CONSOLE select BOOTBLOCK_CUSTOM select BOOT_DEVICE_NOT_SPI_FLASH - select CONSOLE_SERIAL select DRIVERS_UART_PL011 select HAVE_LINEAR_FRAMEBUFFER select MAINBOARD_FORCE_NATIVE_VGA_INIT diff --git a/src/mainboard/emulation/qemu-armv7/Kconfig b/src/mainboard/emulation/qemu-armv7/Kconfig index 64e5bb7..a912998 100644 --- a/src/mainboard/emulation/qemu-armv7/Kconfig +++ b/src/mainboard/emulation/qemu-armv7/Kconfig @@ -13,7 +13,6 @@ def_bool y select CPU_ARMLTD_CORTEX_A9 select DRIVERS_UART_PL011 - select CONSOLE_SERIAL select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_FORCE_NATIVE_VGA_INIT select HAVE_LINEAR_FRAMEBUFFER diff --git a/src/mainboard/intel/saddlebrook/Kconfig b/src/mainboard/intel/saddlebrook/Kconfig index f94cd54..e0f2add3 100644 --- a/src/mainboard/intel/saddlebrook/Kconfig +++ b/src/mainboard/intel/saddlebrook/Kconfig @@ -5,7 +5,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_4096 - select CONSOLE_SERIAL select DRIVERS_UART select GENERIC_SPD_BIN select HAVE_ACPI_RESUME -- To view, visit https://review.coreboot.org/c/coreboot/+/44906 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I350cf12a115c6ebe54a2b0821edc94c29db8d137 Gerrit-Change-Number: 44906 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/puff: Update DPTF parameters and TDP PL1/PL2 values
by David Wu (Code Review) 01 Sep '20

01 Sep '20

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44903 ) Change subject: mb/google/puff: Update DPTF parameters and TDP PL1/PL2 values ...................................................................... mb/google/puff: Update DPTF parameters and TDP PL1/PL2 values Update DPTF parameters and TDP PL1/PL2 override to 15W/51W for kaisa and duffy BUG=b:166696500 TEST=build and verify by thermal team Change-Id: I53a4e8809369883c3ba77744fdc05fb510408209 Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> --- M src/mainboard/google/hatch/variants/duffy/include/variant/acpi/dptf.asl M src/mainboard/google/hatch/variants/duffy/overridetree.cb M src/mainboard/google/hatch/variants/kaisa/include/variant/acpi/dptf.asl M src/mainboard/google/hatch/variants/kaisa/overridetree.cb 4 files changed, 194 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/44903/1 diff --git a/src/mainboard/google/hatch/variants/duffy/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/duffy/include/variant/acpi/dptf.asl index 6694063..f33dd60 100644 --- a/src/mainboard/google/hatch/variants/duffy/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/duffy/include/variant/acpi/dptf.asl @@ -1,3 +1,94 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <puff/acpi/dptf.asl> +#define DPTF_CPU_PASSIVE 95 +#define DPTF_CPU_CRITICAL 100 +#define DPTF_CPU_ACTIVE_AC0 94 + +#define DPTF_TSR0_SENSOR_ID 0 +#define DPTF_TSR0_SENSOR_NAME "Thermal Sensor 1" +#define DPTF_TSR0_PASSIVE 68 +#define DPTF_TSR0_CRITICAL 78 +#define DPTF_TSR0_ACTIVE_AC0 65 +#define DPTF_TSR0_ACTIVE_AC1 61 +#define DPTF_TSR0_ACTIVE_AC2 57 +#define DPTF_TSR0_ACTIVE_AC3 53 +#define DPTF_TSR0_ACTIVE_AC4 49 +#define DPTF_TSR0_ACTIVE_AC5 45 +#define DPTF_TSR0_ACTIVE_AC6 41 + +#define DPTF_ENABLE_CHARGER +#define DPTF_ENABLE_FAN_CONTROL + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ +}) + +/* DFPS: Fan Performance States */ +Name (DFPS, Package () { + 0, // Revision + /* + * TODO : Need to update this Table after characterization. + * These are initial reference values. + */ + /* Control, Trip Point, Speed, NoiseLevel, Power */ + Package () {90, 0xFFFFFFFF, 6700, 220, 2200}, + Package () {80, 0xFFFFFFFF, 5800, 180, 1800}, + Package () {70, 0xFFFFFFFF, 5000, 145, 1450}, + Package () {60, 0xFFFFFFFF, 4900, 115, 1150}, + Package () {50, 0xFFFFFFFF, 3838, 90, 900}, + Package () {40, 0xFFFFFFFF, 2904, 55, 550}, + Package () {30, 0xFFFFFFFF, 2337, 30, 300}, + Package () {20, 0xFFFFFFFF, 1608, 15, 150}, + Package () {10, 0xFFFFFFFF, 800, 10, 100}, + Package () {0, 0xFFFFFFFF, 0, 0, 50} +}) + +Name (DART, Package () { + /* Fan effect on CPU */ + 0, // Revision + Package () { + /* + * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6, + * AC7, AC8, AC9 + */ + \_SB.DPTF.TFN1, \_SB.PCI0.TCPU, 100, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0 + }, + Package () { + \_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 100, 90, 80, 70, 60, 50, 40, 0, + 0, 0, 0 + } +}) + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on Ambient (TSR0) */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 50, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 15000, /* PowerLimitMinimum */ + 15000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 32000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 15000, /* PowerLimitMinimum */ + 51000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 32000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) diff --git a/src/mainboard/google/hatch/variants/duffy/overridetree.cb b/src/mainboard/google/hatch/variants/duffy/overridetree.cb index a4fa09d..5ee3c59 100644 --- a/src/mainboard/google/hatch/variants/duffy/overridetree.cb +++ b/src/mainboard/google/hatch/variants/duffy/overridetree.cb @@ -1,6 +1,11 @@ chip soc/intel/cannonlake register "tcc_offset" = "5" # TCC of 95C + register "power_limits_config" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 51, + }" + # Auto-switch between X4 NVMe and X2 NVMe. register "TetonGlacierMode" = "1" diff --git a/src/mainboard/google/hatch/variants/kaisa/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/kaisa/include/variant/acpi/dptf.asl index 6694063..f33dd60 100644 --- a/src/mainboard/google/hatch/variants/kaisa/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/kaisa/include/variant/acpi/dptf.asl @@ -1,3 +1,94 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <puff/acpi/dptf.asl> +#define DPTF_CPU_PASSIVE 95 +#define DPTF_CPU_CRITICAL 100 +#define DPTF_CPU_ACTIVE_AC0 94 + +#define DPTF_TSR0_SENSOR_ID 0 +#define DPTF_TSR0_SENSOR_NAME "Thermal Sensor 1" +#define DPTF_TSR0_PASSIVE 68 +#define DPTF_TSR0_CRITICAL 78 +#define DPTF_TSR0_ACTIVE_AC0 65 +#define DPTF_TSR0_ACTIVE_AC1 61 +#define DPTF_TSR0_ACTIVE_AC2 57 +#define DPTF_TSR0_ACTIVE_AC3 53 +#define DPTF_TSR0_ACTIVE_AC4 49 +#define DPTF_TSR0_ACTIVE_AC5 45 +#define DPTF_TSR0_ACTIVE_AC6 41 + +#define DPTF_ENABLE_CHARGER +#define DPTF_ENABLE_FAN_CONTROL + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ +}) + +/* DFPS: Fan Performance States */ +Name (DFPS, Package () { + 0, // Revision + /* + * TODO : Need to update this Table after characterization. + * These are initial reference values. + */ + /* Control, Trip Point, Speed, NoiseLevel, Power */ + Package () {90, 0xFFFFFFFF, 6700, 220, 2200}, + Package () {80, 0xFFFFFFFF, 5800, 180, 1800}, + Package () {70, 0xFFFFFFFF, 5000, 145, 1450}, + Package () {60, 0xFFFFFFFF, 4900, 115, 1150}, + Package () {50, 0xFFFFFFFF, 3838, 90, 900}, + Package () {40, 0xFFFFFFFF, 2904, 55, 550}, + Package () {30, 0xFFFFFFFF, 2337, 30, 300}, + Package () {20, 0xFFFFFFFF, 1608, 15, 150}, + Package () {10, 0xFFFFFFFF, 800, 10, 100}, + Package () {0, 0xFFFFFFFF, 0, 0, 50} +}) + +Name (DART, Package () { + /* Fan effect on CPU */ + 0, // Revision + Package () { + /* + * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6, + * AC7, AC8, AC9 + */ + \_SB.DPTF.TFN1, \_SB.PCI0.TCPU, 100, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0 + }, + Package () { + \_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 100, 90, 80, 70, 60, 50, 40, 0, + 0, 0, 0 + } +}) + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on Ambient (TSR0) */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 50, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 15000, /* PowerLimitMinimum */ + 15000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 32000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 15000, /* PowerLimitMinimum */ + 51000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 32000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) diff --git a/src/mainboard/google/hatch/variants/kaisa/overridetree.cb b/src/mainboard/google/hatch/variants/kaisa/overridetree.cb index c6aef05..94edb0a 100644 --- a/src/mainboard/google/hatch/variants/kaisa/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kaisa/overridetree.cb @@ -1,6 +1,11 @@ chip soc/intel/cannonlake register "tcc_offset" = "5" # TCC of 95C + register "power_limits_config" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 51, + }" + # Auto-switch between X4 NVMe and X2 NVMe. register "TetonGlacierMode" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/44903 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I53a4e8809369883c3ba77744fdc05fb510408209 Gerrit-Change-Number: 44903 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

5 19

Change in coreboot[master]: {include,mb,soc,sb,vendorcode}: Make hexadecimal notation consistent
by Subrata Banik (Code Review) 01 Sep '20

01 Sep '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44926 ) Change subject: {include,mb,soc,sb,vendorcode}: Make hexadecimal notation consistent ...................................................................... {include,mb,soc,sb,vendorcode}: Make hexadecimal notation consistent Convert 0X -> 0x Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Change-Id: Iea3ca67908135d0e85083a05bad2ea176ca34095 --- M src/include/device/pci_ids.h M src/mainboard/google/octopus/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/include/variant/sku.h M src/soc/intel/quark/include/soc/cpu.h M src/soc/intel/quark/include/soc/pci_devs.h M src/soc/mediatek/mt8183/gpio.c M src/soc/mediatek/mt8183/include/soc/pmic_wrap.h M src/soc/nvidia/tegra124/include/soc/sdram_param.h M src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c M src/soc/nvidia/tegra210/include/soc/sdram_param.h M src/soc/rockchip/rk3399/clock.c M src/southbridge/intel/i82371eb/i82371eb.h M src/vendorcode/amd/agesa/f14/Include/Filecode.h M src/vendorcode/amd/agesa/f14/Proc/CPU/Table.h M src/vendorcode/amd/agesa/f14/Proc/CPU/cpuRegisters.h M src/vendorcode/amd/agesa/f15tn/Include/Filecode.h M src/vendorcode/amd/agesa/f15tn/Proc/CPU/Table.h M src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuRegisters.h M src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiEnvService.c M src/vendorcode/amd/agesa/f15tn/gcccar.inc M src/vendorcode/amd/agesa/f16kb/Include/Filecode.h M src/vendorcode/amd/agesa/f16kb/Proc/CPU/Table.h M src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuRegisters.h M src/vendorcode/amd/agesa/f16kb/Proc/Fch/Fch.h M src/vendorcode/amd/agesa/f16kb/gcccar.inc M src/vendorcode/amd/pi/00630F01/Include/Filecode.h M src/vendorcode/amd/pi/00630F01/Proc/CPU/cpuRegisters.h M src/vendorcode/amd/pi/00630F01/Proc/Fch/Fch.h M src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc M src/vendorcode/amd/pi/00660F01/Include/Filecode.h M src/vendorcode/amd/pi/00660F01/Include/Ids.h M src/vendorcode/amd/pi/00660F01/Proc/CPU/cpuRegisters.h M src/vendorcode/amd/pi/00660F01/Proc/Fch/Fch.h M src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc M src/vendorcode/amd/pi/00670F00/Proc/CPU/Table.h M src/vendorcode/amd/pi/00670F00/Proc/CPU/cpuRegisters.h M src/vendorcode/amd/pi/00670F00/Proc/Fch/Fch.h M src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc M src/vendorcode/amd/pi/00730F01/Include/Filecode.h M src/vendorcode/amd/pi/00730F01/Proc/CPU/cpuRegisters.h M src/vendorcode/amd/pi/00730F01/Proc/Fch/Fch.h M src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc M src/vendorcode/cavium/bdk/libbdk-hal/qlm/bdk-qlm-errata-cn8xxx.c M src/vendorcode/cavium/bdk/libdram/dram-init-ddr3.c M src/vendorcode/cavium/include/bdk/libbdk-arch/bdk-csrs-ap.h M src/vendorcode/cavium/include/bdk/libbdk-arch/bdk-csrs-usbdrd.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Guid/AprioriFileName.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Tpm20.h M src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Guid/AprioriFileName.h M src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/Tpm20.h M src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h 51 files changed, 869 insertions(+), 869 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/44926/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index f055e52..5aaf7b3 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2894,7 +2894,7 @@ #define PCI_DEVICE_ID_INTEL_MCC_ESPI_2 0x4b05 #define PCI_DEVICE_ID_INTEL_MCC_ESPI_3 0x4b06 #define PCI_DEVICE_ID_INTEL_MCC_ESPI_4 0x4b07 -#define PCI_DEVICE_ID_INTEL_JSP_SUPER_ESPI 0X4d87 +#define PCI_DEVICE_ID_INTEL_JSP_SUPER_ESPI 0x4d87 #define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_0 0x7a00 #define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_1 0x7a01 #define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_2 0x7a02 diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb index ea5325a..9ac02fd 100644 --- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb @@ -273,8 +273,8 @@ # RegOrValue (15:8): 0x2 and RegAndValue (7:0) 0xF8. # The register is defined as: D[7:3] RSVD, D[2:0] PWROKDELAY. # uint8 RegOrValue, RegAndValue, PmicReadReg - # RegOrValue = (UINT8)((PmicPmcIpcCtrl >> 8) & 0Xff); - # RegAndValue = (UINT8)(PmicPmcIpcCtrl & 0Xff); + # RegOrValue = (UINT8)((PmicPmcIpcCtrl >> 8) & 0xff); + # RegAndValue = (UINT8)(PmicPmcIpcCtrl & 0xff); # PmicReadReg &= RegAndValue; # PmicReadReg |= RegOrValue; # PmicReadReg value will be programmed into PMIC D[2:0] PWROKDELAY field diff --git a/src/mainboard/google/poppy/variants/nami/include/variant/sku.h b/src/mainboard/google/poppy/variants/nami/include/variant/sku.h index 158f0d1..5486670 100644 --- a/src/mainboard/google/poppy/variants/nami/include/variant/sku.h +++ b/src/mainboard/google/poppy/variants/nami/include/variant/sku.h @@ -22,15 +22,15 @@ #define SKU_0_SYNDRA 0x2BC63 #define SKU_1_SYNDRA 0x2BC62 #define SKU_2_SYNDRA 0x2BC61 -#define SKU_3_SYNDRA 0X2BC60 -#define SKU_4_SYNDRA 0X6BC63 -#define SKU_5_SYNDRA 0X6BC62 -#define SKU_6_SYNDRA 0X6BC61 -#define SKU_7_SYNDRA 0X6BC60 +#define SKU_3_SYNDRA 0x2BC60 +#define SKU_4_SYNDRA 0x6BC63 +#define SKU_5_SYNDRA 0x6BC62 +#define SKU_6_SYNDRA 0x6BC61 +#define SKU_7_SYNDRA 0x6BC60 #define SKU_0_EKKO 0x10118E3 #define SKU_1_EKKO 0x10018E3 #define SKU_2_EKKO 0x10118E1 -#define SKU_3_EKKO 0X10018E1 +#define SKU_3_EKKO 0x10018E1 #define SKU_4_EKKO 0x10118E2 #define SKU_5_EKKO 0x10018E2 #define SKU_6_EKKO 0x10118E0 @@ -38,9 +38,9 @@ #define SKU_0_BARD 0x1019CE3 #define SKU_1_BARD 0x1009CE3 #define SKU_2_BARD 0x1019CE1 -#define SKU_3_BARD 0X1009CE1 -#define SKU_4_BARD 0X1009CE0 -#define SKU_5_BARD 0X1009CE2 +#define SKU_3_BARD 0x1009CE1 +#define SKU_4_BARD 0x1009CE0 +#define SKU_5_BARD 0x1009CE2 #define SKU_6_BARD 0x1019CE0 #define SKU_7_BARD 0x1019CE2 diff --git a/src/soc/intel/quark/include/soc/cpu.h b/src/soc/intel/quark/include/soc/cpu.h index 84bce7d..e4bcab1 100644 --- a/src/soc/intel/quark/include/soc/cpu.h +++ b/src/soc/intel/quark/include/soc/cpu.h @@ -6,6 +6,6 @@ #include <device/device.h> /* Supported CPUIDs */ -#define CPUID_QUARK_X1000 0X590 +#define CPUID_QUARK_X1000 0x590 #endif /* _QUARK_CPU_H_ */ diff --git a/src/soc/intel/quark/include/soc/pci_devs.h b/src/soc/intel/quark/include/soc/pci_devs.h index 95e5f28..2c6a532 100644 --- a/src/soc/intel/quark/include/soc/pci_devs.h +++ b/src/soc/intel/quark/include/soc/pci_devs.h @@ -13,7 +13,7 @@ #define I2CGPIO_DEVID 0x0934 #define HSUART_DEVID 0x0936 #define EHCI_DEVID 0x0939 -#define LPC_DEVID 0X095E +#define LPC_DEVID 0x095E #define PCIE_PORT0_DEVID 0x11c3 #define PCIE_PORT1_DEVID 0x11c4 diff --git a/src/soc/mediatek/mt8183/gpio.c b/src/soc/mediatek/mt8183/gpio.c index 6565ec5..0c0b54d 100644 --- a/src/soc/mediatek/mt8183/gpio.c +++ b/src/soc/mediatek/mt8183/gpio.c @@ -10,7 +10,7 @@ SEL_OFFSET = 0x80, EH_RSEL_OFFSET = 0xF0, GPIO_DRV0_OFFSET = 0xA0, - GPIO_DRV1_OFFSET = 0XB0, + GPIO_DRV1_OFFSET = 0xB0, }; static void gpio_set_pull_pupd(gpio_t gpio, enum pull_enable enable, diff --git a/src/soc/mediatek/mt8183/include/soc/pmic_wrap.h b/src/soc/mediatek/mt8183/include/soc/pmic_wrap.h index 2c1fa9b..8cfe8b0 100644 --- a/src/soc/mediatek/mt8183/include/soc/pmic_wrap.h +++ b/src/soc/mediatek/mt8183/include/soc/pmic_wrap.h @@ -351,22 +351,22 @@ }; enum { - STA_PD_98_5_US = 0X5, + STA_PD_98_5_US = 0x5, }; enum { - WATCHDOG_TIMER_7_5_MS = 0XF, + WATCHDOG_TIMER_7_5_MS = 0xF, }; enum { - WDT_MONITOR_ALL = 0XFFFF, + WDT_MONITOR_ALL = 0xFFFF, }; enum { MONITOR_LATCH_MATCHED_TRANS = 0x1 << 28, STARV_15 = 0x1 << 24, DCXO = 0x1 << 19, - MONITOR_ALL_INT = 0XFFFFFFFF, + MONITOR_ALL_INT = 0xFFFFFFFF, INT0_MONITOR = MONITOR_ALL_INT, INT1_MONITOR = MONITOR_ALL_INT & ~MONITOR_LATCH_MATCHED_TRANS & ~STARV_15 & ~DCXO, @@ -396,6 +396,6 @@ }; enum { - DUMMY_READ_CYCLES = 0X8, + DUMMY_READ_CYCLES = 0x8, }; #endif /* __SOC_MEDIATEK_MT8183_PMIC_WRAP_H__ */ diff --git a/src/soc/nvidia/tegra124/include/soc/sdram_param.h b/src/soc/nvidia/tegra124/include/soc/sdram_param.h index 45cd914..b19ae5f 100644 --- a/src/soc/nvidia/tegra124/include/soc/sdram_param.h +++ b/src/soc/nvidia/tegra124/include/soc/sdram_param.h @@ -35,7 +35,7 @@ NvBootMemoryType_Num, /* Specifies an entry in the ram_code table that's not in use */ - NvBootMemoryType_Unused = 0X7FFFFFF, + NvBootMemoryType_Unused = 0x7FFFFFF, }; enum { diff --git a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c index 85d331b..b7881de 100644 --- a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c +++ b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c @@ -2,14 +2,14 @@ /* Function unit addresses. */ enum { - UP_TAG_BASE = 0X60000000, - TIMER_BASE = 0X60005000, - CLK_RST_BASE = 0X60006000, - FLOW_CTLR_BASE = 0X60007000, + UP_TAG_BASE = 0x60000000, + TIMER_BASE = 0x60005000, + CLK_RST_BASE = 0x60006000, + FLOW_CTLR_BASE = 0x60007000, TEGRA_EVP_BASE = 0x6000f000, - PMC_CTLR_BASE = 0X7000e400, - MC_CTLR_BASE = 0X70019000, - SYSCTR_CTLR_BASE = 0X700f0000 + PMC_CTLR_BASE = 0x7000e400, + MC_CTLR_BASE = 0x70019000, + SYSCTR_CTLR_BASE = 0x700f0000 }; diff --git a/src/soc/nvidia/tegra210/include/soc/sdram_param.h b/src/soc/nvidia/tegra210/include/soc/sdram_param.h index 7513302..f9d7c6b 100644 --- a/src/soc/nvidia/tegra210/include/soc/sdram_param.h +++ b/src/soc/nvidia/tegra210/include/soc/sdram_param.h @@ -38,7 +38,7 @@ NvBootMemoryType_Num, /* Specifies an entry in the ram_code table that's not in use */ - NvBootMemoryType_Unused = 0X7FFFFFF, + NvBootMemoryType_Unused = 0x7FFFFFF, }; enum { diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c index ea1d7ff..0ba07d6 100644 --- a/src/soc/rockchip/rk3399/clock.c +++ b/src/soc/rockchip/rk3399/clock.c @@ -81,7 +81,7 @@ PLL_SSMOD_RESET_SHIFT = 2, PLL_SSMOD_DOWNSPEAD_MASK = 1, PLL_SSMOD_DOWNSPEAD_SHIFT = 3, - PLL_SSMOD_DIVVAL_MASK = 0Xf, + PLL_SSMOD_DIVVAL_MASK = 0xf, PLL_SSMOD_DIVVAL_SHIFT = 4, PLL_SSMOD_SPREADAMP_MASK = 0x1f, PLL_SSMOD_SPREADAMP_SHIFT = 8, diff --git a/src/southbridge/intel/i82371eb/i82371eb.h b/src/southbridge/intel/i82371eb/i82371eb.h index c6944ed..2a3b167 100644 --- a/src/southbridge/intel/i82371eb/i82371eb.h +++ b/src/southbridge/intel/i82371eb/i82371eb.h @@ -89,9 +89,9 @@ #define PMBA 0x40 /* Power management base address */ #define DEFAULT_PMBASE 0xe400 #define PM_IO_BASE DEFAULT_PMBASE -#define DEVRESA 0X5c /* Device resource A */ -#define DEVRESB 0X60 /* Device resource B */ -#define DEVRESC 0X64 /* Device resource C */ +#define DEVRESA 0x5c /* Device resource A */ +#define DEVRESB 0x60 /* Device resource B */ +#define DEVRESC 0x64 /* Device resource C */ #define DEVRESD 0x52 /* Device resource D */ #define DEVRESE 0x68 /* Device resource E */ #define DEVRESF 0x6c /* Device resource F */ diff --git a/src/vendorcode/amd/agesa/f14/Include/Filecode.h b/src/vendorcode/amd/agesa/f14/Include/Filecode.h index 060e6cc..7420811 100644 --- a/src/vendorcode/amd/agesa/f14/Include/Filecode.h +++ b/src/vendorcode/amd/agesa/f14/Include/Filecode.h @@ -628,31 +628,31 @@ #define PROC_MEM_MAIN_RB_MMFLOWRB_FILECODE (0xF11A) #define PROC_MEM_MAIN_PH_MMFLOWPH_FILECODE (0xF11B) -#define PROC_MEM_NB_DR_MNDR_FILECODE (0XF213) -#define PROC_MEM_NB_DR_MNFLOWDR_FILECODE (0XF214) -#define PROC_MEM_NB_DR_MNIDENDIMMDR_FILECODE (0XF216) -#define PROC_MEM_NB_DR_MNMCTDR_FILECODE (0XF217) -#define PROC_MEM_NB_DR_MNDCTDR_FILECODE (0XF218) -#define PROC_MEM_NB_DR_MNOTDR_FILECODE (0XF219) -#define PROC_MEM_NB_DR_MNPARTRAINDR_FILECODE (0XF21A) -#define PROC_MEM_NB_DR_MNPROTODR_FILECODE (0XF21C) -#define PROC_MEM_NB_DR_MNS3DR_FILECODE (0XF21D) -#define PROC_MEM_NB_DR_MNREGDR_FILECODE (0XF21E) -#define PROC_MEM_NB_RB_MNRB_FILECODE (0XF220) -#define PROC_MEM_NB_RB_MNFLOWRB_FILECODE (0XF221) -#define PROC_MEM_NB_RB_MNS3RB_FILECODE (0XF222) -#define PROC_MEM_NB_RB_MNIDENDIMMRB_FILECODE (0XF223) -#define PROC_MEM_NB_HY_MNFLOWHY_FILECODE (0XF233) -#define PROC_MEM_NB_HY_MNHY_FILECODE (0XF235) -#define PROC_MEM_NB_HY_MNIDENDIMMHY_FILECODE (0XF236) -#define PROC_MEM_NB_HY_MNMCTHY_FILECODE (0XF237) -#define PROC_MEM_NB_HY_MNDCTHY_FILECODE (0XF238) -#define PROC_MEM_NB_HY_MNOTHY_FILECODE (0XF239) -#define PROC_MEM_NB_HY_MNPARTRAINHY_FILECODE (0XF23A) -#define PROC_MEM_NB_HY_MNPHYHY_FILECODE (0XF23B) -#define PROC_MEM_NB_HY_MNPROTOHY_FILECODE (0XF23C) -#define PROC_MEM_NB_HY_MNS3HY_FILECODE (0XF23D) -#define PROC_MEM_NB_HY_MNREGHY_FILECODE (0XF23E) +#define PROC_MEM_NB_DR_MNDR_FILECODE (0xF213) +#define PROC_MEM_NB_DR_MNFLOWDR_FILECODE (0xF214) +#define PROC_MEM_NB_DR_MNIDENDIMMDR_FILECODE (0xF216) +#define PROC_MEM_NB_DR_MNMCTDR_FILECODE (0xF217) +#define PROC_MEM_NB_DR_MNDCTDR_FILECODE (0xF218) +#define PROC_MEM_NB_DR_MNOTDR_FILECODE (0xF219) +#define PROC_MEM_NB_DR_MNPARTRAINDR_FILECODE (0xF21A) +#define PROC_MEM_NB_DR_MNPROTODR_FILECODE (0xF21C) +#define PROC_MEM_NB_DR_MNS3DR_FILECODE (0xF21D) +#define PROC_MEM_NB_DR_MNREGDR_FILECODE (0xF21E) +#define PROC_MEM_NB_RB_MNRB_FILECODE (0xF220) +#define PROC_MEM_NB_RB_MNFLOWRB_FILECODE (0xF221) +#define PROC_MEM_NB_RB_MNS3RB_FILECODE (0xF222) +#define PROC_MEM_NB_RB_MNIDENDIMMRB_FILECODE (0xF223) +#define PROC_MEM_NB_HY_MNFLOWHY_FILECODE (0xF233) +#define PROC_MEM_NB_HY_MNHY_FILECODE (0xF235) +#define PROC_MEM_NB_HY_MNIDENDIMMHY_FILECODE (0xF236) +#define PROC_MEM_NB_HY_MNMCTHY_FILECODE (0xF237) +#define PROC_MEM_NB_HY_MNDCTHY_FILECODE (0xF238) +#define PROC_MEM_NB_HY_MNOTHY_FILECODE (0xF239) +#define PROC_MEM_NB_HY_MNPARTRAINHY_FILECODE (0xF23A) +#define PROC_MEM_NB_HY_MNPHYHY_FILECODE (0xF23B) +#define PROC_MEM_NB_HY_MNPROTOHY_FILECODE (0xF23C) +#define PROC_MEM_NB_HY_MNS3HY_FILECODE (0xF23D) +#define PROC_MEM_NB_HY_MNREGHY_FILECODE (0xF23E) #define PROC_MEM_NB_ON_MNON_FILECODE (0xF240) #define PROC_MEM_NB_ON_MNREGON_FILECODE (0xF241) #define PROC_MEM_NB_ON_MNDCTON_FILECODE (0xF242) @@ -663,190 +663,190 @@ #define PROC_MEM_NB_ON_MNS3ON_FILECODE (0xF248) #define PROC_MEM_NB_ON_MNFLOWON_FILECODE (0xF249) #define PROC_MEM_NB_ON_MNPROTOON_FILECODE (0xF24A) -#define PROC_MEM_NB_LN_MNDCTLN_FILECODE (0XF252) -#define PROC_MEM_NB_LN_MNFLOWLN_FILECODE (0XF253) -#define PROC_MEM_NB_LN_MNIDENDIMMLN_FILECODE (0XF254) -#define PROC_MEM_NB_LN_MNMCTLN_FILECODE (0XF255) -#define PROC_MEM_NB_LN_MNOTLN_FILECODE (0XF256) -#define PROC_MEM_NB_LN_MNPHYLN_FILECODE (0XF257) -#define PROC_MEM_NB_LN_MNPROTOLN_FILECODE (0XF258) -#define PROC_MEM_NB_LN_MNLN_FILECODE (0XF259) -#define PROC_MEM_NB_LN_MNS3LN_FILECODE (0XF25A) -#define PROC_MEM_NB_LN_MNREGLN_FILECODE (0XF25B) -#define PROC_MEM_NB_DA_MNDA_FILECODE (0XF260) -#define PROC_MEM_NB_DA_MNFLOWDA_FILECODE (0XF261) -#define PROC_MEM_NB_DA_MNIDENDIMMDA_FILECODE (0XF263) -#define PROC_MEM_NB_DA_MNMCTDA_FILECODE (0XF264) -#define PROC_MEM_NB_DA_MNDCTDA_FILECODE (0XF265) -#define PROC_MEM_NB_DA_MNOTDA_FILECODE (0XF266) -#define PROC_MEM_NB_DA_MNPARTRAINDA_FILECODE (0XF267) -#define PROC_MEM_NB_DA_MNPROTODA_FILECODE (0XF269) -#define PROC_MEM_NB_DA_MNS3DA_FILECODE (0XF26A) -#define PROC_MEM_NB_DA_MNREGDA_FILECODE (0XF26B) -#define PROC_MEM_NB_C32_MNC32_FILECODE (0XF26C) -#define PROC_MEM_NB_C32_MNDCTC32_FILECODE (0XF26D) -#define PROC_MEM_NB_C32_MNFLOWC32_FILECODE (0XF26E) -#define PROC_MEM_NB_C32_MNIDENDIMMC32_FILECODE (0XF26F) -#define PROC_MEM_NB_C32_MNMCTC32_FILECODE (0XF270) -#define PROC_MEM_NB_C32_MNOTC32_FILECODE (0XF271) -#define PROC_MEM_NB_C32_MNPARTRAINC32_FILECODE (0XF272) -#define PROC_MEM_NB_C32_MNPHYC32_FILECODE (0XF273) -#define PROC_MEM_NB_C32_MNPROTOC32_FILECODE (0XF274) -#define PROC_MEM_NB_C32_MNS3C32_FILECODE (0XF275) -#define PROC_MEM_NB_C32_MNREGC32_FILECODE (0XF277) -#define PROC_MEM_NB_MN_FILECODE (0XF27C) -#define PROC_MEM_NB_MNDCT_FILECODE (0XF27D) -#define PROC_MEM_NB_MNPHY_FILECODE (0XF27E) -#define PROC_MEM_NB_MNMCT_FILECODE (0XF27F) -#define PROC_MEM_NB_MNS3_FILECODE (0XF280) -#define PROC_MEM_NB_MNFLOW_FILECODE (0XF281) -#define PROC_MEM_NB_MNFEAT_FILECODE (0XF282) -#define PROC_MEM_NB_MNTRAIN2_FILECODE (0XF283) -#define PROC_MEM_NB_MNTRAIN3_FILECODE (0XF284) -#define PROC_MEM_NB_MNREG_FILECODE (0XF285) -#define PROC_MEM_NB_NI_MNNI_FILECODE (0XF286) -#define PROC_MEM_NB_NI_MNS3NI_FILECODE (0XF287) -#define PROC_MEM_NB_NI_MNFLOWNI_FILECODE (0XF288) -#define PROC_MEM_NB_PH_MNFLOWPH_FILECODE (0XF289) -#define PROC_MEM_NB_PH_MNPH_FILECODE (0XF28A) -#define PROC_MEM_NB_PH_MNS3PH_FILECODE (0XF28B) -#define PROC_MEM_NB_PH_MNIDENDIMMPH_FILECODE (0XF28C) -#define PROC_MEM_NB_OR_MNFLOWOR_FILECODE (0XF290) -#define PROC_MEM_NB_OR_MNOR_FILECODE (0XF291) -#define PROC_MEM_NB_OR_MNIDENDIMMOR_FILECODE (0XF292) -#define PROC_MEM_NB_OR_MNMCTOR_FILECODE (0XF293) -#define PROC_MEM_NB_OR_MNDCTOR_FILECODE (0XF294) -#define PROC_MEM_NB_OR_MNOTOR_FILECODE (0XF295) -#define PROC_MEM_NB_OR_MNPARTRAINOR_FILECODE (0XF296) -#define PROC_MEM_NB_OR_MNPHYOR_FILECODE (0XF297) -#define PROC_MEM_NB_OR_MNPROTOOR_FILECODE (0XF298) -#define PROC_MEM_NB_OR_MNS3OR_FILECODE (0XF299) -#define PROC_MEM_NB_OR_MNREGOR_FILECODE (0XF29A) +#define PROC_MEM_NB_LN_MNDCTLN_FILECODE (0xF252) +#define PROC_MEM_NB_LN_MNFLOWLN_FILECODE (0xF253) +#define PROC_MEM_NB_LN_MNIDENDIMMLN_FILECODE (0xF254) +#define PROC_MEM_NB_LN_MNMCTLN_FILECODE (0xF255) +#define PROC_MEM_NB_LN_MNOTLN_FILECODE (0xF256) +#define PROC_MEM_NB_LN_MNPHYLN_FILECODE (0xF257) +#define PROC_MEM_NB_LN_MNPROTOLN_FILECODE (0xF258) +#define PROC_MEM_NB_LN_MNLN_FILECODE (0xF259) +#define PROC_MEM_NB_LN_MNS3LN_FILECODE (0xF25A) +#define PROC_MEM_NB_LN_MNREGLN_FILECODE (0xF25B) +#define PROC_MEM_NB_DA_MNDA_FILECODE (0xF260) +#define PROC_MEM_NB_DA_MNFLOWDA_FILECODE (0xF261) +#define PROC_MEM_NB_DA_MNIDENDIMMDA_FILECODE (0xF263) +#define PROC_MEM_NB_DA_MNMCTDA_FILECODE (0xF264) +#define PROC_MEM_NB_DA_MNDCTDA_FILECODE (0xF265) +#define PROC_MEM_NB_DA_MNOTDA_FILECODE (0xF266) +#define PROC_MEM_NB_DA_MNPARTRAINDA_FILECODE (0xF267) +#define PROC_MEM_NB_DA_MNPROTODA_FILECODE (0xF269) +#define PROC_MEM_NB_DA_MNS3DA_FILECODE (0xF26A) +#define PROC_MEM_NB_DA_MNREGDA_FILECODE (0xF26B) +#define PROC_MEM_NB_C32_MNC32_FILECODE (0xF26C) +#define PROC_MEM_NB_C32_MNDCTC32_FILECODE (0xF26D) +#define PROC_MEM_NB_C32_MNFLOWC32_FILECODE (0xF26E) +#define PROC_MEM_NB_C32_MNIDENDIMMC32_FILECODE (0xF26F) +#define PROC_MEM_NB_C32_MNMCTC32_FILECODE (0xF270) +#define PROC_MEM_NB_C32_MNOTC32_FILECODE (0xF271) +#define PROC_MEM_NB_C32_MNPARTRAINC32_FILECODE (0xF272) +#define PROC_MEM_NB_C32_MNPHYC32_FILECODE (0xF273) +#define PROC_MEM_NB_C32_MNPROTOC32_FILECODE (0xF274) +#define PROC_MEM_NB_C32_MNS3C32_FILECODE (0xF275) +#define PROC_MEM_NB_C32_MNREGC32_FILECODE (0xF277) +#define PROC_MEM_NB_MN_FILECODE (0xF27C) +#define PROC_MEM_NB_MNDCT_FILECODE (0xF27D) +#define PROC_MEM_NB_MNPHY_FILECODE (0xF27E) +#define PROC_MEM_NB_MNMCT_FILECODE (0xF27F) +#define PROC_MEM_NB_MNS3_FILECODE (0xF280) +#define PROC_MEM_NB_MNFLOW_FILECODE (0xF281) +#define PROC_MEM_NB_MNFEAT_FILECODE (0xF282) +#define PROC_MEM_NB_MNTRAIN2_FILECODE (0xF283) +#define PROC_MEM_NB_MNTRAIN3_FILECODE (0xF284) +#define PROC_MEM_NB_MNREG_FILECODE (0xF285) +#define PROC_MEM_NB_NI_MNNI_FILECODE (0xF286) +#define PROC_MEM_NB_NI_MNS3NI_FILECODE (0xF287) +#define PROC_MEM_NB_NI_MNFLOWNI_FILECODE (0xF288) +#define PROC_MEM_NB_PH_MNFLOWPH_FILECODE (0xF289) +#define PROC_MEM_NB_PH_MNPH_FILECODE (0xF28A) +#define PROC_MEM_NB_PH_MNS3PH_FILECODE (0xF28B) +#define PROC_MEM_NB_PH_MNIDENDIMMPH_FILECODE (0xF28C) +#define PROC_MEM_NB_OR_MNFLOWOR_FILECODE (0xF290) +#define PROC_MEM_NB_OR_MNOR_FILECODE (0xF291) +#define PROC_MEM_NB_OR_MNIDENDIMMOR_FILECODE (0xF292) +#define PROC_MEM_NB_OR_MNMCTOR_FILECODE (0xF293) +#define PROC_MEM_NB_OR_MNDCTOR_FILECODE (0xF294) +#define PROC_MEM_NB_OR_MNOTOR_FILECODE (0xF295) +#define PROC_MEM_NB_OR_MNPARTRAINOR_FILECODE (0xF296) +#define PROC_MEM_NB_OR_MNPHYOR_FILECODE (0xF297) +#define PROC_MEM_NB_OR_MNPROTOOR_FILECODE (0xF298) +#define PROC_MEM_NB_OR_MNS3OR_FILECODE (0xF299) +#define PROC_MEM_NB_OR_MNREGOR_FILECODE (0xF29A) -#define PROC_MEM_PS_MP_FILECODE (0XF401) -#define PROC_MEM_PS_DR_MPRDR3_FILECODE (0XF402) -#define PROC_MEM_PS_HY_MPRHY3_FILECODE (0XF403) -#define PROC_MEM_PS_LN_MPRLN3_FILECODE (0XF404) -#define PROC_MEM_PS_DR_MPSDR3_FILECODE (0XF405) -#define PROC_MEM_PS_HY_MPSHY3_FILECODE (0XF406) -#define PROC_MEM_PS_LN_MPSLN3_FILECODE (0XF407) -#define PROC_MEM_PS_DR_MPUDR3_FILECODE (0XF408) -#define PROC_MEM_PS_HY_MPUHY3_FILECODE (0XF409) -#define PROC_MEM_PS_LN_MPULN3_FILECODE (0XF40A) -#define PROC_MEM_PS_DA_MPUDA3_FILECODE (0XF40B) -#define PROC_MEM_PS_DA_MPSDA2_FILECODE (0XF40C) -#define PROC_MEM_PS_DA_MPSDA3_FILECODE (0XF40D) -#define PROC_MEM_PS_DR_MPRDR2_FILECODE (0XF40E) -#define PROC_MEM_PS_DR_MPUDR2_FILECODE (0XF40F) -#define PROC_MEM_PS_C32_MPRC32_3_FILECODE (0XF410) -#define PROC_MEM_PS_C32_MPUC32_3_FILECODE (0XF411) -#define PROC_MEM_PS_NI_MPSNI3_FILECODE (0XF412) -#define PROC_MEM_PS_NI_MPUNI3_FILECODE (0XF413) -#define PROC_MEM_PS_ON_MPSON3_FILECODE (0XF414) -#define PROC_MEM_PS_ON_MPUON3_FILECODE (0XF415) -#define PROC_MEM_PS_PH_MPSPH3_FILECODE (0XF416) -#define PROC_MEM_PS_PH_MPUPH3_FILECODE (0XF417) -#define PROC_MEM_PS_RB_MPSRB3_FILECODE (0XF418) -#define PROC_MEM_PS_RB_MPURB3_FILECODE (0XF419) -#define PROC_MEM_PS_OR_AM3_MPUORA3_FILECODE (0XF41A) -#define PROC_MEM_PS_OR_AM3_MPSORA3_FILECODE (0XF41B) -#define PROC_MEM_PS_OR_C32_MPRORC3_FILECODE (0XF41C) -#define PROC_MEM_PS_OR_C32_MPUORC3_FILECODE (0XF41D) -#define PROC_MEM_PS_OR_C32_MPLORC3_FILECODE (0XF41E) -#define PROC_MEM_PS_OR_G34_MPRORG3_FILECODE (0XF41F) -#define PROC_MEM_PS_OR_G34_MPUORG3_FILECODE (0XF420) -#define PROC_MEM_PS_OR_G34_MPLORG3_FILECODE (0XF421) -#define PROC_MEM_PS_MPRTT_FILECODE (0XF422) -#define PROC_MEM_PS_MPMAXFREQ_FILECODE (0XF423) -#define PROC_MEM_PS_MPODTPAT_FILECODE (0XF424) -#define PROC_MEM_PS_MPSAO_FILECODE (0XF425) -#define PROC_MEM_PS_MPMR0_FILECODE (0XF426) -#define PROC_MEM_PS_MPRC2IBT_FILECODE (0XF427) -#define PROC_MEM_PS_MPRC10OPSPD_FILECODE (0XF428) -#define PROC_MEM_PS_MPLRIBT_FILECODE (0XF429) -#define PROC_MEM_PS_MPLRNPR_FILECODE (0XF42A) -#define PROC_MEM_PS_MPLRNLR_FILECODE (0XF42B) -#define PROC_MEM_PS_OR_MPOR3_FILECODE (0XF42C) +#define PROC_MEM_PS_MP_FILECODE (0xF401) +#define PROC_MEM_PS_DR_MPRDR3_FILECODE (0xF402) +#define PROC_MEM_PS_HY_MPRHY3_FILECODE (0xF403) +#define PROC_MEM_PS_LN_MPRLN3_FILECODE (0xF404) +#define PROC_MEM_PS_DR_MPSDR3_FILECODE (0xF405) +#define PROC_MEM_PS_HY_MPSHY3_FILECODE (0xF406) +#define PROC_MEM_PS_LN_MPSLN3_FILECODE (0xF407) +#define PROC_MEM_PS_DR_MPUDR3_FILECODE (0xF408) +#define PROC_MEM_PS_HY_MPUHY3_FILECODE (0xF409) +#define PROC_MEM_PS_LN_MPULN3_FILECODE (0xF40A) +#define PROC_MEM_PS_DA_MPUDA3_FILECODE (0xF40B) +#define PROC_MEM_PS_DA_MPSDA2_FILECODE (0xF40C) +#define PROC_MEM_PS_DA_MPSDA3_FILECODE (0xF40D) +#define PROC_MEM_PS_DR_MPRDR2_FILECODE (0xF40E) +#define PROC_MEM_PS_DR_MPUDR2_FILECODE (0xF40F) +#define PROC_MEM_PS_C32_MPRC32_3_FILECODE (0xF410) +#define PROC_MEM_PS_C32_MPUC32_3_FILECODE (0xF411) +#define PROC_MEM_PS_NI_MPSNI3_FILECODE (0xF412) +#define PROC_MEM_PS_NI_MPUNI3_FILECODE (0xF413) +#define PROC_MEM_PS_ON_MPSON3_FILECODE (0xF414) +#define PROC_MEM_PS_ON_MPUON3_FILECODE (0xF415) +#define PROC_MEM_PS_PH_MPSPH3_FILECODE (0xF416) +#define PROC_MEM_PS_PH_MPUPH3_FILECODE (0xF417) +#define PROC_MEM_PS_RB_MPSRB3_FILECODE (0xF418) +#define PROC_MEM_PS_RB_MPURB3_FILECODE (0xF419) +#define PROC_MEM_PS_OR_AM3_MPUORA3_FILECODE (0xF41A) +#define PROC_MEM_PS_OR_AM3_MPSORA3_FILECODE (0xF41B) +#define PROC_MEM_PS_OR_C32_MPRORC3_FILECODE (0xF41C) +#define PROC_MEM_PS_OR_C32_MPUORC3_FILECODE (0xF41D) +#define PROC_MEM_PS_OR_C32_MPLORC3_FILECODE (0xF41E) +#define PROC_MEM_PS_OR_G34_MPRORG3_FILECODE (0xF41F) +#define PROC_MEM_PS_OR_G34_MPUORG3_FILECODE (0xF420) +#define PROC_MEM_PS_OR_G34_MPLORG3_FILECODE (0xF421) +#define PROC_MEM_PS_MPRTT_FILECODE (0xF422) +#define PROC_MEM_PS_MPMAXFREQ_FILECODE (0xF423) +#define PROC_MEM_PS_MPODTPAT_FILECODE (0xF424) +#define PROC_MEM_PS_MPSAO_FILECODE (0xF425) +#define PROC_MEM_PS_MPMR0_FILECODE (0xF426) +#define PROC_MEM_PS_MPRC2IBT_FILECODE (0xF427) +#define PROC_MEM_PS_MPRC10OPSPD_FILECODE (0xF428) +#define PROC_MEM_PS_MPLRIBT_FILECODE (0xF429) +#define PROC_MEM_PS_MPLRNPR_FILECODE (0xF42A) +#define PROC_MEM_PS_MPLRNLR_FILECODE (0xF42B) +#define PROC_MEM_PS_OR_MPOR3_FILECODE (0xF42C) -#define PROC_MEM_TECH_MT_FILECODE (0XF501) -#define PROC_MEM_TECH_MTHDI_FILECODE (0XF502) -#define PROC_MEM_TECH_MTTDIMBT_FILECODE (0XF504) -#define PROC_MEM_TECH_MTTECC_FILECODE (0XF505) -#define PROC_MEM_TECH_MTTHRC_FILECODE (0XF506) -#define PROC_MEM_TECH_MTTML_FILECODE (0XF507) -#define PROC_MEM_TECH_MTTOPTSRC_FILECODE (0XF509) -#define PROC_MEM_TECH_MTTSRC_FILECODE (0XF50B) -#define PROC_MEM_TECH_MTTEDGEDETECT_FILECODE (0XF50C) -#define PROC_MEM_TECH_DDR2_MT2_FILECODE (0XF541) -#define PROC_MEM_TECH_DDR2_MTOT2_FILECODE (0XF543) -#define PROC_MEM_TECH_DDR2_MTSPD2_FILECODE (0XF544) -#define PROC_MEM_TECH_DDR3_MT3_FILECODE (0XF581) -#define PROC_MEM_TECH_DDR3_MTOT3_FILECODE (0XF583) -#define PROC_MEM_TECH_DDR3_MTRCI3_FILECODE (0XF584) -#define PROC_MEM_TECH_DDR3_MTSDI3_FILECODE (0XF585) -#define PROC_MEM_TECH_DDR3_MTSPD3_FILECODE (0XF586) -#define PROC_MEM_TECH_DDR3_MTTWL3_FILECODE (0XF587) -#define PROC_MEM_TECH_DDR3_MTTECC3_FILECODE (0XF588) -#define PROC_MEM_TECH_DDR3_MTLRDIMM3_FILECODE (0XF589) +#define PROC_MEM_TECH_MT_FILECODE (0xF501) +#define PROC_MEM_TECH_MTHDI_FILECODE (0xF502) +#define PROC_MEM_TECH_MTTDIMBT_FILECODE (0xF504) +#define PROC_MEM_TECH_MTTECC_FILECODE (0xF505) +#define PROC_MEM_TECH_MTTHRC_FILECODE (0xF506) +#define PROC_MEM_TECH_MTTML_FILECODE (0xF507) +#define PROC_MEM_TECH_MTTOPTSRC_FILECODE (0xF509) +#define PROC_MEM_TECH_MTTSRC_FILECODE (0xF50B) +#define PROC_MEM_TECH_MTTEDGEDETECT_FILECODE (0xF50C) +#define PROC_MEM_TECH_DDR2_MT2_FILECODE (0xF541) +#define PROC_MEM_TECH_DDR2_MTOT2_FILECODE (0xF543) +#define PROC_MEM_TECH_DDR2_MTSPD2_FILECODE (0xF544) +#define PROC_MEM_TECH_DDR3_MT3_FILECODE (0xF581) +#define PROC_MEM_TECH_DDR3_MTOT3_FILECODE (0xF583) +#define PROC_MEM_TECH_DDR3_MTRCI3_FILECODE (0xF584) +#define PROC_MEM_TECH_DDR3_MTSDI3_FILECODE (0xF585) +#define PROC_MEM_TECH_DDR3_MTSPD3_FILECODE (0xF586) +#define PROC_MEM_TECH_DDR3_MTTWL3_FILECODE (0xF587) +#define PROC_MEM_TECH_DDR3_MTTECC3_FILECODE (0xF588) +#define PROC_MEM_TECH_DDR3_MTLRDIMM3_FILECODE (0xF589) -#define PROC_RECOVERY_MEM_MRDEF_FILECODE (0XF801) -#define PROC_RECOVERY_MEM_MRINIT_FILECODE (0XF802) -#define PROC_RECOVERY_MEM_MRM_FILECODE (0XF803) -#define PROC_RECOVERY_MEM_MRUC_FILECODE (0XF804) -#define PROC_RECOVERY_MEM_NB_DR_MRNDR_FILECODE (0XF812) -#define PROC_RECOVERY_MEM_NB_DR_MRNMCTDR_FILECODE (0XF813) -#define PROC_RECOVERY_MEM_NB_HY_MRNDCTHY_FILECODE (0XF821) -#define PROC_RECOVERY_MEM_NB_HY_MRNHY_FILECODE (0XF822) -#define PROC_RECOVERY_MEM_NB_HY_MRNMCTHY_FILECODE (0XF823) -#define PROC_RECOVERY_MEM_NB_HY_MRNPROTOHY_FILECODE (0XF825) -#define PROC_RECOVERY_MEM_NB_LN_MRNDCTLN_FILECODE (0XF831) -#define PROC_RECOVERY_MEM_NB_LN_MRNMCTLN_FILECODE (0XF832) -#define PROC_RECOVERY_MEM_NB_LN_MRNLN_FILECODE (0XF833) -#define PROC_RECOVERY_MEM_NB_DA_MRNDA_FILECODE (0XF842) -#define PROC_RECOVERY_MEM_NB_DA_MRNMCTDA_FILECODE (0XF843) -#define PROC_RECOVERY_MEM_NB_NI_MRNNI_FILECODE (0XF845) -#define PROC_RECOVERY_MEM_NB_C32_MRNC32_FILECODE (0XF851) -#define PROC_RECOVERY_MEM_NB_C32_MRNMCTC32_FILECODE (0XF852) -#define PROC_RECOVERY_MEM_NB_C32_MRNPROTOC32_FILECODE (0XF853) +#define PROC_RECOVERY_MEM_MRDEF_FILECODE (0xF801) +#define PROC_RECOVERY_MEM_MRINIT_FILECODE (0xF802) +#define PROC_RECOVERY_MEM_MRM_FILECODE (0xF803) +#define PROC_RECOVERY_MEM_MRUC_FILECODE (0xF804) +#define PROC_RECOVERY_MEM_NB_DR_MRNDR_FILECODE (0xF812) +#define PROC_RECOVERY_MEM_NB_DR_MRNMCTDR_FILECODE (0xF813) +#define PROC_RECOVERY_MEM_NB_HY_MRNDCTHY_FILECODE (0xF821) +#define PROC_RECOVERY_MEM_NB_HY_MRNHY_FILECODE (0xF822) +#define PROC_RECOVERY_MEM_NB_HY_MRNMCTHY_FILECODE (0xF823) +#define PROC_RECOVERY_MEM_NB_HY_MRNPROTOHY_FILECODE (0xF825) +#define PROC_RECOVERY_MEM_NB_LN_MRNDCTLN_FILECODE (0xF831) +#define PROC_RECOVERY_MEM_NB_LN_MRNMCTLN_FILECODE (0xF832) +#define PROC_RECOVERY_MEM_NB_LN_MRNLN_FILECODE (0xF833) +#define PROC_RECOVERY_MEM_NB_DA_MRNDA_FILECODE (0xF842) +#define PROC_RECOVERY_MEM_NB_DA_MRNMCTDA_FILECODE (0xF843) +#define PROC_RECOVERY_MEM_NB_NI_MRNNI_FILECODE (0xF845) +#define PROC_RECOVERY_MEM_NB_C32_MRNC32_FILECODE (0xF851) +#define PROC_RECOVERY_MEM_NB_C32_MRNMCTC32_FILECODE (0xF852) +#define PROC_RECOVERY_MEM_NB_C32_MRNPROTOC32_FILECODE (0xF853) #define PROC_RECOVERY_MEM_NB_ON_MRNDCTON_FILECODE (0xF861) #define PROC_RECOVERY_MEM_NB_ON_MRNMCTON_FILECODE (0xF862) #define PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE (0xF863) #define PROC_RECOVERY_MEM_NB_PH_MRNPH_FILECODE (0xF871) #define PROC_RECOVERY_MEM_NB_RB_MRNRB_FILECODE (0xF881) -#define PROC_RECOVERY_MEM_TECH_MRTTPOS_FILECODE (0XF8C1) -#define PROC_RECOVERY_MEM_TECH_MRTTSRC_FILECODE (0XF8C2) -#define PROC_RECOVERY_MEM_TECH_DDR3_MRT3_FILECODE (0XF8C3) -#define PROC_RECOVERY_MEM_TECH_DDR3_MRTRCI3_FILECODE (0XF8C4) -#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSDI3_FILECODE (0XF8C5) -#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSPD3_FILECODE (0XF8C6) -#define PROC_RECOVERY_MEM_TECH_DDR3_MRTTWL3_FILECODE (0XF8C7) -#define PROC_RECOVERY_MEM_NB_MRN_FILECODE (0XF8C8) -#define PROC_RECOVERY_MEM_NB_MRNDCT_FILECODE (0XF8C9) -#define PROC_RECOVERY_MEM_NB_MRNMCT_FILECODE (0XF8CA) -#define PROC_RECOVERY_MEM_NB_MRNTRAIN3_FILECODE (0XF8CB) -#define PROC_RECOVERY_MEM_TECH_MRTTHRC_FILECODE (0XF8CC) -#define PROC_RECOVERY_MEM_NB_OR_MRNDCTOR_FILECODE (0XF8CD) -#define PROC_RECOVERY_MEM_NB_OR_MRNOR_FILECODE (0XF8CE) -#define PROC_RECOVERY_MEM_NB_OR_MRNMCTOR_FILECODE (0XF8CF) -#define PROC_RECOVERY_MEM_NB_OR_MRNPROTOOR_FILECODE (0XF8D0) -#define PROC_RECOVERY_MEM_PS_MRP_FILECODE (0XF8E0) -#define PROC_RECOVERY_MEM_PS_MRPRTT_FILECODE (0XF8E1) -#define PROC_RECOVERY_MEM_PS_MRPODTPAT_FILECODE (0XF8E2) -#define PROC_RECOVERY_MEM_PS_MRPSAO_FILECODE (0XF8E3) -#define PROC_RECOVERY_MEM_PS_MRPMR0_FILECODE (0XF8E4) -#define PROC_RECOVERY_MEM_PS_MRPRC2IBT_FILECODE (0XF8E5) -#define PROC_RECOVERY_MEM_PS_MRPRC10OPSPD_FILECODE (0XF8E6) -#define PROC_RECOVERY_MEM_PS_MRPLRIBT_FILECODE (0XF8E7) -#define PROC_RECOVERY_MEM_PS_MRPLRNPR_FILECODE (0XF8E8) -#define PROC_RECOVERY_MEM_PS_MRPLRNLR_FILECODE (0XF8E9) -#define PROC_RECOVERY_MEM_PS_OR_MRPOR3_FILECODE (0XF8EA) -#define PROC_RECOVERY_MEM_PS_OR_AM3_MRPSORA3_FILECODE (0XF8EB) -#define PROC_RECOVERY_MEM_PS_OR_AM3_MRPUORA3_FILECODE (0XF8EC) -#define PROC_RECOVERY_MEM_PS_OR_C32_MRPUORC3_FILECODE (0XF8ED) -#define PROC_RECOVERY_MEM_PS_OR_C32_MRPRORC3_FILECODE (0XF8EE) -#define PROC_RECOVERY_MEM_PS_OR_C32_MRPLORC3_FILECODE (0XF8EF) -#define PROC_RECOVERY_MEM_PS_OR_G34_MRPUORG3_FILECODE (0XF8F0) -#define PROC_RECOVERY_MEM_PS_OR_G34_MRPRORG3_FILECODE (0XF8F1) -#define PROC_RECOVERY_MEM_PS_OR_G34_MRPLORG3_FILECODE (0XF8F2) +#define PROC_RECOVERY_MEM_TECH_MRTTPOS_FILECODE (0xF8C1) +#define PROC_RECOVERY_MEM_TECH_MRTTSRC_FILECODE (0xF8C2) +#define PROC_RECOVERY_MEM_TECH_DDR3_MRT3_FILECODE (0xF8C3) +#define PROC_RECOVERY_MEM_TECH_DDR3_MRTRCI3_FILECODE (0xF8C4) +#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSDI3_FILECODE (0xF8C5) +#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSPD3_FILECODE (0xF8C6) +#define PROC_RECOVERY_MEM_TECH_DDR3_MRTTWL3_FILECODE (0xF8C7) +#define PROC_RECOVERY_MEM_NB_MRN_FILECODE (0xF8C8) +#define PROC_RECOVERY_MEM_NB_MRNDCT_FILECODE (0xF8C9) +#define PROC_RECOVERY_MEM_NB_MRNMCT_FILECODE (0xF8CA) +#define PROC_RECOVERY_MEM_NB_MRNTRAIN3_FILECODE (0xF8CB) +#define PROC_RECOVERY_MEM_TECH_MRTTHRC_FILECODE (0xF8CC) +#define PROC_RECOVERY_MEM_NB_OR_MRNDCTOR_FILECODE (0xF8CD) +#define PROC_RECOVERY_MEM_NB_OR_MRNOR_FILECODE (0xF8CE) +#define PROC_RECOVERY_MEM_NB_OR_MRNMCTOR_FILECODE (0xF8CF) +#define PROC_RECOVERY_MEM_NB_OR_MRNPROTOOR_FILECODE (0xF8D0) +#define PROC_RECOVERY_MEM_PS_MRP_FILECODE (0xF8E0) +#define PROC_RECOVERY_MEM_PS_MRPRTT_FILECODE (0xF8E1) +#define PROC_RECOVERY_MEM_PS_MRPODTPAT_FILECODE (0xF8E2) +#define PROC_RECOVERY_MEM_PS_MRPSAO_FILECODE (0xF8E3) +#define PROC_RECOVERY_MEM_PS_MRPMR0_FILECODE (0xF8E4) +#define PROC_RECOVERY_MEM_PS_MRPRC2IBT_FILECODE (0xF8E5) +#define PROC_RECOVERY_MEM_PS_MRPRC10OPSPD_FILECODE (0xF8E6) +#define PROC_RECOVERY_MEM_PS_MRPLRIBT_FILECODE (0xF8E7) +#define PROC_RECOVERY_MEM_PS_MRPLRNPR_FILECODE (0xF8E8) +#define PROC_RECOVERY_MEM_PS_MRPLRNLR_FILECODE (0xF8E9) +#define PROC_RECOVERY_MEM_PS_OR_MRPOR3_FILECODE (0xF8EA) +#define PROC_RECOVERY_MEM_PS_OR_AM3_MRPSORA3_FILECODE (0xF8EB) +#define PROC_RECOVERY_MEM_PS_OR_AM3_MRPUORA3_FILECODE (0xF8EC) +#define PROC_RECOVERY_MEM_PS_OR_C32_MRPUORC3_FILECODE (0xF8ED) +#define PROC_RECOVERY_MEM_PS_OR_C32_MRPRORC3_FILECODE (0xF8EE) +#define PROC_RECOVERY_MEM_PS_OR_C32_MRPLORC3_FILECODE (0xF8EF) +#define PROC_RECOVERY_MEM_PS_OR_G34_MRPUORG3_FILECODE (0xF8F0) +#define PROC_RECOVERY_MEM_PS_OR_G34_MRPRORG3_FILECODE (0xF8F1) +#define PROC_RECOVERY_MEM_PS_OR_G34_MRPLORG3_FILECODE (0xF8F2) #endif // _FILECODE_H_ diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Table.h b/src/vendorcode/amd/agesa/f14/Proc/CPU/Table.h index 2d33021..6c047a1 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Table.h +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Table.h @@ -474,7 +474,7 @@ } PACKAGE_TYPE_FEATURES; // Initializer Values for Package Type -#define PACKAGE_TYPE_ALL 0XFFFF ///< Package Type apply all packages +#define PACKAGE_TYPE_ALL 0xFFFF ///< Package Type apply all packages // Initializer Values for Ht Host Pci Config Registers #define HT_HOST_FEAT_COHERENT BIT0 diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuRegisters.h b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuRegisters.h index 7d43c17..c2ffcb6 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuRegisters.h +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuRegisters.h @@ -203,7 +203,7 @@ #define MSR_CPUID_NAME_STRING0 0xC0010030 // First CPUID namestring register #define MSR_CPUID_NAME_STRING1 0xC0010031 -#define MSR_CPUID_NAME_STRING2 0XC0010032 +#define MSR_CPUID_NAME_STRING2 0xC0010032 #define MSR_CPUID_NAME_STRING3 0xC0010033 #define MSR_CPUID_NAME_STRING4 0xC0010034 #define MSR_CPUID_NAME_STRING5 0xC0010035 // Last CPUID namestring register diff --git a/src/vendorcode/amd/agesa/f15tn/Include/Filecode.h b/src/vendorcode/amd/agesa/f15tn/Include/Filecode.h index 274ef14..670d7a9 100644 --- a/src/vendorcode/amd/agesa/f15tn/Include/Filecode.h +++ b/src/vendorcode/amd/agesa/f15tn/Include/Filecode.h @@ -836,31 +836,31 @@ #define PROC_MEM_MAIN_PH_MMFLOWPH_FILECODE (0xF11B) #define PROC_MEM_MAIN_TN_MMFLOWTN_FILECODE (0xF11C) -#define PROC_MEM_NB_DR_MNDR_FILECODE (0XF213) -#define PROC_MEM_NB_DR_MNFLOWDR_FILECODE (0XF214) -#define PROC_MEM_NB_DR_MNIDENDIMMDR_FILECODE (0XF216) -#define PROC_MEM_NB_DR_MNMCTDR_FILECODE (0XF217) -#define PROC_MEM_NB_DR_MNDCTDR_FILECODE (0XF218) -#define PROC_MEM_NB_DR_MNOTDR_FILECODE (0XF219) -#define PROC_MEM_NB_DR_MNPARTRAINDR_FILECODE (0XF21A) -#define PROC_MEM_NB_DR_MNPROTODR_FILECODE (0XF21C) -#define PROC_MEM_NB_DR_MNS3DR_FILECODE (0XF21D) -#define PROC_MEM_NB_DR_MNREGDR_FILECODE (0XF21E) -#define PROC_MEM_NB_RB_MNRB_FILECODE (0XF220) -#define PROC_MEM_NB_RB_MNFLOWRB_FILECODE (0XF221) -#define PROC_MEM_NB_RB_MNS3RB_FILECODE (0XF222) -#define PROC_MEM_NB_RB_MNIDENDIMMRB_FILECODE (0XF223) -#define PROC_MEM_NB_HY_MNFLOWHY_FILECODE (0XF233) -#define PROC_MEM_NB_HY_MNHY_FILECODE (0XF235) -#define PROC_MEM_NB_HY_MNIDENDIMMHY_FILECODE (0XF236) -#define PROC_MEM_NB_HY_MNMCTHY_FILECODE (0XF237) -#define PROC_MEM_NB_HY_MNDCTHY_FILECODE (0XF238) -#define PROC_MEM_NB_HY_MNOTHY_FILECODE (0XF239) -#define PROC_MEM_NB_HY_MNPARTRAINHY_FILECODE (0XF23A) -#define PROC_MEM_NB_HY_MNPHYHY_FILECODE (0XF23B) -#define PROC_MEM_NB_HY_MNPROTOHY_FILECODE (0XF23C) -#define PROC_MEM_NB_HY_MNS3HY_FILECODE (0XF23D) -#define PROC_MEM_NB_HY_MNREGHY_FILECODE (0XF23E) +#define PROC_MEM_NB_DR_MNDR_FILECODE (0xF213) +#define PROC_MEM_NB_DR_MNFLOWDR_FILECODE (0xF214) +#define PROC_MEM_NB_DR_MNIDENDIMMDR_FILECODE (0xF216) +#define PROC_MEM_NB_DR_MNMCTDR_FILECODE (0xF217) +#define PROC_MEM_NB_DR_MNDCTDR_FILECODE (0xF218) +#define PROC_MEM_NB_DR_MNOTDR_FILECODE (0xF219) +#define PROC_MEM_NB_DR_MNPARTRAINDR_FILECODE (0xF21A) +#define PROC_MEM_NB_DR_MNPROTODR_FILECODE (0xF21C) +#define PROC_MEM_NB_DR_MNS3DR_FILECODE (0xF21D) +#define PROC_MEM_NB_DR_MNREGDR_FILECODE (0xF21E) +#define PROC_MEM_NB_RB_MNRB_FILECODE (0xF220) +#define PROC_MEM_NB_RB_MNFLOWRB_FILECODE (0xF221) +#define PROC_MEM_NB_RB_MNS3RB_FILECODE (0xF222) +#define PROC_MEM_NB_RB_MNIDENDIMMRB_FILECODE (0xF223) +#define PROC_MEM_NB_HY_MNFLOWHY_FILECODE (0xF233) +#define PROC_MEM_NB_HY_MNHY_FILECODE (0xF235) +#define PROC_MEM_NB_HY_MNIDENDIMMHY_FILECODE (0xF236) +#define PROC_MEM_NB_HY_MNMCTHY_FILECODE (0xF237) +#define PROC_MEM_NB_HY_MNDCTHY_FILECODE (0xF238) +#define PROC_MEM_NB_HY_MNOTHY_FILECODE (0xF239) +#define PROC_MEM_NB_HY_MNPARTRAINHY_FILECODE (0xF23A) +#define PROC_MEM_NB_HY_MNPHYHY_FILECODE (0xF23B) +#define PROC_MEM_NB_HY_MNPROTOHY_FILECODE (0xF23C) +#define PROC_MEM_NB_HY_MNS3HY_FILECODE (0xF23D) +#define PROC_MEM_NB_HY_MNREGHY_FILECODE (0xF23E) #define PROC_MEM_NB_ON_MNON_FILECODE (0xF240) #define PROC_MEM_NB_ON_MNREGON_FILECODE (0xF241) #define PROC_MEM_NB_ON_MNDCTON_FILECODE (0xF242) @@ -871,171 +871,171 @@ #define PROC_MEM_NB_ON_MNS3ON_FILECODE (0xF248) #define PROC_MEM_NB_ON_MNFLOWON_FILECODE (0xF249) #define PROC_MEM_NB_ON_MNPROTOON_FILECODE (0xF24A) -#define PROC_MEM_NB_LN_MNDCTLN_FILECODE (0XF252) -#define PROC_MEM_NB_LN_MNFLOWLN_FILECODE (0XF253) -#define PROC_MEM_NB_LN_MNIDENDIMMLN_FILECODE (0XF254) -#define PROC_MEM_NB_LN_MNMCTLN_FILECODE (0XF255) -#define PROC_MEM_NB_LN_MNOTLN_FILECODE (0XF256) -#define PROC_MEM_NB_LN_MNPHYLN_FILECODE (0XF257) -#define PROC_MEM_NB_LN_MNPROTOLN_FILECODE (0XF258) -#define PROC_MEM_NB_LN_MNLN_FILECODE (0XF259) -#define PROC_MEM_NB_LN_MNS3LN_FILECODE (0XF25A) -#define PROC_MEM_NB_LN_MNREGLN_FILECODE (0XF25B) -#define PROC_MEM_NB_DA_MNDA_FILECODE (0XF260) -#define PROC_MEM_NB_DA_MNFLOWDA_FILECODE (0XF261) -#define PROC_MEM_NB_DA_MNIDENDIMMDA_FILECODE (0XF263) -#define PROC_MEM_NB_DA_MNMCTDA_FILECODE (0XF264) -#define PROC_MEM_NB_DA_MNDCTDA_FILECODE (0XF265) -#define PROC_MEM_NB_DA_MNOTDA_FILECODE (0XF266) -#define PROC_MEM_NB_DA_MNPARTRAINDA_FILECODE (0XF267) -#define PROC_MEM_NB_DA_MNPROTODA_FILECODE (0XF269) -#define PROC_MEM_NB_DA_MNS3DA_FILECODE (0XF26A) -#define PROC_MEM_NB_DA_MNREGDA_FILECODE (0XF26B) -#define PROC_MEM_NB_C32_MNC32_FILECODE (0XF26C) -#define PROC_MEM_NB_C32_MNDCTC32_FILECODE (0XF26D) -#define PROC_MEM_NB_C32_MNFLOWC32_FILECODE (0XF26E) -#define PROC_MEM_NB_C32_MNIDENDIMMC32_FILECODE (0XF26F) -#define PROC_MEM_NB_C32_MNMCTC32_FILECODE (0XF270) -#define PROC_MEM_NB_C32_MNOTC32_FILECODE (0XF271) -#define PROC_MEM_NB_C32_MNPARTRAINC32_FILECODE (0XF272) -#define PROC_MEM_NB_C32_MNPHYC32_FILECODE (0XF273) -#define PROC_MEM_NB_C32_MNPROTOC32_FILECODE (0XF274) -#define PROC_MEM_NB_C32_MNS3C32_FILECODE (0XF275) -#define PROC_MEM_NB_C32_MNREGC32_FILECODE (0XF277) -#define PROC_MEM_NB_MN_FILECODE (0XF27C) -#define PROC_MEM_NB_MNDCT_FILECODE (0XF27D) -#define PROC_MEM_NB_MNPHY_FILECODE (0XF27E) -#define PROC_MEM_NB_MNMCT_FILECODE (0XF27F) -#define PROC_MEM_NB_MNS3_FILECODE (0XF280) -#define PROC_MEM_NB_MNFLOW_FILECODE (0XF281) -#define PROC_MEM_NB_MNFEAT_FILECODE (0XF282) -#define PROC_MEM_NB_MNTRAIN2_FILECODE (0XF283) -#define PROC_MEM_NB_MNTRAIN3_FILECODE (0XF284) -#define PROC_MEM_NB_MNREG_FILECODE (0XF285) -#define PROC_MEM_NB_NI_MNNI_FILECODE (0XF286) -#define PROC_MEM_NB_NI_MNS3NI_FILECODE (0XF287) -#define PROC_MEM_NB_NI_MNFLOWNI_FILECODE (0XF288) -#define PROC_MEM_NB_PH_MNFLOWPH_FILECODE (0XF289) -#define PROC_MEM_NB_PH_MNPH_FILECODE (0XF28A) -#define PROC_MEM_NB_PH_MNS3PH_FILECODE (0XF28B) -#define PROC_MEM_NB_PH_MNIDENDIMMPH_FILECODE (0XF28C) -#define PROC_MEM_NB_OR_MNFLOWOR_FILECODE (0XF290) -#define PROC_MEM_NB_OR_MNOR_FILECODE (0XF291) -#define PROC_MEM_NB_OR_MNIDENDIMMOR_FILECODE (0XF292) -#define PROC_MEM_NB_OR_MNMCTOR_FILECODE (0XF293) -#define PROC_MEM_NB_OR_MNDCTOR_FILECODE (0XF294) -#define PROC_MEM_NB_OR_MNOTOR_FILECODE (0XF295) -#define PROC_MEM_NB_OR_MNPARTRAINOR_FILECODE (0XF296) -#define PROC_MEM_NB_OR_MNPHYOR_FILECODE (0XF297) -#define PROC_MEM_NB_OR_MNPROTOOR_FILECODE (0XF298) -#define PROC_MEM_NB_OR_MNS3OR_FILECODE (0XF299) -#define PROC_MEM_NB_OR_MNREGOR_FILECODE (0XF29A) -#define PROC_MEM_NB_TN_MNREGTN_FILECODE (0XF29B) -#define PROC_MEM_NB_TN_MNTN_FILECODE (0XF29C) -#define PROC_MEM_NB_TN_MNMCTTN_FILECODE (0XF29D) -#define PROC_MEM_NB_TN_MNOTTN_FILECODE (0XF29E) -#define PROC_MEM_NB_TN_MNDCTTN_FILECODE (0XF29F) -#define PROC_MEM_NB_TN_MNPHYTN_FILECODE (0XF2A0) -#define PROC_MEM_NB_TN_MNS3TN_FILECODE (0XF2A1) -#define PROC_MEM_NB_TN_MNIDENDIMMTN_FILECODE (0XF2A2) -#define PROC_MEM_NB_TN_MNFLOWTN_FILECODE (0XF2A3) -#define PROC_MEM_NB_TN_MNPROTOTN_FILECODE (0XF2A4) +#define PROC_MEM_NB_LN_MNDCTLN_FILECODE (0xF252) +#define PROC_MEM_NB_LN_MNFLOWLN_FILECODE (0xF253) +#define PROC_MEM_NB_LN_MNIDENDIMMLN_FILECODE (0xF254) +#define PROC_MEM_NB_LN_MNMCTLN_FILECODE (0xF255) +#define PROC_MEM_NB_LN_MNOTLN_FILECODE (0xF256) +#define PROC_MEM_NB_LN_MNPHYLN_FILECODE (0xF257) +#define PROC_MEM_NB_LN_MNPROTOLN_FILECODE (0xF258) +#define PROC_MEM_NB_LN_MNLN_FILECODE (0xF259) +#define PROC_MEM_NB_LN_MNS3LN_FILECODE (0xF25A) +#define PROC_MEM_NB_LN_MNREGLN_FILECODE (0xF25B) +#define PROC_MEM_NB_DA_MNDA_FILECODE (0xF260) +#define PROC_MEM_NB_DA_MNFLOWDA_FILECODE (0xF261) +#define PROC_MEM_NB_DA_MNIDENDIMMDA_FILECODE (0xF263) +#define PROC_MEM_NB_DA_MNMCTDA_FILECODE (0xF264) +#define PROC_MEM_NB_DA_MNDCTDA_FILECODE (0xF265) +#define PROC_MEM_NB_DA_MNOTDA_FILECODE (0xF266) +#define PROC_MEM_NB_DA_MNPARTRAINDA_FILECODE (0xF267) +#define PROC_MEM_NB_DA_MNPROTODA_FILECODE (0xF269) +#define PROC_MEM_NB_DA_MNS3DA_FILECODE (0xF26A) +#define PROC_MEM_NB_DA_MNREGDA_FILECODE (0xF26B) +#define PROC_MEM_NB_C32_MNC32_FILECODE (0xF26C) +#define PROC_MEM_NB_C32_MNDCTC32_FILECODE (0xF26D) +#define PROC_MEM_NB_C32_MNFLOWC32_FILECODE (0xF26E) +#define PROC_MEM_NB_C32_MNIDENDIMMC32_FILECODE (0xF26F) +#define PROC_MEM_NB_C32_MNMCTC32_FILECODE (0xF270) +#define PROC_MEM_NB_C32_MNOTC32_FILECODE (0xF271) +#define PROC_MEM_NB_C32_MNPARTRAINC32_FILECODE (0xF272) +#define PROC_MEM_NB_C32_MNPHYC32_FILECODE (0xF273) +#define PROC_MEM_NB_C32_MNPROTOC32_FILECODE (0xF274) +#define PROC_MEM_NB_C32_MNS3C32_FILECODE (0xF275) +#define PROC_MEM_NB_C32_MNREGC32_FILECODE (0xF277) +#define PROC_MEM_NB_MN_FILECODE (0xF27C) +#define PROC_MEM_NB_MNDCT_FILECODE (0xF27D) +#define PROC_MEM_NB_MNPHY_FILECODE (0xF27E) +#define PROC_MEM_NB_MNMCT_FILECODE (0xF27F) +#define PROC_MEM_NB_MNS3_FILECODE (0xF280) +#define PROC_MEM_NB_MNFLOW_FILECODE (0xF281) +#define PROC_MEM_NB_MNFEAT_FILECODE (0xF282) +#define PROC_MEM_NB_MNTRAIN2_FILECODE (0xF283) +#define PROC_MEM_NB_MNTRAIN3_FILECODE (0xF284) +#define PROC_MEM_NB_MNREG_FILECODE (0xF285) +#define PROC_MEM_NB_NI_MNNI_FILECODE (0xF286) +#define PROC_MEM_NB_NI_MNS3NI_FILECODE (0xF287) +#define PROC_MEM_NB_NI_MNFLOWNI_FILECODE (0xF288) +#define PROC_MEM_NB_PH_MNFLOWPH_FILECODE (0xF289) +#define PROC_MEM_NB_PH_MNPH_FILECODE (0xF28A) +#define PROC_MEM_NB_PH_MNS3PH_FILECODE (0xF28B) +#define PROC_MEM_NB_PH_MNIDENDIMMPH_FILECODE (0xF28C) +#define PROC_MEM_NB_OR_MNFLOWOR_FILECODE (0xF290) +#define PROC_MEM_NB_OR_MNOR_FILECODE (0xF291) +#define PROC_MEM_NB_OR_MNIDENDIMMOR_FILECODE (0xF292) +#define PROC_MEM_NB_OR_MNMCTOR_FILECODE (0xF293) +#define PROC_MEM_NB_OR_MNDCTOR_FILECODE (0xF294) +#define PROC_MEM_NB_OR_MNOTOR_FILECODE (0xF295) +#define PROC_MEM_NB_OR_MNPARTRAINOR_FILECODE (0xF296) +#define PROC_MEM_NB_OR_MNPHYOR_FILECODE (0xF297) +#define PROC_MEM_NB_OR_MNPROTOOR_FILECODE (0xF298) +#define PROC_MEM_NB_OR_MNS3OR_FILECODE (0xF299) +#define PROC_MEM_NB_OR_MNREGOR_FILECODE (0xF29A) +#define PROC_MEM_NB_TN_MNREGTN_FILECODE (0xF29B) +#define PROC_MEM_NB_TN_MNTN_FILECODE (0xF29C) +#define PROC_MEM_NB_TN_MNMCTTN_FILECODE (0xF29D) +#define PROC_MEM_NB_TN_MNOTTN_FILECODE (0xF29E) +#define PROC_MEM_NB_TN_MNDCTTN_FILECODE (0xF29F) +#define PROC_MEM_NB_TN_MNPHYTN_FILECODE (0xF2A0) +#define PROC_MEM_NB_TN_MNS3TN_FILECODE (0xF2A1) +#define PROC_MEM_NB_TN_MNIDENDIMMTN_FILECODE (0xF2A2) +#define PROC_MEM_NB_TN_MNFLOWTN_FILECODE (0xF2A3) +#define PROC_MEM_NB_TN_MNPROTOTN_FILECODE (0xF2A4) -#define PROC_MEM_PS_MP_FILECODE (0XF401) -#define PROC_MEM_PS_DR_MPRDR3_FILECODE (0XF402) -#define PROC_MEM_PS_HY_MPRHY3_FILECODE (0XF403) -#define PROC_MEM_PS_LN_MPRLN3_FILECODE (0XF404) -#define PROC_MEM_PS_DR_MPSDR3_FILECODE (0XF405) -#define PROC_MEM_PS_HY_MPSHY3_FILECODE (0XF406) -#define PROC_MEM_PS_LN_MPSLN3_FILECODE (0XF407) -#define PROC_MEM_PS_DR_MPUDR3_FILECODE (0XF408) -#define PROC_MEM_PS_HY_MPUHY3_FILECODE (0XF409) -#define PROC_MEM_PS_LN_MPULN3_FILECODE (0XF40A) -#define PROC_MEM_PS_DA_MPUDA3_FILECODE (0XF40B) -#define PROC_MEM_PS_DA_MPSDA2_FILECODE (0XF40C) -#define PROC_MEM_PS_DA_MPSDA3_FILECODE (0XF40D) -#define PROC_MEM_PS_DR_MPRDR2_FILECODE (0XF40E) -#define PROC_MEM_PS_DR_MPUDR2_FILECODE (0XF40F) -#define PROC_MEM_PS_C32_MPRC32_3_FILECODE (0XF410) -#define PROC_MEM_PS_C32_MPUC32_3_FILECODE (0XF411) -#define PROC_MEM_PS_NI_MPSNI3_FILECODE (0XF412) -#define PROC_MEM_PS_NI_MPUNI3_FILECODE (0XF413) -#define PROC_MEM_PS_ON_MPSON3_FILECODE (0XF414) -#define PROC_MEM_PS_ON_MPUON3_FILECODE (0XF415) -#define PROC_MEM_PS_PH_MPSPH3_FILECODE (0XF416) -#define PROC_MEM_PS_PH_MPUPH3_FILECODE (0XF417) -#define PROC_MEM_PS_RB_MPSRB3_FILECODE (0XF418) -#define PROC_MEM_PS_RB_MPURB3_FILECODE (0XF419) -#define PROC_MEM_PS_OR_AM3_MPUORA3_FILECODE (0XF41A) -#define PROC_MEM_PS_OR_AM3_MPSORA3_FILECODE (0XF41B) -#define PROC_MEM_PS_OR_C32_MPRORC3_FILECODE (0XF41C) -#define PROC_MEM_PS_OR_C32_MPUORC3_FILECODE (0XF41D) -#define PROC_MEM_PS_OR_C32_MPLORC3_FILECODE (0XF41E) -#define PROC_MEM_PS_OR_G34_MPRORG3_FILECODE (0XF41F) -#define PROC_MEM_PS_OR_G34_MPUORG3_FILECODE (0XF420) -#define PROC_MEM_PS_OR_G34_MPLORG3_FILECODE (0XF421) -#define PROC_MEM_PS_MPRTT_FILECODE (0XF422) -#define PROC_MEM_PS_MPMAXFREQ_FILECODE (0XF423) -#define PROC_MEM_PS_MPODTPAT_FILECODE (0XF424) -#define PROC_MEM_PS_MPSAO_FILECODE (0XF425) -#define PROC_MEM_PS_MPMR0_FILECODE (0XF426) -#define PROC_MEM_PS_MPRC2IBT_FILECODE (0XF427) -#define PROC_MEM_PS_MPRC10OPSPD_FILECODE (0XF428) -#define PROC_MEM_PS_MPLRIBT_FILECODE (0XF429) -#define PROC_MEM_PS_MPLRNPR_FILECODE (0XF42A) -#define PROC_MEM_PS_MPLRNLR_FILECODE (0XF42B) -#define PROC_MEM_PS_OR_MPOR3_FILECODE (0XF42C) -#define PROC_MEM_PS_TN_MPSTN3_FILECODE (0XF42D) -#define PROC_MEM_PS_TN_MPTN3_FILECODE (0XF42E) -#define PROC_MEM_PS_TN_MPUTN3_FILECODE (0XF42F) -#define PROC_MEM_PS_TN_FM2_MPUTNFM2_FILECODE (0XF430) -#define PROC_MEM_PS_TN_FP2_MPSTNFP2_FILECODE (0XF431) -#define PROC_MEM_PS_TN_FS1_MPSTNFS1_FILECODE (0XF432) -#define PROC_MEM_PS_MPSEEDS_FILECODE (0XF43F) +#define PROC_MEM_PS_MP_FILECODE (0xF401) +#define PROC_MEM_PS_DR_MPRDR3_FILECODE (0xF402) +#define PROC_MEM_PS_HY_MPRHY3_FILECODE (0xF403) +#define PROC_MEM_PS_LN_MPRLN3_FILECODE (0xF404) +#define PROC_MEM_PS_DR_MPSDR3_FILECODE (0xF405) +#define PROC_MEM_PS_HY_MPSHY3_FILECODE (0xF406) +#define PROC_MEM_PS_LN_MPSLN3_FILECODE (0xF407) +#define PROC_MEM_PS_DR_MPUDR3_FILECODE (0xF408) +#define PROC_MEM_PS_HY_MPUHY3_FILECODE (0xF409) +#define PROC_MEM_PS_LN_MPULN3_FILECODE (0xF40A) +#define PROC_MEM_PS_DA_MPUDA3_FILECODE (0xF40B) +#define PROC_MEM_PS_DA_MPSDA2_FILECODE (0xF40C) +#define PROC_MEM_PS_DA_MPSDA3_FILECODE (0xF40D) +#define PROC_MEM_PS_DR_MPRDR2_FILECODE (0xF40E) +#define PROC_MEM_PS_DR_MPUDR2_FILECODE (0xF40F) +#define PROC_MEM_PS_C32_MPRC32_3_FILECODE (0xF410) +#define PROC_MEM_PS_C32_MPUC32_3_FILECODE (0xF411) +#define PROC_MEM_PS_NI_MPSNI3_FILECODE (0xF412) +#define PROC_MEM_PS_NI_MPUNI3_FILECODE (0xF413) +#define PROC_MEM_PS_ON_MPSON3_FILECODE (0xF414) +#define PROC_MEM_PS_ON_MPUON3_FILECODE (0xF415) +#define PROC_MEM_PS_PH_MPSPH3_FILECODE (0xF416) +#define PROC_MEM_PS_PH_MPUPH3_FILECODE (0xF417) +#define PROC_MEM_PS_RB_MPSRB3_FILECODE (0xF418) +#define PROC_MEM_PS_RB_MPURB3_FILECODE (0xF419) +#define PROC_MEM_PS_OR_AM3_MPUORA3_FILECODE (0xF41A) +#define PROC_MEM_PS_OR_AM3_MPSORA3_FILECODE (0xF41B) +#define PROC_MEM_PS_OR_C32_MPRORC3_FILECODE (0xF41C) +#define PROC_MEM_PS_OR_C32_MPUORC3_FILECODE (0xF41D) +#define PROC_MEM_PS_OR_C32_MPLORC3_FILECODE (0xF41E) +#define PROC_MEM_PS_OR_G34_MPRORG3_FILECODE (0xF41F) +#define PROC_MEM_PS_OR_G34_MPUORG3_FILECODE (0xF420) +#define PROC_MEM_PS_OR_G34_MPLORG3_FILECODE (0xF421) +#define PROC_MEM_PS_MPRTT_FILECODE (0xF422) +#define PROC_MEM_PS_MPMAXFREQ_FILECODE (0xF423) +#define PROC_MEM_PS_MPODTPAT_FILECODE (0xF424) +#define PROC_MEM_PS_MPSAO_FILECODE (0xF425) +#define PROC_MEM_PS_MPMR0_FILECODE (0xF426) +#define PROC_MEM_PS_MPRC2IBT_FILECODE (0xF427) +#define PROC_MEM_PS_MPRC10OPSPD_FILECODE (0xF428) +#define PROC_MEM_PS_MPLRIBT_FILECODE (0xF429) +#define PROC_MEM_PS_MPLRNPR_FILECODE (0xF42A) +#define PROC_MEM_PS_MPLRNLR_FILECODE (0xF42B) +#define PROC_MEM_PS_OR_MPOR3_FILECODE (0xF42C) +#define PROC_MEM_PS_TN_MPSTN3_FILECODE (0xF42D) +#define PROC_MEM_PS_TN_MPTN3_FILECODE (0xF42E) +#define PROC_MEM_PS_TN_MPUTN3_FILECODE (0xF42F) +#define PROC_MEM_PS_TN_FM2_MPUTNFM2_FILECODE (0xF430) +#define PROC_MEM_PS_TN_FP2_MPSTNFP2_FILECODE (0xF431) +#define PROC_MEM_PS_TN_FS1_MPSTNFS1_FILECODE (0xF432) +#define PROC_MEM_PS_MPSEEDS_FILECODE (0xF43F) -#define PROC_MEM_TECH_MT_FILECODE (0XF501) -#define PROC_MEM_TECH_MTHDI_FILECODE (0XF502) -#define PROC_MEM_TECH_MTTDIMBT_FILECODE (0XF504) -#define PROC_MEM_TECH_MTTECC_FILECODE (0XF505) -#define PROC_MEM_TECH_MTTHRC_FILECODE (0XF506) -#define PROC_MEM_TECH_MTTML_FILECODE (0XF507) -#define PROC_MEM_TECH_MTTOPTSRC_FILECODE (0XF509) -#define PROC_MEM_TECH_MTTSRC_FILECODE (0XF50B) -#define PROC_MEM_TECH_MTTEDGEDETECT_FILECODE (0XF50C) -#define PROC_MEM_TECH_DDR2_MT2_FILECODE (0XF541) -#define PROC_MEM_TECH_DDR2_MTOT2_FILECODE (0XF543) -#define PROC_MEM_TECH_DDR2_MTSPD2_FILECODE (0XF544) -#define PROC_MEM_TECH_DDR3_MT3_FILECODE (0XF581) -#define PROC_MEM_TECH_DDR3_MTOT3_FILECODE (0XF583) -#define PROC_MEM_TECH_DDR3_MTRCI3_FILECODE (0XF584) -#define PROC_MEM_TECH_DDR3_MTSDI3_FILECODE (0XF585) -#define PROC_MEM_TECH_DDR3_MTSPD3_FILECODE (0XF586) -#define PROC_MEM_TECH_DDR3_MTTWL3_FILECODE (0XF587) -#define PROC_MEM_TECH_DDR3_MTTECC3_FILECODE (0XF588) -#define PROC_MEM_TECH_DDR3_MTLRDIMM3_FILECODE (0XF589) -#define PROC_MEM_TECH_MTTHRCSEEDTRAIN_FILECODE (0XF58A) +#define PROC_MEM_TECH_MT_FILECODE (0xF501) +#define PROC_MEM_TECH_MTHDI_FILECODE (0xF502) +#define PROC_MEM_TECH_MTTDIMBT_FILECODE (0xF504) +#define PROC_MEM_TECH_MTTECC_FILECODE (0xF505) +#define PROC_MEM_TECH_MTTHRC_FILECODE (0xF506) +#define PROC_MEM_TECH_MTTML_FILECODE (0xF507) +#define PROC_MEM_TECH_MTTOPTSRC_FILECODE (0xF509) +#define PROC_MEM_TECH_MTTSRC_FILECODE (0xF50B) +#define PROC_MEM_TECH_MTTEDGEDETECT_FILECODE (0xF50C) +#define PROC_MEM_TECH_DDR2_MT2_FILECODE (0xF541) +#define PROC_MEM_TECH_DDR2_MTOT2_FILECODE (0xF543) +#define PROC_MEM_TECH_DDR2_MTSPD2_FILECODE (0xF544) +#define PROC_MEM_TECH_DDR3_MT3_FILECODE (0xF581) +#define PROC_MEM_TECH_DDR3_MTOT3_FILECODE (0xF583) +#define PROC_MEM_TECH_DDR3_MTRCI3_FILECODE (0xF584) +#define PROC_MEM_TECH_DDR3_MTSDI3_FILECODE (0xF585) +#define PROC_MEM_TECH_DDR3_MTSPD3_FILECODE (0xF586) +#define PROC_MEM_TECH_DDR3_MTTWL3_FILECODE (0xF587) +#define PROC_MEM_TECH_DDR3_MTTECC3_FILECODE (0xF588) +#define PROC_MEM_TECH_DDR3_MTLRDIMM3_FILECODE (0xF589) +#define PROC_MEM_TECH_MTTHRCSEEDTRAIN_FILECODE (0xF58A) -#define PROC_RECOVERY_MEM_MRDEF_FILECODE (0XF801) -#define PROC_RECOVERY_MEM_MRINIT_FILECODE (0XF802) -#define PROC_RECOVERY_MEM_MRM_FILECODE (0XF803) -#define PROC_RECOVERY_MEM_MRUC_FILECODE (0XF804) -#define PROC_RECOVERY_MEM_NB_DR_MRNDR_FILECODE (0XF812) -#define PROC_RECOVERY_MEM_NB_DR_MRNMCTDR_FILECODE (0XF813) -#define PROC_RECOVERY_MEM_NB_HY_MRNDCTHY_FILECODE (0XF821) -#define PROC_RECOVERY_MEM_NB_HY_MRNHY_FILECODE (0XF822) -#define PROC_RECOVERY_MEM_NB_HY_MRNMCTHY_FILECODE (0XF823) -#define PROC_RECOVERY_MEM_NB_HY_MRNPROTOHY_FILECODE (0XF825) -#define PROC_RECOVERY_MEM_NB_LN_MRNDCTLN_FILECODE (0XF831) -#define PROC_RECOVERY_MEM_NB_LN_MRNMCTLN_FILECODE (0XF832) -#define PROC_RECOVERY_MEM_NB_LN_MRNLN_FILECODE (0XF833) -#define PROC_RECOVERY_MEM_NB_DA_MRNDA_FILECODE (0XF842) -#define PROC_RECOVERY_MEM_NB_DA_MRNMCTDA_FILECODE (0XF843) -#define PROC_RECOVERY_MEM_NB_NI_MRNNI_FILECODE (0XF845) -#define PROC_RECOVERY_MEM_NB_C32_MRNC32_FILECODE (0XF851) -#define PROC_RECOVERY_MEM_NB_C32_MRNMCTC32_FILECODE (0XF852) -#define PROC_RECOVERY_MEM_NB_C32_MRNPROTOC32_FILECODE (0XF853) +#define PROC_RECOVERY_MEM_MRDEF_FILECODE (0xF801) +#define PROC_RECOVERY_MEM_MRINIT_FILECODE (0xF802) +#define PROC_RECOVERY_MEM_MRM_FILECODE (0xF803) +#define PROC_RECOVERY_MEM_MRUC_FILECODE (0xF804) +#define PROC_RECOVERY_MEM_NB_DR_MRNDR_FILECODE (0xF812) +#define PROC_RECOVERY_MEM_NB_DR_MRNMCTDR_FILECODE (0xF813) +#define PROC_RECOVERY_MEM_NB_HY_MRNDCTHY_FILECODE (0xF821) +#define PROC_RECOVERY_MEM_NB_HY_MRNHY_FILECODE (0xF822) +#define PROC_RECOVERY_MEM_NB_HY_MRNMCTHY_FILECODE (0xF823) +#define PROC_RECOVERY_MEM_NB_HY_MRNPROTOHY_FILECODE (0xF825) +#define PROC_RECOVERY_MEM_NB_LN_MRNDCTLN_FILECODE (0xF831) +#define PROC_RECOVERY_MEM_NB_LN_MRNMCTLN_FILECODE (0xF832) +#define PROC_RECOVERY_MEM_NB_LN_MRNLN_FILECODE (0xF833) +#define PROC_RECOVERY_MEM_NB_DA_MRNDA_FILECODE (0xF842) +#define PROC_RECOVERY_MEM_NB_DA_MRNMCTDA_FILECODE (0xF843) +#define PROC_RECOVERY_MEM_NB_NI_MRNNI_FILECODE (0xF845) +#define PROC_RECOVERY_MEM_NB_C32_MRNC32_FILECODE (0xF851) +#define PROC_RECOVERY_MEM_NB_C32_MRNMCTC32_FILECODE (0xF852) +#define PROC_RECOVERY_MEM_NB_C32_MRNPROTOC32_FILECODE (0xF853) #define PROC_RECOVERY_MEM_NB_ON_MRNDCTON_FILECODE (0xF861) #define PROC_RECOVERY_MEM_NB_ON_MRNMCTON_FILECODE (0xF862) #define PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE (0xF863) @@ -1044,43 +1044,43 @@ #define PROC_RECOVERY_MEM_NB_KR_MRNDCTKR_FILECODE (0xF891) #define PROC_RECOVERY_MEM_NB_KR_MRNMCTKR_FILECODE (0xF892) #define PROC_RECOVERY_MEM_NB_KR_MRNKR_FILECODE (0xF893) -#define PROC_RECOVERY_MEM_TECH_MRTTPOS_FILECODE (0XF8C1) -#define PROC_RECOVERY_MEM_TECH_MRTTSRC_FILECODE (0XF8C2) -#define PROC_RECOVERY_MEM_TECH_DDR3_MRT3_FILECODE (0XF8C3) -#define PROC_RECOVERY_MEM_TECH_DDR3_MRTRCI3_FILECODE (0XF8C4) -#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSDI3_FILECODE (0XF8C5) -#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSPD3_FILECODE (0XF8C6) -#define PROC_RECOVERY_MEM_TECH_DDR3_MRTTWL3_FILECODE (0XF8C7) -#define PROC_RECOVERY_MEM_NB_MRN_FILECODE (0XF8C8) -#define PROC_RECOVERY_MEM_NB_MRNDCT_FILECODE (0XF8C9) -#define PROC_RECOVERY_MEM_NB_MRNMCT_FILECODE (0XF8CA) -#define PROC_RECOVERY_MEM_NB_MRNTRAIN3_FILECODE (0XF8CB) -#define PROC_RECOVERY_MEM_TECH_MRTTHRC_FILECODE (0XF8CC) -#define PROC_RECOVERY_MEM_NB_OR_MRNDCTOR_FILECODE (0XF8CD) -#define PROC_RECOVERY_MEM_NB_OR_MRNOR_FILECODE (0XF8CE) -#define PROC_RECOVERY_MEM_NB_OR_MRNMCTOR_FILECODE (0XF8CF) -#define PROC_RECOVERY_MEM_NB_OR_MRNPROTOOR_FILECODE (0XF8D0) -#define PROC_RECOVERY_MEM_PS_MRP_FILECODE (0XF8E0) -#define PROC_RECOVERY_MEM_PS_MRPRTT_FILECODE (0XF8E1) -#define PROC_RECOVERY_MEM_PS_MRPODTPAT_FILECODE (0XF8E2) -#define PROC_RECOVERY_MEM_PS_MRPSAO_FILECODE (0XF8E3) -#define PROC_RECOVERY_MEM_PS_MRPMR0_FILECODE (0XF8E4) -#define PROC_RECOVERY_MEM_PS_MRPRC2IBT_FILECODE (0XF8E5) -#define PROC_RECOVERY_MEM_PS_MRPRC10OPSPD_FILECODE (0XF8E6) -#define PROC_RECOVERY_MEM_PS_MRPLRIBT_FILECODE (0XF8E7) -#define PROC_RECOVERY_MEM_PS_MRPLRNPR_FILECODE (0XF8E8) -#define PROC_RECOVERY_MEM_PS_MRPLRNLR_FILECODE (0XF8E9) -#define PROC_RECOVERY_MEM_NB_TN_MRNDCTTN_FILECODE (0XF8F3) -#define PROC_RECOVERY_MEM_NB_TN_MRNTN_FILECODE (0XF8F4) -#define PROC_RECOVERY_MEM_NB_TN_MRNMCTTN_FILECODE (0XF8F5) -#define PROC_RECOVERY_MEM_NB_TN_MRNPROTOTN_FILECODE (0XF8F6) -#define PROC_RECOVERY_MEM_PS_TN_MRPSTN3_FILECODE (0XF8F7) -#define PROC_RECOVERY_MEM_PS_TN_MRPTN3_FILECODE (0XF8F8) -#define PROC_RECOVERY_MEM_PS_TN_MRPUTN3_FILECODE (0XF8F9) -#define PROC_RECOVERY_MEM_NB_KM_MRNDCTKM_FILECODE (0XF8FA) -#define PROC_RECOVERY_MEM_NB_KM_MRNKM_FILECODE (0XF8FB) -#define PROC_RECOVERY_MEM_NB_KM_MRNMCTKM_FILECODE (0XF8FC) -#define PROC_RECOVERY_MEM_NB_KM_MRNPROTOKM_FILECODE (0XF8FD) -#define PROC_RECOVERY_MEM_TECH_MRTTHRCSEEDTRAIN_FILECODE (0XF8FE) +#define PROC_RECOVERY_MEM_TECH_MRTTPOS_FILECODE (0xF8C1) +#define PROC_RECOVERY_MEM_TECH_MRTTSRC_FILECODE (0xF8C2) +#define PROC_RECOVERY_MEM_TECH_DDR3_MRT3_FILECODE (0xF8C3) +#define PROC_RECOVERY_MEM_TECH_DDR3_MRTRCI3_FILECODE (0xF8C4) +#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSDI3_FILECODE (0xF8C5) +#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSPD3_FILECODE (0xF8C6) +#define PROC_RECOVERY_MEM_TECH_DDR3_MRTTWL3_FILECODE (0xF8C7) +#define PROC_RECOVERY_MEM_NB_MRN_FILECODE (0xF8C8) +#define PROC_RECOVERY_MEM_NB_MRNDCT_FILECODE (0xF8C9) +#define PROC_RECOVERY_MEM_NB_MRNMCT_FILECODE (0xF8CA) +#define PROC_RECOVERY_MEM_NB_MRNTRAIN3_FILECODE (0xF8CB) +#define PROC_RECOVERY_MEM_TECH_MRTTHRC_FILECODE (0xF8CC) +#define PROC_RECOVERY_MEM_NB_OR_MRNDCTOR_FILECODE (0xF8CD) +#define PROC_RECOVERY_MEM_NB_OR_MRNOR_FILECODE (0xF8CE) +#define PROC_RECOVERY_MEM_NB_OR_MRNMCTOR_FILECODE (0xF8CF) +#define PROC_RECOVERY_MEM_NB_OR_MRNPROTOOR_FILECODE (0xF8D0) +#define PROC_RECOVERY_MEM_PS_MRP_FILECODE (0xF8E0) +#define PROC_RECOVERY_MEM_PS_MRPRTT_FILECODE (0xF8E1) +#define PROC_RECOVERY_MEM_PS_MRPODTPAT_FILECODE (0xF8E2) +#define PROC_RECOVERY_MEM_PS_MRPSAO_FILECODE (0xF8E3) +#define PROC_RECOVERY_MEM_PS_MRPMR0_FILECODE (0xF8E4) +#define PROC_RECOVERY_MEM_PS_MRPRC2IBT_FILECODE (0xF8E5) +#define PROC_RECOVERY_MEM_PS_MRPRC10OPSPD_FILECODE (0xF8E6) +#define PROC_RECOVERY_MEM_PS_MRPLRIBT_FILECODE (0xF8E7) +#define PROC_RECOVERY_MEM_PS_MRPLRNPR_FILECODE (0xF8E8) +#define PROC_RECOVERY_MEM_PS_MRPLRNLR_FILECODE (0xF8E9) +#define PROC_RECOVERY_MEM_NB_TN_MRNDCTTN_FILECODE (0xF8F3) +#define PROC_RECOVERY_MEM_NB_TN_MRNTN_FILECODE (0xF8F4) +#define PROC_RECOVERY_MEM_NB_TN_MRNMCTTN_FILECODE (0xF8F5) +#define PROC_RECOVERY_MEM_NB_TN_MRNPROTOTN_FILECODE (0xF8F6) +#define PROC_RECOVERY_MEM_PS_TN_MRPSTN3_FILECODE (0xF8F7) +#define PROC_RECOVERY_MEM_PS_TN_MRPTN3_FILECODE (0xF8F8) +#define PROC_RECOVERY_MEM_PS_TN_MRPUTN3_FILECODE (0xF8F9) +#define PROC_RECOVERY_MEM_NB_KM_MRNDCTKM_FILECODE (0xF8FA) +#define PROC_RECOVERY_MEM_NB_KM_MRNKM_FILECODE (0xF8FB) +#define PROC_RECOVERY_MEM_NB_KM_MRNMCTKM_FILECODE (0xF8FC) +#define PROC_RECOVERY_MEM_NB_KM_MRNPROTOKM_FILECODE (0xF8FD) +#define PROC_RECOVERY_MEM_TECH_MRTTHRCSEEDTRAIN_FILECODE (0xF8FE) #endif // _FILECODE_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Table.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Table.h index c21cb9c..ca44580 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Table.h +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Table.h @@ -490,7 +490,7 @@ } PACKAGE_TYPE_FEATURES; // Initializer Values for Package Type -#define PACKAGE_TYPE_ALL 0XFFFF ///< Package Type apply all packages +#define PACKAGE_TYPE_ALL 0xFFFF ///< Package Type apply all packages // Initializer Values for Ht Host Pci Config Registers #define HT_HOST_FEAT_COHERENT BIT0 diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuRegisters.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuRegisters.h index 48fcb24..ecef9a7 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuRegisters.h +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuRegisters.h @@ -212,7 +212,7 @@ #define MSR_CPUID_NAME_STRING0 0xC0010030ul // First CPUID namestring register #define MSR_CPUID_NAME_STRING1 0xC0010031ul -#define MSR_CPUID_NAME_STRING2 0XC0010032ul +#define MSR_CPUID_NAME_STRING2 0xC0010032ul #define MSR_CPUID_NAME_STRING3 0xC0010033ul #define MSR_CPUID_NAME_STRING4 0xC0010034ul #define MSR_CPUID_NAME_STRING5 0xC0010035ul // Last CPUID namestring register diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiEnvService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiEnvService.c index cd52636..1cfddbe 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiEnvService.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiEnvService.c @@ -154,8 +154,8 @@ // SMBUS Device (Bus 0, Dev 20, Func 0) // {0x00, SMBUS_BUS_DEV_FUN, 0}, - {FCH_CFG_REG10, 0X00, (FCH_VERSION & 0xFF)}, ///Program the version information - {FCH_CFG_REG11, 0X00, (FCH_VERSION >> 8)}, + {FCH_CFG_REG10, 0x00, (FCH_VERSION & 0xFF)}, ///Program the version information + {FCH_CFG_REG11, 0x00, (FCH_VERSION >> 8)}, {0xFF, 0xFF, 0xFF}, }; diff --git a/src/vendorcode/amd/agesa/f15tn/gcccar.inc b/src/vendorcode/amd/agesa/f15tn/gcccar.inc index b13e02a..68eaed8 100644 --- a/src/vendorcode/amd/agesa/f15tn/gcccar.inc +++ b/src/vendorcode/amd/agesa/f15tn/gcccar.inc @@ -157,7 +157,7 @@ CPUID_MODEL = 1 AMD_CPUID_FMF = 0x80000001 /* Family Model Features information */ -AMD_CPUID_L2Cache = 0X80000006 /* L2/L3 cache info */ +AMD_CPUID_L2Cache = 0x80000006 /* L2/L3 cache info */ AMD_CPUID_APIC = 0x80000008 /* Long Mode and APIC info., core count */ APIC_ID_CORE_ID_SIZE = 12 /* ApicIdCoreIdSize bit position */ diff --git a/src/vendorcode/amd/agesa/f16kb/Include/Filecode.h b/src/vendorcode/amd/agesa/f16kb/Include/Filecode.h index dcec443..8f73399 100644 --- a/src/vendorcode/amd/agesa/f16kb/Include/Filecode.h +++ b/src/vendorcode/amd/agesa/f16kb/Include/Filecode.h @@ -515,67 +515,67 @@ #define PROC_MEM_MAIN_MMAGGRESSOR_FILECODE (0xF119) #define PROC_MEM_MAIN_KB_MMFLOWKB_FILECODE (0xF124) -#define PROC_MEM_NB_MN_FILECODE (0XF27C) -#define PROC_MEM_NB_MNDCT_FILECODE (0XF27D) -#define PROC_MEM_NB_MNPHY_FILECODE (0XF27E) -#define PROC_MEM_NB_MNMCT_FILECODE (0XF27F) -#define PROC_MEM_NB_MNS3_FILECODE (0XF280) -#define PROC_MEM_NB_MNFLOW_FILECODE (0XF281) -#define PROC_MEM_NB_MNFEAT_FILECODE (0XF282) -#define PROC_MEM_NB_MNTRAIN3_FILECODE (0XF284) -#define PROC_MEM_NB_MNREG_FILECODE (0XF285) +#define PROC_MEM_NB_MN_FILECODE (0xF27C) +#define PROC_MEM_NB_MNDCT_FILECODE (0xF27D) +#define PROC_MEM_NB_MNPHY_FILECODE (0xF27E) +#define PROC_MEM_NB_MNMCT_FILECODE (0xF27F) +#define PROC_MEM_NB_MNS3_FILECODE (0xF280) +#define PROC_MEM_NB_MNFLOW_FILECODE (0xF281) +#define PROC_MEM_NB_MNFEAT_FILECODE (0xF282) +#define PROC_MEM_NB_MNTRAIN3_FILECODE (0xF284) +#define PROC_MEM_NB_MNREG_FILECODE (0xF285) #define PROC_MEM_NB_MNPMU_FILECODE (0xF2B7) -#define PROC_MEM_NB_KB_MNREGKB_FILECODE (0XF2B8) -#define PROC_MEM_NB_KB_MNKB_FILECODE (0XF2B9) -#define PROC_MEM_NB_KB_MNMCTKB_FILECODE (0XF2BA) -#define PROC_MEM_NB_KB_MNOTKB_FILECODE (0XF2BB) -#define PROC_MEM_NB_KB_MNDCTKB_FILECODE (0XF2BC) -#define PROC_MEM_NB_KB_MNPHYKB_FILECODE (0XF2BD) -#define PROC_MEM_NB_KB_MNS3KB_FILECODE (0XF2BE) -#define PROC_MEM_NB_KB_MNIDENDIMMKB_FILECODE (0XF2BF) -#define PROC_MEM_NB_KB_MNFLOWKB_FILECODE (0XF2C0) -#define PROC_MEM_NB_KB_MNPROTOKB_FILECODE (0XF2C1) +#define PROC_MEM_NB_KB_MNREGKB_FILECODE (0xF2B8) +#define PROC_MEM_NB_KB_MNKB_FILECODE (0xF2B9) +#define PROC_MEM_NB_KB_MNMCTKB_FILECODE (0xF2BA) +#define PROC_MEM_NB_KB_MNOTKB_FILECODE (0xF2BB) +#define PROC_MEM_NB_KB_MNDCTKB_FILECODE (0xF2BC) +#define PROC_MEM_NB_KB_MNPHYKB_FILECODE (0xF2BD) +#define PROC_MEM_NB_KB_MNS3KB_FILECODE (0xF2BE) +#define PROC_MEM_NB_KB_MNIDENDIMMKB_FILECODE (0xF2BF) +#define PROC_MEM_NB_KB_MNFLOWKB_FILECODE (0xF2C0) +#define PROC_MEM_NB_KB_MNPROTOKB_FILECODE (0xF2C1) -#define PROC_MEM_PS_MP_FILECODE (0XF401) -#define PROC_MEM_PS_MPRTT_FILECODE (0XF422) -#define PROC_MEM_PS_MPMAXFREQ_FILECODE (0XF423) -#define PROC_MEM_PS_MPODTPAT_FILECODE (0XF424) -#define PROC_MEM_PS_MPSAO_FILECODE (0XF425) -#define PROC_MEM_PS_MPMR0_FILECODE (0XF426) -#define PROC_MEM_PS_MPRC2IBT_FILECODE (0XF427) -#define PROC_MEM_PS_MPRC10OPSPD_FILECODE (0XF428) -#define PROC_MEM_PS_MPLRIBT_FILECODE (0XF429) -#define PROC_MEM_PS_MPLRNPR_FILECODE (0XF42A) -#define PROC_MEM_PS_MPLRNLR_FILECODE (0XF42B) -#define PROC_MEM_PS_MPS2D_FILECODE (0XF436) -#define PROC_MEM_PS_MPSEEDS_FILECODE (0XF437) -#define PROC_MEM_PS_KB_MPSKB3_FILECODE (0XF438) -#define PROC_MEM_PS_KB_MPKB3_FILECODE (0XF439) -#define PROC_MEM_PS_KB_MPUKB3_FILECODE (0XF43A) -#define PROC_MEM_PS_KB_FT3_MPSKBFT3_FILECODE (0XF43B) -#define PROC_MEM_PS_MPCADCFG_FILECODE (0XF43C) -#define PROC_MEM_PS_MPDATACFG_FILECODE (0XF43D) +#define PROC_MEM_PS_MP_FILECODE (0xF401) +#define PROC_MEM_PS_MPRTT_FILECODE (0xF422) +#define PROC_MEM_PS_MPMAXFREQ_FILECODE (0xF423) +#define PROC_MEM_PS_MPODTPAT_FILECODE (0xF424) +#define PROC_MEM_PS_MPSAO_FILECODE (0xF425) +#define PROC_MEM_PS_MPMR0_FILECODE (0xF426) +#define PROC_MEM_PS_MPRC2IBT_FILECODE (0xF427) +#define PROC_MEM_PS_MPRC10OPSPD_FILECODE (0xF428) +#define PROC_MEM_PS_MPLRIBT_FILECODE (0xF429) +#define PROC_MEM_PS_MPLRNPR_FILECODE (0xF42A) +#define PROC_MEM_PS_MPLRNLR_FILECODE (0xF42B) +#define PROC_MEM_PS_MPS2D_FILECODE (0xF436) +#define PROC_MEM_PS_MPSEEDS_FILECODE (0xF437) +#define PROC_MEM_PS_KB_MPSKB3_FILECODE (0xF438) +#define PROC_MEM_PS_KB_MPKB3_FILECODE (0xF439) +#define PROC_MEM_PS_KB_MPUKB3_FILECODE (0xF43A) +#define PROC_MEM_PS_KB_FT3_MPSKBFT3_FILECODE (0xF43B) +#define PROC_MEM_PS_MPCADCFG_FILECODE (0xF43C) +#define PROC_MEM_PS_MPDATACFG_FILECODE (0xF43D) -#define PROC_MEM_TECH_MT_FILECODE (0XF501) -#define PROC_MEM_TECH_MTHDI_FILECODE (0XF502) -#define PROC_MEM_TECH_MTTDIMBT_FILECODE (0XF504) -#define PROC_MEM_TECH_MTTECC_FILECODE (0XF505) -#define PROC_MEM_TECH_MTTHRC_FILECODE (0XF506) -#define PROC_MEM_TECH_MTTML_FILECODE (0XF507) -#define PROC_MEM_TECH_MTTOPTSRC_FILECODE (0XF509) -#define PROC_MEM_TECH_MTTSRC_FILECODE (0XF50B) -#define PROC_MEM_TECH_MTTEDGEDETECT_FILECODE (0XF50C) -#define PROC_MEM_TECH_DDR3_MT3_FILECODE (0XF581) -#define PROC_MEM_TECH_DDR3_MTOT3_FILECODE (0XF583) -#define PROC_MEM_TECH_DDR3_MTRCI3_FILECODE (0XF584) -#define PROC_MEM_TECH_DDR3_MTSDI3_FILECODE (0XF585) -#define PROC_MEM_TECH_DDR3_MTSPD3_FILECODE (0XF586) -#define PROC_MEM_TECH_DDR3_MTTWL3_FILECODE (0XF587) -#define PROC_MEM_TECH_DDR3_MTTECC3_FILECODE (0XF588) -#define PROC_MEM_TECH_DDR3_MTLRDIMM3_FILECODE (0XF589) -#define PROC_MEM_TECH_MTTHRCSEEDTRAIN_FILECODE (0XF58A) -#define PROC_MEM_TECH_MTRRDDQS2DTRAINING_FILECODE (0XF58B) -#define PROC_MEM_TECH_MTRRDDQS2DEYERIMSEARCH_FILECODE (0XF58C) +#define PROC_MEM_TECH_MT_FILECODE (0xF501) +#define PROC_MEM_TECH_MTHDI_FILECODE (0xF502) +#define PROC_MEM_TECH_MTTDIMBT_FILECODE (0xF504) +#define PROC_MEM_TECH_MTTECC_FILECODE (0xF505) +#define PROC_MEM_TECH_MTTHRC_FILECODE (0xF506) +#define PROC_MEM_TECH_MTTML_FILECODE (0xF507) +#define PROC_MEM_TECH_MTTOPTSRC_FILECODE (0xF509) +#define PROC_MEM_TECH_MTTSRC_FILECODE (0xF50B) +#define PROC_MEM_TECH_MTTEDGEDETECT_FILECODE (0xF50C) +#define PROC_MEM_TECH_DDR3_MT3_FILECODE (0xF581) +#define PROC_MEM_TECH_DDR3_MTOT3_FILECODE (0xF583) +#define PROC_MEM_TECH_DDR3_MTRCI3_FILECODE (0xF584) +#define PROC_MEM_TECH_DDR3_MTSDI3_FILECODE (0xF585) +#define PROC_MEM_TECH_DDR3_MTSPD3_FILECODE (0xF586) +#define PROC_MEM_TECH_DDR3_MTTWL3_FILECODE (0xF587) +#define PROC_MEM_TECH_DDR3_MTTECC3_FILECODE (0xF588) +#define PROC_MEM_TECH_DDR3_MTLRDIMM3_FILECODE (0xF589) +#define PROC_MEM_TECH_MTTHRCSEEDTRAIN_FILECODE (0xF58A) +#define PROC_MEM_TECH_MTRRDDQS2DTRAINING_FILECODE (0xF58B) +#define PROC_MEM_TECH_MTRRDDQS2DEYERIMSEARCH_FILECODE (0xF58C) #endif // _FILECODE_H_ diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Table.h b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Table.h index 1f6341a..85fb9e4 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Table.h +++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Table.h @@ -508,7 +508,7 @@ } PACKAGE_TYPE_FEATURES; // Initializer Values for Package Type -#define PACKAGE_TYPE_ALL 0XFFFF ///< Package Type apply all packages +#define PACKAGE_TYPE_ALL 0xFFFF ///< Package Type apply all packages // Initializer Values for Ht Host Pci Config Registers #define HT_HOST_FEAT_COHERENT BIT0 diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuRegisters.h b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuRegisters.h index e59bb88..b1df184 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuRegisters.h +++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuRegisters.h @@ -290,7 +290,7 @@ #define MSR_CPUID_NAME_STRING0 0xC0010030ul // First CPUID namestring register #define MSR_CPUID_NAME_STRING1 0xC0010031ul -#define MSR_CPUID_NAME_STRING2 0XC0010032ul +#define MSR_CPUID_NAME_STRING2 0xC0010032ul #define MSR_CPUID_NAME_STRING3 0xC0010033ul #define MSR_CPUID_NAME_STRING4 0xC0010034ul #define MSR_CPUID_NAME_STRING5 0xC0010035ul // Last CPUID namestring register diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Fch.h b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Fch.h index c370d4c..67a0f4b 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Fch.h +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Fch.h @@ -1580,12 +1580,12 @@ #define FCH_SMB_POLL2BYTE BIT7 -#define FCH_EC_ENTER_CONFIG 0X5A -#define FCH_EC_EXIT_CONFIG 0XA5 -#define FCH_EC_REG07 0X07 -#define FCH_EC_REG30 0X30 -#define FCH_EC_REG60 0X60 -#define FCH_EC_REG61 0X61 +#define FCH_EC_ENTER_CONFIG 0x5A +#define FCH_EC_EXIT_CONFIG 0xA5 +#define FCH_EC_REG07 0x07 +#define FCH_EC_REG30 0x30 +#define FCH_EC_REG60 0x60 +#define FCH_EC_REG61 0x61 #define FCH_IMC_ROMSIG 0x55aa55aaul diff --git a/src/vendorcode/amd/agesa/f16kb/gcccar.inc b/src/vendorcode/amd/agesa/f16kb/gcccar.inc index c818d97..9c7bf47 100644 --- a/src/vendorcode/amd/agesa/f16kb/gcccar.inc +++ b/src/vendorcode/amd/agesa/f16kb/gcccar.inc @@ -151,7 +151,7 @@ CPUID_MODEL = 1 AMD_CPUID_FMF = 0x80000001 /* Family Model Features information */ -AMD_CPUID_L2Cache = 0X80000006 /* L2/L3 cache info */ +AMD_CPUID_L2Cache = 0x80000006 /* L2/L3 cache info */ AMD_CPUID_APIC = 0x80000008 /* Long Mode and APIC info., core count */ APIC_ID_CORE_ID_SIZE = 12 /* ApicIdCoreIdSize bit position */ diff --git a/src/vendorcode/amd/pi/00630F01/Include/Filecode.h b/src/vendorcode/amd/pi/00630F01/Include/Filecode.h index af31c46..3c46301 100644 --- a/src/vendorcode/amd/pi/00630F01/Include/Filecode.h +++ b/src/vendorcode/amd/pi/00630F01/Include/Filecode.h @@ -648,25 +648,25 @@ #define PROC_MEM_MAIN_TN_MMFLOWTN_FILECODE (0xF11C) #define PROC_MEM_MAIN_KV_MMFLOWD3KV_FILECODE (0xF122) -#define PROC_MEM_NB_MN_FILECODE (0XF27C) -#define PROC_MEM_NB_MNDCT_FILECODE (0XF27D) -#define PROC_MEM_NB_MNPHY_FILECODE (0XF27E) -#define PROC_MEM_NB_MNMCT_FILECODE (0XF27F) -#define PROC_MEM_NB_MNS3_FILECODE (0XF280) -#define PROC_MEM_NB_MNFLOW_FILECODE (0XF281) -#define PROC_MEM_NB_MNFEAT_FILECODE (0XF282) -#define PROC_MEM_NB_MNTRAIN3_FILECODE (0XF284) -#define PROC_MEM_NB_MNREG_FILECODE (0XF285) -#define PROC_MEM_NB_TN_MNREGTN_FILECODE (0XF29B) -#define PROC_MEM_NB_TN_MNTN_FILECODE (0XF29C) -#define PROC_MEM_NB_TN_MNMCTTN_FILECODE (0XF29D) -#define PROC_MEM_NB_TN_MNOTTN_FILECODE (0XF29E) -#define PROC_MEM_NB_TN_MNDCTTN_FILECODE (0XF29F) -#define PROC_MEM_NB_TN_MNPHYTN_FILECODE (0XF2A0) -#define PROC_MEM_NB_TN_MNS3TN_FILECODE (0XF2A1) -#define PROC_MEM_NB_TN_MNIDENDIMMTN_FILECODE (0XF2A2) -#define PROC_MEM_NB_TN_MNFLOWTN_FILECODE (0XF2A3) -#define PROC_MEM_NB_TN_MNPROTOTN_FILECODE (0XF2A4) +#define PROC_MEM_NB_MN_FILECODE (0xF27C) +#define PROC_MEM_NB_MNDCT_FILECODE (0xF27D) +#define PROC_MEM_NB_MNPHY_FILECODE (0xF27E) +#define PROC_MEM_NB_MNMCT_FILECODE (0xF27F) +#define PROC_MEM_NB_MNS3_FILECODE (0xF280) +#define PROC_MEM_NB_MNFLOW_FILECODE (0xF281) +#define PROC_MEM_NB_MNFEAT_FILECODE (0xF282) +#define PROC_MEM_NB_MNTRAIN3_FILECODE (0xF284) +#define PROC_MEM_NB_MNREG_FILECODE (0xF285) +#define PROC_MEM_NB_TN_MNREGTN_FILECODE (0xF29B) +#define PROC_MEM_NB_TN_MNTN_FILECODE (0xF29C) +#define PROC_MEM_NB_TN_MNMCTTN_FILECODE (0xF29D) +#define PROC_MEM_NB_TN_MNOTTN_FILECODE (0xF29E) +#define PROC_MEM_NB_TN_MNDCTTN_FILECODE (0xF29F) +#define PROC_MEM_NB_TN_MNPHYTN_FILECODE (0xF2A0) +#define PROC_MEM_NB_TN_MNS3TN_FILECODE (0xF2A1) +#define PROC_MEM_NB_TN_MNIDENDIMMTN_FILECODE (0xF2A2) +#define PROC_MEM_NB_TN_MNFLOWTN_FILECODE (0xF2A3) +#define PROC_MEM_NB_TN_MNPROTOTN_FILECODE (0xF2A4) #define PROC_MEM_NB_KV_MNKV_FILECODE (0xF2AF) #define PROC_MEM_NB_KV_MNMCTKV_FILECODE (0xF2B0) #define PROC_MEM_NB_KV_MNDCTKV_FILECODE (0xF2B1) @@ -676,91 +676,91 @@ #define PROC_MEM_NB_KV_MNPROTOKV_FILECODE (0xF2B5) #define PROC_MEM_NB_KV_MNREGKV_FILECODE (0xF2B6) #define PROC_MEM_NB_MNPMU_FILECODE (0xF2B7) -#define PROC_MEM_NB_KV_MNPMUKV_FILECODE (0XF2C2) -#define PROC_MEM_NB_KV_MNPMUSRAMMSGBLOCKKV_FILECODE (0XF2D7) +#define PROC_MEM_NB_KV_MNPMUKV_FILECODE (0xF2C2) +#define PROC_MEM_NB_KV_MNPMUSRAMMSGBLOCKKV_FILECODE (0xF2D7) -#define PROC_MEM_PS_MP_FILECODE (0XF401) -#define PROC_MEM_PS_MPRTT_FILECODE (0XF422) -#define PROC_MEM_PS_MPMAXFREQ_FILECODE (0XF423) -#define PROC_MEM_PS_MPODTPAT_FILECODE (0XF424) -#define PROC_MEM_PS_MPSAO_FILECODE (0XF425) -#define PROC_MEM_PS_MPMR0_FILECODE (0XF426) -#define PROC_MEM_PS_MPRC2IBT_FILECODE (0XF427) -#define PROC_MEM_PS_MPRC10OPSPD_FILECODE (0XF428) -#define PROC_MEM_PS_MPLRIBT_FILECODE (0XF429) -#define PROC_MEM_PS_MPLRNPR_FILECODE (0XF42A) -#define PROC_MEM_PS_MPLRNLR_FILECODE (0XF42B) -#define PROC_MEM_PS_TN_MPSTN3_FILECODE (0XF42D) -#define PROC_MEM_PS_TN_MPTN3_FILECODE (0XF42E) -#define PROC_MEM_PS_TN_MPUTN3_FILECODE (0XF42F) -#define PROC_MEM_PS_TN_FM2_MPUTNFM2_FILECODE (0XF430) -#define PROC_MEM_PS_TN_FP2_MPSTNFP2_FILECODE (0XF431) -#define PROC_MEM_PS_TN_FS1_MPSTNFS1_FILECODE (0XF432) -#define PROC_MEM_PS_MPS2D_FILECODE (0XF436) -#define PROC_MEM_PS_MPSEEDS_FILECODE (0XF437) -#define PROC_MEM_PS_MPCADCFG_FILECODE (0XF43C) -#define PROC_MEM_PS_MPDATACFG_FILECODE (0XF43D) -#define PROC_MEM_PS_KV_MPKV3_FILECODE (0XF43E) -#define PROC_MEM_PS_KV_MPSKV3_FILECODE (0XF43F) -#define PROC_MEM_PS_KV_MPUKV3_FILECODE (0XF440) +#define PROC_MEM_PS_MP_FILECODE (0xF401) +#define PROC_MEM_PS_MPRTT_FILECODE (0xF422) +#define PROC_MEM_PS_MPMAXFREQ_FILECODE (0xF423) +#define PROC_MEM_PS_MPODTPAT_FILECODE (0xF424) +#define PROC_MEM_PS_MPSAO_FILECODE (0xF425) +#define PROC_MEM_PS_MPMR0_FILECODE (0xF426) +#define PROC_MEM_PS_MPRC2IBT_FILECODE (0xF427) +#define PROC_MEM_PS_MPRC10OPSPD_FILECODE (0xF428) +#define PROC_MEM_PS_MPLRIBT_FILECODE (0xF429) +#define PROC_MEM_PS_MPLRNPR_FILECODE (0xF42A) +#define PROC_MEM_PS_MPLRNLR_FILECODE (0xF42B) +#define PROC_MEM_PS_TN_MPSTN3_FILECODE (0xF42D) +#define PROC_MEM_PS_TN_MPTN3_FILECODE (0xF42E) +#define PROC_MEM_PS_TN_MPUTN3_FILECODE (0xF42F) +#define PROC_MEM_PS_TN_FM2_MPUTNFM2_FILECODE (0xF430) +#define PROC_MEM_PS_TN_FP2_MPSTNFP2_FILECODE (0xF431) +#define PROC_MEM_PS_TN_FS1_MPSTNFS1_FILECODE (0xF432) +#define PROC_MEM_PS_MPS2D_FILECODE (0xF436) +#define PROC_MEM_PS_MPSEEDS_FILECODE (0xF437) +#define PROC_MEM_PS_MPCADCFG_FILECODE (0xF43C) +#define PROC_MEM_PS_MPDATACFG_FILECODE (0xF43D) +#define PROC_MEM_PS_KV_MPKV3_FILECODE (0xF43E) +#define PROC_MEM_PS_KV_MPSKV3_FILECODE (0xF43F) +#define PROC_MEM_PS_KV_MPUKV3_FILECODE (0xF440) -#define PROC_MEM_TECH_MT_FILECODE (0XF501) -#define PROC_MEM_TECH_MTHDI_FILECODE (0XF502) -#define PROC_MEM_TECH_MTTDIMBT_FILECODE (0XF504) -#define PROC_MEM_TECH_MTTECC_FILECODE (0XF505) -#define PROC_MEM_TECH_MTTHRC_FILECODE (0XF506) -#define PROC_MEM_TECH_MTTML_FILECODE (0XF507) -#define PROC_MEM_TECH_MTTOPTSRC_FILECODE (0XF509) -#define PROC_MEM_TECH_MTTSRC_FILECODE (0XF50B) -#define PROC_MEM_TECH_MTTEDGEDETECT_FILECODE (0XF50C) -#define PROC_MEM_TECH_DDR3_MT3_FILECODE (0XF581) -#define PROC_MEM_TECH_DDR3_MTOT3_FILECODE (0XF583) -#define PROC_MEM_TECH_DDR3_MTRCI3_FILECODE (0XF584) -#define PROC_MEM_TECH_DDR3_MTSDI3_FILECODE (0XF585) -#define PROC_MEM_TECH_DDR3_MTSPD3_FILECODE (0XF586) -#define PROC_MEM_TECH_DDR3_MTTWL3_FILECODE (0XF587) -#define PROC_MEM_TECH_DDR3_MTTECC3_FILECODE (0XF588) -#define PROC_MEM_TECH_DDR3_MTLRDIMM3_FILECODE (0XF589) -#define PROC_MEM_TECH_MTTHRCSEEDTRAIN_FILECODE (0XF58A) -#define PROC_MEM_TECH_MTTRDDQS2DTRAINING_FILECODE (0XF58B) -#define PROC_MEM_TECH_MTTRDDQS2DEYERIMSEARCH_FILECODE (0XF58C) -#define PROC_MEM_TECH_GDDR5_MNSPDG5_FILECODE (0XF58E) +#define PROC_MEM_TECH_MT_FILECODE (0xF501) +#define PROC_MEM_TECH_MTHDI_FILECODE (0xF502) +#define PROC_MEM_TECH_MTTDIMBT_FILECODE (0xF504) +#define PROC_MEM_TECH_MTTECC_FILECODE (0xF505) +#define PROC_MEM_TECH_MTTHRC_FILECODE (0xF506) +#define PROC_MEM_TECH_MTTML_FILECODE (0xF507) +#define PROC_MEM_TECH_MTTOPTSRC_FILECODE (0xF509) +#define PROC_MEM_TECH_MTTSRC_FILECODE (0xF50B) +#define PROC_MEM_TECH_MTTEDGEDETECT_FILECODE (0xF50C) +#define PROC_MEM_TECH_DDR3_MT3_FILECODE (0xF581) +#define PROC_MEM_TECH_DDR3_MTOT3_FILECODE (0xF583) +#define PROC_MEM_TECH_DDR3_MTRCI3_FILECODE (0xF584) +#define PROC_MEM_TECH_DDR3_MTSDI3_FILECODE (0xF585) +#define PROC_MEM_TECH_DDR3_MTSPD3_FILECODE (0xF586) +#define PROC_MEM_TECH_DDR3_MTTWL3_FILECODE (0xF587) +#define PROC_MEM_TECH_DDR3_MTTECC3_FILECODE (0xF588) +#define PROC_MEM_TECH_DDR3_MTLRDIMM3_FILECODE (0xF589) +#define PROC_MEM_TECH_MTTHRCSEEDTRAIN_FILECODE (0xF58A) +#define PROC_MEM_TECH_MTTRDDQS2DTRAINING_FILECODE (0xF58B) +#define PROC_MEM_TECH_MTTRDDQS2DEYERIMSEARCH_FILECODE (0xF58C) +#define PROC_MEM_TECH_GDDR5_MNSPDG5_FILECODE (0xF58E) #define PROC_MEM_TECH_GDDR5_MNDCTG5_FILECODE (0xF58F) -#define PROC_RECOVERY_MEM_MRDEF_FILECODE (0XF801) -#define PROC_RECOVERY_MEM_MRINIT_FILECODE (0XF802) -#define PROC_RECOVERY_MEM_MRM_FILECODE (0XF803) -#define PROC_RECOVERY_MEM_MRUC_FILECODE (0XF804) -#define PROC_RECOVERY_MEM_TECH_MRTTPOS_FILECODE (0XF8C1) -#define PROC_RECOVERY_MEM_TECH_MRTTSRC_FILECODE (0XF8C2) -#define PROC_RECOVERY_MEM_TECH_DDR3_MRT3_FILECODE (0XF8C3) -#define PROC_RECOVERY_MEM_TECH_DDR3_MRTRCI3_FILECODE (0XF8C4) -#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSDI3_FILECODE (0XF8C5) -#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSPD3_FILECODE (0XF8C6) -#define PROC_RECOVERY_MEM_TECH_DDR3_MRTTWL3_FILECODE (0XF8C7) -#define PROC_RECOVERY_MEM_NB_MRN_FILECODE (0XF8C8) -#define PROC_RECOVERY_MEM_NB_MRNDCT_FILECODE (0XF8C9) -#define PROC_RECOVERY_MEM_NB_MRNMCT_FILECODE (0XF8CA) -#define PROC_RECOVERY_MEM_NB_MRNTRAIN3_FILECODE (0XF8CB) -#define PROC_RECOVERY_MEM_TECH_MRTTHRC_FILECODE (0XF8CC) -#define PROC_RECOVERY_MEM_PS_MRP_FILECODE (0XF8E0) -#define PROC_RECOVERY_MEM_PS_MRPRTT_FILECODE (0XF8E1) -#define PROC_RECOVERY_MEM_PS_MRPODTPAT_FILECODE (0XF8E2) -#define PROC_RECOVERY_MEM_PS_MRPSAO_FILECODE (0XF8E3) -#define PROC_RECOVERY_MEM_PS_MRPMR0_FILECODE (0XF8E4) -#define PROC_RECOVERY_MEM_PS_MRPRC2IBT_FILECODE (0XF8E5) -#define PROC_RECOVERY_MEM_PS_MRPRC10OPSPD_FILECODE (0XF8E6) -#define PROC_RECOVERY_MEM_PS_MRPLRIBT_FILECODE (0XF8E7) -#define PROC_RECOVERY_MEM_PS_MRPLRNPR_FILECODE (0XF8E8) -#define PROC_RECOVERY_MEM_PS_MRPLRNLR_FILECODE (0XF8E9) -#define PROC_RECOVERY_MEM_NB_TN_MRNDCTTN_FILECODE (0XF8F3) -#define PROC_RECOVERY_MEM_NB_TN_MRNTN_FILECODE (0XF8F4) -#define PROC_RECOVERY_MEM_NB_TN_MRNMCTTN_FILECODE (0XF8F5) -#define PROC_RECOVERY_MEM_NB_TN_MRNPROTOTN_FILECODE (0XF8F6) -#define PROC_RECOVERY_MEM_PS_TN_MRPSTN3_FILECODE (0XF8F7) -#define PROC_RECOVERY_MEM_PS_TN_MRPTN3_FILECODE (0XF8F8) -#define PROC_RECOVERY_MEM_PS_TN_MRPUTN3_FILECODE (0XF8F9) -#define PROC_RECOVERY_MEM_TECH_MRTTHRCSEEDTRAIN_FILECODE (0XF8FA) +#define PROC_RECOVERY_MEM_MRDEF_FILECODE (0xF801) +#define PROC_RECOVERY_MEM_MRINIT_FILECODE (0xF802) +#define PROC_RECOVERY_MEM_MRM_FILECODE (0xF803) +#define PROC_RECOVERY_MEM_MRUC_FILECODE (0xF804) +#define PROC_RECOVERY_MEM_TECH_MRTTPOS_FILECODE (0xF8C1) +#define PROC_RECOVERY_MEM_TECH_MRTTSRC_FILECODE (0xF8C2) +#define PROC_RECOVERY_MEM_TECH_DDR3_MRT3_FILECODE (0xF8C3) +#define PROC_RECOVERY_MEM_TECH_DDR3_MRTRCI3_FILECODE (0xF8C4) +#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSDI3_FILECODE (0xF8C5) +#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSPD3_FILECODE (0xF8C6) +#define PROC_RECOVERY_MEM_TECH_DDR3_MRTTWL3_FILECODE (0xF8C7) +#define PROC_RECOVERY_MEM_NB_MRN_FILECODE (0xF8C8) +#define PROC_RECOVERY_MEM_NB_MRNDCT_FILECODE (0xF8C9) +#define PROC_RECOVERY_MEM_NB_MRNMCT_FILECODE (0xF8CA) +#define PROC_RECOVERY_MEM_NB_MRNTRAIN3_FILECODE (0xF8CB) +#define PROC_RECOVERY_MEM_TECH_MRTTHRC_FILECODE (0xF8CC) +#define PROC_RECOVERY_MEM_PS_MRP_FILECODE (0xF8E0) +#define PROC_RECOVERY_MEM_PS_MRPRTT_FILECODE (0xF8E1) +#define PROC_RECOVERY_MEM_PS_MRPODTPAT_FILECODE (0xF8E2) +#define PROC_RECOVERY_MEM_PS_MRPSAO_FILECODE (0xF8E3) +#define PROC_RECOVERY_MEM_PS_MRPMR0_FILECODE (0xF8E4) +#define PROC_RECOVERY_MEM_PS_MRPRC2IBT_FILECODE (0xF8E5) +#define PROC_RECOVERY_MEM_PS_MRPRC10OPSPD_FILECODE (0xF8E6) +#define PROC_RECOVERY_MEM_PS_MRPLRIBT_FILECODE (0xF8E7) +#define PROC_RECOVERY_MEM_PS_MRPLRNPR_FILECODE (0xF8E8) +#define PROC_RECOVERY_MEM_PS_MRPLRNLR_FILECODE (0xF8E9) +#define PROC_RECOVERY_MEM_NB_TN_MRNDCTTN_FILECODE (0xF8F3) +#define PROC_RECOVERY_MEM_NB_TN_MRNTN_FILECODE (0xF8F4) +#define PROC_RECOVERY_MEM_NB_TN_MRNMCTTN_FILECODE (0xF8F5) +#define PROC_RECOVERY_MEM_NB_TN_MRNPROTOTN_FILECODE (0xF8F6) +#define PROC_RECOVERY_MEM_PS_TN_MRPSTN3_FILECODE (0xF8F7) +#define PROC_RECOVERY_MEM_PS_TN_MRPTN3_FILECODE (0xF8F8) +#define PROC_RECOVERY_MEM_PS_TN_MRPUTN3_FILECODE (0xF8F9) +#define PROC_RECOVERY_MEM_TECH_MRTTHRCSEEDTRAIN_FILECODE (0xF8FA) //Psp #define UEFI_PSP_DRIVERS_ITPMDXE_ITPMDXE_FILECODE (0xFA00) diff --git a/src/vendorcode/amd/pi/00630F01/Proc/CPU/cpuRegisters.h b/src/vendorcode/amd/pi/00630F01/Proc/CPU/cpuRegisters.h index e41226a..4c8a0a2 100644 --- a/src/vendorcode/amd/pi/00630F01/Proc/CPU/cpuRegisters.h +++ b/src/vendorcode/amd/pi/00630F01/Proc/CPU/cpuRegisters.h @@ -307,7 +307,7 @@ #define MSR_CPUID_NAME_STRING0 0xC0010030ul // First CPUID namestring register #define MSR_CPUID_NAME_STRING1 0xC0010031ul -#define MSR_CPUID_NAME_STRING2 0XC0010032ul +#define MSR_CPUID_NAME_STRING2 0xC0010032ul #define MSR_CPUID_NAME_STRING3 0xC0010033ul #define MSR_CPUID_NAME_STRING4 0xC0010034ul #define MSR_CPUID_NAME_STRING5 0xC0010035ul // Last CPUID namestring register diff --git a/src/vendorcode/amd/pi/00630F01/Proc/Fch/Fch.h b/src/vendorcode/amd/pi/00630F01/Proc/Fch/Fch.h index 6685c67..b64fb57 100644 --- a/src/vendorcode/amd/pi/00630F01/Proc/Fch/Fch.h +++ b/src/vendorcode/amd/pi/00630F01/Proc/Fch/Fch.h @@ -2234,12 +2234,12 @@ #define SBTSI_REG10 0x10 #define SBTSI_READORDER BIT5 -#define FCH_EC_ENTER_CONFIG 0X5A -#define FCH_EC_EXIT_CONFIG 0XA5 -#define FCH_EC_REG07 0X07 -#define FCH_EC_REG30 0X30 -#define FCH_EC_REG60 0X60 -#define FCH_EC_REG61 0X61 +#define FCH_EC_ENTER_CONFIG 0x5A +#define FCH_EC_EXIT_CONFIG 0xA5 +#define FCH_EC_REG07 0x07 +#define FCH_EC_REG30 0x30 +#define FCH_EC_REG60 0x60 +#define FCH_EC_REG61 0x61 #define FCH_IMC_ROMSIG 0x55aa55aaul diff --git a/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc index cecf5ca..887bf9a 100644 --- a/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc +++ b/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc @@ -152,7 +152,7 @@ CPUID_MODEL = 1 AMD_CPUID_FMF = 0x80000001 /* Family Model Features information */ -AMD_CPUID_L2Cache = 0X80000006 /* L2/L3 cache info */ +AMD_CPUID_L2Cache = 0x80000006 /* L2/L3 cache info */ AMD_CPUID_APIC = 0x80000008 /* Long Mode and APIC info., core count */ APIC_ID_CORE_ID_SIZE = 12 /* ApicIdCoreIdSize bit position */ diff --git a/src/vendorcode/amd/pi/00660F01/Include/Filecode.h b/src/vendorcode/amd/pi/00660F01/Include/Filecode.h index 0e01812..e17ac02 100644 --- a/src/vendorcode/amd/pi/00660F01/Include/Filecode.h +++ b/src/vendorcode/amd/pi/00660F01/Include/Filecode.h @@ -545,15 +545,15 @@ #define PROC_MEM_MAIN_MMAGGRESSOR_FILECODE (0xF119) #define PROC_MEM_MAIN_CZ_MMFLOWD3CZ_FILECODE (0xF127) -#define PROC_MEM_NB_MN_FILECODE (0XF27C) -#define PROC_MEM_NB_MNDCT_FILECODE (0XF27D) -#define PROC_MEM_NB_MNPHY_FILECODE (0XF27E) -#define PROC_MEM_NB_MNMCT_FILECODE (0XF27F) -#define PROC_MEM_NB_MNS3_FILECODE (0XF280) -#define PROC_MEM_NB_MNFLOW_FILECODE (0XF281) -#define PROC_MEM_NB_MNFEAT_FILECODE (0XF282) -#define PROC_MEM_NB_MNTRAIN3_FILECODE (0XF284) -#define PROC_MEM_NB_MNREG_FILECODE (0XF285) +#define PROC_MEM_NB_MN_FILECODE (0xF27C) +#define PROC_MEM_NB_MNDCT_FILECODE (0xF27D) +#define PROC_MEM_NB_MNPHY_FILECODE (0xF27E) +#define PROC_MEM_NB_MNMCT_FILECODE (0xF27F) +#define PROC_MEM_NB_MNS3_FILECODE (0xF280) +#define PROC_MEM_NB_MNFLOW_FILECODE (0xF281) +#define PROC_MEM_NB_MNFEAT_FILECODE (0xF282) +#define PROC_MEM_NB_MNTRAIN3_FILECODE (0xF284) +#define PROC_MEM_NB_MNREG_FILECODE (0xF285) #define PROC_MEM_NB_MNPMU_FILECODE (0xF2B7) #define PROC_MEM_NB_CZ_MNCZ_FILECODE (0xF2D8) #define PROC_MEM_NB_CZ_MNDCTCZ_FILECODE (0xF2D9) @@ -565,82 +565,82 @@ #define PROC_MEM_NB_CZ_MNPROTOCZ_FILECODE (0xF2DF) #define PROC_MEM_NB_CZ_MNREGCZ_FILECODE (0xF2E0) #define PROC_MEM_NB_CZ_MNS3CZ_FILECODE (0xF2E1) -#define PROC_MEM_NB_CZ_MNPSPCZ_FILECODE (0XF2E3) +#define PROC_MEM_NB_CZ_MNPSPCZ_FILECODE (0xF2E3) -#define PROC_MEM_PS_MP_FILECODE (0XF401) -#define PROC_MEM_PS_MPRTT_FILECODE (0XF422) -#define PROC_MEM_PS_MPMAXFREQ_FILECODE (0XF423) -#define PROC_MEM_PS_MPODTPAT_FILECODE (0XF424) -#define PROC_MEM_PS_MPSAO_FILECODE (0XF425) -#define PROC_MEM_PS_MPMR0_FILECODE (0XF426) -#define PROC_MEM_PS_MPRC2IBT_FILECODE (0XF427) -#define PROC_MEM_PS_MPRC10OPSPD_FILECODE (0XF428) -#define PROC_MEM_PS_MPLRIBT_FILECODE (0XF429) -#define PROC_MEM_PS_MPLRNPR_FILECODE (0XF42A) -#define PROC_MEM_PS_MPLRNLR_FILECODE (0XF42B) -#define PROC_MEM_PS_MPS2D_FILECODE (0XF436) -#define PROC_MEM_PS_MPSEEDS_FILECODE (0XF437) -#define PROC_MEM_PS_MPCADCFG_FILECODE (0XF43C) -#define PROC_MEM_PS_MPDATACFG_FILECODE (0XF43D) -#define PROC_MEM_PS_CZ_MPCZ3_FILECODE (0XF445) -#define PROC_MEM_PS_CZ_MPSCZ3_FILECODE (0XF446) -#define PROC_MEM_PS_CZ_MPUCZ3_FILECODE (0XF447) -#define PROC_MEM_PS_CZ_FP4_MPSCZFP4_FILECODE (0XF44A) -#define PROC_MEM_PS_CZ_FP4_MPUCZFP4_FILECODE (0XF44B) +#define PROC_MEM_PS_MP_FILECODE (0xF401) +#define PROC_MEM_PS_MPRTT_FILECODE (0xF422) +#define PROC_MEM_PS_MPMAXFREQ_FILECODE (0xF423) +#define PROC_MEM_PS_MPODTPAT_FILECODE (0xF424) +#define PROC_MEM_PS_MPSAO_FILECODE (0xF425) +#define PROC_MEM_PS_MPMR0_FILECODE (0xF426) +#define PROC_MEM_PS_MPRC2IBT_FILECODE (0xF427) +#define PROC_MEM_PS_MPRC10OPSPD_FILECODE (0xF428) +#define PROC_MEM_PS_MPLRIBT_FILECODE (0xF429) +#define PROC_MEM_PS_MPLRNPR_FILECODE (0xF42A) +#define PROC_MEM_PS_MPLRNLR_FILECODE (0xF42B) +#define PROC_MEM_PS_MPS2D_FILECODE (0xF436) +#define PROC_MEM_PS_MPSEEDS_FILECODE (0xF437) +#define PROC_MEM_PS_MPCADCFG_FILECODE (0xF43C) +#define PROC_MEM_PS_MPDATACFG_FILECODE (0xF43D) +#define PROC_MEM_PS_CZ_MPCZ3_FILECODE (0xF445) +#define PROC_MEM_PS_CZ_MPSCZ3_FILECODE (0xF446) +#define PROC_MEM_PS_CZ_MPUCZ3_FILECODE (0xF447) +#define PROC_MEM_PS_CZ_FP4_MPSCZFP4_FILECODE (0xF44A) +#define PROC_MEM_PS_CZ_FP4_MPUCZFP4_FILECODE (0xF44B) -#define PROC_MEM_TECH_MT_FILECODE (0XF501) -#define PROC_MEM_TECH_MTHDI_FILECODE (0XF502) -#define PROC_MEM_TECH_MTTDIMBT_FILECODE (0XF504) -#define PROC_MEM_TECH_MTTECC_FILECODE (0XF505) -#define PROC_MEM_TECH_MTTHRC_FILECODE (0XF506) -#define PROC_MEM_TECH_MTTML_FILECODE (0XF507) -#define PROC_MEM_TECH_MTTOPTSRC_FILECODE (0XF509) -#define PROC_MEM_TECH_MTTSRC_FILECODE (0XF50B) -#define PROC_MEM_TECH_MTTEDGEDETECT_FILECODE (0XF50C) -#define PROC_MEM_TECH_DDR3_MT3_FILECODE (0XF581) -#define PROC_MEM_TECH_DDR3_MTOT3_FILECODE (0XF583) -#define PROC_MEM_TECH_DDR3_MTRCI3_FILECODE (0XF584) -#define PROC_MEM_TECH_DDR3_MTSDI3_FILECODE (0XF585) -#define PROC_MEM_TECH_DDR3_MTSPD3_FILECODE (0XF586) -#define PROC_MEM_TECH_DDR3_MTTWL3_FILECODE (0XF587) -#define PROC_MEM_TECH_DDR3_MTTECC3_FILECODE (0XF588) -#define PROC_MEM_TECH_DDR3_MTLRDIMM3_FILECODE (0XF589) -#define PROC_MEM_TECH_MTTHRCSEEDTRAIN_FILECODE (0XF58A) -#define PROC_MEM_TECH_MTTRDDQS2DTRAINING_FILECODE (0XF58B) -#define PROC_MEM_TECH_MTTRDDQS2DEYERIMSEARCH_FILECODE (0XF58C) +#define PROC_MEM_TECH_MT_FILECODE (0xF501) +#define PROC_MEM_TECH_MTHDI_FILECODE (0xF502) +#define PROC_MEM_TECH_MTTDIMBT_FILECODE (0xF504) +#define PROC_MEM_TECH_MTTECC_FILECODE (0xF505) +#define PROC_MEM_TECH_MTTHRC_FILECODE (0xF506) +#define PROC_MEM_TECH_MTTML_FILECODE (0xF507) +#define PROC_MEM_TECH_MTTOPTSRC_FILECODE (0xF509) +#define PROC_MEM_TECH_MTTSRC_FILECODE (0xF50B) +#define PROC_MEM_TECH_MTTEDGEDETECT_FILECODE (0xF50C) +#define PROC_MEM_TECH_DDR3_MT3_FILECODE (0xF581) +#define PROC_MEM_TECH_DDR3_MTOT3_FILECODE (0xF583) +#define PROC_MEM_TECH_DDR3_MTRCI3_FILECODE (0xF584) +#define PROC_MEM_TECH_DDR3_MTSDI3_FILECODE (0xF585) +#define PROC_MEM_TECH_DDR3_MTSPD3_FILECODE (0xF586) +#define PROC_MEM_TECH_DDR3_MTTWL3_FILECODE (0xF587) +#define PROC_MEM_TECH_DDR3_MTTECC3_FILECODE (0xF588) +#define PROC_MEM_TECH_DDR3_MTLRDIMM3_FILECODE (0xF589) +#define PROC_MEM_TECH_MTTHRCSEEDTRAIN_FILECODE (0xF58A) +#define PROC_MEM_TECH_MTTRDDQS2DTRAINING_FILECODE (0xF58B) +#define PROC_MEM_TECH_MTTRDDQS2DEYERIMSEARCH_FILECODE (0xF58C) #define PROC_MEM_X86_MEMINITLIBX86_FILECODE (0xF590) #define PROC_MEM_A57_MEMINITLIBA57_FILECODE (0xF591) -#define PROC_RECOVERY_MEM_MRDEF_FILECODE (0XF801) -#define PROC_RECOVERY_MEM_MRINIT_FILECODE (0XF802) -#define PROC_RECOVERY_MEM_MRM_FILECODE (0XF803) -#define PROC_RECOVERY_MEM_MRUC_FILECODE (0XF804) -#define PROC_RECOVERY_MEM_TECH_MRTTPOS_FILECODE (0XF8C1) -#define PROC_RECOVERY_MEM_TECH_MRTTSRC_FILECODE (0XF8C2) -#define PROC_RECOVERY_MEM_TECH_DDR3_MRT3_FILECODE (0XF8C3) -#define PROC_RECOVERY_MEM_TECH_DDR3_MRTRCI3_FILECODE (0XF8C4) -#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSDI3_FILECODE (0XF8C5) -#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSPD3_FILECODE (0XF8C6) -#define PROC_RECOVERY_MEM_TECH_DDR3_MRTTWL3_FILECODE (0XF8C7) -#define PROC_RECOVERY_MEM_NB_MRN_FILECODE (0XF8C8) -#define PROC_RECOVERY_MEM_NB_MRNDCT_FILECODE (0XF8C9) -#define PROC_RECOVERY_MEM_NB_MRNMCT_FILECODE (0XF8CA) -#define PROC_RECOVERY_MEM_NB_MRNTRAIN3_FILECODE (0XF8CB) -#define PROC_RECOVERY_MEM_TECH_MRTTHRC_FILECODE (0XF8CC) -#define PROC_RECOVERY_MEM_PS_MRP_FILECODE (0XF8E0) -#define PROC_RECOVERY_MEM_PS_MRPRTT_FILECODE (0XF8E1) -#define PROC_RECOVERY_MEM_PS_MRPODTPAT_FILECODE (0XF8E2) -#define PROC_RECOVERY_MEM_PS_MRPSAO_FILECODE (0XF8E3) -#define PROC_RECOVERY_MEM_PS_MRPMR0_FILECODE (0XF8E4) -#define PROC_RECOVERY_MEM_PS_MRPRC2IBT_FILECODE (0XF8E5) -#define PROC_RECOVERY_MEM_PS_MRPRC10OPSPD_FILECODE (0XF8E6) -#define PROC_RECOVERY_MEM_PS_MRPLRIBT_FILECODE (0XF8E7) -#define PROC_RECOVERY_MEM_PS_MRPLRNPR_FILECODE (0XF8E8) -#define PROC_RECOVERY_MEM_PS_MRPLRNLR_FILECODE (0XF8E9) -#define PROC_RECOVERY_MEM_TECH_MRTTHRCSEEDTRAIN_FILECODE (0XF8FA) +#define PROC_RECOVERY_MEM_MRDEF_FILECODE (0xF801) +#define PROC_RECOVERY_MEM_MRINIT_FILECODE (0xF802) +#define PROC_RECOVERY_MEM_MRM_FILECODE (0xF803) +#define PROC_RECOVERY_MEM_MRUC_FILECODE (0xF804) +#define PROC_RECOVERY_MEM_TECH_MRTTPOS_FILECODE (0xF8C1) +#define PROC_RECOVERY_MEM_TECH_MRTTSRC_FILECODE (0xF8C2) +#define PROC_RECOVERY_MEM_TECH_DDR3_MRT3_FILECODE (0xF8C3) +#define PROC_RECOVERY_MEM_TECH_DDR3_MRTRCI3_FILECODE (0xF8C4) +#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSDI3_FILECODE (0xF8C5) +#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSPD3_FILECODE (0xF8C6) +#define PROC_RECOVERY_MEM_TECH_DDR3_MRTTWL3_FILECODE (0xF8C7) +#define PROC_RECOVERY_MEM_NB_MRN_FILECODE (0xF8C8) +#define PROC_RECOVERY_MEM_NB_MRNDCT_FILECODE (0xF8C9) +#define PROC_RECOVERY_MEM_NB_MRNMCT_FILECODE (0xF8CA) +#define PROC_RECOVERY_MEM_NB_MRNTRAIN3_FILECODE (0xF8CB) +#define PROC_RECOVERY_MEM_TECH_MRTTHRC_FILECODE (0xF8CC) +#define PROC_RECOVERY_MEM_PS_MRP_FILECODE (0xF8E0) +#define PROC_RECOVERY_MEM_PS_MRPRTT_FILECODE (0xF8E1) +#define PROC_RECOVERY_MEM_PS_MRPODTPAT_FILECODE (0xF8E2) +#define PROC_RECOVERY_MEM_PS_MRPSAO_FILECODE (0xF8E3) +#define PROC_RECOVERY_MEM_PS_MRPMR0_FILECODE (0xF8E4) +#define PROC_RECOVERY_MEM_PS_MRPRC2IBT_FILECODE (0xF8E5) +#define PROC_RECOVERY_MEM_PS_MRPRC10OPSPD_FILECODE (0xF8E6) +#define PROC_RECOVERY_MEM_PS_MRPLRIBT_FILECODE (0xF8E7) +#define PROC_RECOVERY_MEM_PS_MRPLRNPR_FILECODE (0xF8E8) +#define PROC_RECOVERY_MEM_PS_MRPLRNLR_FILECODE (0xF8E9) +#define PROC_RECOVERY_MEM_TECH_MRTTHRCSEEDTRAIN_FILECODE (0xF8FA) //Psp #define PROC_PSP_PSPBASELIB_PSPBASELIB_FILECODE (0xFA20) diff --git a/src/vendorcode/amd/pi/00660F01/Include/Ids.h b/src/vendorcode/amd/pi/00660F01/Include/Ids.h index cb10186..b711345 100644 --- a/src/vendorcode/amd/pi/00660F01/Include/Ids.h +++ b/src/vendorcode/amd/pi/00660F01/Include/Ids.h @@ -1081,7 +1081,7 @@ TpProcCpuEntryPstateGather, ///< 54 .. Entry point PStateGatherData TpProcCpuEntryWhea, ///< 55 .. Entry point CreateAcpiWhea TpProcS3Init, ///< 56 Entry point S3Init - TpProcCpuProcessRegisterTables = 0X58, ///< 58 .. Register table processing + TpProcCpuProcessRegisterTables = 0x58, ///< 58 .. Register table processing TpProcCpuSetBrandID, ///< 59 .. Set brand ID TpProcCpuLocalApicInit, ///< 5A .. Initialize local APIC TpProcCpuLoadUcode, ///< 5B .. Load microcode patch diff --git a/src/vendorcode/amd/pi/00660F01/Proc/CPU/cpuRegisters.h b/src/vendorcode/amd/pi/00660F01/Proc/CPU/cpuRegisters.h index 889be76..c16371f 100644 --- a/src/vendorcode/amd/pi/00660F01/Proc/CPU/cpuRegisters.h +++ b/src/vendorcode/amd/pi/00660F01/Proc/CPU/cpuRegisters.h @@ -332,7 +332,7 @@ #define MSR_CPUID_NAME_STRING0 0xC0010030ul // First CPUID namestring register #define MSR_CPUID_NAME_STRING1 0xC0010031ul -#define MSR_CPUID_NAME_STRING2 0XC0010032ul +#define MSR_CPUID_NAME_STRING2 0xC0010032ul #define MSR_CPUID_NAME_STRING3 0xC0010033ul #define MSR_CPUID_NAME_STRING4 0xC0010034ul #define MSR_CPUID_NAME_STRING5 0xC0010035ul // Last CPUID namestring register diff --git a/src/vendorcode/amd/pi/00660F01/Proc/Fch/Fch.h b/src/vendorcode/amd/pi/00660F01/Proc/Fch/Fch.h index 92201b8..d061b5b 100644 --- a/src/vendorcode/amd/pi/00660F01/Proc/Fch/Fch.h +++ b/src/vendorcode/amd/pi/00660F01/Proc/Fch/Fch.h @@ -2545,12 +2545,12 @@ #define SBTSI_REG10 0x10 #define SBTSI_READORDER BIT5 -#define FCH_EC_ENTER_CONFIG 0X5A -#define FCH_EC_EXIT_CONFIG 0XA5 -#define FCH_EC_REG07 0X07 -#define FCH_EC_REG30 0X30 -#define FCH_EC_REG60 0X60 -#define FCH_EC_REG61 0X61 +#define FCH_EC_ENTER_CONFIG 0x5A +#define FCH_EC_EXIT_CONFIG 0xA5 +#define FCH_EC_REG07 0x07 +#define FCH_EC_REG30 0x30 +#define FCH_EC_REG60 0x60 +#define FCH_EC_REG61 0x61 #define FCH_IMC_ROMSIG 0x55aa55aaul diff --git a/src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc index 88e1a7d..87aeb4f 100644 --- a/src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc +++ b/src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc @@ -161,7 +161,7 @@ CPUID_MODEL = 1 AMD_CPUID_FMF = 0x80000001 /* Family Model Features information */ -AMD_CPUID_L2Cache = 0X80000006 /* L2/L3 cache info */ +AMD_CPUID_L2Cache = 0x80000006 /* L2/L3 cache info */ AMD_CPUID_APIC = 0x80000008 /* Long Mode and APIC info., core count */ APIC_ID_CORE_ID_SIZE = 12 /* ApicIdCoreIdSize bit position */ diff --git a/src/vendorcode/amd/pi/00670F00/Proc/CPU/Table.h b/src/vendorcode/amd/pi/00670F00/Proc/CPU/Table.h index 1d53990..3742c19 100644 --- a/src/vendorcode/amd/pi/00670F00/Proc/CPU/Table.h +++ b/src/vendorcode/amd/pi/00670F00/Proc/CPU/Table.h @@ -317,7 +317,7 @@ } PERFORMANCE_PROFILE_FEATS; // Initializer Values for Package Type -#define PACKAGE_TYPE_ALL 0XFFFF ///< Package Type apply all packages +#define PACKAGE_TYPE_ALL 0xFFFF ///< Package Type apply all packages // Core Range Initializer values. #define COUNT_RANGE_LOW 0ul diff --git a/src/vendorcode/amd/pi/00670F00/Proc/CPU/cpuRegisters.h b/src/vendorcode/amd/pi/00670F00/Proc/CPU/cpuRegisters.h index 46906a8..bafe84f 100644 --- a/src/vendorcode/amd/pi/00670F00/Proc/CPU/cpuRegisters.h +++ b/src/vendorcode/amd/pi/00670F00/Proc/CPU/cpuRegisters.h @@ -334,7 +334,7 @@ #define MSR_CPUID_NAME_STRING0 0xC0010030ul // First CPUID namestring register #define MSR_CPUID_NAME_STRING1 0xC0010031ul -#define MSR_CPUID_NAME_STRING2 0XC0010032ul +#define MSR_CPUID_NAME_STRING2 0xC0010032ul #define MSR_CPUID_NAME_STRING3 0xC0010033ul #define MSR_CPUID_NAME_STRING4 0xC0010034ul #define MSR_CPUID_NAME_STRING5 0xC0010035ul // Last CPUID namestring register diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Fch.h b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Fch.h index ee8c961..653d92c 100644 --- a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Fch.h +++ b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Fch.h @@ -2553,12 +2553,12 @@ #define SBTSI_REG10 0x10 #define SBTSI_READORDER BIT5 -#define FCH_EC_ENTER_CONFIG 0X5A -#define FCH_EC_EXIT_CONFIG 0XA5 -#define FCH_EC_REG07 0X07 -#define FCH_EC_REG30 0X30 -#define FCH_EC_REG60 0X60 -#define FCH_EC_REG61 0X61 +#define FCH_EC_ENTER_CONFIG 0x5A +#define FCH_EC_EXIT_CONFIG 0xA5 +#define FCH_EC_REG07 0x07 +#define FCH_EC_REG30 0x30 +#define FCH_EC_REG60 0x60 +#define FCH_EC_REG61 0x61 #define FCH_IMC_ROMSIG 0x55aa55aaul diff --git a/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc index 4694632..152e279 100644 --- a/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc +++ b/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc @@ -161,7 +161,7 @@ CPUID_MODEL = 1 AMD_CPUID_FMF = 0x80000001 /* Family Model Features information */ -AMD_CPUID_L2Cache = 0X80000006 /* L2/L3 cache info */ +AMD_CPUID_L2Cache = 0x80000006 /* L2/L3 cache info */ AMD_CPUID_APIC = 0x80000008 /* Long Mode and APIC info., core count */ APIC_ID_CORE_ID_SIZE = 12 /* ApicIdCoreIdSize bit position */ diff --git a/src/vendorcode/amd/pi/00730F01/Include/Filecode.h b/src/vendorcode/amd/pi/00730F01/Include/Filecode.h index c2893a7..2e7398d 100644 --- a/src/vendorcode/amd/pi/00730F01/Include/Filecode.h +++ b/src/vendorcode/amd/pi/00730F01/Include/Filecode.h @@ -703,105 +703,105 @@ #define PROC_MEM_MAIN_MMAGGRESSOR_FILECODE (0xF119) #define PROC_MEM_MAIN_ML_MMFLOWML_FILECODE (0xF126) -#define PROC_MEM_NB_MN_FILECODE (0XF27C) -#define PROC_MEM_NB_MNDCT_FILECODE (0XF27D) -#define PROC_MEM_NB_MNPHY_FILECODE (0XF27E) -#define PROC_MEM_NB_MNMCT_FILECODE (0XF27F) -#define PROC_MEM_NB_MNS3_FILECODE (0XF280) -#define PROC_MEM_NB_MNFLOW_FILECODE (0XF281) -#define PROC_MEM_NB_MNFEAT_FILECODE (0XF282) -#define PROC_MEM_NB_MNTRAIN3_FILECODE (0XF284) -#define PROC_MEM_NB_MNREG_FILECODE (0XF285) +#define PROC_MEM_NB_MN_FILECODE (0xF27C) +#define PROC_MEM_NB_MNDCT_FILECODE (0xF27D) +#define PROC_MEM_NB_MNPHY_FILECODE (0xF27E) +#define PROC_MEM_NB_MNMCT_FILECODE (0xF27F) +#define PROC_MEM_NB_MNS3_FILECODE (0xF280) +#define PROC_MEM_NB_MNFLOW_FILECODE (0xF281) +#define PROC_MEM_NB_MNFEAT_FILECODE (0xF282) +#define PROC_MEM_NB_MNTRAIN3_FILECODE (0xF284) +#define PROC_MEM_NB_MNREG_FILECODE (0xF285) #define PROC_MEM_NB_MNPMU_FILECODE (0xF2B7) -#define PROC_MEM_NB_ML_MNREGML_FILECODE (0XF2CD) -#define PROC_MEM_NB_ML_MNML_FILECODE (0XF2CE) -#define PROC_MEM_NB_ML_MNMCTML_FILECODE (0XF2CF) -#define PROC_MEM_NB_ML_MNOTML_FILECODE (0XF2D0) -#define PROC_MEM_NB_ML_MNDCTML_FILECODE (0XF2D1) -#define PROC_MEM_NB_ML_MNPHYML_FILECODE (0XF2D2) -#define PROC_MEM_NB_ML_MNS3ML_FILECODE (0XF2D3) -#define PROC_MEM_NB_ML_MNIDENDIMMML_FILECODE (0XF2D4) -#define PROC_MEM_NB_ML_MNFLOWML_FILECODE (0XF2D5) -#define PROC_MEM_NB_ML_MNPROTOML_FILECODE (0XF2D6) -#define PROC_MEM_NB_ML_MNPSPML_FILECODE (0XF2E2) +#define PROC_MEM_NB_ML_MNREGML_FILECODE (0xF2CD) +#define PROC_MEM_NB_ML_MNML_FILECODE (0xF2CE) +#define PROC_MEM_NB_ML_MNMCTML_FILECODE (0xF2CF) +#define PROC_MEM_NB_ML_MNOTML_FILECODE (0xF2D0) +#define PROC_MEM_NB_ML_MNDCTML_FILECODE (0xF2D1) +#define PROC_MEM_NB_ML_MNPHYML_FILECODE (0xF2D2) +#define PROC_MEM_NB_ML_MNS3ML_FILECODE (0xF2D3) +#define PROC_MEM_NB_ML_MNIDENDIMMML_FILECODE (0xF2D4) +#define PROC_MEM_NB_ML_MNFLOWML_FILECODE (0xF2D5) +#define PROC_MEM_NB_ML_MNPROTOML_FILECODE (0xF2D6) +#define PROC_MEM_NB_ML_MNPSPML_FILECODE (0xF2E2) -#define PROC_MEM_PS_MP_FILECODE (0XF401) -#define PROC_MEM_PS_MPRTT_FILECODE (0XF422) -#define PROC_MEM_PS_MPMAXFREQ_FILECODE (0XF423) -#define PROC_MEM_PS_MPODTPAT_FILECODE (0XF424) -#define PROC_MEM_PS_MPSAO_FILECODE (0XF425) -#define PROC_MEM_PS_MPMR0_FILECODE (0XF426) -#define PROC_MEM_PS_MPRC2IBT_FILECODE (0XF427) -#define PROC_MEM_PS_MPRC10OPSPD_FILECODE (0XF428) -#define PROC_MEM_PS_MPLRIBT_FILECODE (0XF429) -#define PROC_MEM_PS_MPLRNPR_FILECODE (0XF42A) -#define PROC_MEM_PS_MPLRNLR_FILECODE (0XF42B) -#define PROC_MEM_PS_MPS2D_FILECODE (0XF436) -#define PROC_MEM_PS_MPSEEDS_FILECODE (0XF437) -#define PROC_MEM_PS_MPCADCFG_FILECODE (0XF43C) -#define PROC_MEM_PS_MPDATACFG_FILECODE (0XF43D) -#define PROC_MEM_PS_ML_MPSML3_FILECODE (0XF441) -#define PROC_MEM_PS_ML_MPML3_FILECODE (0XF442) -#define PROC_MEM_PS_ML_MPUML3_FILECODE (0XF443) -#define PROC_MEM_PS_ML_FT3_MPSMLFT3_FILECODE (0XF444) +#define PROC_MEM_PS_MP_FILECODE (0xF401) +#define PROC_MEM_PS_MPRTT_FILECODE (0xF422) +#define PROC_MEM_PS_MPMAXFREQ_FILECODE (0xF423) +#define PROC_MEM_PS_MPODTPAT_FILECODE (0xF424) +#define PROC_MEM_PS_MPSAO_FILECODE (0xF425) +#define PROC_MEM_PS_MPMR0_FILECODE (0xF426) +#define PROC_MEM_PS_MPRC2IBT_FILECODE (0xF427) +#define PROC_MEM_PS_MPRC10OPSPD_FILECODE (0xF428) +#define PROC_MEM_PS_MPLRIBT_FILECODE (0xF429) +#define PROC_MEM_PS_MPLRNPR_FILECODE (0xF42A) +#define PROC_MEM_PS_MPLRNLR_FILECODE (0xF42B) +#define PROC_MEM_PS_MPS2D_FILECODE (0xF436) +#define PROC_MEM_PS_MPSEEDS_FILECODE (0xF437) +#define PROC_MEM_PS_MPCADCFG_FILECODE (0xF43C) +#define PROC_MEM_PS_MPDATACFG_FILECODE (0xF43D) +#define PROC_MEM_PS_ML_MPSML3_FILECODE (0xF441) +#define PROC_MEM_PS_ML_MPML3_FILECODE (0xF442) +#define PROC_MEM_PS_ML_MPUML3_FILECODE (0xF443) +#define PROC_MEM_PS_ML_FT3_MPSMLFT3_FILECODE (0xF444) -#define PROC_MEM_TECH_MT_FILECODE (0XF501) -#define PROC_MEM_TECH_MTHDI_FILECODE (0XF502) -#define PROC_MEM_TECH_MTTDIMBT_FILECODE (0XF504) -#define PROC_MEM_TECH_MTTECC_FILECODE (0XF505) -#define PROC_MEM_TECH_MTTHRC_FILECODE (0XF506) -#define PROC_MEM_TECH_MTTML_FILECODE (0XF507) -#define PROC_MEM_TECH_MTTOPTSRC_FILECODE (0XF509) -#define PROC_MEM_TECH_MTTSRC_FILECODE (0XF50B) -#define PROC_MEM_TECH_MTTEDGEDETECT_FILECODE (0XF50C) -#define PROC_MEM_TECH_DDR3_MT3_FILECODE (0XF581) -#define PROC_MEM_TECH_DDR3_MTOT3_FILECODE (0XF583) -#define PROC_MEM_TECH_DDR3_MTRCI3_FILECODE (0XF584) -#define PROC_MEM_TECH_DDR3_MTSDI3_FILECODE (0XF585) -#define PROC_MEM_TECH_DDR3_MTSPD3_FILECODE (0XF586) -#define PROC_MEM_TECH_DDR3_MTTWL3_FILECODE (0XF587) -#define PROC_MEM_TECH_DDR3_MTTECC3_FILECODE (0XF588) -#define PROC_MEM_TECH_DDR3_MTLRDIMM3_FILECODE (0XF589) -#define PROC_MEM_TECH_MTTHRCSEEDTRAIN_FILECODE (0XF58A) -#define PROC_MEM_TECH_MTTRDDQS2DTRAINING_FILECODE (0XF58B) -#define PROC_MEM_TECH_MTTRDDQS2DEYERIMSEARCH_FILECODE (0XF58C) +#define PROC_MEM_TECH_MT_FILECODE (0xF501) +#define PROC_MEM_TECH_MTHDI_FILECODE (0xF502) +#define PROC_MEM_TECH_MTTDIMBT_FILECODE (0xF504) +#define PROC_MEM_TECH_MTTECC_FILECODE (0xF505) +#define PROC_MEM_TECH_MTTHRC_FILECODE (0xF506) +#define PROC_MEM_TECH_MTTML_FILECODE (0xF507) +#define PROC_MEM_TECH_MTTOPTSRC_FILECODE (0xF509) +#define PROC_MEM_TECH_MTTSRC_FILECODE (0xF50B) +#define PROC_MEM_TECH_MTTEDGEDETECT_FILECODE (0xF50C) +#define PROC_MEM_TECH_DDR3_MT3_FILECODE (0xF581) +#define PROC_MEM_TECH_DDR3_MTOT3_FILECODE (0xF583) +#define PROC_MEM_TECH_DDR3_MTRCI3_FILECODE (0xF584) +#define PROC_MEM_TECH_DDR3_MTSDI3_FILECODE (0xF585) +#define PROC_MEM_TECH_DDR3_MTSPD3_FILECODE (0xF586) +#define PROC_MEM_TECH_DDR3_MTTWL3_FILECODE (0xF587) +#define PROC_MEM_TECH_DDR3_MTTECC3_FILECODE (0xF588) +#define PROC_MEM_TECH_DDR3_MTLRDIMM3_FILECODE (0xF589) +#define PROC_MEM_TECH_MTTHRCSEEDTRAIN_FILECODE (0xF58A) +#define PROC_MEM_TECH_MTTRDDQS2DTRAINING_FILECODE (0xF58B) +#define PROC_MEM_TECH_MTTRDDQS2DEYERIMSEARCH_FILECODE (0xF58C) -#define PROC_RECOVERY_MEM_MRDEF_FILECODE (0XF801) -#define PROC_RECOVERY_MEM_MRINIT_FILECODE (0XF802) -#define PROC_RECOVERY_MEM_MRM_FILECODE (0XF803) -#define PROC_RECOVERY_MEM_MRUC_FILECODE (0XF804) -#define PROC_RECOVERY_MEM_TECH_MRTTPOS_FILECODE (0XF8C1) -#define PROC_RECOVERY_MEM_TECH_MRTTSRC_FILECODE (0XF8C2) -#define PROC_RECOVERY_MEM_TECH_DDR3_MRT3_FILECODE (0XF8C3) -#define PROC_RECOVERY_MEM_TECH_DDR3_MRTRCI3_FILECODE (0XF8C4) -#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSDI3_FILECODE (0XF8C5) -#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSPD3_FILECODE (0XF8C6) -#define PROC_RECOVERY_MEM_TECH_DDR3_MRTTWL3_FILECODE (0XF8C7) -#define PROC_RECOVERY_MEM_NB_MRN_FILECODE (0XF8C8) -#define PROC_RECOVERY_MEM_NB_MRNDCT_FILECODE (0XF8C9) -#define PROC_RECOVERY_MEM_NB_MRNMCT_FILECODE (0XF8CA) -#define PROC_RECOVERY_MEM_NB_MRNTRAIN3_FILECODE (0XF8CB) -#define PROC_RECOVERY_MEM_TECH_MRTTHRC_FILECODE (0XF8CC) -#define PROC_RECOVERY_MEM_PS_MRP_FILECODE (0XF8E0) -#define PROC_RECOVERY_MEM_PS_MRPRTT_FILECODE (0XF8E1) -#define PROC_RECOVERY_MEM_PS_MRPODTPAT_FILECODE (0XF8E2) -#define PROC_RECOVERY_MEM_PS_MRPSAO_FILECODE (0XF8E3) -#define PROC_RECOVERY_MEM_PS_MRPMR0_FILECODE (0XF8E4) -#define PROC_RECOVERY_MEM_PS_MRPRC2IBT_FILECODE (0XF8E5) -#define PROC_RECOVERY_MEM_PS_MRPRC10OPSPD_FILECODE (0XF8E6) -#define PROC_RECOVERY_MEM_PS_MRPLRIBT_FILECODE (0XF8E7) -#define PROC_RECOVERY_MEM_PS_MRPLRNPR_FILECODE (0XF8E8) -#define PROC_RECOVERY_MEM_PS_MRPLRNLR_FILECODE (0XF8E9) -#define PROC_RECOVERY_MEM_TECH_MRTTHRCSEEDTRAIN_FILECODE (0XF8FA) -#define PROC_RECOVERY_MEM_NB_ML_MRNDCTML_FILECODE (0XF902) -#define PROC_RECOVERY_MEM_NB_ML_MRNML_FILECODE (0XF903) -#define PROC_RECOVERY_MEM_NB_ML_MRNMCTML_FILECODE (0XF904) -#define PROC_RECOVERY_MEM_NB_ML_MRNPROTOML_FILECODE (0XF905) -#define PROC_RECOVERY_MEM_PS_ML_MRPSML3_FILECODE (0XF906) -#define PROC_RECOVERY_MEM_PS_ML_MRPML3_FILECODE (0XF907) -#define PROC_RECOVERY_MEM_PS_ML_MRPUML3_FILECODE (0XF908) +#define PROC_RECOVERY_MEM_MRDEF_FILECODE (0xF801) +#define PROC_RECOVERY_MEM_MRINIT_FILECODE (0xF802) +#define PROC_RECOVERY_MEM_MRM_FILECODE (0xF803) +#define PROC_RECOVERY_MEM_MRUC_FILECODE (0xF804) +#define PROC_RECOVERY_MEM_TECH_MRTTPOS_FILECODE (0xF8C1) +#define PROC_RECOVERY_MEM_TECH_MRTTSRC_FILECODE (0xF8C2) +#define PROC_RECOVERY_MEM_TECH_DDR3_MRT3_FILECODE (0xF8C3) +#define PROC_RECOVERY_MEM_TECH_DDR3_MRTRCI3_FILECODE (0xF8C4) +#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSDI3_FILECODE (0xF8C5) +#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSPD3_FILECODE (0xF8C6) +#define PROC_RECOVERY_MEM_TECH_DDR3_MRTTWL3_FILECODE (0xF8C7) +#define PROC_RECOVERY_MEM_NB_MRN_FILECODE (0xF8C8) +#define PROC_RECOVERY_MEM_NB_MRNDCT_FILECODE (0xF8C9) +#define PROC_RECOVERY_MEM_NB_MRNMCT_FILECODE (0xF8CA) +#define PROC_RECOVERY_MEM_NB_MRNTRAIN3_FILECODE (0xF8CB) +#define PROC_RECOVERY_MEM_TECH_MRTTHRC_FILECODE (0xF8CC) +#define PROC_RECOVERY_MEM_PS_MRP_FILECODE (0xF8E0) +#define PROC_RECOVERY_MEM_PS_MRPRTT_FILECODE (0xF8E1) +#define PROC_RECOVERY_MEM_PS_MRPODTPAT_FILECODE (0xF8E2) +#define PROC_RECOVERY_MEM_PS_MRPSAO_FILECODE (0xF8E3) +#define PROC_RECOVERY_MEM_PS_MRPMR0_FILECODE (0xF8E4) +#define PROC_RECOVERY_MEM_PS_MRPRC2IBT_FILECODE (0xF8E5) +#define PROC_RECOVERY_MEM_PS_MRPRC10OPSPD_FILECODE (0xF8E6) +#define PROC_RECOVERY_MEM_PS_MRPLRIBT_FILECODE (0xF8E7) +#define PROC_RECOVERY_MEM_PS_MRPLRNPR_FILECODE (0xF8E8) +#define PROC_RECOVERY_MEM_PS_MRPLRNLR_FILECODE (0xF8E9) +#define PROC_RECOVERY_MEM_TECH_MRTTHRCSEEDTRAIN_FILECODE (0xF8FA) +#define PROC_RECOVERY_MEM_NB_ML_MRNDCTML_FILECODE (0xF902) +#define PROC_RECOVERY_MEM_NB_ML_MRNML_FILECODE (0xF903) +#define PROC_RECOVERY_MEM_NB_ML_MRNMCTML_FILECODE (0xF904) +#define PROC_RECOVERY_MEM_NB_ML_MRNPROTOML_FILECODE (0xF905) +#define PROC_RECOVERY_MEM_PS_ML_MRPSML3_FILECODE (0xF906) +#define PROC_RECOVERY_MEM_PS_ML_MRPML3_FILECODE (0xF907) +#define PROC_RECOVERY_MEM_PS_ML_MRPUML3_FILECODE (0xF908) //Psp #define UEFI_PSP_DRIVERS_ITPMDXE_ITPMDXE_FILECODE (0xFA00) diff --git a/src/vendorcode/amd/pi/00730F01/Proc/CPU/cpuRegisters.h b/src/vendorcode/amd/pi/00730F01/Proc/CPU/cpuRegisters.h index 601a643..e01e0f2 100644 --- a/src/vendorcode/amd/pi/00730F01/Proc/CPU/cpuRegisters.h +++ b/src/vendorcode/amd/pi/00730F01/Proc/CPU/cpuRegisters.h @@ -307,7 +307,7 @@ #define MSR_CPUID_NAME_STRING0 0xC0010030ul // First CPUID namestring register #define MSR_CPUID_NAME_STRING1 0xC0010031ul -#define MSR_CPUID_NAME_STRING2 0XC0010032ul +#define MSR_CPUID_NAME_STRING2 0xC0010032ul #define MSR_CPUID_NAME_STRING3 0xC0010033ul #define MSR_CPUID_NAME_STRING4 0xC0010034ul #define MSR_CPUID_NAME_STRING5 0xC0010035ul // Last CPUID namestring register diff --git a/src/vendorcode/amd/pi/00730F01/Proc/Fch/Fch.h b/src/vendorcode/amd/pi/00730F01/Proc/Fch/Fch.h index ab6f3c0..50e839f 100644 --- a/src/vendorcode/amd/pi/00730F01/Proc/Fch/Fch.h +++ b/src/vendorcode/amd/pi/00730F01/Proc/Fch/Fch.h @@ -2257,12 +2257,12 @@ #define SBTSI_REG10 0x10 #define SBTSI_READORDER BIT5 -#define FCH_EC_ENTER_CONFIG 0X5A -#define FCH_EC_EXIT_CONFIG 0XA5 -#define FCH_EC_REG07 0X07 -#define FCH_EC_REG30 0X30 -#define FCH_EC_REG60 0X60 -#define FCH_EC_REG61 0X61 +#define FCH_EC_ENTER_CONFIG 0x5A +#define FCH_EC_EXIT_CONFIG 0xA5 +#define FCH_EC_REG07 0x07 +#define FCH_EC_REG30 0x30 +#define FCH_EC_REG60 0x60 +#define FCH_EC_REG61 0x61 #define FCH_IMC_ROMSIG 0x55aa55aaul diff --git a/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc index c246b99..ef08c87 100644 --- a/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc +++ b/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc @@ -151,7 +151,7 @@ CPUID_MODEL = 1 AMD_CPUID_FMF = 0x80000001 /* Family Model Features information */ -AMD_CPUID_L2Cache = 0X80000006 /* L2/L3 cache info */ +AMD_CPUID_L2Cache = 0x80000006 /* L2/L3 cache info */ AMD_CPUID_APIC = 0x80000008 /* Long Mode and APIC info., core count */ APIC_ID_CORE_ID_SIZE = 12 /* ApicIdCoreIdSize bit position */ diff --git a/src/vendorcode/cavium/bdk/libbdk-hal/qlm/bdk-qlm-errata-cn8xxx.c b/src/vendorcode/cavium/bdk/libbdk-hal/qlm/bdk-qlm-errata-cn8xxx.c index a7602de..4eeeca3 100644 --- a/src/vendorcode/cavium/bdk/libbdk-hal/qlm/bdk-qlm-errata-cn8xxx.c +++ b/src/vendorcode/cavium/bdk/libbdk-hal/qlm/bdk-qlm-errata-cn8xxx.c @@ -166,7 +166,7 @@ Enable Rx power state override */ BDK_CSR_MODIFY(c, node, BDK_GSERX_LANEX_PCS_CTLIFC_2(qlm, i), c.s.cfg_tx_pstate_req_ovrrd_en = 0x1; - c.s.cfg_rx_pstate_req_ovrrd_en = 0X1); + c.s.cfg_rx_pstate_req_ovrrd_en = 0x1); /* Step 4: Set GSER()_LANE(lane_n)_PCS_CTLIFC_2[CTLIFC_OVRRD_REQ] = 1 Start the CTLIFC override state machine */ BDK_CSR_MODIFY(c, node, BDK_GSERX_LANEX_PCS_CTLIFC_2(qlm, i), @@ -200,7 +200,7 @@ Enable Rx power state override */ BDK_CSR_MODIFY(c, node, BDK_GSERX_LANEX_PCS_CTLIFC_2(qlm, i), c.s.cfg_tx_pstate_req_ovrrd_en = 0x1; - c.s.cfg_rx_pstate_req_ovrrd_en = 0X1); + c.s.cfg_rx_pstate_req_ovrrd_en = 0x1); /* Step 10: Set GSER()_LANE(lane_n)_PCS_CTLIFC_2[CTLIFC_OVRRD_REQ] = 1 Start the CTLIFC override state machine */ BDK_CSR_MODIFY(c, node, BDK_GSERX_LANEX_PCS_CTLIFC_2(qlm, i), @@ -219,7 +219,7 @@ Disable Rx power state override */ BDK_CSR_MODIFY(c, node, BDK_GSERX_LANEX_PCS_CTLIFC_2(qlm, i), c.s.cfg_tx_pstate_req_ovrrd_en = 0x0; - c.s.cfg_rx_pstate_req_ovrrd_en = 0X0); + c.s.cfg_rx_pstate_req_ovrrd_en = 0x0); } /* Step 13: Poll GSER()_PLL_STAT.[PLL_LOCK] = 1 Poll and check that PLL is locked */ diff --git a/src/vendorcode/cavium/bdk/libdram/dram-init-ddr3.c b/src/vendorcode/cavium/bdk/libdram/dram-init-ddr3.c index 3066787..92cbe74 100644 --- a/src/vendorcode/cavium/bdk/libdram/dram-init-ddr3.c +++ b/src/vendorcode/cavium/bdk/libdram/dram-init-ddr3.c @@ -3148,7 +3148,7 @@ bank_bits = (2 + ((spd_banks >> 4) & 0x3)) + ((spd_banks >> 6) & 0x3); bank_bits = min((int)bank_bits, 4); /* Controller can only address 4 bits. */ - spd_package = 0XFF & read_spd(node, &dimm_config_table[0], DDR4_SPD_PACKAGE_TYPE); + spd_package = 0xFF & read_spd(node, &dimm_config_table[0], DDR4_SPD_PACKAGE_TYPE); if (spd_package & 0x80) { // non-monolithic device is_stacked_die = (!disable_stacked_die) ? ((spd_package & 0x73) == 0x11) : 0; ddr_print("DDR4: Package Type 0x%x (%s), %d die\n", spd_package, diff --git a/src/vendorcode/cavium/include/bdk/libbdk-arch/bdk-csrs-ap.h b/src/vendorcode/cavium/include/bdk/libbdk-arch/bdk-csrs-ap.h index 20ed3af..25887b4 100644 --- a/src/vendorcode/cavium/include/bdk/libbdk-arch/bdk-csrs-ap.h +++ b/src/vendorcode/cavium/include/bdk/libbdk-arch/bdk-csrs-ap.h @@ -17483,7 +17483,7 @@ uint64_t tgran4 : 4; /**< [ 31: 28](RO) Support for 4KB memory translation granule size. All other values are reserved. 0x0 = 4KB granule supported. - 0XF = 4KB granule not supported. + 0xF = 4KB granule not supported. In CNXXXX, supported. */ uint64_t tgran64 : 4; /**< [ 27: 24](RO) Support for 64KB memory translation granule size. @@ -17600,7 +17600,7 @@ uint64_t tgran4 : 4; /**< [ 31: 28](RO) Support for 4KB memory translation granule size. All other values are reserved. 0x0 = 4KB granule supported. - 0XF = 4KB granule not supported. + 0xF = 4KB granule not supported. In CNXXXX, supported. */ uint64_t reserved_32_63 : 32; @@ -17614,7 +17614,7 @@ uint64_t tgran4 : 4; /**< [ 31: 28](RO) Support for 4KB memory translation granule size. All other values are reserved. 0x0 = 4KB granule supported. - 0XF = 4KB granule not supported. + 0xF = 4KB granule not supported. In CNXXXX, supported. */ uint64_t tgran64 : 4; /**< [ 27: 24](RO) Support for 64KB memory translation granule size. @@ -17735,7 +17735,7 @@ uint64_t tgran4 : 4; /**< [ 31: 28](RO) Support for 4KB memory translation granule size. All other values are reserved. 0x0 = 4KB granule supported. - 0XF = 4KB granule not supported. + 0xF = 4KB granule not supported. In CNXXXX, supported. */ uint64_t reserved_32_63 : 32; @@ -23442,14 +23442,14 @@ \<pre\> Bit Event number Event mnemonic - 24 0X0038 = REMOTE_ACCESS_RD. - 23 0X0037 = LL_CACHE_MISS_RD. - 22 0X0036 = LL_CACHE_RD. - 21 0X0035 = ITLB_WALK. - 20 0X0034 = DTLB_WALK. - 19 0X0033 = LL_CACHE MISS. - 18 0X0032 = LL_CACHE. - 17 0X0031 = REMOTE_ACCESS. + 24 0x0038 = REMOTE_ACCESS_RD. + 23 0x0037 = LL_CACHE_MISS_RD. + 22 0x0036 = LL_CACHE_RD. + 21 0x0035 = ITLB_WALK. + 20 0x0034 = DTLB_WALK. + 19 0x0033 = LL_CACHE MISS. + 18 0x0032 = LL_CACHE. + 17 0x0031 = REMOTE_ACCESS. 16 RAZ 15 0x002f = L2D_TLB. 14 0x002e = L2I_TLB_REFILL. @@ -23474,14 +23474,14 @@ \<pre\> Bit Event number Event mnemonic - 24 0X0038 = REMOTE_ACCESS_RD. - 23 0X0037 = LL_CACHE_MISS_RD. - 22 0X0036 = LL_CACHE_RD. - 21 0X0035 = ITLB_WALK. - 20 0X0034 = DTLB_WALK. - 19 0X0033 = LL_CACHE MISS. - 18 0X0032 = LL_CACHE. - 17 0X0031 = REMOTE_ACCESS. + 24 0x0038 = REMOTE_ACCESS_RD. + 23 0x0037 = LL_CACHE_MISS_RD. + 22 0x0036 = LL_CACHE_RD. + 21 0x0035 = ITLB_WALK. + 20 0x0034 = DTLB_WALK. + 19 0x0033 = LL_CACHE MISS. + 18 0x0032 = LL_CACHE. + 17 0x0031 = REMOTE_ACCESS. 16 RAZ 15 0x002f = L2D_TLB. 14 0x002e = L2I_TLB_REFILL. diff --git a/src/vendorcode/cavium/include/bdk/libbdk-arch/bdk-csrs-usbdrd.h b/src/vendorcode/cavium/include/bdk/libbdk-arch/bdk-csrs-usbdrd.h index fc28b58..949a560 100644 --- a/src/vendorcode/cavium/include/bdk/libbdk-arch/bdk-csrs-usbdrd.h +++ b/src/vendorcode/cavium/include/bdk/libbdk-arch/bdk-csrs-usbdrd.h @@ -9446,7 +9446,7 @@ [REF_SSP_EN] is asserted. */ uint64_t ref_clk_div2 : 1; /**< [ 38: 38](R/W) Divides the reference clock by two before feeding it into the REF_CLK_FSEL divider. - If [REF_CLK_SEL] = 0x0, 0x1 or 0X2 then the legal values are: + If [REF_CLK_SEL] = 0x0, 0x1 or 0x2 then the legal values are: all DLMC_REF_CLK* frequencies: 0x0 is the only legal value. If [REF_CLK_SEL] = 0x4, 0x5 or 0x6 then the legal values are: @@ -9814,7 +9814,7 @@ 0x07 is the only legal value. */ uint64_t ref_clk_div2 : 1; /**< [ 38: 38](R/W) Divides the reference clock by two before feeding it into the REF_CLK_FSEL divider. - If [REF_CLK_SEL] = 0x0, 0x1 or 0X2 then the legal values are: + If [REF_CLK_SEL] = 0x0, 0x1 or 0x2 then the legal values are: all DLMC_REF_CLK* frequencies: 0x0 is the only legal value. If [REF_CLK_SEL] = 0x4, 0x5 or 0x6 then the legal values are: @@ -10106,7 +10106,7 @@ [REF_SSP_EN] is asserted. */ uint64_t ref_clk_div2 : 1; /**< [ 38: 38](R/W) Divides the reference clock by two before feeding it into the REF_CLK_FSEL divider. - If [REF_CLK_SEL] = 0x0, 0x1 or 0X2 then the legal values are: + If [REF_CLK_SEL] = 0x0, 0x1 or 0x2 then the legal values are: all DLMC_REF_CLK* frequencies: 0x0 is the only legal value. If [REF_CLK_SEL] = 0x4, 0x5 or 0x6 then the legal values are: @@ -10458,7 +10458,7 @@ 0x07 is the only legal value. */ uint64_t ref_clk_div2 : 1; /**< [ 38: 38](R/W) Divides the reference clock by two before feeding it into the REF_CLK_FSEL divider. - If [REF_CLK_SEL] = 0x0, 0x1 or 0X2 then the legal values are: + If [REF_CLK_SEL] = 0x0, 0x1 or 0x2 then the legal values are: all DLMC_REF_CLK* frequencies: 0x0 is the only legal value. If [REF_CLK_SEL] = 0x4, 0x5 or 0x6 then the legal values are: diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Guid/AprioriFileName.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Guid/AprioriFileName.h index eac2385..4c1691f 100644 --- a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Guid/AprioriFileName.h +++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Guid/AprioriFileName.h @@ -21,7 +21,7 @@ #define __PEI_APRIORI_FILE_NAME_H__ #define PEI_APRIORI_FILE_NAME_GUID \ - { 0x1b45cc0a, 0x156a, 0x428a, { 0x62, 0XAF, 0x49, 0x86, 0x4d, 0xa0, 0xe6, 0xe6 } } + { 0x1b45cc0a, 0x156a, 0x428a, { 0x62, 0xAF, 0x49, 0x86, 0x4d, 0xa0, 0xe6, 0xe6 } } /// diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Tpm20.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Tpm20.h index 697a2d7..066ce16 100644 --- a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Tpm20.h +++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Tpm20.h @@ -486,7 +486,7 @@ // Table 18 - TPM_ST Constants typedef UINT16 TPM_ST; #define TPM_ST_RSP_COMMAND (TPM_ST)(0x00C4) -#define TPM_ST_NULL (TPM_ST)(0X8000) +#define TPM_ST_NULL (TPM_ST)(0x8000) #define TPM_ST_NO_SESSIONS (TPM_ST)(0x8001) #define TPM_ST_SESSIONS (TPM_ST)(0x8002) #define TPM_ST_ATTEST_NV (TPM_ST)(0x8014) diff --git a/src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Guid/AprioriFileName.h b/src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Guid/AprioriFileName.h index ab34b17..f899ed9 100644 --- a/src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Guid/AprioriFileName.h +++ b/src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Guid/AprioriFileName.h @@ -15,7 +15,7 @@ #define __PEI_APRIORI_FILE_NAME_H__ #define PEI_APRIORI_FILE_NAME_GUID \ - { 0x1b45cc0a, 0x156a, 0x428a, { 0x62, 0XAF, 0x49, 0x86, 0x4d, 0xa0, 0xe6, 0xe6 } } + { 0x1b45cc0a, 0x156a, 0x428a, { 0x62, 0xAF, 0x49, 0x86, 0x4d, 0xa0, 0xe6, 0xe6 } } /// diff --git a/src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/Tpm20.h b/src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/Tpm20.h index 39332b1..a294dcb 100644 --- a/src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/Tpm20.h +++ b/src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/Tpm20.h @@ -480,7 +480,7 @@ // Table 18 - TPM_ST Constants typedef UINT16 TPM_ST; #define TPM_ST_RSP_COMMAND (TPM_ST)(0x00C4) -#define TPM_ST_NULL (TPM_ST)(0X8000) +#define TPM_ST_NULL (TPM_ST)(0x8000) #define TPM_ST_NO_SESSIONS (TPM_ST)(0x8001) #define TPM_ST_SESSIONS (TPM_ST)(0x8002) #define TPM_ST_ATTEST_NV (TPM_ST)(0x8014) diff --git a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h index 770390d..05210d6 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h @@ -683,7 +683,7 @@ /** Offset 0x0124 - PCIe Disable Spread Spectrum Clocking PCIe Disable Spread Spectrum Clocking. Normal Operation(0x0)(Default) - SSC enabled, - Disable SSC(0X1) - Disable SSC per platform design or for compliance testing + Disable SSC(0x1) - Disable SSC per platform design or for compliance testing 0:Normal Operation, 1:Disable SSC **/ UINT8 PegDisableSpreadSpectrumClocking; -- To view, visit https://review.coreboot.org/c/coreboot/+/44926 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea3ca67908135d0e85083a05bad2ea176ca34095 Gerrit-Change-Number: 44926 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/cnl: Allow using the remaining Comet Lake FSPs
by Subrata Banik (Code Review) 01 Sep '20

01 Sep '20

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44954 ) Change subject: soc/intel/cnl: Allow using the remaining Comet Lake FSPs ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/44954 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4272a6ee08e19769a8a17c93bb3ce2421be0bbc9 Gerrit-Change-Number: 44954 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 01 Sep 2020 03:07:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/puff: Convert ASL file to new DPTF dt impl
by Edward O'Callaghan (Code Review) 01 Sep '20

01 Sep '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44905 ) Change subject: mb/google/puff: Convert ASL file to new DPTF dt impl ...................................................................... mb/google/puff: Convert ASL file to new DPTF dt impl This patch converts the current DPTF policies from static ASL files into the new SSDT-based DPTF implementation. All settings are intended to be copied exactly. BUG=b:158986928 BRANCH=puff TEST=none Change-Id: I45987f44ec381917173f8d2a878edb50da454b4b Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M src/mainboard/google/hatch/Kconfig D src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl M src/mainboard/google/hatch/variants/puff/overridetree.cb 3 files changed, 59 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/44905/1 diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index a658b2a..8b1eb09 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -12,6 +12,7 @@ select ROMSTAGE_SPD_SMBUS select SPD_READ_BY_WORD select SOC_INTEL_CSE_LITE_SKU + select DRIVERS_INTEL_DPTF config BOARD_GOOGLE_HATCH_COMMON def_bool n diff --git a/src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl deleted file mode 100644 index 6694063..0000000 --- a/src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <puff/acpi/dptf.asl> diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb index a5aa702..2a0bb15 100644 --- a/src/mainboard/google/hatch/variants/puff/overridetree.cb +++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb @@ -205,6 +205,64 @@ register "sata_port[1].TxGen3DeEmph" = "0x20" device domain 0 on + device pci 04.0 on + # Default DPTF Policy for all Puff boards if not overridden + chip drivers/intel/dptf + ## Active Policy + register "policies.active[0]" = "{.target=DPTF_CPU, + .thresholds={TEMP_PCT(85, 90), + TEMP_PCT(80, 69), + TEMP_PCT(75, 56), + TEMP_PCT(70, 46), + TEMP_PCT(65, 36),}}" + + ## Passive Policy + register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 93, 5000)" + + ## Critical Policy + register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)" + + ## Power Limits Control + # 10-15W PL1 in 200mW increments, avg over 28-32s interval + # PL2 is fixed at 64W, avg over 28-32s interval + register "controls.power_limits.pl1" = "{ + .min_power = 3000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200,}" + register "controls.power_limits.pl2" = "{ + .min_power = 15000, + .max_power = 60000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000,}" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf[0]" = "{ 255, 1700 }" + register "controls.charger_perf[1]" = "{ 24, 1500 }" + register "controls.charger_perf[2]" = "{ 16, 1000 }" + register "controls.charger_perf[3]" = "{ 8, 500 }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf[0]" = "{ 90, 6700, 220, 2200, }" + register "controls.fan_perf[1]" = "{ 80, 5800, 180, 1800, }" + register "controls.fan_perf[2]" = "{ 70, 5000, 145, 1450, }" + register "controls.fan_perf[3]" = "{ 60, 4900, 115, 1150, }" + register "controls.fan_perf[4]" = "{ 50, 3838, 90, 900, }" + register "controls.fan_perf[5]" = "{ 40, 2904, 55, 550, }" + register "controls.fan_perf[6]" = "{ 30, 2337, 30, 300, }" + register "controls.fan_perf[7]" = "{ 20, 1608, 15, 150, }" + register "controls.fan_perf[8]" = "{ 10, 800, 10, 100, }" + register "controls.fan_perf[9]" = "{ 0, 0, 0, 50, }" + + # Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + + device generic 0 on end + end + end # DPTF 0x1903 device pci 14.0 on chip drivers/usb/acpi device usb 0.0 on -- To view, visit https://review.coreboot.org/c/coreboot/+/44905 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45987f44ec381917173f8d2a878edb50da454b4b Gerrit-Change-Number: 44905 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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coreboot-gerrit September 2020