coreboot-gerrit December 2018

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Change in ...coreboot[master]: mb/google/hatch: Make WP_RO range align with winbond specification
by Subrata Banik (Code Review) 31 Dec '18

31 Dec '18

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30552 Change subject: mb/google/hatch: Make WP_RO range align with winbond specification ...................................................................... mb/google/hatch: Make WP_RO range align with winbond specification This patch ensures to make memory protected range between 0x800000 - 0xFFFFFF as per winbond spi datasheet https://www.winbond.com/resource-files/w25q128fv_revhh1_100913_website1.pdf Change-Id: I52d8dbba14bd060b48a7fe8ee009219413ef89ca Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/mainboard/google/hatch/chromeos.fmd 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/30552/1 diff --git a/src/mainboard/google/hatch/chromeos.fmd b/src/mainboard/google/hatch/chromeos.fmd index 53ba338..5a2aeec 100644 --- a/src/mainboard/google/hatch/chromeos.fmd +++ b/src/mainboard/google/hatch/chromeos.fmd @@ -27,15 +27,15 @@ RW_VPD@0x28000 0x2000 RW_NVRAM@0x2a000 0x6000 } - RW_LEGACY(CBFS)@0x5d0000 0x200000 - WP_RO@0x7d0000 0x430000 { + RW_LEGACY(CBFS)@0x5d0000 0x230000 + WP_RO@0x800000 0x400000 { RO_VPD@0x0 0x4000 - RO_SECTION@0x4000 0x42c000 { + RO_SECTION@0x4000 0x3fc000 { FMAP@0x0 0x800 RO_FRID@0x800 0x40 RO_FRID_PAD@0x840 0x7c0 GBB@0x1000 0xef000 - COREBOOT(CBFS)@0xf0000 0x33c000 + COREBOOT(CBFS)@0xf0000 0x30c000 } } } -- To view, visit https://review.coreboot.org/c/coreboot/+/30552 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I52d8dbba14bd060b48a7fe8ee009219413ef89ca Gerrit-Change-Number: 30552 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/dragonegg: Make WP_RO range align with winbond specification
by Subrata Banik (Code Review) 31 Dec '18

31 Dec '18

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30551 Change subject: mb/google/dragonegg: Make WP_RO range align with winbond specification ...................................................................... mb/google/dragonegg: Make WP_RO range align with winbond specification This patch ensures to make memory protected range between 0x800000 - 0xFFFFFF as per winbond spi datasheet https://www.winbond.com/resource-files/w25q128fv_revhh1_100913_website1.pdf Change-Id: Ife451233f60ef680088babbc824bfc5a17078cb9 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/mainboard/google/dragonegg/chromeos.fmd 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/30551/1 diff --git a/src/mainboard/google/dragonegg/chromeos.fmd b/src/mainboard/google/dragonegg/chromeos.fmd index 07a6987..ea449fe 100644 --- a/src/mainboard/google/dragonegg/chromeos.fmd +++ b/src/mainboard/google/dragonegg/chromeos.fmd @@ -27,15 +27,15 @@ RW_VPD@0x28000 0x2000 RW_NVRAM@0x2a000 0x6000 } - RW_LEGACY(CBFS)@0x5d0000 0x200000 - WP_RO@0x7d0000 0x430000 { + RW_LEGACY(CBFS)@0x5d0000 0x230000 + WP_RO@0x800000 0x400000 { RO_VPD@0x0 0x4000 - RO_SECTION@0x4000 0x42c000 { + RO_SECTION@0x4000 0x3fc000 { FMAP@0x0 0x800 RO_FRID@0x800 0x40 RO_FRID_PAD@0x840 0x7c0 GBB@0x1000 0xef000 - COREBOOT(CBFS)@0xf0000 0x33c000 + COREBOOT(CBFS)@0xf0000 0x30c000 } } } -- To view, visit https://review.coreboot.org/c/coreboot/+/30551 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife451233f60ef680088babbc824bfc5a17078cb9 Gerrit-Change-Number: 30551 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util/chromeos/crosfirmware.sh: Print more messages
by Tristan Corrick (Code Review) 31 Dec '18

31 Dec '18

Tristan Corrick has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30550 Change subject: util/chromeos/crosfirmware.sh: Print more messages ...................................................................... util/chromeos/crosfirmware.sh: Print more messages The existing code has several messages that are only printed when the DEBUG variable is set. These messages are not verbose, and are quite useful to see how the script is progressing. So, print them unconditionally. Change-Id: I8f78e4563f0b4a42f831194a6e526284c2fbcd92 Signed-off-by: Tristan Corrick <tristan(a)corrick.kiwi> --- M util/chromeos/crosfirmware.sh 1 file changed, 6 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/30550/1 diff --git a/util/chromeos/crosfirmware.sh b/util/chromeos/crosfirmware.sh index 567d58e..7198c8e 100755 --- a/util/chromeos/crosfirmware.sh +++ b/util/chromeos/crosfirmware.sh @@ -14,15 +14,8 @@ # GNU General Public License for more details. # -#DEBUG=1 - export PATH="$PATH:/sbin" -debug() -{ - test "$DEBUG" == "1" && echo "$*" -} - exit_if_uninstalled() { local cmd_name="$1" local deb_pkg_name="$2" @@ -50,7 +43,7 @@ _conf=$1 _url=https://dl.google.com/dl/edgedl/chromeos/recovery/recovery.conf - debug "Downloading recovery image inventory..." + echo "Downloading recovery image inventory..." curl -s "$_url" > $_conf } @@ -60,9 +53,9 @@ _url=$1 _file=$2 - debug "Downloading recovery image" + echo "Downloading recovery image" curl "$_url" > "$_file.zip" - debug "Decompressing recovery image" + echo "Decompressing recovery image" unzip -q "$_file.zip" rm "$_file.zip" } @@ -74,7 +67,7 @@ ROOTFS=$3 _bs=1024 - debug "Extracting ROOT-A partition" + echo "Extracting ROOT-A partition" ROOTP=$( printf "unit\nB\nprint\nquit\n" | \ parted $FILE 2>/dev/null | grep $NAME ) @@ -90,7 +83,7 @@ ROOTFS=$1 SHELLBALL=$2 - debug "Extracting chromeos-firmwareupdate" + echo "Extracting chromeos-firmwareupdate" printf "cd /usr/sbin\ndump chromeos-firmwareupdate $SHELLBALL\nquit" | \ debugfs $ROOTFS > /dev/null 2>&1 } @@ -100,7 +93,7 @@ _shellball=$1 _unpacked=$( mktemp -d ) - debug "Extracting coreboot image" + echo "Extracting coreboot image" sh $_shellball --sb_extract $_unpacked > /dev/null _version=$( cat $_unpacked/VERSION | grep BIOS\ version: | \ -- To view, visit https://review.coreboot.org/c/coreboot/+/30550 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8f78e4563f0b4a42f831194a6e526284c2fbcd92 Gerrit-Change-Number: 30550 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util/chromeos/crosfirmware.sh: Check for dependencies
by Tristan Corrick (Code Review) 31 Dec '18

31 Dec '18

Tristan Corrick has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30549 Change subject: util/chromeos/crosfirmware.sh: Check for dependencies ...................................................................... util/chromeos/crosfirmware.sh: Check for dependencies crosfirmware.sh has dependencies that might not be installed on some systems. If a dependency is missing, provide a clear message about the issue and how to resolve it. Change-Id: I265bd03666f1273d3c22b60aae860c48c758005b Signed-off-by: Tristan Corrick <tristan(a)corrick.kiwi> --- M util/chromeos/crosfirmware.sh 1 file changed, 24 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/30549/1 diff --git a/util/chromeos/crosfirmware.sh b/util/chromeos/crosfirmware.sh index 7cd9af9..567d58e 100755 --- a/util/chromeos/crosfirmware.sh +++ b/util/chromeos/crosfirmware.sh @@ -14,9 +14,6 @@ # GNU General Public License for more details. # -# This script needs -# * sharutils - #DEBUG=1 export PATH="$PATH:/sbin" @@ -26,6 +23,28 @@ test "$DEBUG" == "1" && echo "$*" } +exit_if_uninstalled() { + local cmd_name="$1" + local deb_pkg_name="$2" + + if type "$cmd_name" >/dev/null 2>&1; then + return + fi + + printf '`%s` was not found. ' "$cmd_name" >&2 + printf 'On Debian-based systems, it can be installed\n' >&2 + printf 'by running `apt install %s`.\n' "$deb_pkg_name" >&2 + + exit 1 +} + +exit_if_dependencies_are_missing() { + exit_if_uninstalled "uudecode" "sharutils" + exit_if_uninstalled "debugfs" "e2fsprogs" + exit_if_uninstalled "parted" "parted" + exit_if_uninstalled "curl" "curl" +} + get_inventory() { _conf=$1 @@ -112,6 +131,8 @@ BOARD=$1 +exit_if_dependencies_are_missing + if [ "$BOARD" == "all" ]; then CONF=$( mktemp ) get_inventory $CONF -- To view, visit https://review.coreboot.org/c/coreboot/+/30549 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I265bd03666f1273d3c22b60aae860c48c758005b Gerrit-Change-Number: 30549 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util/chromeos/crosfirmware.sh: Print download status
by Tristan Corrick (Code Review) 31 Dec '18

31 Dec '18

Tristan Corrick has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30548 Change subject: util/chromeos/crosfirmware.sh: Print download status ...................................................................... util/chromeos/crosfirmware.sh: Print download status It's quite useful to know the download progress, as it can take a while even with a fast connection. For example, the peppy recovery image is ~600 MiB. It also lets the user know that disk space is being filled. Change-Id: I8c175f9095478ffe33c95b7ef9907c25b5f10f8c Signed-off-by: Tristan Corrick <tristan(a)corrick.kiwi> --- M util/chromeos/crosfirmware.sh 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/30548/1 diff --git a/util/chromeos/crosfirmware.sh b/util/chromeos/crosfirmware.sh index b4eae1a..7cd9af9 100755 --- a/util/chromeos/crosfirmware.sh +++ b/util/chromeos/crosfirmware.sh @@ -42,7 +42,7 @@ _file=$2 debug "Downloading recovery image" - curl -s "$_url" > "$_file.zip" + curl "$_url" > "$_file.zip" debug "Decompressing recovery image" unzip -q "$_file.zip" rm "$_file.zip" -- To view, visit https://review.coreboot.org/c/coreboot/+/30548 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8c175f9095478ffe33c95b7ef9907c25b5f10f8c Gerrit-Change-Number: 30548 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util/chromeos/crosfirmware.sh: Add /sbin to PATH
by Tristan Corrick (Code Review) 31 Dec '18

31 Dec '18

Tristan Corrick has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30547 Change subject: util/chromeos/crosfirmware.sh: Add /sbin to PATH ...................................................................... util/chromeos/crosfirmware.sh: Add /sbin to PATH On some systems, such as Debian 9.6, `parted` and `debugfs` are located in /sbin. Adding /sbin to PATH means that this script can work when run as a regular user. Change-Id: I151dba467e2b196f13093334273dae8a05865491 Signed-off-by: Tristan Corrick <tristan(a)corrick.kiwi> --- M util/chromeos/crosfirmware.sh 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/30547/1 diff --git a/util/chromeos/crosfirmware.sh b/util/chromeos/crosfirmware.sh index ba0c259..b4eae1a 100755 --- a/util/chromeos/crosfirmware.sh +++ b/util/chromeos/crosfirmware.sh @@ -19,6 +19,8 @@ #DEBUG=1 +export PATH="$PATH:/sbin" + debug() { test "$DEBUG" == "1" && echo "$*" -- To view, visit https://review.coreboot.org/c/coreboot/+/30547 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I151dba467e2b196f13093334273dae8a05865491 Gerrit-Change-Number: 30547 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Doc/nb/intel/haswell: Mention util/chromeos as a way to get mrc.bin
by Tristan Corrick (Code Review) 31 Dec '18

31 Dec '18

Tristan Corrick has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30546 Change subject: Doc/nb/intel/haswell: Mention util/chromeos as a way to get mrc.bin ...................................................................... Doc/nb/intel/haswell: Mention util/chromeos as a way to get mrc.bin Change-Id: Ic099d0f052db5ef6a699d54b26028bae2fae4770 Signed-off-by: Tristan Corrick <tristan(a)corrick.kiwi> --- M Documentation/northbridge/intel/haswell/mrc.bin.md 1 file changed, 5 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/30546/1 diff --git a/Documentation/northbridge/intel/haswell/mrc.bin.md b/Documentation/northbridge/intel/haswell/mrc.bin.md index e27e9d6..36ab4c4 100644 --- a/Documentation/northbridge/intel/haswell/mrc.bin.md +++ b/Documentation/northbridge/intel/haswell/mrc.bin.md @@ -14,12 +14,13 @@ Unfortunately, it is not currently possible to distribute `mrc.bin` as part of coreboot. Though, it can be obtained from a Haswell Chromebook -or Chromebox firmware image, and you might find one online. `mrc.bin` -can be extracted with the following command. If extracting from a -"standard" coreboot image, omit `-r RO_SECTION`. +firmware image like so, starting in the root of the coreboot directory: ```bash -cbfstool coreboot.rom extract -f mrc.bin -n mrc.bin -r RO_SECTION +make -C util/cbfstool +cd util/chromeos +./crosfirmware.sh peppy +../cbfstool/cbfstool coreboot-*.bin extract -f mrc.bin -n mrc.bin -r RO_SECTION ``` Now, place `mrc.bin` in the root of the coreboot directory. -- To view, visit https://review.coreboot.org/c/coreboot/+/30546 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic099d0f052db5ef6a699d54b26028bae2fae4770 Gerrit-Change-Number: 30546 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/hatch: Add NC gpios for display and correct the order
by Maulik V Vaghela (Code Review) 30 Dec '18

30 Dec '18

Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30544 Change subject: mb/google/hatch: Add NC gpios for display and correct the order ...................................................................... mb/google/hatch: Add NC gpios for display and correct the order Correcting order of display related GPIOs and also adding not connected pin definitions for display GPIOs BUG=b:120914069 BRANCH=none TEST=check if code compiles with changes. Change-Id: I9498284d263516f65513d6395883b6b09dd70fd5 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/mainboard/google/hatch/variants/baseboard/gpio.c 1 file changed, 16 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/30544/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index 47d8c6c..1011695 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -65,6 +65,22 @@ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* USB_A_OC_OD USB_OC3*/ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), + /* USB_C0_DP_HPD */ + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), + /* DDI2_HPD_ODL */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + /* DDPD_HPD2 => NC */ + PAD_NC(GPP_E15, DN_20K), + /* DDPE_HPD2 => NC */ + PAD_NC(GPP_E16, DN_20K), + /* EDP_HPD */ + PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), + /* DDPB_CTRLCLK => NC */ + PAD_NC(GPP_E18, DN_20K), + /* DDPC_CTRLCLK => NC */ + PAD_NC(GPP_E20, DN_20K), + /* DDPD_CTRLCLK => NC */ + PAD_NC(GPP_E22, DN_20K), /* PCH_MEM_STRAP0 */ PAD_CFG_GPI(GPP_F20, NONE, PLTRST), /* PCH_MEM_STRAP1 */ @@ -73,12 +89,6 @@ PAD_CFG_GPI(GPP_F11, NONE, PLTRST), /* PCH_MEM_STRAP3 */ PAD_CFG_GPI(GPP_F22, NONE, PLTRST), - /* USB_C0_DP_HPD */ - PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), - /* DDI2_HPD_ODL */ - PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), - /* EDP_HPD */ - PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), }; const struct pad_config *__weak variant_gpio_table(size_t *num) -- To view, visit https://review.coreboot.org/c/coreboot/+/30544 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9498284d263516f65513d6395883b6b09dd70fd5 Gerrit-Change-Number: 30544 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: sb/intel/*: Use common files for PCIe ACPI
by Arthur Heymans (Code Review) 30 Dec '18

30 Dec '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30528 Change subject: sb/intel/*: Use common files for PCIe ACPI ...................................................................... sb/intel/*: Use common files for PCIe ACPI The result is that i82801{g,i,j} now use the correct _PRT table for their root port number. Change-Id: I92bba3c669f3e6a44a42e19a88a33dfcfc2b9b42 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/i82801gx/acpi/ich7.asl D src/southbridge/intel/i82801gx/acpi/pcie.asl M src/southbridge/intel/i82801ix/acpi/ich9.asl D src/southbridge/intel/i82801ix/acpi/pcie.asl D src/southbridge/intel/i82801ix/acpi/pcie_port.asl M src/southbridge/intel/i82801jx/acpi/ich10.asl D src/southbridge/intel/i82801jx/acpi/pcie.asl D src/southbridge/intel/i82801jx/acpi/pcie_port.asl M src/southbridge/intel/lynxpoint/acpi/pch.asl D src/southbridge/intel/lynxpoint/acpi/pcie.asl D src/southbridge/intel/lynxpoint/acpi/pcie_port.asl 11 files changed, 4 insertions(+), 841 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/30528/1 diff --git a/src/southbridge/intel/i82801gx/acpi/ich7.asl b/src/southbridge/intel/i82801gx/acpi/ich7.asl index c28f4b9..38ca483 100644 --- a/src/southbridge/intel/i82801gx/acpi/ich7.asl +++ b/src/southbridge/intel/i82801gx/acpi/ich7.asl @@ -163,7 +163,7 @@ #include "audio.asl" // PCI Express Ports -#include "pcie.asl" +#include <southbridge/intel/common/acpi/pcie.asl> // USB #include "usb.asl" diff --git a/src/southbridge/intel/i82801gx/acpi/pcie.asl b/src/southbridge/intel/i82801gx/acpi/pcie.asl deleted file mode 100644 index 3c644e2..0000000 --- a/src/southbridge/intel/i82801gx/acpi/pcie.asl +++ /dev/null @@ -1,179 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Intel i82801G PCIe support */ - -// PCI Express Ports - -Device (RP01) -{ - NAME(_ADR, 0x001c0000) // FIXME: Have a macro for PCI Devices -> ACPI notation? - //#include "pcie_port.asl" - Method(_PRT) - { - If (PICM) { - Return (Package() { - Package() { 0x0000ffff, 0, 0, 16 }, - Package() { 0x0000ffff, 1, 0, 17 }, - Package() { 0x0000ffff, 2, 0, 18 }, - Package() { 0x0000ffff, 3, 0, 19 } - }) - } Else { - Return (Package() { - Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 } - }) - - } - - } -} - -Device (RP02) -{ - NAME(_ADR, 0x001c0001) // FIXME: Have a macro for PCI Devices -> ACPI notation? - //#include "pcie_port.asl" - Method(_PRT) - { - If (PICM) { - Return (Package() { - Package() { 0x0000ffff, 0, 0, 17 }, - Package() { 0x0000ffff, 1, 0, 18 }, - Package() { 0x0000ffff, 2, 0, 19 }, - Package() { 0x0000ffff, 3, 0, 16 } - }) - } Else { - Return (Package() { - Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKA, 0 } - }) - - } - - } -} - - -Device (RP03) -{ - NAME(_ADR, 0x001c0002) // FIXME: Have a macro for PCI Devices -> ACPI notation? - //#include "pcie_port.asl" - Method(_PRT) - { - If (PICM) { - Return (Package() { - Package() { 0x0000ffff, 0, 0, 18 }, - Package() { 0x0000ffff, 1, 0, 19 }, - Package() { 0x0000ffff, 2, 0, 16 }, - Package() { 0x0000ffff, 3, 0, 17 } - }) - } Else { - Return (Package() { - Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKB, 0 } - }) - - } - - } -} - - -Device (RP04) -{ - NAME(_ADR, 0x001c0003) // FIXME: Have a macro for PCI Devices -> ACPI notation? - //#include "pcie_port.asl" - Method(_PRT) - { - If (PICM) { - Return (Package() { - Package() { 0x0000ffff, 0, 0, 19 }, - Package() { 0x0000ffff, 1, 0, 16 }, - Package() { 0x0000ffff, 2, 0, 17 }, - Package() { 0x0000ffff, 3, 0, 18 } - }) - } Else { - Return (Package() { - Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKC, 0 } - }) - - } - - } -} - - -Device (RP05) -{ - NAME(_ADR, 0x001c0004) // FIXME: Have a macro for PCI Devices -> ACPI notation? - //#include "pcie_port.asl" - Method(_PRT) - { - If (PICM) { - Return (Package() { - Package() { 0x0000ffff, 0, 0, 16 }, - Package() { 0x0000ffff, 1, 0, 17 }, - Package() { 0x0000ffff, 2, 0, 18 }, - Package() { 0x0000ffff, 3, 0, 19 } - }) - } Else { - Return (Package() { - Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 } - }) - - } - - } -} - - -Device (RP06) -{ - NAME(_ADR, 0x001c0005) // FIXME: Have a macro for PCI Devices -> ACPI notation? - //#include "pcie_port.asl" - Method(_PRT) - { - If (PICM) { - Return (Package() { - Package() { 0x0000ffff, 0, 0, 17 }, - Package() { 0x0000ffff, 1, 0, 18 }, - Package() { 0x0000ffff, 2, 0, 19 }, - Package() { 0x0000ffff, 3, 0, 16 } - }) - } Else { - Return (Package() { - Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKA, 0 } - }) - - } - - } -} diff --git a/src/southbridge/intel/i82801ix/acpi/ich9.asl b/src/southbridge/intel/i82801ix/acpi/ich9.asl index 78d1f53..d155d15 100644 --- a/src/southbridge/intel/i82801ix/acpi/ich9.asl +++ b/src/southbridge/intel/i82801ix/acpi/ich9.asl @@ -168,7 +168,7 @@ #include "audio.asl" // PCI Express Ports -#include "pcie.asl" +#include <southbridge/intel/common/acpi/pcie.asl> // USB #include "usb.asl" diff --git a/src/southbridge/intel/i82801ix/acpi/pcie.asl b/src/southbridge/intel/i82801ix/acpi/pcie.asl deleted file mode 100644 index b484064..0000000 --- a/src/southbridge/intel/i82801ix/acpi/pcie.asl +++ /dev/null @@ -1,179 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Intel i82801G PCIe support */ - -// PCI Express Ports - -Device (RP01) -{ - NAME(_ADR, 0x001c0000) // FIXME: Have a macro for PCI Devices -> ACPI notation? -#include "pcie_port.asl" - Method(_PRT) - { - If (PICM) { - Return (Package() { - Package() { 0x0000ffff, 0, 0, 16 }, - Package() { 0x0000ffff, 1, 0, 17 }, - Package() { 0x0000ffff, 2, 0, 18 }, - Package() { 0x0000ffff, 3, 0, 19 } - }) - } Else { - Return (Package() { - Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 } - }) - - } - - } -} - -Device (RP02) -{ - NAME(_ADR, 0x001c0001) // FIXME: Have a macro for PCI Devices -> ACPI notation? -#include "pcie_port.asl" - Method(_PRT) - { - If (PICM) { - Return (Package() { - Package() { 0x0000ffff, 0, 0, 17 }, - Package() { 0x0000ffff, 1, 0, 18 }, - Package() { 0x0000ffff, 2, 0, 19 }, - Package() { 0x0000ffff, 3, 0, 16 } - }) - } Else { - Return (Package() { - Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKA, 0 } - }) - - } - - } -} - - -Device (RP03) -{ - NAME(_ADR, 0x001c0002) // FIXME: Have a macro for PCI Devices -> ACPI notation? -#include "pcie_port.asl" - Method(_PRT) - { - If (PICM) { - Return (Package() { - Package() { 0x0000ffff, 0, 0, 18 }, - Package() { 0x0000ffff, 1, 0, 19 }, - Package() { 0x0000ffff, 2, 0, 16 }, - Package() { 0x0000ffff, 3, 0, 17 } - }) - } Else { - Return (Package() { - Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKB, 0 } - }) - - } - - } -} - - -Device (RP04) -{ - NAME(_ADR, 0x001c0003) // FIXME: Have a macro for PCI Devices -> ACPI notation? -#include "pcie_port.asl" - Method(_PRT) - { - If (PICM) { - Return (Package() { - Package() { 0x0000ffff, 0, 0, 19 }, - Package() { 0x0000ffff, 1, 0, 16 }, - Package() { 0x0000ffff, 2, 0, 17 }, - Package() { 0x0000ffff, 3, 0, 18 } - }) - } Else { - Return (Package() { - Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKC, 0 } - }) - - } - - } -} - - -Device (RP05) -{ - NAME(_ADR, 0x001c0004) // FIXME: Have a macro for PCI Devices -> ACPI notation? -#include "pcie_port.asl" - Method(_PRT) - { - If (PICM) { - Return (Package() { - Package() { 0x0000ffff, 0, 0, 16 }, - Package() { 0x0000ffff, 1, 0, 17 }, - Package() { 0x0000ffff, 2, 0, 18 }, - Package() { 0x0000ffff, 3, 0, 19 } - }) - } Else { - Return (Package() { - Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 } - }) - - } - - } -} - - -Device (RP06) -{ - NAME(_ADR, 0x001c0005) // FIXME: Have a macro for PCI Devices -> ACPI notation? -#include "pcie_port.asl" - Method(_PRT) - { - If (PICM) { - Return (Package() { - Package() { 0x0000ffff, 0, 0, 17 }, - Package() { 0x0000ffff, 1, 0, 18 }, - Package() { 0x0000ffff, 2, 0, 19 }, - Package() { 0x0000ffff, 3, 0, 16 } - }) - } Else { - Return (Package() { - Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKA, 0 } - }) - - } - - } -} diff --git a/src/southbridge/intel/i82801ix/acpi/pcie_port.asl b/src/southbridge/intel/i82801ix/acpi/pcie_port.asl deleted file mode 100644 index 4e04ab2..0000000 --- a/src/southbridge/intel/i82801ix/acpi/pcie_port.asl +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 The Chromium OS Authors. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Included in each PCIe Root Port device */ - -OperationRegion (RPCS, PCI_Config, 0x00, 0xFF) -Field (RPCS, AnyAcc, NoLock, Preserve) -{ - Offset (0x4c), // Link Capabilities - , 24, - RPPN, 8, // Root Port Number - Offset (0x5A), - , 3, - PDC, 1, - Offset (0xDF), - , 6, - HPCS, 1, -} diff --git a/src/southbridge/intel/i82801jx/acpi/ich10.asl b/src/southbridge/intel/i82801jx/acpi/ich10.asl index b7d8a33..200dfb5 100644 --- a/src/southbridge/intel/i82801jx/acpi/ich10.asl +++ b/src/southbridge/intel/i82801jx/acpi/ich10.asl @@ -167,7 +167,7 @@ #include "audio.asl" // PCI Express Ports -#include "pcie.asl" +#include <southbridge/intel/common/acpi/pcie.asl> // USB #include "usb.asl" diff --git a/src/southbridge/intel/i82801jx/acpi/pcie.asl b/src/southbridge/intel/i82801jx/acpi/pcie.asl deleted file mode 100644 index b484064..0000000 --- a/src/southbridge/intel/i82801jx/acpi/pcie.asl +++ /dev/null @@ -1,179 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Intel i82801G PCIe support */ - -// PCI Express Ports - -Device (RP01) -{ - NAME(_ADR, 0x001c0000) // FIXME: Have a macro for PCI Devices -> ACPI notation? -#include "pcie_port.asl" - Method(_PRT) - { - If (PICM) { - Return (Package() { - Package() { 0x0000ffff, 0, 0, 16 }, - Package() { 0x0000ffff, 1, 0, 17 }, - Package() { 0x0000ffff, 2, 0, 18 }, - Package() { 0x0000ffff, 3, 0, 19 } - }) - } Else { - Return (Package() { - Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 } - }) - - } - - } -} - -Device (RP02) -{ - NAME(_ADR, 0x001c0001) // FIXME: Have a macro for PCI Devices -> ACPI notation? -#include "pcie_port.asl" - Method(_PRT) - { - If (PICM) { - Return (Package() { - Package() { 0x0000ffff, 0, 0, 17 }, - Package() { 0x0000ffff, 1, 0, 18 }, - Package() { 0x0000ffff, 2, 0, 19 }, - Package() { 0x0000ffff, 3, 0, 16 } - }) - } Else { - Return (Package() { - Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKA, 0 } - }) - - } - - } -} - - -Device (RP03) -{ - NAME(_ADR, 0x001c0002) // FIXME: Have a macro for PCI Devices -> ACPI notation? -#include "pcie_port.asl" - Method(_PRT) - { - If (PICM) { - Return (Package() { - Package() { 0x0000ffff, 0, 0, 18 }, - Package() { 0x0000ffff, 1, 0, 19 }, - Package() { 0x0000ffff, 2, 0, 16 }, - Package() { 0x0000ffff, 3, 0, 17 } - }) - } Else { - Return (Package() { - Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKB, 0 } - }) - - } - - } -} - - -Device (RP04) -{ - NAME(_ADR, 0x001c0003) // FIXME: Have a macro for PCI Devices -> ACPI notation? -#include "pcie_port.asl" - Method(_PRT) - { - If (PICM) { - Return (Package() { - Package() { 0x0000ffff, 0, 0, 19 }, - Package() { 0x0000ffff, 1, 0, 16 }, - Package() { 0x0000ffff, 2, 0, 17 }, - Package() { 0x0000ffff, 3, 0, 18 } - }) - } Else { - Return (Package() { - Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKC, 0 } - }) - - } - - } -} - - -Device (RP05) -{ - NAME(_ADR, 0x001c0004) // FIXME: Have a macro for PCI Devices -> ACPI notation? -#include "pcie_port.asl" - Method(_PRT) - { - If (PICM) { - Return (Package() { - Package() { 0x0000ffff, 0, 0, 16 }, - Package() { 0x0000ffff, 1, 0, 17 }, - Package() { 0x0000ffff, 2, 0, 18 }, - Package() { 0x0000ffff, 3, 0, 19 } - }) - } Else { - Return (Package() { - Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 } - }) - - } - - } -} - - -Device (RP06) -{ - NAME(_ADR, 0x001c0005) // FIXME: Have a macro for PCI Devices -> ACPI notation? -#include "pcie_port.asl" - Method(_PRT) - { - If (PICM) { - Return (Package() { - Package() { 0x0000ffff, 0, 0, 17 }, - Package() { 0x0000ffff, 1, 0, 18 }, - Package() { 0x0000ffff, 2, 0, 19 }, - Package() { 0x0000ffff, 3, 0, 16 } - }) - } Else { - Return (Package() { - Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKA, 0 } - }) - - } - - } -} diff --git a/src/southbridge/intel/i82801jx/acpi/pcie_port.asl b/src/southbridge/intel/i82801jx/acpi/pcie_port.asl deleted file mode 100644 index 4e04ab2..0000000 --- a/src/southbridge/intel/i82801jx/acpi/pcie_port.asl +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 The Chromium OS Authors. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Included in each PCIe Root Port device */ - -OperationRegion (RPCS, PCI_Config, 0x00, 0xFF) -Field (RPCS, AnyAcc, NoLock, Preserve) -{ - Offset (0x4c), // Link Capabilities - , 24, - RPPN, 8, // Root Port Number - Offset (0x5A), - , 3, - PDC, 1, - Offset (0xDF), - , 6, - HPCS, 1, -} diff --git a/src/southbridge/intel/lynxpoint/acpi/pch.asl b/src/southbridge/intel/lynxpoint/acpi/pch.asl index eaa2690..a25282a 100644 --- a/src/southbridge/intel/lynxpoint/acpi/pch.asl +++ b/src/southbridge/intel/lynxpoint/acpi/pch.asl @@ -81,7 +81,7 @@ #include "audio.asl" // PCI Express Ports 0:1c.x -#include "pcie.asl" +#include <southbridge/intel/common/acpi/pcie.asl> // USB 0:1d.0 and 0:1a.0 #include "usb.asl" diff --git a/src/southbridge/intel/lynxpoint/acpi/pcie.asl b/src/southbridge/intel/lynxpoint/acpi/pcie.asl deleted file mode 100644 index d7842cd..0000000 --- a/src/southbridge/intel/lynxpoint/acpi/pcie.asl +++ /dev/null @@ -1,213 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2012 The Chromium OS Authors. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Intel 6/7 Series PCH PCIe support */ - -// PCI Express Ports - -Method (IRQM, 1, Serialized) { - - /* Interrupt Map INTA->INTA, INTB->INTB, INTC->INTC, INTD->INTD */ - Name (IQAA, Package() { - Package() { 0x0000ffff, 0, 0, 16 }, - Package() { 0x0000ffff, 1, 0, 17 }, - Package() { 0x0000ffff, 2, 0, 18 }, - Package() { 0x0000ffff, 3, 0, 19 } }) - Name (IQAP, Package() { - Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 } }) - - /* Interrupt Map INTA->INTB, INTB->INTC, INTC->INTD, INTD->INTA */ - Name (IQBA, Package() { - Package() { 0x0000ffff, 0, 0, 17 }, - Package() { 0x0000ffff, 1, 0, 18 }, - Package() { 0x0000ffff, 2, 0, 19 }, - Package() { 0x0000ffff, 3, 0, 16 } }) - Name (IQBP, Package() { - Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKA, 0 } }) - - /* Interrupt Map INTA->INTC, INTB->INTD, INTC->INTA, INTD->INTB */ - Name (IQCA, Package() { - Package() { 0x0000ffff, 0, 0, 18 }, - Package() { 0x0000ffff, 1, 0, 19 }, - Package() { 0x0000ffff, 2, 0, 16 }, - Package() { 0x0000ffff, 3, 0, 17 } }) - Name (IQCP, Package() { - Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKB, 0 } }) - - /* Interrupt Map INTA->INTD, INTB->INTA, INTC->INTB, INTD->INTC */ - Name (IQDA, Package() { - Package() { 0x0000ffff, 0, 0, 19 }, - Package() { 0x0000ffff, 1, 0, 16 }, - Package() { 0x0000ffff, 2, 0, 17 }, - Package() { 0x0000ffff, 3, 0, 18 } }) - Name (IQDP, Package() { - Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKC, 0 } }) - - Switch (ToInteger (Arg0)) { - /* PCIe Root Port 1 and 5 */ - Case (Package() { 1, 5 }) { - If (PICM) { - Return (IQAA) - } Else { - Return (IQAP) - } - } - - /* PCIe Root Port 2 and 6 */ - Case (Package() { 2, 6 }) { - If (PICM) { - Return (IQBA) - } Else { - Return (IQBP) - } - } - - /* PCIe Root Port 3 and 7 */ - Case (Package() { 3, 7 }) { - If (PICM) { - Return (IQCA) - } Else { - Return (IQCP) - } - } - - /* PCIe Root Port 4 and 8 */ - Case (Package() { 4, 8 }) { - If (PICM) { - Return (IQDA) - } Else { - Return (IQDP) - } - } - - Default { - If (PICM) { - Return (IQDA) - } Else { - Return (IQDP) - } - } - } -} - -Device (RP01) -{ - Name (_ADR, 0x001c0000) - - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP02) -{ - Name (_ADR, 0x001c0001) - - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP03) -{ - Name (_ADR, 0x001c0002) - - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP04) -{ - Name (_ADR, 0x001c0003) - - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP05) -{ - Name (_ADR, 0x001c0004) - - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP06) -{ - Name (_ADR, 0x001c0005) - - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP07) -{ - Name (_ADR, 0x001c0006) - - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP08) -{ - Name (_ADR, 0x001c0007) - - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} diff --git a/src/southbridge/intel/lynxpoint/acpi/pcie_port.asl b/src/southbridge/intel/lynxpoint/acpi/pcie_port.asl deleted file mode 100644 index 32ddead..0000000 --- a/src/southbridge/intel/lynxpoint/acpi/pcie_port.asl +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 The Chromium OS Authors. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Included in each PCIe Root Port device */ - -OperationRegion (RPCS, PCI_Config, 0x00, 0xFF) -Field (RPCS, AnyAcc, NoLock, Preserve) -{ - Offset (0x4c), // Link Capabilities - , 24, - RPPN, 8, // Root Port Number -} -- To view, visit https://review.coreboot.org/c/coreboot/+/30528 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I92bba3c669f3e6a44a42e19a88a33dfcfc2b9b42 Gerrit-Change-Number: 30528 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: sb/intel/bd82x6x: Move pcie ACPI code to a common place
by Arthur Heymans (Code Review) 30 Dec '18

30 Dec '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30527 Change subject: sb/intel/bd82x6x: Move pcie ACPI code to a common place ...................................................................... sb/intel/bd82x6x: Move pcie ACPI code to a common place Change-Id: I45144f9c397ff9a0be011990ba33db9ffef351e7 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/bd82x6x/acpi/pch.asl R src/southbridge/intel/common/acpi/pcie.asl R src/southbridge/intel/common/acpi/pcie_port.asl 3 files changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/30527/1 diff --git a/src/southbridge/intel/bd82x6x/acpi/pch.asl b/src/southbridge/intel/bd82x6x/acpi/pch.asl index a068bc0..d3aa7a4 100644 --- a/src/southbridge/intel/bd82x6x/acpi/pch.asl +++ b/src/southbridge/intel/bd82x6x/acpi/pch.asl @@ -238,7 +238,7 @@ #include "audio.asl" // PCI Express Ports 0:1c.x -#include "pcie.asl" +#include <southbridge/intel/common/acpi/pcie.asl> // USB EHCI 0:1d.0 and 0:1a.0, XHCI 0:14.0 #include "usb.asl" diff --git a/src/southbridge/intel/bd82x6x/acpi/pcie.asl b/src/southbridge/intel/common/acpi/pcie.asl similarity index 100% rename from src/southbridge/intel/bd82x6x/acpi/pcie.asl rename to src/southbridge/intel/common/acpi/pcie.asl diff --git a/src/southbridge/intel/bd82x6x/acpi/pcie_port.asl b/src/southbridge/intel/common/acpi/pcie_port.asl similarity index 100% rename from src/southbridge/intel/bd82x6x/acpi/pcie_port.asl rename to src/southbridge/intel/common/acpi/pcie_port.asl -- To view, visit https://review.coreboot.org/c/coreboot/+/30527 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45144f9c397ff9a0be011990ba33db9ffef351e7 Gerrit-Change-Number: 30527 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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coreboot-gerrit December 2018