coreboot-gerrit December 2018

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Change in ...coreboot[master]: soc/intel/cannonlake: Enable options for wakeup
by Lijian Zhao (Code Review) 10 May '19

10 May '19

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30447 Change subject: soc/intel/cannonlake: Enable options for wakeup ...................................................................... soc/intel/cannonlake: Enable options for wakeup Cannonlake FSP silicon init have dedicated wake up capability settings for several IP, expose the selection into coreboot. Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> Change-Id: I260e655417ca79d458784c9ec0e8e35d03b02e06 --- M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/fsp_params.c 2 files changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/30447/1 diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 3a723d2..e5a3ae1 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -302,6 +302,13 @@ /* SATA Power Optimizer */ uint8_t satapwroptimize; + + /* Wake Up Capability */ + uint8_t codec_wake_sx; + uint8_t pcie_wake_deepsx; + uint8_t wlan_wake_sx; + uint8_t wlan_wake_deepsx; + uint8_t glan_wake_deepsx; }; typedef struct soc_intel_cannonlake_config config_t; diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 78b27e9..9a24242 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -225,6 +225,14 @@ /* Power Optimizer */ params->PchPwrOptEnable = config->dmipwroptimize; params->SataPwrOptEnable = config->satapwroptimize; + + /* Wakeup Capability */ + params->PchHdaCodecSxWakeCapability = config->codec_wake_sx; + params->PchPmWoWlanEnable = config->wlan_wake_sx; + params->PchPmPcieWakeFromDeepSx = config->pcie_wake_deepsx; + params->PchPmWoWlanDeepSxEnable = config->wlan_wake_deepsx; + params->PchPmLanWakeFromDeepSx = config->glan_wake_deepsx; + } /* Mainboard GPIO Configuration */ -- To view, visit https://review.coreboot.org/c/coreboot/+/30447 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I260e655417ca79d458784c9ec0e8e35d03b02e06 Gerrit-Change-Number: 30447 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/packardbell/ms2290/acpi: Update _OSI strings and OSYS values
by HAOUAS Elyes (Code Review) 18 Apr '19

18 Apr '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30468 Change subject: mb/packardbell/ms2290/acpi: Update _OSI strings and OSYS values ...................................................................... mb/packardbell/ms2290/acpi: Update _OSI strings and OSYS values Change-Id: I3f5ee4d68c96e8ee0d964c62edebfcfa37fd1c45 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/packardbell/ms2290/acpi/platform.asl 1 file changed, 67 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/30468/1 diff --git a/src/mainboard/packardbell/ms2290/acpi/platform.asl b/src/mainboard/packardbell/ms2290/acpi/platform.asl index 9812d14..e3f95ed 100644 --- a/src/mainboard/packardbell/ms2290/acpi/platform.asl +++ b/src/mainboard/packardbell/ms2290/acpi/platform.asl @@ -90,51 +90,101 @@ * 2001 | Windows XP(+SP1) * 2002 | Windows XP SP2 * 2006 | Windows Vista - * ???? | Windows 7 + * 2009 | Windows 7 + * 2012 | Windows 8 + * 2013 | Windows 8.1 + * 2015 | Windows 10 + * 2016 | Windows 10, version 1607 + * 2017 | Windows 10, version 1703 + * 2017.2 | Windows 10, version 1709 + * 2018 | Windows 10, version 1803 + * 2018.2 | Windows 10, version 1809 */ /* Let's assume we're running at least Windows 2000 */ Store (2000, OSYS) If (CondRefOf(_OSI)) { + /* Linux answers _OSI with "True" for a couple of + * Windows version queries. But unlike Windows it + * needs a Video repost, so let's determine whether + * we're running Linux. + */ + + If (_OSI("Linux")) { + Store (1, LINX) + } + + If (_OSI("Windows 2000")) { + Store (0x07D0, OSYS) + } + If (_OSI("Windows 2001")) { - Store (2001, OSYS) + Store (0x07D1, OSYS) } If (_OSI("Windows 2001 SP1")) { - Store (2001, OSYS) - } - - If (_OSI("Windows 2001 SP2")) { - Store (2002, OSYS) + Store (0x07D1, OSYS) } If (_OSI("Windows 2001.1")) { - Store (2001, OSYS) + Store (0x07D1, OSYS) + } + + If (_OSI("Windows 2001 SP2")) { + Store (0x07D1, OSYS) } If (_OSI("Windows 2001.1 SP1")) { - Store (2001, OSYS) + Store (0x07D1, OSYS) } If (_OSI("Windows 2006")) { - Store (2006, OSYS) - } - - If (_OSI("Windows 2006.1")) { - Store (2006, OSYS) + Store (0x07D6, OSYS) } If (_OSI("Windows 2006 SP1")) { - Store (2006, OSYS) + Store (0x07D6, OSYS) + } + + If (_OSI("Windows 2006.1")) { + Store (0x07D6, OSYS) } If (_OSI("Windows 2009")) { - Store (2009, OSYS) + Store (0x07D9, OSYS) } If (_OSI("Windows 2012")) { - Store (2012, OSYS) + Store (0x07DC, OSYS) + } + + If (_OSI("Windows 2013")) { + Store (0x07DD, OSYS) + } + + If (_OSI("Windows 2015")) { + Store (0x07DF, OSYS) + } + + If (_OSI("Windows 2016")) { + Store (0x07E0, OSYS) + } + + If (_OSI("Windows 2017")) { + Store (0x07E1, OSYS) + } + + If (_OSI("Windows 2017.2")) { + Store (0x07E1, OSYS) + } + + If (_OSI("Windows 2018")) { + Store (0x07E2, OSYS) + } + + If (_OSI("Windows 2018.2")) { + Store (0x07E2, OSYS) } } } -- To view, visit https://review.coreboot.org/c/coreboot/+/30468 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f5ee4d68c96e8ee0d964c62edebfcfa37fd1c45 Gerrit-Change-Number: 30468 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/lenovo/x201/acpi: Update _OSI strings and OSYS values
by HAOUAS Elyes (Code Review) 18 Apr '19

18 Apr '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30469 Change subject: mb/lenovo/x201/acpi: Update _OSI strings and OSYS values ...................................................................... mb/lenovo/x201/acpi: Update _OSI strings and OSYS values Change-Id: I503bd92f2a1fa56e3f97c8090431abe92a51fd0e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/lenovo/x201/acpi/platform.asl 1 file changed, 68 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/30469/1 diff --git a/src/mainboard/lenovo/x201/acpi/platform.asl b/src/mainboard/lenovo/x201/acpi/platform.asl index 7d7013b..1f55624 100644 --- a/src/mainboard/lenovo/x201/acpi/platform.asl +++ b/src/mainboard/lenovo/x201/acpi/platform.asl @@ -111,52 +111,103 @@ * 2001 | Windows XP(+SP1) * 2002 | Windows XP SP2 * 2006 | Windows Vista - * ???? | Windows 7 + * 2009 | Windows 7 + * 2012 | Windows 8 + * 2013 | Windows 8.1 + * 2015 | Windows 10 + * 2016 | Windows 10, version 1607 + * 2017 | Windows 10, version 1703 + * 2017.2 | Windows 10, version 1709 + * 2018 | Windows 10, version 1803 + * 2018.2 | Windows 10, version 1809 */ /* Let's assume we're running at least Windows 2000 */ Store (2000, OSYS) If (CondRefOf(_OSI)) { + /* Linux answers _OSI with "True" for a couple of + * Windows version queries. But unlike Windows it + * needs a Video repost, so let's determine whether + * we're running Linux. + */ + + If (_OSI("Linux")) { + Store (1, LINX) + } + + If (_OSI("Windows 2000")) { + Store (0x07D0, OSYS) + } + If (_OSI("Windows 2001")) { - Store (2001, OSYS) + Store (0x07D1, OSYS) } If (_OSI("Windows 2001 SP1")) { - Store (2001, OSYS) - } - - If (_OSI("Windows 2001 SP2")) { - Store (2002, OSYS) + Store (0x07D1, OSYS) } If (_OSI("Windows 2001.1")) { - Store (2001, OSYS) + Store (0x07D1, OSYS) + } + + If (_OSI("Windows 2001 SP2")) { + Store (0x07D1, OSYS) } If (_OSI("Windows 2001.1 SP1")) { - Store (2001, OSYS) + Store (0x07D1, OSYS) } If (_OSI("Windows 2006")) { - Store (2006, OSYS) - } - - If (_OSI("Windows 2006.1")) { - Store (2006, OSYS) + Store (0x07D6, OSYS) } If (_OSI("Windows 2006 SP1")) { - Store (2006, OSYS) + Store (0x07D6, OSYS) + } + + If (_OSI("Windows 2006.1")) { + Store (0x07D6, OSYS) } If (_OSI("Windows 2009")) { - Store (2009, OSYS) + Store (0x07D9, OSYS) } If (_OSI("Windows 2012")) { - Store (2012, OSYS) + Store (0x07DC, OSYS) } + + If (_OSI("Windows 2013")) { + Store (0x07DD, OSYS) + } + + If (_OSI("Windows 2015")) { + Store (0x07DF, OSYS) + } + + If (_OSI("Windows 2016")) { + Store (0x07E0, OSYS) + } + + If (_OSI("Windows 2017")) { + Store (0x07E1, OSYS) + } + + If (_OSI("Windows 2017.2")) { + Store (0x07E1, OSYS) + } + + If (_OSI("Windows 2018")) { + Store (0x07E2, OSYS) + } + + If (_OSI("Windows 2018.2")) { + Store (0x07E2, OSYS) + } + } } } -- To view, visit https://review.coreboot.org/c/coreboot/+/30469 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I503bd92f2a1fa56e3f97c8090431abe92a51fd0e Gerrit-Change-Number: 30469 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/qemu-{i440fx,q35}: Use POSTCAR stage to load the ramstage
by Patrick Rudolph (Code Review) 05 Mar '19

05 Mar '19

Hello Arthur Heymans, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/30499 to review the following change. Change subject: mb/qemu-{i440fx,q35}: Use POSTCAR stage to load the ramstage ...................................................................... mb/qemu-{i440fx,q35}: Use POSTCAR stage to load the ramstage Qemu does not have a real CAR but postcar stage is still useful to setup pagetables for x86_64 ramstage. Change-Id: I6638534d99fde312e55b6a6be8c95e4cb25cca80 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/lib/Makefile.inc M src/mainboard/emulation/qemu-i440fx/Kconfig M src/mainboard/emulation/qemu-i440fx/Makefile.inc A src/mainboard/emulation/qemu-i440fx/exit_car.S M src/mainboard/emulation/qemu-i440fx/romstage.c M src/mainboard/emulation/qemu-q35/Kconfig M src/mainboard/emulation/qemu-q35/Makefile.inc M src/mainboard/emulation/qemu-q35/romstage.c 8 files changed, 75 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/30499/1 diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 2fd4e4c..48dc664 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -132,6 +132,7 @@ ramstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c ramstage-$(CONFIG_BOOTSPLASH) += jpeg.c ramstage-$(CONFIG_TRACE) += trace.c +postcar-$(CONFIG_TRACE) += trace.c ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c ramstage-$(CONFIG_COVERAGE) += libgcov.c ramstage-y += edid.c diff --git a/src/mainboard/emulation/qemu-i440fx/Kconfig b/src/mainboard/emulation/qemu-i440fx/Kconfig index eb9f011..3a507d3 100644 --- a/src/mainboard/emulation/qemu-i440fx/Kconfig +++ b/src/mainboard/emulation/qemu-i440fx/Kconfig @@ -14,6 +14,8 @@ select MAINBOARD_FORCE_NATIVE_VGA_INIT select BOOTBLOCK_CONSOLE select NO_CAR_GLOBAL_MIGRATION + select POSTCAR_STAGE + select POSTCAR_CONSOLE config MAINBOARD_DIR string diff --git a/src/mainboard/emulation/qemu-i440fx/Makefile.inc b/src/mainboard/emulation/qemu-i440fx/Makefile.inc index 9e2880a..de790e6 100644 --- a/src/mainboard/emulation/qemu-i440fx/Makefile.inc +++ b/src/mainboard/emulation/qemu-i440fx/Makefile.inc @@ -2,3 +2,5 @@ ramstage-y += fw_cfg.c romstage-y += memory.c ramstage-y += memory.c +postcar-y += memory.c +postcar-y += exit_car.S diff --git a/src/mainboard/emulation/qemu-i440fx/exit_car.S b/src/mainboard/emulation/qemu-i440fx/exit_car.S new file mode 100644 index 0000000..74f6ed2 --- /dev/null +++ b/src/mainboard/emulation/qemu-i440fx/exit_car.S @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <cpu/x86/mtrr.h> +#include <cpu/x86/cr.h> +/* jump directly to the main function, as there is no real CAR to tear down. */ +.text +.global chipset_teardown_car +chipset_teardown_car: + /* Set up new stack. */ + mov post_car_stack_top, %esp + /* Call C code */ + call main diff --git a/src/mainboard/emulation/qemu-i440fx/romstage.c b/src/mainboard/emulation/qemu-i440fx/romstage.c index e31394c..137dfbf 100644 --- a/src/mainboard/emulation/qemu-i440fx/romstage.c +++ b/src/mainboard/emulation/qemu-i440fx/romstage.c @@ -20,14 +20,35 @@ #include <cpu/intel/romstage.h> #include <timestamp.h> #include <program_loading.h> +#include <cpu/x86/mtrr.h> + +#include "memory.h" asmlinkage void car_stage_entry(void) { + struct postcar_frame pcf; + console_init(); cbmem_recovery(0); timestamp_add_now(TS_START_ROMSTAGE); - run_ramstage(); + if (postcar_frame_init(&pcf, 5 * KiB)) + die("Unable to initialize postcar frame.\n"); + + /* Cache the ROM as WP just below 4GiB. */ + postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); + + /* Cache memory below 4 GiB */ + postcar_frame_add_mtrr(&pcf, 0, qemu_get_memory_size() * KiB, + MTRR_TYPE_WRBACK); + + /* Cache memory beyond 4 GiB */ + if (qemu_get_high_memory_size() > 0) + postcar_frame_add_mtrr(&pcf, (4ULL * GiB), + qemu_get_high_memory_size() * KiB, + MTRR_TYPE_WRBACK); + + run_postcar_phase(&pcf); } diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig index 1cc7148..07c15f3 100644 --- a/src/mainboard/emulation/qemu-q35/Kconfig +++ b/src/mainboard/emulation/qemu-q35/Kconfig @@ -13,6 +13,8 @@ select MAINBOARD_FORCE_NATIVE_VGA_INIT select BOOTBLOCK_CONSOLE select NO_CAR_GLOBAL_MIGRATION + select POSTCAR_STAGE + select POSTCAR_CONSOLE config MAINBOARD_DIR string diff --git a/src/mainboard/emulation/qemu-q35/Makefile.inc b/src/mainboard/emulation/qemu-q35/Makefile.inc index 1c06d77..a0ac5dd 100644 --- a/src/mainboard/emulation/qemu-q35/Makefile.inc +++ b/src/mainboard/emulation/qemu-q35/Makefile.inc @@ -3,4 +3,6 @@ ramstage-y += ../qemu-i440fx/fw_cfg.c romstage-y += ../qemu-i440fx/memory.c +postcar-y += ../qemu-i440fx/memory.c +postcar-y += ../qemu-i440fx/exit_car.S bootblock-y += bootblock.c diff --git a/src/mainboard/emulation/qemu-q35/romstage.c b/src/mainboard/emulation/qemu-q35/romstage.c index 2b8d935..badafdd 100644 --- a/src/mainboard/emulation/qemu-q35/romstage.c +++ b/src/mainboard/emulation/qemu-q35/romstage.c @@ -21,9 +21,13 @@ #include <timestamp.h> #include <southbridge/intel/i82801ix/i82801ix.h> #include <program_loading.h> +#include <cpu/x86/mtrr.h> + +#include "../qemu-i440fx/memory.h" asmlinkage void car_stage_entry(void) { + struct postcar_frame pcf; i82801ix_early_init(); console_init(); @@ -31,5 +35,21 @@ timestamp_add_now(TS_START_ROMSTAGE); - run_ramstage(); + if (postcar_frame_init(&pcf, 5 * KiB)) + die("Unable to initialize postcar frame.\n"); + + /* Cache the ROM as WP just below 4GiB. */ + postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); + + /* Cache memory below 4 GiB */ + postcar_frame_add_mtrr(&pcf, 0, qemu_get_memory_size() * KiB, + MTRR_TYPE_WRBACK); + + /* Cache memory beyond 4 GiB */ + if (qemu_get_high_memory_size() > 0) + postcar_frame_add_mtrr(&pcf, (4ULL * GiB), + qemu_get_high_memory_size() * KiB, + MTRR_TYPE_WRBACK); + + run_postcar_phase(&pcf); } -- To view, visit https://review.coreboot.org/c/coreboot/+/30499 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6638534d99fde312e55b6a6be8c95e4cb25cca80 Gerrit-Change-Number: 30499 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/sarien: Set CPU boot up mode to turbo
by Lijian Zhao (Code Review) 01 Mar '19

01 Mar '19

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30446 Change subject: mb/google/sarien: Set CPU boot up mode to turbo ...................................................................... mb/google/sarien: Set CPU boot up mode to turbo Set CPU to be running at non-turbo maxium speed first and then switch to turbo maxium speed to accelerate boot performance. BUG=N/A TEST=Boot up with sarien platform, check with cbmem -t, boot time had been 110ms less. Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> Change-Id: I43bdb7ef82a5e6e147b3b506756c118dacdb0321 --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/30446/1 diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 52840de..ce83d10 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -24,6 +24,7 @@ register "SkipExtGfxScan" = "1" register "VmxEnable" = "1" + register "bootfreq" = "2" register "speed_shift_enable" = "1" register "s0ix_enable" = "1" register "dptf_enable" = "1" diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 47abadc..98566f1 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -28,6 +28,7 @@ register "SkipExtGfxScan" = "1" register "VmxEnable" = "1" + register "bootfreq" = "2" register "speed_shift_enable" = "1" register "s0ix_enable" = "1" register "dptf_enable" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/30446 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43bdb7ef82a5e6e147b3b506756c118dacdb0321 Gerrit-Change-Number: 30446 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/cannonlake: Add option for boot frquency
by Lijian Zhao (Code Review) 01 Mar '19

01 Mar '19

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30445 Change subject: soc/intel/cannonlake: Add option for boot frquency ...................................................................... soc/intel/cannonlake: Add option for boot frquency Cannonlake/Coffeelake FSP have options for CPU boot up frequency selection, expose that in coreboot side. Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> Change-Id: I6bd5849122c9035bb7f448acf08e258e8c207013 --- M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/romstage/fsp_params.c 2 files changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/30445/1 diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 3a723d2..7e50a73 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -110,6 +110,11 @@ SaGv_Enabled, } SaGv; + /* Boot Frequency from reset vector. + * 0: Maximum battery performance, 1: Maximum non-turbo performance, 2: + * Maximum turbo performance @note If 2 is selected, system will start + * with non-turbo mode and then switch to turbo. */ + uint8_t bootfreq; /* Rank Margin Tool. 1:Enable, 0:Disable */ uint8_t RMT; diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index c3a2509..0514844 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -54,6 +54,8 @@ #if IS_ENABLED(CONFIG_SOC_INTEL_COFFEELAKE) m_cfg->SkipMpInit = !chip_get_fsp_mp_init(); #endif + m_cfg->BootFrequency = config->bootfreq; + /* If ISH is enabled, enable ISH elements */ if (!dev) m_cfg->PchIshEnable = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/30445 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6bd5849122c9035bb7f448acf08e258e8c207013 Gerrit-Change-Number: 30445 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/soc/intel/common/block/pcie: Add a workaround for ThP2 9260
by Gaggery Tsai (Code Review) 22 Feb '19

22 Feb '19

Gaggery Tsai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30486 Change subject: src/soc/intel/common/block/pcie: Add a workaround for ThP2 9260 ...................................................................... src/soc/intel/common/block/pcie: Add a workaround for ThP2 9260 This patch adds a workaround for ThP2. The PCIe root port LCTL2.TLS is by default GEN1 and ThP has bad synchronization on polarity inversion. When the root port request for speed change, ThP doesn’t confirm the request, and both sides are moving to polling after timeout, hot reset is issued, and then most of the CFG space is initialized. From the observation, CCC/ECPM/LTR would be reset to default but CCC/ECPM of root port and end devices have been reconfigured in pci_scan. The LTR configuration for root port is still missing. BUG=B:117618636 BRANCH=None TEST=Add THP2_9260_WORKAROUND in Atlas configuration & emerge-atlas coreboot chromeos-bootimage & Warm/cold reset for 10 times and didn't see unsupported request related AER error messages & $lspci -vvs 00:1c.0|grep LTR and ensure LTR+ is present. Change-Id: Id5d2814488fbc9db927edb2ead972b73ebc336ce Signed-off-by: Gaggery Tsai <gaggery.tsai(a)intel.com> --- M src/soc/intel/common/block/pcie/Kconfig M src/soc/intel/common/block/pcie/pcie.c 2 files changed, 29 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/30486/1 diff --git a/src/soc/intel/common/block/pcie/Kconfig b/src/soc/intel/common/block/pcie/Kconfig index aa32324..36915fa 100644 --- a/src/soc/intel/common/block/pcie/Kconfig +++ b/src/soc/intel/common/block/pcie/Kconfig @@ -13,3 +13,8 @@ Enable debug logs in PCIe module. Allows debug information on memory base and limit, prefetchable memory base and limit, prefetchable memory base upper 32 bits and prefetchable memory limit upper 32 bits. + +config THP2_9260_WORKAROUND + bool + help + THP2 workaround diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c index 3ebb4f6..07a2321 100644 --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -28,12 +28,36 @@ /* PCI-E Sub-System ID */ #define PCIE_SUBSYSTEM_VENDOR_ID 0x94 +/* + * Check the LTR for root port and enable it + */ +static void pciexp_enable_root_port_ltr(struct device *root, unsigned root_cap) +{ + u16 root_ltr; + unsigned int val; + + val = pci_read_config16(root, root_cap + PCI_EXP_DEV_CAP2_OFFSET); + + if (val & LTR_MECHANISM_SUPPORT) { + root_ltr = pci_read_config16(root, root_cap + PCI_EXP_DEV_CTL_STS2_CAP_OFFSET); + root_ltr |= LTR_MECHANISM_EN; + pci_write_config16(root, root_cap + PCI_EXP_DEV_CTL_STS2_CAP_OFFSET, root_ltr); + } +} + static void pch_pcie_init(struct device *dev) { u16 reg16; + unsigned int dev_cap; printk(BIOS_DEBUG, "Initializing PCH PCIe bridge.\n"); + if (IS_ENABLED(CONFIG_THP2_9260_WORKAROUND)) { + dev_cap = pci_find_capability(dev, PCI_CAP_ID_PCIE); + if (dev_cap) + pciexp_enable_root_port_ltr(dev, dev_cap); + } + /* Enable SERR */ pci_or_config32(dev, PCI_COMMAND, PCI_COMMAND_SERR); -- To view, visit https://review.coreboot.org/c/coreboot/+/30486 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5d2814488fbc9db927edb2ead972b73ebc336ce Gerrit-Change-Number: 30486 Gerrit-PatchSet: 1 Gerrit-Owner: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: [TEST]sb/intel/common: Remove CAR_GLOBAL use
by Arthur Heymans (Code Review) 20 Feb '19

20 Feb '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30506 Change subject: [TEST]sb/intel/common: Remove CAR_GLOBAL use ...................................................................... [TEST]sb/intel/common: Remove CAR_GLOBAL use We have NO_CAR_GLOBAL_MIGRATION now. (yes?) Change-Id: Ic2c90d264d851ab4abeca07f412d43d088ad96dc Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/common/gpio.c M src/southbridge/intel/common/pmbase.c M src/southbridge/intel/common/spi.c 3 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/30506/1 diff --git a/src/southbridge/intel/common/gpio.c b/src/southbridge/intel/common/gpio.c index 7c8cfe8..140839f 100644 --- a/src/southbridge/intel/common/gpio.c +++ b/src/southbridge/intel/common/gpio.c @@ -40,7 +40,7 @@ /* Don't assume GPIO_BASE is still the same */ return pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffe; #else - static u16 gpiobase CAR_GLOBAL; + static u16 gpiobase; if (gpiobase) return gpiobase; diff --git a/src/southbridge/intel/common/pmbase.c b/src/southbridge/intel/common/pmbase.c index 2de57d6..b022629 100644 --- a/src/southbridge/intel/common/pmbase.c +++ b/src/southbridge/intel/common/pmbase.c @@ -42,7 +42,7 @@ /* Don't assume PMBASE is still the same */ return pci_read_config16(PCH_LPC_DEV, PMBASE) & 0xfffc; #else - static u16 pmbase CAR_GLOBAL; + static u16 pmbase; if (pmbase) return pmbase; diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 3ca0d6c..6ef6769 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -69,7 +69,7 @@ typedef struct spi_slave ich_spi_slave; -static int g_ichspi_lock CAR_GLOBAL = 0; +static int g_ichspi_lock = 0; typedef struct ich7_spi_regs { uint16_t spis; @@ -138,7 +138,7 @@ uint8_t fpr_max; } ich_spi_controller; -static ich_spi_controller g_cntlr CAR_GLOBAL; +static ich_spi_controller g_cntlr; enum { SPIS_SCIP = 0x0001, -- To view, visit https://review.coreboot.org/c/coreboot/+/30506 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic2c90d264d851ab4abeca07f412d43d088ad96dc Gerrit-Change-Number: 30506 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/baytrail: Don't use CAR_GLOBAL
by Arthur Heymans (Code Review) 13 Feb '19

13 Feb '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30511 Change subject: soc/intel/baytrail: Don't use CAR_GLOBAL ...................................................................... soc/intel/baytrail: Don't use CAR_GLOBAL All platforms using this code have NO_CAR_GLOBAL_MIGRATION. Change-Id: I731bc1c9dec6cb5bbb228b7949a73848cb73eee3 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/baytrail/romstage/romstage.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/30511/1 diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 0e1d57e..72ded61 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -134,7 +134,7 @@ return NULL; } -static struct chipset_power_state power_state CAR_GLOBAL; +static struct chipset_power_state power_state; static void migrate_power_state(int is_recovery) { -- To view, visit https://review.coreboot.org/c/coreboot/+/30511 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I731bc1c9dec6cb5bbb228b7949a73848cb73eee3 Gerrit-Change-Number: 30511 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: nb/intel/nehalem: Remove CAR_GLOBAL use
by Arthur Heymans (Code Review) 12 Feb '19

12 Feb '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30505 Change subject: nb/intel/nehalem: Remove CAR_GLOBAL use ...................................................................... nb/intel/nehalem: Remove CAR_GLOBAL use We have NO_CAR_GLOBAL_MIGRATION now. Change-Id: I077f235029e3fe3b1368f028981985895d8b766b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/nehalem/raminit.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/30505/1 diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index 54ef278..3af88bb 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -225,7 +225,7 @@ }; /* Global allocation of timings_car */ -timing_bounds_t timings_car[64] CAR_GLOBAL; +timing_bounds_t timings_car[64]; static void write_500(struct raminfo *info, int channel, u32 val, u16 addr, int bits, -- To view, visit https://review.coreboot.org/c/coreboot/+/30505 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I077f235029e3fe3b1368f028981985895d8b766b Gerrit-Change-Number: 30505 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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