Change in ...coreboot[master]: src/soc/intel/common/block/pcie: Add a workaround for ThP2 9260
Gaggery Tsai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30486
Change subject: src/soc/intel/common/block/pcie: Add a workaround for ThP2 9260 ......................................................................
src/soc/intel/common/block/pcie: Add a workaround for ThP2 9260
This patch adds a workaround for ThP2. The PCIe root port LCTL2.TLS is by default GEN1 and ThP has bad synchronization on polarity inversion. When the root port request for speed change, ThP doesn’t confirm the request, and both sides are moving to polling after timeout, hot reset is issued, and then most of the CFG space is initialized. From the observation, CCC/ECPM/LTR would be reset to default but CCC/ECPM of root port and end devices have been reconfigured in pci_scan. The LTR configuration for root port is still missing.
BUG=B:117618636 BRANCH=None TEST=Add THP2_9260_WORKAROUND in Atlas configuration & emerge-atlas coreboot chromeos-bootimage & Warm/cold reset for 10 times and didn't see unsupported request related AER error messages & $lspci -vvs 00:1c.0|grep LTR and ensure LTR+ is present.
Change-Id: Id5d2814488fbc9db927edb2ead972b73ebc336ce Signed-off-by: Gaggery Tsai gaggery.tsai@intel.com --- M src/soc/intel/common/block/pcie/Kconfig M src/soc/intel/common/block/pcie/pcie.c 2 files changed, 29 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/30486/1
diff --git a/src/soc/intel/common/block/pcie/Kconfig b/src/soc/intel/common/block/pcie/Kconfig index aa32324..36915fa 100644 --- a/src/soc/intel/common/block/pcie/Kconfig +++ b/src/soc/intel/common/block/pcie/Kconfig @@ -13,3 +13,8 @@ Enable debug logs in PCIe module. Allows debug information on memory base and limit, prefetchable memory base and limit, prefetchable memory base upper 32 bits and prefetchable memory limit upper 32 bits. + +config THP2_9260_WORKAROUND + bool + help + THP2 workaround diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c index 3ebb4f6..07a2321 100644 --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -28,12 +28,36 @@ /* PCI-E Sub-System ID */ #define PCIE_SUBSYSTEM_VENDOR_ID 0x94
+/* + * Check the LTR for root port and enable it + */ +static void pciexp_enable_root_port_ltr(struct device *root, unsigned root_cap) +{ + u16 root_ltr; + unsigned int val; + + val = pci_read_config16(root, root_cap + PCI_EXP_DEV_CAP2_OFFSET); + + if (val & LTR_MECHANISM_SUPPORT) { + root_ltr = pci_read_config16(root, root_cap + PCI_EXP_DEV_CTL_STS2_CAP_OFFSET); + root_ltr |= LTR_MECHANISM_EN; + pci_write_config16(root, root_cap + PCI_EXP_DEV_CTL_STS2_CAP_OFFSET, root_ltr); + } +} + static void pch_pcie_init(struct device *dev) { u16 reg16; + unsigned int dev_cap;
printk(BIOS_DEBUG, "Initializing PCH PCIe bridge.\n");
+ if (IS_ENABLED(CONFIG_THP2_9260_WORKAROUND)) { + dev_cap = pci_find_capability(dev, PCI_CAP_ID_PCIE); + if (dev_cap) + pciexp_enable_root_port_ltr(dev, dev_cap); + } + /* Enable SERR */ pci_or_config32(dev, PCI_COMMAND, PCI_COMMAND_SERR);
Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30486 )
Change subject: src/drivers/intel/wifi: Add a W/A for Intel ThP2 9260 ......................................................................
Patch Set 8: Code-Review+2
Duncan Laurie has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30486 )
Change subject: src/drivers/intel/wifi: Add a W/A for Intel ThP2 9260 ......................................................................
src/drivers/intel/wifi: Add a W/A for Intel ThP2 9260
This patch adds a workaround for ThP2. The PCIe root port LCTL2.TLS is by default GEN1 and ThP has bad synchronization on polarity inversion. When the root port request for speed change, ThP doesn’t confirm the request, and both sides are moving to polling after timeout, hot reset is issued, and then most of the CFG space is initialized. From the observation, CCC/ECPM/LTR would be reset to default but CCC/ECPM of root port and end devices have been reconfigured in pci_scan. The LTR configuration for root port is still missing.
BUG=B:117618636 BRANCH=None TEST=Warm/cold reset for 10 times and didn't see unsupported request related AER error messages & $lspci -vvs 00:1c.0|grep LTR and ensure LTR+ is presenti & $iotools pci_read32 0 0x1c 0 0x68 and ensure bit10 is set.
Change-Id: Id5d2814488fbc9db927edb2ead972b73ebc336ce Signed-off-by: Gaggery Tsai gaggery.tsai@intel.com Reviewed-on: https://review.coreboot.org/c/30486 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Patrick Rudolph siro@das-labor.org Reviewed-by: Duncan Laurie dlaurie@chromium.org --- M src/drivers/intel/wifi/wifi.c 1 file changed, 25 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Duncan Laurie: Looks good to me, approved Patrick Rudolph: Looks good to me, but someone else must approve
diff --git a/src/drivers/intel/wifi/wifi.c b/src/drivers/intel/wifi/wifi.c index e197114..01a338d 100644 --- a/src/drivers/intel/wifi/wifi.c +++ b/src/drivers/intel/wifi/wifi.c @@ -255,9 +255,34 @@ } #endif
+static void pci_dev_apply_quirks(struct device *dev) +{ + unsigned int cap; + uint16_t val; + struct device *root = dev->bus->dev; + + switch (dev->device) { + case PCI_DEVICE_ID_TP_9260_SERIES_WIFI: + cap = pci_find_capability(root, PCI_CAP_ID_PCIE); + /* Check the LTR for root port and enable it */ + if (cap) { + val = pci_read_config16(root, cap + + PCI_EXP_DEV_CAP2_OFFSET); + if (val & LTR_MECHANISM_SUPPORT) { + val = pci_read_config16(root, cap + + PCI_EXP_DEV_CTL_STS2_CAP_OFFSET); + val |= LTR_MECHANISM_EN; + pci_write_config16(root, cap + + PCI_EXP_DEV_CTL_STS2_CAP_OFFSET, val); + } + } + } +} + static void wifi_pci_dev_init(struct device *dev) { pci_dev_init(dev); + pci_dev_apply_quirks(dev);
if (IS_ENABLED(CONFIG_ELOG)) { uint32_t val;
Duncan Laurie has created a revert of this change. ( https://review.coreboot.org/c/coreboot/+/30486 )
Change subject: src/drivers/intel/wifi: Add a W/A for Intel ThP2 9260 ......................................................................
-
Duncan Laurie (Code Review) -
Gaggery Tsai (Code Review)