coreboot-gerrit December 2018

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Change in ...coreboot[master]: sb/intel/bd82x6x: Move pcie ACPI code to a common place
by Arthur Heymans (Code Review) 30 Dec '18

30 Dec '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30527 Change subject: sb/intel/bd82x6x: Move pcie ACPI code to a common place ...................................................................... sb/intel/bd82x6x: Move pcie ACPI code to a common place Change-Id: I45144f9c397ff9a0be011990ba33db9ffef351e7 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/bd82x6x/acpi/pch.asl R src/southbridge/intel/common/acpi/pcie.asl R src/southbridge/intel/common/acpi/pcie_port.asl 3 files changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/30527/1 diff --git a/src/southbridge/intel/bd82x6x/acpi/pch.asl b/src/southbridge/intel/bd82x6x/acpi/pch.asl index a068bc0..d3aa7a4 100644 --- a/src/southbridge/intel/bd82x6x/acpi/pch.asl +++ b/src/southbridge/intel/bd82x6x/acpi/pch.asl @@ -238,7 +238,7 @@ #include "audio.asl" // PCI Express Ports 0:1c.x -#include "pcie.asl" +#include <southbridge/intel/common/acpi/pcie.asl> // USB EHCI 0:1d.0 and 0:1a.0, XHCI 0:14.0 #include "usb.asl" diff --git a/src/southbridge/intel/bd82x6x/acpi/pcie.asl b/src/southbridge/intel/common/acpi/pcie.asl similarity index 100% rename from src/southbridge/intel/bd82x6x/acpi/pcie.asl rename to src/southbridge/intel/common/acpi/pcie.asl diff --git a/src/southbridge/intel/bd82x6x/acpi/pcie_port.asl b/src/southbridge/intel/common/acpi/pcie_port.asl similarity index 100% rename from src/southbridge/intel/bd82x6x/acpi/pcie_port.asl rename to src/southbridge/intel/common/acpi/pcie_port.asl -- To view, visit https://review.coreboot.org/c/coreboot/+/30527 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45144f9c397ff9a0be011990ba33db9ffef351e7 Gerrit-Change-Number: 30527 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: cpu/intel/common: improve VMX/lock bit debug output
by Matt DeVillier (Code Review) 30 Dec '18

30 Dec '18

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30524 Change subject: cpu/intel/common: improve VMX/lock bit debug output ...................................................................... cpu/intel/common: improve VMX/lock bit debug output Currently, if the IA32_FEATURE_CONTROL lock bit is already set, VMX status isn't reported. Adjust debug output to provide more useful infomation on both VMX and lock bit statuses. Test: build/boot google/chell, observe useful output in cbmem log regardless of lock bit status. Change-Id: Ie50f214f7e3fcfd6c3d0d2de034a93518c0a6b46 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/cpu/intel/common/common_init.c 1 file changed, 16 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/30524/1 diff --git a/src/cpu/intel/common/common_init.c b/src/cpu/intel/common/common_init.c index 9c0fcbb..486e412 100644 --- a/src/cpu/intel/common/common_init.c +++ b/src/cpu/intel/common/common_init.c @@ -43,27 +43,26 @@ msr = rdmsr(IA32_FEATURE_CONTROL); if (msr.lo & (1 << 0)) { - printk(BIOS_ERR, "IA32_FEATURE_CONTROL is locked, so %s will do nothing\n", - __func__); + printk(BIOS_DEBUG, "IA32_FEATURE_CONTROL already locked; "); /* IA32_FEATURE_CONTROL locked. If we set it again we get an * illegal instruction */ - return; + } else { + + /* IA32_FEATURE_CONTROL MSR may initialize with random values. + * It must be cleared regardless of VMX config setting. + */ + msr.hi = msr.lo = 0; + + if (enable) { + msr.lo |= (1 << 2); + if (feature_flag & CPUID_SMX) + msr.lo |= (1 << 1); + } + + wrmsr(IA32_FEATURE_CONTROL, msr); } - /* The IA32_FEATURE_CONTROL MSR may initialize with random values. - * It must be cleared regardless of VMX config setting. - */ - msr.hi = msr.lo = 0; - - if (enable) { - msr.lo |= (1 << 2); - if (feature_flag & CPUID_SMX) - msr.lo |= (1 << 1); - } - - wrmsr(IA32_FEATURE_CONTROL, msr); - printk(BIOS_DEBUG, "VMX status: %s\n", enable ? "enabled" : "disabled"); } @@ -75,15 +74,10 @@ msr = rdmsr(IA32_FEATURE_CONTROL); if (msr.lo & (1 << 0)) { - printk(BIOS_ERR, "IA32_FEATURE_CONTROL is locked, so %s will do nothing\n", - __func__); /* IA32_FEATURE_CONTROL locked. If we set it again we get an * illegal instruction */ - return; - } - - if (lock) { + } else if (lock) { /* Set lock bit */ msr.lo |= (1 << 0); wrmsr(IA32_FEATURE_CONTROL, msr); -- To view, visit https://review.coreboot.org/c/coreboot/+/30524 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie50f214f7e3fcfd6c3d0d2de034a93518c0a6b46 Gerrit-Change-Number: 30524 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: dell/optiplex_7010: Use a common acpi/cpu.asl file
by Piotr Król (Code Review) 30 Dec '18

30 Dec '18

Piotr Król has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30519 Change subject: dell/optiplex_7010: Use a common acpi/cpu.asl file ...................................................................... dell/optiplex_7010: Use a common acpi/cpu.asl file Signed-off-by: Piotr Król <piotr.krol(a)3mdeb.com> Change-Id: I15517b7a1274f579ccb1b063e31bc14320a4eae3 --- M src/mainboard/dell/optiplex_7010/dsdt.asl 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/30519/1 diff --git a/src/mainboard/dell/optiplex_7010/dsdt.asl b/src/mainboard/dell/optiplex_7010/dsdt.asl index 9b32670..fffe14e 100644 --- a/src/mainboard/dell/optiplex_7010/dsdt.asl +++ b/src/mainboard/dell/optiplex_7010/dsdt.asl @@ -12,7 +12,7 @@ { // Some generic macros #include "acpi/platform.asl" - #include <cpu/intel/model_206ax/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> #include <southbridge/intel/bd82x6x/acpi/platform.asl> /* global NVS and variables. */ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> -- To view, visit https://review.coreboot.org/c/coreboot/+/30519 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15517b7a1274f579ccb1b063e31bc14320a4eae3 Gerrit-Change-Number: 30519 Gerrit-PatchSet: 1 Gerrit-Owner: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/cannonlake: Enable CNVi based on devicetree
by Maulik V Vaghela (Code Review) 29 Dec '18

29 Dec '18

Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30516 Change subject: soc/intel/cannonlake: Enable CNVi based on devicetree ...................................................................... soc/intel/cannonlake: Enable CNVi based on devicetree Set PchCnvimode to Auto if CNVi is enabled in device tree. This will allow FSP to configure CNVi. Change-Id: I4f77fe5e9f561d3b498403e42dfc7afdcfaedf6f Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/soc/intel/cannonlake/fsp_params.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/30516/1 diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 78b27e9..8166dea 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -162,6 +162,10 @@ dev->enabled = 0; params->XdciEnable = dev->enabled; + /* Enable CNVi Wifi if enabled in device tree */ + dev = dev_find_slot(0, PCH_DEVFN_CNViWIFI); + params->PchCnviMode = dev->enabled; + /* PCI Express */ for (i = 0; i < ARRAY_SIZE(config->PcieClkSrcUsage); i++) { if (config->PcieClkSrcUsage[i] == 0) -- To view, visit https://review.coreboot.org/c/coreboot/+/30516 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f77fe5e9f561d3b498403e42dfc7afdcfaedf6f Gerrit-Change-Number: 30516 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: [TEST]ec/google/chromeec/ec.c: Don't use CAR_GLOBAL
by Arthur Heymans (Code Review) 29 Dec '18

29 Dec '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30508 Change subject: [TEST]ec/google/chromeec/ec.c: Don't use CAR_GLOBAL ...................................................................... [TEST]ec/google/chromeec/ec.c: Don't use CAR_GLOBAL All platforms using this code have NO_CAR_GLOBAL_MIGRATION. Change-Id: Id63ff0f9cfbf29f23cb26d3731a286f58b9aa8d6 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/ec/google/chromeec/ec.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/30508/1 diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index d2a0849..a440e12 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -232,7 +232,7 @@ #define UHEPI_SUPPORTED 1 #define UHEPI_NOT_SUPPORTED 2 - static int uhepi_support CAR_GLOBAL; + static int uhepi_support; if (!uhepi_support) { uhepi_support = google_chromeec_check_feature -- To view, visit https://review.coreboot.org/c/coreboot/+/30508 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id63ff0f9cfbf29f23cb26d3731a286f58b9aa8d6 Gerrit-Change-Number: 30508 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: drivers/aspeed: Fix AST2400 POST failure without BMC FW or VBIOS
by Tristan Corrick (Code Review) 29 Dec '18

29 Dec '18

Tristan Corrick has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30507 Change subject: drivers/aspeed: Fix AST2400 POST failure without BMC FW or VBIOS ...................................................................... drivers/aspeed: Fix AST2400 POST failure without BMC FW or VBIOS This patch is from Linux, commit 3856081eede2. The commit message there is: > commit 3856081eede297b617560b85e948cfb00bb395ec > Author: Y.C. Chen <yc_chen(a)aspeedtech.com> > Date: Thu Feb 23 15:52:33 2017 +0800 > > drm/ast: Fix AST2400 POST failure without BMC FW or VBIOS > > The current POST code for the AST2300/2400 family doesn't work properly > if the chip hasn't been initialized previously by either the BMC own FW > or the VBIOS. This fixes it. > > Signed-off-by: Y.C. Chen <yc_chen(a)aspeedtech.com> > Signed-off-by: Benjamin Herrenschmidt <benh(a)kernel.crashing.org> > Tested-by: Y.C. Chen <yc_chen(a)aspeedtech.com> > Acked-by: Joel Stanley <joel(a)jms.id.au> > Cc: <stable(a)vger.kernel.org> > Signed-off-by: Dave Airlie <airlied(a)redhat.com> Tested on a Supermicro X10SLM+-F with an AST 2400 where the BMC flash chip has been completely erased. Before the patch, the display resembled a rainbow. After the patch, the display works well. Original-Signed-off-by: Y.C. Chen <yc_chen(a)aspeedtech.com> Original-Signed-off-by: Benjamin Herrenschmidt <benh(a)kernel.crashing.org> Original-Tested-by: Y.C. Chen <yc_chen(a)aspeedtech.com> Original-Signed-off-by: Dave Airlie <airlied(a)redhat.com> Change-Id: I72efcf907fbd1263fe21d4f36fe900b305419c44 Signed-off-by: Tristan Corrick <tristan(a)corrick.kiwi> --- M src/drivers/aspeed/common/ast_post.c 1 file changed, 35 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/30507/1 diff --git a/src/drivers/aspeed/common/ast_post.c b/src/drivers/aspeed/common/ast_post.c index 8f0d998..6e646a6 100644 --- a/src/drivers/aspeed/common/ast_post.c +++ b/src/drivers/aspeed/common/ast_post.c @@ -1693,12 +1693,44 @@ temp |= 0x73; ast_write32(ast, 0x12008, temp); + param.dram_freq = 396; param.dram_type = AST_DDR3; + temp = ast_mindwm(ast, 0x1e6e2070); if (temp & 0x01000000) param.dram_type = AST_DDR2; - param.dram_chipid = ast->dram_type; - param.dram_freq = ast->mclk; - param.vram_size = ast->vram_size; + switch (temp & 0x18000000) { + case 0: + param.dram_chipid = AST_DRAM_512Mx16; + break; + default: + case 0x08000000: + param.dram_chipid = AST_DRAM_1Gx16; + break; + case 0x10000000: + param.dram_chipid = AST_DRAM_2Gx16; + break; + case 0x18000000: + param.dram_chipid = AST_DRAM_4Gx16; + break; + } + switch (temp & 0x0c) { + default: + case 0x00: + param.vram_size = AST_VIDMEM_SIZE_8M; + break; + + case 0x04: + param.vram_size = AST_VIDMEM_SIZE_16M; + break; + + case 0x08: + param.vram_size = AST_VIDMEM_SIZE_32M; + break; + + case 0x0c: + param.vram_size = AST_VIDMEM_SIZE_64M; + break; + } if (param.dram_type == AST_DDR3) { get_ddr3_info(ast, &param); -- To view, visit https://review.coreboot.org/c/coreboot/+/30507 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72efcf907fbd1263fe21d4f36fe900b305419c44 Gerrit-Change-Number: 30507 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/asrock/h81m-hds: Move GPIO header to a linked C file
by Tristan Corrick (Code Review) 29 Dec '18

29 Dec '18

Tristan Corrick has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30503 Change subject: mb/asrock/h81m-hds: Move GPIO header to a linked C file ...................................................................... mb/asrock/h81m-hds: Move GPIO header to a linked C file Change-Id: I6a5ca65bc1553bd382589d67379eafd03dc0b0a3 Signed-off-by: Tristan Corrick <tristan(a)corrick.kiwi> --- M src/mainboard/asrock/h81m-hds/Makefile.inc R src/mainboard/asrock/h81m-hds/gpio.c M src/mainboard/asrock/h81m-hds/romstage.c 3 files changed, 2 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/30503/1 diff --git a/src/mainboard/asrock/h81m-hds/Makefile.inc b/src/mainboard/asrock/h81m-hds/Makefile.inc index 94bd1cfe..7c1bf9e 100644 --- a/src/mainboard/asrock/h81m-hds/Makefile.inc +++ b/src/mainboard/asrock/h81m-hds/Makefile.inc @@ -14,4 +14,5 @@ ## GNU General Public License for more details. ## +romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asrock/h81m-hds/gpio.h b/src/mainboard/asrock/h81m-hds/gpio.c similarity index 97% rename from src/mainboard/asrock/h81m-hds/gpio.h rename to src/mainboard/asrock/h81m-hds/gpio.c index dde3e53..a03a52e 100644 --- a/src/mainboard/asrock/h81m-hds/gpio.h +++ b/src/mainboard/asrock/h81m-hds/gpio.c @@ -14,9 +14,6 @@ * GNU General Public License for more details. */ -#ifndef ASROCK_H81M_HDS_GPIO_H -#define ASROCK_H81M_HDS_GPIO_H - #include <southbridge/intel/common/gpio.h> static const struct pch_gpio_set1 pch_gpio_set1_mode = { @@ -164,5 +161,3 @@ .reset = &pch_gpio_set3_reset, }, }; - -#endif /* ASROCK_H81M_HDS_GPIO_H */ diff --git a/src/mainboard/asrock/h81m-hds/romstage.c b/src/mainboard/asrock/h81m-hds/romstage.c index f3c2b3b..c6bef9f 100644 --- a/src/mainboard/asrock/h81m-hds/romstage.c +++ b/src/mainboard/asrock/h81m-hds/romstage.c @@ -20,10 +20,10 @@ #include <cpu/intel/haswell/haswell.h> #include <northbridge/intel/haswell/haswell.h> #include <northbridge/intel/haswell/pei_data.h> +#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/lynxpoint/pch.h> #include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/nct6776/nct6776.h> -#include "gpio.h" static const struct rcba_config_instruction rcba_config[] = { RCBA_SET_REG_16(D31IR, DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQA)), -- To view, visit https://review.coreboot.org/c/coreboot/+/30503 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6a5ca65bc1553bd382589d67379eafd03dc0b0a3 Gerrit-Change-Number: 30503 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/slippy: Add a VBT for all variants
by Arthur Heymans (Code Review) 28 Dec '18

28 Dec '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30487 Change subject: mb/google/slippy: Add a VBT for all variants ...................................................................... mb/google/slippy: Add a VBT for all variants The vbt.bin is the same across all variants. Change-Id: I82c72c561e1058e0b77d80baf330b64f7c6b08e3 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/google/slippy/Kconfig A src/mainboard/google/slippy/data.vbt 2 files changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/30487/1 diff --git a/src/mainboard/google/slippy/Kconfig b/src/mainboard/google/slippy/Kconfig index 9d206dc..ecc8aff 100644 --- a/src/mainboard/google/slippy/Kconfig +++ b/src/mainboard/google/slippy/Kconfig @@ -15,6 +15,7 @@ select MAINBOARD_HAS_TPM1 select INTEL_INT15 select MAINBOARD_HAS_LIBGFXINIT + select INTEL_GMA_HAVE_VBT if BOARD_GOOGLE_BASEBOARD_SLIPPY @@ -65,4 +66,10 @@ string default "pci8086,0406.rom" +# Override the default variant behavior, since the data.vbt is the same +# for all variants. +config INTEL_GMA_VBT_FILE + default "src/mainboard/$(MAINBOARDDIR)/data.vbt" + + endif # BOARD_GOOGLE_BASEBOARD_SLIPPY diff --git a/src/mainboard/google/slippy/data.vbt b/src/mainboard/google/slippy/data.vbt new file mode 100644 index 0000000..915b152 --- /dev/null +++ b/src/mainboard/google/slippy/data.vbt Binary files differ -- To view, visit https://review.coreboot.org/c/coreboot/+/30487 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82c72c561e1058e0b77d80baf330b64f7c6b08e3 Gerrit-Change-Number: 30487 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/mainboard: Use smm-$(CONFIG_HAVE_SMI_HANDLER)
by HAOUAS Elyes (Code Review) 28 Dec '18

28 Dec '18

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30485 Change subject: src/mainboard: Use smm-$(CONFIG_HAVE_SMI_HANDLER) ...................................................................... src/mainboard: Use smm-$(CONFIG_HAVE_SMI_HANDLER) Use smm-$(CONFIG_HAVE_SMI_HANDLER) instead of smm-y Change-Id: I0f91bc3e6c8ab31d837ab89af62d700b35c1e01b Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/google/octopus/variants/ampton/Makefile.inc M src/mainboard/google/octopus/variants/baseboard/Makefile.inc M src/mainboard/google/octopus/variants/bip/Makefile.inc M src/mainboard/google/poppy/variants/nocturne/Makefile.inc M src/mainboard/google/reef/variants/baseboard/Makefile.inc M src/mainboard/google/reef/variants/coral/Makefile.inc M src/mainboard/hp/pavilion_m6_1035dx/Makefile.inc M src/mainboard/intel/dcp847ske/Makefile.inc M src/mainboard/intel/glkrvp/variants/baseboard/Makefile.inc M src/mainboard/lenovo/g505s/Makefile.inc M src/mainboard/lenovo/l520/Makefile.inc M src/mainboard/lenovo/s230u/Makefile.inc M src/mainboard/lenovo/t430/Makefile.inc 13 files changed, 13 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/30485/1 diff --git a/src/mainboard/google/octopus/variants/ampton/Makefile.inc b/src/mainboard/google/octopus/variants/ampton/Makefile.inc index 7c092e4..dc9e435 100644 --- a/src/mainboard/google/octopus/variants/ampton/Makefile.inc +++ b/src/mainboard/google/octopus/variants/ampton/Makefile.inc @@ -2,4 +2,4 @@ ramstage-y += gpio.c -smm-y += gpio.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += gpio.c diff --git a/src/mainboard/google/octopus/variants/baseboard/Makefile.inc b/src/mainboard/google/octopus/variants/baseboard/Makefile.inc index 63b03a6..bad4f10 100644 --- a/src/mainboard/google/octopus/variants/baseboard/Makefile.inc +++ b/src/mainboard/google/octopus/variants/baseboard/Makefile.inc @@ -5,4 +5,4 @@ ramstage-y += gpio.c ramstage-y += nhlt.c -smm-y += gpio.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += gpio.c diff --git a/src/mainboard/google/octopus/variants/bip/Makefile.inc b/src/mainboard/google/octopus/variants/bip/Makefile.inc index 7c092e4..dc9e435 100644 --- a/src/mainboard/google/octopus/variants/bip/Makefile.inc +++ b/src/mainboard/google/octopus/variants/bip/Makefile.inc @@ -2,4 +2,4 @@ ramstage-y += gpio.c -smm-y += gpio.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += gpio.c diff --git a/src/mainboard/google/poppy/variants/nocturne/Makefile.inc b/src/mainboard/google/poppy/variants/nocturne/Makefile.inc index e558cfc..4d5397f 100644 --- a/src/mainboard/google/poppy/variants/nocturne/Makefile.inc +++ b/src/mainboard/google/poppy/variants/nocturne/Makefile.inc @@ -21,5 +21,5 @@ ramstage-y += nhlt.c ramstage-y += mainboard.c -smm-y += ec.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += ec.c ramstage-y += ec.c diff --git a/src/mainboard/google/reef/variants/baseboard/Makefile.inc b/src/mainboard/google/reef/variants/baseboard/Makefile.inc index 63b03a6..bad4f10 100644 --- a/src/mainboard/google/reef/variants/baseboard/Makefile.inc +++ b/src/mainboard/google/reef/variants/baseboard/Makefile.inc @@ -5,4 +5,4 @@ ramstage-y += gpio.c ramstage-y += nhlt.c -smm-y += gpio.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += gpio.c diff --git a/src/mainboard/google/reef/variants/coral/Makefile.inc b/src/mainboard/google/reef/variants/coral/Makefile.inc index e52d959..814590f 100644 --- a/src/mainboard/google/reef/variants/coral/Makefile.inc +++ b/src/mainboard/google/reef/variants/coral/Makefile.inc @@ -3,4 +3,4 @@ ramstage-y += mainboard.c ramstage-y += gpio.c -smm-y += gpio.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += gpio.c diff --git a/src/mainboard/hp/pavilion_m6_1035dx/Makefile.inc b/src/mainboard/hp/pavilion_m6_1035dx/Makefile.inc index f030989..80dd0d2 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/Makefile.inc +++ b/src/mainboard/hp/pavilion_m6_1035dx/Makefile.inc @@ -22,4 +22,4 @@ ramstage-y += OemCustomize.c ramstage-y += ec.c -smm-y += mainboard_smi.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c diff --git a/src/mainboard/intel/dcp847ske/Makefile.inc b/src/mainboard/intel/dcp847ske/Makefile.inc index 96bac06..4d516f6 100644 --- a/src/mainboard/intel/dcp847ske/Makefile.inc +++ b/src/mainboard/intel/dcp847ske/Makefile.inc @@ -1,4 +1,4 @@ romstage-y += early_southbridge.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads -smm-y += smihandler.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/Makefile.inc b/src/mainboard/intel/glkrvp/variants/baseboard/Makefile.inc index d2d344c..99c5e52 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/Makefile.inc +++ b/src/mainboard/intel/glkrvp/variants/baseboard/Makefile.inc @@ -7,4 +7,4 @@ ramstage-y += gpio.c ramstage-y += nhlt.c -smm-y += gpio.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += gpio.c diff --git a/src/mainboard/lenovo/g505s/Makefile.inc b/src/mainboard/lenovo/g505s/Makefile.inc index f030989..80dd0d2 100644 --- a/src/mainboard/lenovo/g505s/Makefile.inc +++ b/src/mainboard/lenovo/g505s/Makefile.inc @@ -22,4 +22,4 @@ ramstage-y += OemCustomize.c ramstage-y += ec.c -smm-y += mainboard_smi.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c diff --git a/src/mainboard/lenovo/l520/Makefile.inc b/src/mainboard/lenovo/l520/Makefile.inc index 5331f25..3afb227 100644 --- a/src/mainboard/lenovo/l520/Makefile.inc +++ b/src/mainboard/lenovo/l520/Makefile.inc @@ -15,4 +15,4 @@ romstage-y += romstage.c romstage-y += gpio.c -smm-y += smihandler.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c diff --git a/src/mainboard/lenovo/s230u/Makefile.inc b/src/mainboard/lenovo/s230u/Makefile.inc index 226eca8..39142ed 100644 --- a/src/mainboard/lenovo/s230u/Makefile.inc +++ b/src/mainboard/lenovo/s230u/Makefile.inc @@ -1,6 +1,6 @@ romstage-y += gpio.c ramstage-y += ec.c -smm-y += smihandler.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c # FIXME: SPD images for samsung_8gb and hynix_8gb are missing. # It's possible that no mainboards with that variation were manufactured. diff --git a/src/mainboard/lenovo/t430/Makefile.inc b/src/mainboard/lenovo/t430/Makefile.inc index 558ab0a..ada25f7 100644 --- a/src/mainboard/lenovo/t430/Makefile.inc +++ b/src/mainboard/lenovo/t430/Makefile.inc @@ -1,5 +1,5 @@ romstage-y += romstage.c romstage-y += gpio.c -smm-y += smihandler.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads -- To view, visit https://review.coreboot.org/c/coreboot/+/30485 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f91bc3e6c8ab31d837ab89af62d700b35c1e01b Gerrit-Change-Number: 30485 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/intel/wtm2: Remove duplicated HAVE_SMI_HANDLER
by HAOUAS Elyes (Code Review) 28 Dec '18

28 Dec '18

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30484 Change subject: mb/intel/wtm2: Remove duplicated HAVE_SMI_HANDLER ...................................................................... mb/intel/wtm2: Remove duplicated HAVE_SMI_HANDLER HAVE_SMI_HANDLER already selected in broadwell/Kconfig file. Change-Id: Ic40b5296eae78cd83c59212042d94424251524b1 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/intel/wtm2/Kconfig 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/30484/1 diff --git a/src/mainboard/intel/wtm2/Kconfig b/src/mainboard/intel/wtm2/Kconfig index cbc560e..27545fe 100644 --- a/src/mainboard/intel/wtm2/Kconfig +++ b/src/mainboard/intel/wtm2/Kconfig @@ -7,7 +7,6 @@ select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME - select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LPC_TPM select INTEL_INT15 -- To view, visit https://review.coreboot.org/c/coreboot/+/30484 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic40b5296eae78cd83c59212042d94424251524b1 Gerrit-Change-Number: 30484 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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