coreboot-gerrit December 2018

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Change in ...coreboot[master]: soc/intel/cannonlake: [TEST ONLY] Use UART IO interface
by Aamir Bohra (Code Review) 28 Dec '18

28 Dec '18

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30464 Change subject: soc/intel/cannonlake: [TEST ONLY] Use UART IO interface ...................................................................... soc/intel/cannonlake: [TEST ONLY] Use UART IO interface *** DO NOT MERGE **** Change-Id: Ic163f2d9fffc7483e0dd1a8b377116ef3bba3492 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/soc/intel/cannonlake/Kconfig 1 file changed, 4 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/30464/1 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 9e007b6..a529af7 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -83,12 +83,13 @@ select CONSOLE_SERIAL select BOOTBLOCK_CONSOLE select DRIVERS_UART - select DRIVERS_UART_8250MEM_32 - select NO_UART_ON_SUPERIO +# select DRIVERS_UART_8250MEM_32 +# select NO_UART_ON_SUPERIO + select DRIVERS_UART_8250IO config UART_FOR_CONSOLE int "Index for LPSS UART port to use for console" - default 2 if DRIVERS_UART_8250MEM_32 + default 2 if !DRIVERS_UART_8250MEM_32 default 0 help Index for LPSS UART port to use for console: -- To view, visit https://review.coreboot.org/c/coreboot/+/30464 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic163f2d9fffc7483e0dd1a8b377116ef3bba3492 Gerrit-Change-Number: 30464 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/cannonlake: Add cannonlake ACPI GPIO op
by Lijian Zhao (Code Review) 28 Dec '18

28 Dec '18

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30461 Change subject: soc/intel/cannonlake: Add cannonlake ACPI GPIO op ...................................................................... soc/intel/cannonlake: Add cannonlake ACPI GPIO op Follow instrcution from https://doc.coreboot.org/acpi/gpio.html to implenet GPIO toggling method, covered for both CNP_LP and CNP_H pch. BUG=N/A TEST=Build and boot up fine on sarien platform. Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> Change-Id: I006a6a8fc580c73ac0938968397a628a4ffe504f --- M src/soc/intel/cannonlake/acpi.c M src/soc/intel/cannonlake/acpi/gpio.asl M src/soc/intel/cannonlake/acpi/gpio_cnp_h.asl 3 files changed, 131 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/30461/1 diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index 84dfdad..b4840fa 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -3,7 +3,7 @@ * * Copyright (C) 2009 coresystems GmbH * Copyright (C) 2014 Google Inc. - * Copyright (C) 2017 Intel Corporation. + * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -248,3 +248,40 @@ { return MP_IRQ_POLARITY_HIGH; } + +static int acpigen_soc_gpio_op(const char *op, unsigned int gpio_num) +{ + /* op (gpio_num) */ + acpigen_emit_namestring(op); + acpigen_write_integer(gpio_num); + return 0; +} + +static int acpigen_soc_get_gpio_state(const char *op, unsigned int gpio_num) +{ + /* Store (op (gpio_num), Local0) */ + acpigen_write_store(); + acpigen_soc_gpio_op(op, gpio_num); + acpigen_emit_byte(LOCAL0_OP); + return 0; +} + +int acpigen_soc_read_rx_gpio(unsigned int gpio_num) +{ + return acpigen_soc_get_gpio_state("\\_SB.PCI0.GRXS", gpio_num); +} + +int acpigen_soc_get_tx_gpio(unsigned int gpio_num) +{ + return acpigen_soc_get_gpio_state("\\_SB.PCI0.GTXS", gpio_num); +} + +int acpigen_soc_set_tx_gpio(unsigned int gpio_num) +{ + return acpigen_soc_gpio_op("\\_SB.PCI0.STXS", gpio_num); +} + +int acpigen_soc_clear_tx_gpio(unsigned int gpio_num) +{ + return acpigen_soc_gpio_op("\\_SB.PCI0.CTXS", gpio_num); +} diff --git a/src/soc/intel/cannonlake/acpi/gpio.asl b/src/soc/intel/cannonlake/acpi/gpio.asl index e05cb68..82cfc34 100644 --- a/src/soc/intel/cannonlake/acpi/gpio.asl +++ b/src/soc/intel/cannonlake/acpi/gpio.asl @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. + * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,6 +17,8 @@ #include <soc/irq.h> #include <soc/pcr_ids.h> +#define GPIOTXSTATE_MASK 0x1 +#define GPIORXSTATE_MASK 0x1 Device (GPIO) { @@ -123,3 +125,47 @@ Return (Local0) } + +/* + * Get GPIO Tx Value + * Arg0 - GPIO Number + */ +Method (GTXS, 1, Serialized) +{ + OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) + Field (PREG, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + And (GPIOTXSTATE_MASK, VAL0, Local0) + + Return (Local0) +} + +/* + * Set GPIO Tx Value + * Arg0 - GPIO Number + */ +Method (STXS, 1, Serialized) +{ + OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) + Field (PREG, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + Or (GPIOTXSTATE_MASK, VAL0, VAL0) +} + +/* + * Clear GPIO Tx Value + * Arg0 - GPIO Number + */ +Method (CTXS, 1, Serialized) +{ + OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) + Field (PREG, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + And (Not (GPIOTXSTATE_MASK), VAL0, VAL0) +} diff --git a/src/soc/intel/cannonlake/acpi/gpio_cnp_h.asl b/src/soc/intel/cannonlake/acpi/gpio_cnp_h.asl index e872b09..8b31b26 100644 --- a/src/soc/intel/cannonlake/acpi/gpio_cnp_h.asl +++ b/src/soc/intel/cannonlake/acpi/gpio_cnp_h.asl @@ -16,6 +16,8 @@ #include <soc/irq.h> #include <soc/pcr_ids.h> +#define GPIOTXSTATE_MASK 0x1 +#define GPIORXSTATE_MASK 0x1 Device (GPIO) { @@ -123,3 +125,47 @@ Return (Local0) } + +/* + * Get GPIO Tx Value + * Arg0 - GPIO Number + */ +Method (GTXS, 1, Serialized) +{ + OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) + Field (PREG, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + And (GPIOTXSTATE_MASK, VAL0, Local0) + + Return (Local0) +} + +/* + * Set GPIO Tx Value + * Arg0 - GPIO Number + */ +Method (STXS, 1, Serialized) +{ + OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) + Field (PREG, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + Or (GPIOTXSTATE_MASK, VAL0, VAL0) +} + +/* + * Clear GPIO Tx Value + * Arg0 - GPIO Number + */ +Method (CTXS, 1, Serialized) +{ + OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) + Field (PREG, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + And (Not (GPIOTXSTATE_MASK), VAL0, VAL0) +} -- To view, visit https://review.coreboot.org/c/coreboot/+/30461 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I006a6a8fc580c73ac0938968397a628a4ffe504f Gerrit-Change-Number: 30461 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/glados/variants/caroline/devicetree.cb: Remove unneeded whi...
by HAOUAS Elyes (Code Review) 27 Dec '18

27 Dec '18

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30460 Change subject: mb/google/glados/variants/caroline/devicetree.cb: Remove unneeded white spaces ...................................................................... mb/google/glados/variants/caroline/devicetree.cb: Remove unneeded white spaces Change-Id: I7fdf8934187d2786fdac23ed4460147867c25044 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/google/glados/variants/caroline/devicetree.cb 1 file changed, 7 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/30460/1 diff --git a/src/mainboard/google/glados/variants/caroline/devicetree.cb b/src/mainboard/google/glados/variants/caroline/devicetree.cb index 0c3c861..8caf8fd 100644 --- a/src/mainboard/google/glados/variants/caroline/devicetree.cb +++ b/src/mainboard/google/glados/variants/caroline/devicetree.cb @@ -153,16 +153,16 @@ register "PcieRpClkReqNumber[0]" = "1" register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-C Port (main) - register "usb2_ports[1]" = "USB2_PORT_MAX(OC_SKIP)" # Type-C Port (sub) - register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth - register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Empty - register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera - register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Empty + register "usb2_ports[1]" = "USB2_PORT_MAX(OC_SKIP)" # Type-C Port (sub) + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Empty + register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera + register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Empty register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port (main) register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port (sub) - register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Empty - register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Empty + register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Empty + register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Empty # Must leave UART0 enabled or SD/eMMC will not work as PCI register "SerialIoDevMode" = "{ -- To view, visit https://review.coreboot.org/c/coreboot/+/30460 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7fdf8934187d2786fdac23ed4460147867c25044 Gerrit-Change-Number: 30460 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: superio/smsc/sch5147/acpi/superio.asl: Remove unneeded white space
by HAOUAS Elyes (Code Review) 27 Dec '18

27 Dec '18

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30458 Change subject: superio/smsc/sch5147/acpi/superio.asl: Remove unneeded white space ...................................................................... superio/smsc/sch5147/acpi/superio.asl: Remove unneeded white space Change-Id: I8a5d937bfc1e0ff61736c19a24b03c1a8defc427 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/superio/smsc/sch5147/acpi/superio.asl 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/30458/1 diff --git a/src/superio/smsc/sch5147/acpi/superio.asl b/src/superio/smsc/sch5147/acpi/superio.asl index d1caff1..209dca1 100644 --- a/src/superio/smsc/sch5147/acpi/superio.asl +++ b/src/superio/smsc/sch5147/acpi/superio.asl @@ -122,7 +122,7 @@ #ifdef SCH5147_SHOW_KBC /* we can't read back the IO resources so hardcode them */ - #define SUPERIO_KBC_LDN 7 + #define SUPERIO_KBC_LDN 7 Device (SUPERIO_ID(KBD, SUPERIO_KBC_LDN)) { Name (_HID, EisaId ("PNP0303")) Name (_UID, SUPERIO_UID(KBD, SUPERIO_KBC_LDN)) -- To view, visit https://review.coreboot.org/c/coreboot/+/30458 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8a5d937bfc1e0ff61736c19a24b03c1a8defc427 Gerrit-Change-Number: 30458 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/hatch: Add the USB port configuration
by V Sowmya (Code Review) 27 Dec '18

27 Dec '18

V Sowmya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30457 Change subject: mb/google/hatch: Add the USB port configuration ...................................................................... mb/google/hatch: Add the USB port configuration This patch adds the configurations for, * USB 2.0 ports * USB 3.0 ports * Enables USB xHCI controller * GPIO config for USB2_OC2 and USB2_OC3 Change-Id: Ia7b25c25b8208c678aeae3a32033611b69b54062 Signed-off-by: V Sowmya <v.sowmya(a)intel.com> --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/hatch/variants/baseboard/gpio.c 2 files changed, 22 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/30457/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 1600be9..352f8ea 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -49,6 +49,23 @@ register "SataPortsDevSlp[1]" = "1" register "satapwroptimize" = "1" + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 0 + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 1 + register "usb2_ports[2]" = "USB2_PORT_LONG(OC3)" # Type-A Port 0 + register "usb2_ports[3]" = "USB2_PORT_LONG(OC3)" # Type-A Port 1 + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # WLAN and BT + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # WWAN + register "usb2_ports[6]" = "USB2_PORT_LONG(OC_SKIP)" # Camera + register "usb2_ports[7]" = "USB2_PORT_EMPTY" + register "usb2_ports[8]" = "USB2_PORT_EMPTY" + register "usb2_ports[9]" = "USB2_PORT_EMPTY" + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 0 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 1 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port 0 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port 1 + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN + register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Enable Root port 9(x4) for NVMe. # Enable CLKREQ# @@ -58,9 +75,6 @@ # ClkReq-to-ClkSrc mapping for CLK SRC 1 register "PcieClkSrcClkReq[1]" = "1" - # USB PORT 5 for BT and WLAN - register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" - # PCIe port 13 for M.2 E-key WLAN register "PcieRpEnable[13]" = "1" register "PcieClkSrcUsage[3]" = "9" @@ -73,7 +87,7 @@ device pci 12.0 off end # Thermal Subsystem device pci 12.5 off end # UFS SCS device pci 12.6 off end # GSPI #2 - device pci 14.0 off end # USB xHCI + device pci 14.0 on end # USB xHCI TODO: Configure ACPI entries device pci 14.1 off end # USB xDCI (OTG) chip drivers/intel/wifi register "wake" = "GPE0_PME_B0" diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index 728fe11..5daaad4 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -68,6 +68,10 @@ PAD_CFG_GPO(GPP_E4, 1, DEEP), /* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), + /* USB_C_OC_OD USB_OC2*/ + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), + /* USB_A_OC_OD USB_OC3*/ + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* USB_C0_DP_HPD */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDI2_HPD_ODL */ -- To view, visit https://review.coreboot.org/c/coreboot/+/30457 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia7b25c25b8208c678aeae3a32033611b69b54062 Gerrit-Change-Number: 30457 Gerrit-PatchSet: 1 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Doc/nb/intel/haswell: Add a list of known issues
by Tristan Corrick (Code Review) 27 Dec '18

27 Dec '18

Tristan Corrick has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30455 Change subject: Doc/nb/intel/haswell: Add a list of known issues ...................................................................... Doc/nb/intel/haswell: Add a list of known issues Change-Id: If0339831550f6c70e8056f78633e9a402f35a793 Signed-off-by: Tristan Corrick <tristan(a)corrick.kiwi> --- M Documentation/mainboard/asrock/h81m-hds.md M Documentation/northbridge/intel/haswell/index.md A Documentation/northbridge/intel/haswell/known-issues.md 3 files changed, 36 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/30455/1 diff --git a/Documentation/mainboard/asrock/h81m-hds.md b/Documentation/mainboard/asrock/h81m-hds.md index 460af8f..5e80f2b 100644 --- a/Documentation/mainboard/asrock/h81m-hds.md +++ b/Documentation/mainboard/asrock/h81m-hds.md @@ -78,6 +78,10 @@ in coreboot. The `coretemp` driver can still be used for accurate CPU temperature readings from an OS. +```eval_rst +Please also see :doc:`../../northbridge/intel/haswell/known-issues`. +``` + ## Untested - parallel port diff --git a/Documentation/northbridge/intel/haswell/index.md b/Documentation/northbridge/intel/haswell/index.md index 3eb8059..87fb56f 100644 --- a/Documentation/northbridge/intel/haswell/index.md +++ b/Documentation/northbridge/intel/haswell/index.md @@ -6,3 +6,7 @@ ## Proprietary blobs - [mrc.bin](mrc.bin.md) + +## Issues + +- [Known issues](known-issues.md) diff --git a/Documentation/northbridge/intel/haswell/known-issues.md b/Documentation/northbridge/intel/haswell/known-issues.md new file mode 100644 index 0000000..d257265 --- /dev/null +++ b/Documentation/northbridge/intel/haswell/known-issues.md @@ -0,0 +1,28 @@ +# Known issues with Haswell + +These issues are specific to the Haswell architecture. For a given +mainboard, there might be additional issues to those listed here. + +## PCIe graphics + +```eval_rst +Using a PCIe graphics card for display output is not currently +supported. This is because :doc:`./mrc.bin` requires workarounds to +have such a feature working correctly. +``` + +However, there is a [patch on Gerrit][hsw-gfx-gerrit] that allows PCIe +graphics to be used for display output. This patch is not guaranteed to +be of the same level of quality as code committed to coreboot. + +Still, in some cases, a PCIe graphics card can be used for rendering, +while the integrated graphics device is used for display output. This +can be achieved under GNU/Linux by using [PRIME GPU offloading][PRIME]. + +## PCIe 3.0 + +Only PCIe 2.0 has been tested so far. PCIe 3.0 could potentially have +stability issues. + +[PRIME]: https://wiki.archlinux.org/index.php/PRIME +[hsw-gfx-gerrit]: https://review.coreboot.org/q/topic:%22haswell-graphics%22+(status:open%20O… -- To view, visit https://review.coreboot.org/c/coreboot/+/30455 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If0339831550f6c70e8056f78633e9a402f35a793 Gerrit-Change-Number: 30455 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: intel/fsp1_0/cache_as_ram.inc: Use tabs instead of white spaces
by HAOUAS Elyes (Code Review) 27 Dec '18

27 Dec '18

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30454 Change subject: intel/fsp1_0/cache_as_ram.inc: Use tabs instead of white spaces ...................................................................... intel/fsp1_0/cache_as_ram.inc: Use tabs instead of white spaces Change-Id: I93cf734daefabe1f7cfaa5f49ba789ac04c8a635 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/drivers/intel/fsp1_0/cache_as_ram.inc 1 file changed, 43 insertions(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/30454/1 diff --git a/src/drivers/intel/fsp1_0/cache_as_ram.inc b/src/drivers/intel/fsp1_0/cache_as_ram.inc index d08f582..8ac3595 100644 --- a/src/drivers/intel/fsp1_0/cache_as_ram.inc +++ b/src/drivers/intel/fsp1_0/cache_as_ram.inc @@ -19,10 +19,10 @@ #include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> - cmp $0, %eax - je cache_as_ram - mov $0xa0, %eax - jmp .Lhlt + cmp $0, %eax + je cache_as_ram + mov $0xa0, %eax + jmp .Lhlt cache_as_ram: post_code(0x20) @@ -31,75 +31,75 @@ * Find the FSP binary in cbfs. * Make a fake stack that has the return value back to this code. */ - lea fake_fsp_stack, %esp - jmp find_fsp_bypass_prologue + lea fake_fsp_stack, %esp + jmp find_fsp_bypass_prologue find_fsp_ret: /* Save the FSP location */ - mov %eax, %ebp - cmp $CONFIG_FSP_LOC, %eax - jae find_fsp_ok - mov $0xb0, %eax - jmp .Lhlt + mov %eax, %ebp + cmp $CONFIG_FSP_LOC, %eax + jae find_fsp_ok + mov $0xb0, %eax + jmp .Lhlt find_fsp_ok: post_code(POST_FSP_TEMP_RAM_INIT) /* Calculate entry into FSP */ - mov 0x30(%ebp), %eax /* Load TempRamInitEntry */ - add 0x1c(%ebp), %eax /* add in the offset for the FSP base address */ + mov 0x30(%ebp), %eax /* Load TempRamInitEntry */ + add 0x1c(%ebp), %eax /* add in the offset for the FSP base address */ /* * Pass early init variables on a fake stack (no memory yet) * as well as the return location */ - lea CAR_init_stack, %esp + lea CAR_init_stack, %esp /* call FSP binary to setup temporary stack */ - jmp *%eax + jmp *%eax CAR_init_done: - addl $4, %esp - cmp $0, %eax - je car_init_ok - add $0xc0, %eax - jmp .Lhlt + addl $4, %esp + cmp $0, %eax + je car_init_ok + add $0xc0, %eax + jmp .Lhlt car_init_ok: /* Save FSP_INFO_HEADER location in ebx */ - mov %ebp, %ebx + mov %ebp, %ebx /* * set up bootloader stack * ecx: stack base * edx: stack top */ - mov %edx, %esp - movl %esp, %ebp + mov %edx, %esp + movl %esp, %ebp /* Clear the cbmem CAR memory region. */ - movl %ecx, %edi - movl %edx, %ecx - sub %edi, %ecx - shr $2, %ecx - xorl %eax, %eax - rep stosl + movl %ecx, %edi + movl %edx, %ecx + sub %edi, %ecx + shr $2, %ecx + xorl %eax, %eax + rep stosl before_romstage: post_code(0x23) /* Call romstage.c main function. */ - pushl %ebx /* main takes FSP_INFO_HEADER as its argument */ - call main /* does not return */ - movb $0xB8, %ah - jmp .Lhlt + pushl %ebx /* main takes FSP_INFO_HEADER as its argument */ + call main /* does not return */ + movb $0xB8, %ah + jmp .Lhlt .Lhlt: #if IS_ENABLED(CONFIG_POST_IO) - outb %al, $CONFIG_POST_IO_PORT + outb %al, $CONFIG_POST_IO_PORT #endif hlt - jmp .Lhlt + jmp .Lhlt /* * esp is set to this location so that the call into and return from the FSP @@ -107,17 +107,17 @@ */ .align 4 fake_fsp_stack: - .long find_fsp_ret + .long find_fsp_ret CAR_init_params: - .long dummy_microcode - .long 0 - .long CACHE_ROM_BASE /* Firmware Location */ - .long CACHE_ROM_SIZE /* Total Firmware Length */ + .long dummy_microcode + .long 0 + .long CACHE_ROM_BASE /* Firmware Location */ + .long CACHE_ROM_SIZE /* Total Firmware Length */ CAR_init_stack: - .long CAR_init_done - .long CAR_init_params + .long CAR_init_done + .long CAR_init_params dummy_microcode: - .long 0 + .long 0 -- To view, visit https://review.coreboot.org/c/coreboot/+/30454 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93cf734daefabe1f7cfaa5f49ba789ac04c8a635 Gerrit-Change-Number: 30454 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: arch/x86/c_start.S: Use tabs instead of white spaces
by HAOUAS Elyes (Code Review) 27 Dec '18

27 Dec '18

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30453 Change subject: arch/x86/c_start.S: Use tabs instead of white spaces ...................................................................... arch/x86/c_start.S: Use tabs instead of white spaces Change-Id: I415993bf11f6a019ff8ef4c0cba3b5bb511271fd Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/x86/c_start.S 1 file changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/30453/1 diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S index 6426ef3..3fbdac1 100644 --- a/src/arch/x86/c_start.S +++ b/src/arch/x86/c_start.S @@ -49,8 +49,8 @@ movl %eax, %fs movl %eax, %gs #ifdef __x86_64__ - mov $0x48, %ecx - call SetCodeSelector + mov $0x48, %ecx + call SetCodeSelector #endif post_code(POST_ENTRY_C_START) /* post 13 */ @@ -177,12 +177,12 @@ /* The next two entries are used for executing VGA option ROMs */ /* selgdt 0x28 16 bit 64k code at 0x00000000 */ - .word 0xffff, 0x0000 - .byte 0, 0x9a, 0, 0 + .word 0xffff, 0x0000 + .byte 0, 0x9a, 0, 0 /* selgdt 0x30 16 bit 64k data at 0x00000000 */ - .word 0xffff, 0x0000 - .byte 0, 0x92, 0, 0 + .word 0xffff, 0x0000 + .byte 0, 0x92, 0, 0 /* The next two entries are used for ACPI S3 RESUME */ -- To view, visit https://review.coreboot.org/c/coreboot/+/30453 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I415993bf11f6a019ff8ef4c0cba3b5bb511271fd Gerrit-Change-Number: 30453 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: drivers/amd/agesa/cache_as_ram.S: Fix coding style
by HAOUAS Elyes (Code Review) 27 Dec '18

27 Dec '18

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30452 Change subject: drivers/amd/agesa/cache_as_ram.S: Fix coding style ...................................................................... drivers/amd/agesa/cache_as_ram.S: Fix coding style Change-Id: Iada9b3ba71b991b6f9c7ebb5f300c8d28829ab4f Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/drivers/amd/agesa/cache_as_ram.S 1 file changed, 75 insertions(+), 75 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/30452/1 diff --git a/src/drivers/amd/agesa/cache_as_ram.S b/src/drivers/amd/agesa/cache_as_ram.S index 50242f7..09302d7 100644 --- a/src/drivers/amd/agesa/cache_as_ram.S +++ b/src/drivers/amd/agesa/cache_as_ram.S @@ -33,86 +33,86 @@ _cache_as_ram_setup: - /* Preserve BIST. */ - movd %eax, %mm0 + /* Preserve BIST. */ + movd %eax, %mm0 - post_code(0xa0) + post_code(0xa0) - /* enable SSE2 128bit instructions */ - /* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */ + /* enable SSE2 128bit instructions */ + /* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */ - movl %cr4, %eax - orl $(3 << 9), %eax - movl %eax, %cr4 + movl %cr4, %eax + orl $(3 << 9), %eax + movl %eax, %cr4 - post_code(0xa1) + post_code(0xa1) - AMD_ENABLE_STACK + AMD_ENABLE_STACK - /* Align the stack. */ - and $0xFFFFFFF0, %esp + /* Align the stack. */ + and $0xFFFFFFF0, %esp #ifdef __x86_64__ - /* switch to 64 bit long mode */ - mov %esi, %ecx - add $0, %ecx # core number - xor %eax, %eax - lea (0x1000+0x23)(%ecx), %edi - mov %edi, (%ecx) - mov %eax, 4(%ecx) + /* switch to 64 bit long mode */ + mov %esi, %ecx + add $0, %ecx # core number + xor %eax, %eax + lea (0x1000+0x23)(%ecx), %edi + mov %edi, (%ecx) + mov %eax, 4(%ecx) - lea 0x1000(%ecx), %edi - movl $0x000000e3, 0x00(%edi) - movl %eax, 0x04(%edi) - movl $0x400000e3, 0x08(%edi) - movl %eax, 0x0c(%edi) - movl $0x800000e3, 0x10(%edi) - movl %eax, 0x14(%edi) - movl $0xc00000e3, 0x18(%edi) - movl %eax, 0x1c(%edi) + lea 0x1000(%ecx), %edi + movl $0x000000e3, 0x00(%edi) + movl %eax, 0x04(%edi) + movl $0x400000e3, 0x08(%edi) + movl %eax, 0x0c(%edi) + movl $0x800000e3, 0x10(%edi) + movl %eax, 0x14(%edi) + movl $0xc00000e3, 0x18(%edi) + movl %eax, 0x1c(%edi) - # load ROM based identity mapped page tables - mov %ecx, %eax - mov %eax, %cr3 + # load ROM based identity mapped page tables + mov %ecx, %eax + mov %eax, %cr3 - # enable PAE - mov %cr4, %eax - bts $5, %eax - mov %eax, %cr4 + # enable PAE + mov %cr4, %eax + bts $5, %eax + mov %eax, %cr4 - # enable long mode - mov $0xC0000080, %ecx - rdmsr - bts $8, %eax - wrmsr + # enable long mode + mov $0xC0000080, %ecx + rdmsr + bts $8, %eax + wrmsr - # enable paging - mov %cr0, %eax - bts $31, %eax - mov %eax, %cr0 + # enable paging + mov %cr0, %eax + bts $31, %eax + mov %eax, %cr0 - # use call far to switch to 64-bit code segment - ljmp $0x18, $1f + # use call far to switch to 64-bit code segment + ljmp $0x18, $1f 1: #endif - call early_all_cores + call early_all_cores - /* Must maintain 16-byte stack alignment here. */ - pushl $0x0 - pushl $0x0 - pushl $0x0 - movd %mm0, %eax /* bist */ - pushl %eax - call romstage_main + /* Must maintain 16-byte stack alignment here. */ + pushl $0x0 + pushl $0x0 + pushl $0x0 + movd %mm0, %eax /* bist */ + pushl %eax + call romstage_main #if IS_ENABLED(CONFIG_POSTCAR_STAGE) /* We do not return. Execution continues with run_postcar_phase() * calling to chipset_teardown_car below. */ - jmp postcar_entry_failure + jmp postcar_entry_failure chipset_teardown_car: @@ -120,53 +120,53 @@ * Retrieve return address from stack as it will get trashed below if * execution is utilizing the cache-as-ram stack. */ - pop %esp + pop %esp #else - movl %eax, %esp + movl %eax, %esp /* Register %esp is new stacktop for remaining of romstage. */ #endif - /* Disable cache */ - movl %cr0, %eax - orl $CR0_CacheDisable, %eax - movl %eax, %cr0 + /* Disable cache */ + movl %cr0, %eax + orl $CR0_CacheDisable, %eax + movl %eax, %cr0 /* Register %esp is preserved in AMD_DISABLE_STACK. */ - AMD_DISABLE_STACK + AMD_DISABLE_STACK #if IS_ENABLED(CONFIG_POSTCAR_STAGE) - jmp *%esp + jmp *%esp #else - /* enable cache */ - movl %cr0, %eax - andl $0x9fffffff, %eax - movl %eax, %cr0 + /* enable cache */ + movl %cr0, %eax + andl $0x9fffffff, %eax + movl %eax, %cr0 - call romstage_after_car + call romstage_after_car #endif - /* Should never see this postcode */ - post_code(0xaf) + /* Should never see this postcode */ + post_code(0xaf) stop: - hlt - jmp stop + hlt + jmp stop /* These are here for linking purposes. */ .weak early_all_cores, romstage_main early_all_cores: romstage_main: postcar_entry_failure: - /* Should never see this postcode */ - post_code(0xae) - jmp stop + /* Should never see this postcode */ + post_code(0xae) + jmp stop _cache_as_ram_setup_end: -- To view, visit https://review.coreboot.org/c/coreboot/+/30452 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iada9b3ba71b991b6f9c7ebb5f300c8d28829ab4f Gerrit-Change-Number: 30452 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/sarien: Add settings for noise mitgation
by Lijian Zhao (Code Review) 27 Dec '18

27 Dec '18

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30448 Change subject: mb/google/sarien: Add settings for noise mitgation ...................................................................... mb/google/sarien: Add settings for noise mitgation Enable acoustic noise mitgation for sarien platform, the slow slew rates are fast time dived by 8. Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> Change-Id: I5d38a1e03af08f106e2422a319b34c3fb54bdf28 --- M src/mainboard/google/sarien/variants/sarien/devicetree.cb 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/30448/1 diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 47abadc..0b8e5c6 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -33,6 +33,11 @@ register "dptf_enable" = "1" register "dmipwroptimize" = "1" register "satapwroptimize" = "1" + register "AcousticNoiseMitigation" = "1" + register "SlowSlewRateForIa" = "2" + register "SlowSlewRateForGt" = "2" + register "SlowSlewRateForSa" = "2" + register "SlowSlewRateForFivr" = "2" # Intel Common SoC Config register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Left Type-C Port -- To view, visit https://review.coreboot.org/c/coreboot/+/30448 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5d38a1e03af08f106e2422a319b34c3fb54bdf28 Gerrit-Change-Number: 30448 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-MessageType: newchange

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