coreboot-gerrit December 2018

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: mb/google/hatch: Enable LPC controller
by Aamir Bohra (Code Review) 25 Dec '18

25 Dec '18

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30423 Change subject: mb/google/hatch: Enable LPC controller ...................................................................... mb/google/hatch: Enable LPC controller BUG=b:120914069 TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot Change-Id: Ia4baf80a775ba8898055f82e80dc583e65c4ed0b Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/30423/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 3cdc3e0..164c842 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -96,7 +96,7 @@ end end # GSPI #0 device pci 1e.3 off end # GSPI #1 - device pci 1f.0 off end # LPC/eSPI + device pci 1f.0 on end # LPC/eSPI device pci 1f.1 off end # P2SB device pci 1f.2 off end # Power Management Controller device pci 1f.3 off end # Intel HDA -- To view, visit https://review.coreboot.org/c/coreboot/+/30423 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia4baf80a775ba8898055f82e80dc583e65c4ed0b Gerrit-Change-Number: 30423 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/octopus/variants: Add 20ms reset delay for WACOM device
by Marco Chen (Code Review) 25 Dec '18

25 Dec '18

Hello Marco Chen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/30422 to review the following change. Change subject: mb/google/octopus/variants: Add 20ms reset delay for WACOM device ...................................................................... mb/google/octopus/variants: Add 20ms reset delay for WACOM device Add reset delay in power resource to prevent from failing to bind after unbinding. And boards including yorp series - bobba / phaser and bip series - ampton are affected. BUG=b:121286833 BUG=b:117474421 BUG=b:121019320 BRANCH=None TEST=emerge-octopus coreboot, verified that WACOM touchscreen can re-bind successfully. Change-Id: Icf690fc8e9450d559b642d1c88e29ff5d52c5488 Signed-off-by: Marco Chen <marcochen(a)chromium.org> --- M src/mainboard/google/octopus/variants/ampton/overridetree.cb M src/mainboard/google/octopus/variants/bip/overridetree.cb M src/mainboard/google/octopus/variants/bobba/overridetree.cb M src/mainboard/google/octopus/variants/phaser/overridetree.cb M src/mainboard/google/octopus/variants/yorp/overridetree.cb 5 files changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/30422/1 diff --git a/src/mainboard/google/octopus/variants/ampton/overridetree.cb b/src/mainboard/google/octopus/variants/ampton/overridetree.cb index b3f9416..1b4b9ba 100644 --- a/src/mainboard/google/octopus/variants/ampton/overridetree.cb +++ b/src/mainboard/google/octopus/variants/ampton/overridetree.cb @@ -36,6 +36,7 @@ register "generic.desc" = ""WCOM Digitizer"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_139_IRQ)" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" + register "generic.reset_delay_ms" = "20" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x1" device i2c 0x9 on end diff --git a/src/mainboard/google/octopus/variants/bip/overridetree.cb b/src/mainboard/google/octopus/variants/bip/overridetree.cb index 1403ac6..7271d56 100644 --- a/src/mainboard/google/octopus/variants/bip/overridetree.cb +++ b/src/mainboard/google/octopus/variants/bip/overridetree.cb @@ -7,6 +7,7 @@ register "generic.desc" = ""WCOM Digitizer"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_139_IRQ)" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" + register "generic.reset_delay_ms" = "20" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x1" device i2c 0x9 on end diff --git a/src/mainboard/google/octopus/variants/bobba/overridetree.cb b/src/mainboard/google/octopus/variants/bobba/overridetree.cb index 17686f6..9706e69 100644 --- a/src/mainboard/google/octopus/variants/bobba/overridetree.cb +++ b/src/mainboard/google/octopus/variants/bobba/overridetree.cb @@ -92,6 +92,7 @@ register "generic.desc" = ""WCOM Digitizer"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_139_IRQ)" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" + register "generic.reset_delay_ms" = "20" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x1" device i2c 0x9 on end diff --git a/src/mainboard/google/octopus/variants/phaser/overridetree.cb b/src/mainboard/google/octopus/variants/phaser/overridetree.cb index d42fe81..b07748d 100644 --- a/src/mainboard/google/octopus/variants/phaser/overridetree.cb +++ b/src/mainboard/google/octopus/variants/phaser/overridetree.cb @@ -48,6 +48,7 @@ register "generic.desc" = ""WCOM Digitizer"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_139_IRQ)" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" + register "generic.reset_delay_ms" = "20" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x1" device i2c 0x9 on end diff --git a/src/mainboard/google/octopus/variants/yorp/overridetree.cb b/src/mainboard/google/octopus/variants/yorp/overridetree.cb index 8d4cd15..a7fec75 100644 --- a/src/mainboard/google/octopus/variants/yorp/overridetree.cb +++ b/src/mainboard/google/octopus/variants/yorp/overridetree.cb @@ -48,6 +48,7 @@ register "generic.desc" = ""WCOM Digitizer"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_139_IRQ)" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" + register "generic.reset_delay_ms" = "20" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x1" device i2c 0x9 on end -- To view, visit https://review.coreboot.org/c/coreboot/+/30422 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icf690fc8e9450d559b642d1c88e29ff5d52c5488 Gerrit-Change-Number: 30422 Gerrit-PatchSet: 1 Gerrit-Owner: Marco Chen <marcochen(a)google.com> Gerrit-Reviewer: Marco Chen <marcochen(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/hatch: Enable LPC IO decode range for EC
by Aamir Bohra (Code Review) 24 Dec '18

24 Dec '18

Aamir Bohra has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/30417 ) Change subject: mb/google/hatch: Enable LPC IO decode range for EC ...................................................................... Abandoned squashed into https://review.coreboot.org/c/coreboot/+/30416/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/30417 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id97424c4921a3f6afa1a69a9de637a90158c55d4 Gerrit-Change-Number: 30417 Gerrit-PatchSet: 2 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in ...coreboot[master]: mb/google/hatch: Enable EC LPC interface and configure IO decode range
by Aamir Bohra (Code Review) 24 Dec '18

24 Dec '18

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30416 ) Change subject: mb/google/hatch: Enable EC LPC interface and configure IO decode range ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/#/c/30416/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/30416/1//COMMIT_MSG@8 PS1, Line 8: > BUG=b:120914069 Done -- To view, visit https://review.coreboot.org/c/coreboot/+/30416 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie5d92df80d6b3a5913d0cbe78c1b8eefb5269d4a Gerrit-Change-Number: 30416 Gerrit-PatchSet: 4 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 24 Dec 2018 18:49:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/hatch: Enable LPC IO decode range for EC
by Aamir Bohra (Code Review) 24 Dec '18

24 Dec '18

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30417 ) Change subject: mb/google/hatch: Enable LPC IO decode range for EC ...................................................................... Patch Set 2: > Patch Set 1: > > Why not just squash this into the previous CL? Ok. Done. Abandoning this. -- To view, visit https://review.coreboot.org/c/coreboot/+/30417 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id97424c4921a3f6afa1a69a9de637a90158c55d4 Gerrit-Change-Number: 30417 Gerrit-PatchSet: 2 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 24 Dec 2018 18:48:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/hatch: Enable EC LPC interface and configure IO decode range
by Aamir Bohra (Code Review) 24 Dec '18

24 Dec '18

Hello Subrata Banik, Rizwan Qureshi, Shelley Chen, build bot (Jenkins), Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/30416 to look at the new patch set (#4). Change subject: mb/google/hatch: Enable EC LPC interface and configure IO decode range ...................................................................... mb/google/hatch: Enable EC LPC interface and configure IO decode range Enable EC LPC interface and configure below LPC IO decode ranges: 1. 0x200-020F: EC host command range. 2. 0x800-0x8FF: EC host command args and params. 3. 0x900-0x9ff: EC memory map range. BUG=b:120914069 TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot Change-Id: Ie5d92df80d6b3a5913d0cbe78c1b8eefb5269d4a Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/variants/baseboard/devicetree.cb 2 files changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/30416/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/30416 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie5d92df80d6b3a5913d0cbe78c1b8eefb5269d4a Gerrit-Change-Number: 30416 Gerrit-PatchSet: 4 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: mb/google/hatch: Enable EC LPC interface and configure IO decode range
by Aamir Bohra (Code Review) 24 Dec '18

24 Dec '18

Hello Subrata Banik, Rizwan Qureshi, Shelley Chen, build bot (Jenkins), Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/30416 to look at the new patch set (#3). Change subject: mb/google/hatch: Enable EC LPC interface and configure IO decode range ...................................................................... mb/google/hatch: Enable EC LPC interface and configure IO decode range Enable EC LPC interface and configure below LPC IO decode ranges: 1. 0x200-020F: EC host command range. 2. 0x800-0x8FF: EC host command args and params. 3. 0x900-0x9ff: EC memory map range. Change-Id: Ie5d92df80d6b3a5913d0cbe78c1b8eefb5269d4a Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/variants/baseboard/devicetree.cb 2 files changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/30416/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/30416 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie5d92df80d6b3a5913d0cbe78c1b8eefb5269d4a Gerrit-Change-Number: 30416 Gerrit-PatchSet: 3 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: mb/google/hatch: Add SoC and EC asl files in DSDT
by Aamir Bohra (Code Review) 24 Dec '18

24 Dec '18

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30282 ) Change subject: mb/google/hatch: Add SoC and EC asl files in DSDT ...................................................................... Patch Set 15: (2 comments) https://review.coreboot.org/#/c/30282/14/src/mainboard/google/hatch/dsdt.asl File src/mainboard/google/hatch/dsdt.asl: https://review.coreboot.org/#/c/30282/14/src/mainboard/google/hatch/dsdt.as… PS14, Line 17: <variant/ec.h> > <variant/ec. […] Done https://review.coreboot.org/#/c/30282/14/src/mainboard/google/hatch/dsdt.as… PS14, Line 18: <variant/gpio.h> > <variant/gpio. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/30282 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icf1b1d7e34a7e863139c3583903f3b1e2cdc8da6 Gerrit-Change-Number: 30282 Gerrit-PatchSet: 15 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 24 Dec 2018 18:39:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/hatch: Add SoC and EC asl files in DSDT
by Aamir Bohra (Code Review) 24 Dec '18

24 Dec '18

Hello Subrata Banik, Rizwan Qureshi, Shelley Chen, build bot (Jenkins), Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/30282 to look at the new patch set (#15). Change subject: mb/google/hatch: Add SoC and EC asl files in DSDT ...................................................................... mb/google/hatch: Add SoC and EC asl files in DSDT This implementation adds below code: 1. Add SOC ACPI code in dsdt.asl -> platform.asl -> globalnvs.asl -> cpu.asl -> northbridge.asl -> southbridge.asl -> sleepstate.asl 2. Add chromeos.asl in dsdt.asl 3. Add EC ACPI code in dsdt.asl -> superio.asl -> ec.asl 4. Remove config for WAK/PTS ACPI method as chromeec doesn't implement those. BUG=b:120914069 TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot Change-Id: Icf1b1d7e34a7e863139c3583903f3b1e2cdc8da6 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/dsdt.asl M src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h 3 files changed, 39 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/30282/15 -- To view, visit https://review.coreboot.org/c/coreboot/+/30282 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icf1b1d7e34a7e863139c3583903f3b1e2cdc8da6 Gerrit-Change-Number: 30282 Gerrit-PatchSet: 15 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: mb/google/hatch: Enable LPC IO decode range for EC
by Furquan Shaikh (Code Review) 24 Dec '18

24 Dec '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30417 ) Change subject: mb/google/hatch: Enable LPC IO decode range for EC ...................................................................... Patch Set 1: Why not just squash this into the previous CL? -- To view, visit https://review.coreboot.org/c/coreboot/+/30417 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id97424c4921a3f6afa1a69a9de637a90158c55d4 Gerrit-Change-Number: 30417 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 24 Dec 2018 18:34:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit December 2018