coreboot-gerrit December 2018

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Change in ...coreboot[master]: ec/chromeec: fix LPC read/write for MEC devices
by Matt DeVillier (Code Review) 27 Dec '18

27 Dec '18

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30444 Change subject: ec/chromeec: fix LPC read/write for MEC devices ...................................................................... ec/chromeec: fix LPC read/write for MEC devices Commit 8cf8aa2 [ec/google/chromeec: Use common MEC interface] changed the return mechanism for the checksum on reads/writes for MEC devices, but incorrectly handled the passed-in csum parameter by not dereferencing. This led to the returned csum value always being zero, which causes all EC commands with non- NULL data_in to fail with a checksum error. Fix this by storing the returned checksum in a temp variable, and only assigning to csum when the pointer isn't NULL; Test: build/boot google/chell, verify EC hello command succeeds, keyboard backlight turned on at boot. Change-Id: I7122c3fdc5a19f87f12975ee448728cf29948436 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/ec/google/chromeec/ec_lpc.c 1 file changed, 6 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/30444/1 diff --git a/src/ec/google/chromeec/ec_lpc.c b/src/ec/google/chromeec/ec_lpc.c index c8665c9..61005d3 100644 --- a/src/ec/google/chromeec/ec_lpc.c +++ b/src/ec/google/chromeec/ec_lpc.c @@ -41,9 +41,11 @@ #if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_MEC) /* Access desired range though EMI interface */ if (port >= MEC_EMI_RANGE_START && port <= MEC_EMI_RANGE_END) { - csum += mec_io_bytes(MEC_IO_READ, MEC_EMI_BASE, + u8 ret = mec_io_bytes(MEC_IO_READ, MEC_EMI_BASE, port - MEC_EMI_RANGE_START, dest, length); + if (csum) + *csum += ret; return; } #endif @@ -78,9 +80,11 @@ #if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_MEC) /* Access desired range though EMI interface */ if (port >= MEC_EMI_RANGE_START && port <= MEC_EMI_RANGE_END) { - csum += mec_io_bytes(MEC_IO_WRITE, MEC_EMI_BASE, + u8 ret = mec_io_bytes(MEC_IO_WRITE, MEC_EMI_BASE, port - MEC_EMI_RANGE_START, msg, length); + if (csum) + *csum += ret; return; } #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/30444 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7122c3fdc5a19f87f12975ee448728cf29948436 Gerrit-Change-Number: 30444 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/hatch: Add SMI handlers
by Aamir Bohra (Code Review) 26 Dec '18

26 Dec '18

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30443 Change subject: mb/google/hatch: Add SMI handlers ...................................................................... mb/google/hatch: Add SMI handlers Add SMI handlers for below SMI events: 1. eSPI SMI event. 2. ACPI enable/disable SMI event -> Add support for EC to configure SMI mask on ACPI disable. -> Add support for EC to configure SCI mask on ACPI enable. 3. Sleep(S3/S5) SMI event -> Add support for EC to configure wake mask for S3/S5 event Change-Id: I7127b44712cd89b3d583e9948698870ca0c64b2b Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/mainboard/google/hatch/smihandler.c 1 file changed, 23 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/30443/1 diff --git a/src/mainboard/google/hatch/smihandler.c b/src/mainboard/google/hatch/smihandler.c index f8f43eb..68ef155 100644 --- a/src/mainboard/google/hatch/smihandler.c +++ b/src/mainboard/google/hatch/smihandler.c @@ -12,3 +12,26 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ + +#include <cpu/x86/smm.h> +#include <ec/google/chromeec/smm.h> +#include <soc/smm.h> +#include <variant/ec.h> + +void mainboard_smi_espi_handler(void) +{ + chromeec_smi_process_events(); +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, + MAINBOARD_EC_S5_WAKE_EVENTS); +} + +int mainboard_smi_apmc(u8 apmc) +{ + chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, + MAINBOARD_EC_SMI_EVENTS); + return 0; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/30443 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7127b44712cd89b3d583e9948698870ca0c64b2b Gerrit-Change-Number: 30443 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/hatch: Enable SPI controller for Hatch
by Rizwan Qureshi (Code Review) 26 Dec '18

26 Dec '18

Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30438 Change subject: mb/google/hatch: Enable SPI controller for Hatch ...................................................................... mb/google/hatch: Enable SPI controller for Hatch Enable SPI controller(D31:F5). BUG=b:120914069 TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot Change-Id: I4d3acd3f31650d5b39927f8e3cfbb6187541653f Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/30438/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 3025087..1f61856 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -127,7 +127,7 @@ device pci 1f.2 off end # Power Management Controller device pci 1f.3 off end # Intel HDA device pci 1f.4 off end # SMBus - device pci 1f.5 off end # PCH SPI + device pci 1f.5 on end # PCH SPI device pci 1f.6 off end # GbE end end -- To view, visit https://review.coreboot.org/c/coreboot/+/30438 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d3acd3f31650d5b39927f8e3cfbb6187541653f Gerrit-Change-Number: 30438 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/hatch: Enable CNVi Wifi and Bluetooth for hatch
by Maulik V Vaghela (Code Review) 26 Dec '18

26 Dec '18

Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30436 Change subject: mb/google/hatch: Enable CNVi Wifi and Bluetooth for hatch ...................................................................... mb/google/hatch: Enable CNVi Wifi and Bluetooth for hatch This patch incorporates following changes to enable CNVi bluetooth and Wifi. 1. Enable CNVi PCI device 14.3 2. Enable USB port 5 for Bluetooth 3. Enable PCI clock source 3 4. Configure GPIO pads for CNVi, BT and WLAN. BUG=b:120914069 BRANCH=none TEST=check if code compiles correctly and verify GPIO configuration with schematics Change-Id: I0c5542737d3a629b6a40116b4aa8ab6cbdd6a4dc Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/hatch/variants/baseboard/gpio.c 2 files changed, 36 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/30436/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 731ebba..ee73f9e 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -44,6 +44,10 @@ register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" + # USB PORT 5 for BT and WLAN + register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" + + register "PcieClkSrcUsage[3]" = "PCIE_CLK_LAN" device domain 0 on device pci 00.0 off end # Host Bridge device pci 02.0 on end # Integrated Graphics Device @@ -53,6 +57,10 @@ device pci 12.6 off end # GSPI #2 device pci 14.0 off end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) + chip drivers/intel/wifi + register "wake" = "PME_B0_EN_BIT" + device pci 14.3 on end # CNVi wifi + end device pci 14.5 off end # SDCard device pci 15.0 on chip drivers/i2c/generic @@ -64,7 +72,7 @@ end # I2C #0 device pci 15.1 on end # I2C #1 device pci 15.2 off end # I2C #2 - device pci 15.3 off end # I2C #3 + device pci 15.3 on end # I2C #3 device pci 16.0 off end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index 9f7512c..b4aedab 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -63,6 +63,33 @@ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), + /* MODEM_CLKREQ */ + PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3), + /* CNV_BT_I2S_SCLK */ + PAD_CFG_NF(GPP_H1, NONE, DEEP, NF2), + /* UART_WWANRX_WLANTX_COEX2 */ + PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), + /* UART_WWANTX_WLANRX_COEX1 */ + PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), + /* CNV_RGI_RSP */ + PAD_CFG_NF(GPP_F7, UP_20K, DEEP, NF1), + /* CNV_RGI_DT_R */ + PAD_CFG_NF(GPP_F6, UP_20K, DEEP, NF1), + /* CNV_BRI_RSP */ + PAD_CFG_NF(GPP_F5, UP_20K, DEEP, NF1), + /* CNV_BRI_DT_R */ + PAD_CFG_NF(GPP_F4, UP_20K, DEEP, NF1), + /* GPIO_WWAN_WLAN_COEX3 */ + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), + /* WLAN_PE_RST# */ + PAD_CFG_GPO(GPP_C23, 1, DEEP), + /* BT_DISABLE_L */ + PAD_CFG_GPO(GPP_C14, 1, DEEP), + /* PCIE_14_WLAN_WAKE_ODL */ + PAD_CFG_GPI(GPP_C1, NONE, PLTRST), + /* PCIE_14_WLAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), + }; const struct pad_config *__weak variant_gpio_table(size_t *num) -- To view, visit https://review.coreboot.org/c/coreboot/+/30436 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c5542737d3a629b6a40116b4aa8ab6cbdd6a4dc Gerrit-Change-Number: 30436 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/hatch: Enable SATA for Hatch
by V Sowmya (Code Review) 26 Dec '18

26 Dec '18

V Sowmya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30435 Change subject: mb/google/hatch: Enable SATA for Hatch ...................................................................... mb/google/hatch: Enable SATA for Hatch This patch enables the SATA for hatch, * Enable the SATA port 1. * Configure the GPIO for SATA. Change-Id: Iaf800d1531688c3d3b82600038ea1d7160ae4b0b Signed-off-by: V Sowmya <v.sowmya(a)intel.com> --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/hatch/variants/baseboard/gpio.c 2 files changed, 16 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/30435/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index ff48b54..5330f4d 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -39,6 +39,12 @@ # FSP configuration register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" + register "SataSalpSupport" = "1" + register "SataMode" = "Sata_AHCI" + register "SataPortsEnable[1]" = "1" + register "SataPortsDevSlp[1]" = "1" + register "satapwroptimize" = "1" + # Enable Root port 9(x4) for NVMe. # Enable CLKREQ# @@ -75,7 +81,7 @@ device pci 16.3 off end # Management Engine KT Redirection device pci 16.4 off end # Management Engine Interface 3 device pci 16.5 off end # Management Engine Interface 4 - device pci 17.0 off end # SATA + device pci 17.0 on end # SATA device pci 19.0 off end # I2C #4 device pci 19.1 off end # I2C #5 device pci 19.2 off end # UART #2 diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index ba7f734..346af0d 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -49,6 +49,15 @@ PAD_CFG_GPI(GPP_F11, NONE, PLTRST), /* PCH_MEM_STRAP3 */ PAD_CFG_GPI(GPP_F22, NONE, PLTRST), + /* SATAGP1 */ + PAD_CFG_NF(GPP_E1, NONE, DEEP, NF2), + /* + * M2_SSD_PE_WAKE_ODL This pin is not connected because of the resistor + * unstuff. + */ + PAD_CFG_GPO(GPP_E4, 1, DEEP), + /* SATA_DEVSLP1 */ + PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* USB_C0_DP_HPD */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDI2_HPD_ODL */ -- To view, visit https://review.coreboot.org/c/coreboot/+/30435 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf800d1531688c3d3b82600038ea1d7160ae4b0b Gerrit-Change-Number: 30435 Gerrit-PatchSet: 1 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/hatch: Enable NVME support for Hatch
by V Sowmya (Code Review) 26 Dec '18

26 Dec '18

V Sowmya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30431 Change subject: mb/google/hatch: Enable NVME support for Hatch ...................................................................... mb/google/hatch: Enable NVME support for Hatch This patch enables the x4 NVME device for hatch, * Enable the Root port 9. * Assign the usage type for clock source. * Configure the GPIO for CLK SRC 1. Change-Id: I69be6b21a5ae5962877a5c38180b5ffac532fed4 Signed-off-by: V Sowmya <v.sowmya(a)intel.com> --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/hatch/variants/baseboard/gpio.c 2 files changed, 11 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/30431/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 3cdc3e0..ff48b54 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -40,6 +40,14 @@ register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" + # Enable Root port 9(x4) for NVMe. + # Enable CLKREQ# + register "PcieRpEnable[8]" = "1" + # RP 9 uses CLK SRC 1 + register "PcieClkSrcUsage[1]" = "8" + # ClkReq-to-ClkSrc mapping for CLK SRC 1 + register "PcieClkSrcClkReq[1]" = "1" + device domain 0 on device pci 00.0 off end # Host Bridge device pci 02.0 on end # Integrated Graphics Device @@ -80,7 +88,7 @@ device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 off end # PCI Express Port 9 + device pci 1d.0 on end # PCI Express Port 9 (X4 NVME) device pci 1d.1 off end # PCI Express Port 10 device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index 489c489..ba7f734 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -21,6 +21,8 @@ static const struct pad_config gpio_table[] = { /* TRACKPAD_INT_ODL */ PAD_CFG_GPI_APIC(GPP_A21, NONE, PLTRST, LEVEL, INVERT), + /* SRCCLKREQ1 */ + PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* H1_SLAVE_SPI_CS_L */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* H1_SLAVE_SPI_CLK */ -- To view, visit https://review.coreboot.org/c/coreboot/+/30431 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69be6b21a5ae5962877a5c38180b5ffac532fed4 Gerrit-Change-Number: 30431 Gerrit-PatchSet: 1 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: intel/gma/Makefile.inc: Add a helper function to add VBT binaries
by Arthur Heymans (Code Review) 25 Dec '18

25 Dec '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30430 Change subject: intel/gma/Makefile.inc: Add a helper function to add VBT binaries ...................................................................... intel/gma/Makefile.inc: Add a helper function to add VBT binaries This adds a convenient helper function to add vbt binaries to cbfs. Change-Id: I80d9b3421f6e539879ad4802119fe81d7ea1e234 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/intel/gma/Makefile.inc M src/mainboard/lenovo/x200/Makefile.inc 2 files changed, 11 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/30430/1 diff --git a/src/drivers/intel/gma/Makefile.inc b/src/drivers/intel/gma/Makefile.inc index 30b3749..69cf58b 100644 --- a/src/drivers/intel/gma/Makefile.inc +++ b/src/drivers/intel/gma/Makefile.inc @@ -21,10 +21,17 @@ ramstage-$(CONFIG_INTEL_GMA_ACPI) += acpi.c ramstage-$(CONFIG_INTEL_GMA_ACPI) += opregion.c -cbfs-files-$(CONFIG_INTEL_GMA_ADD_VBT) += vbt.bin -vbt.bin-file := $(call strip_quotes,$(CONFIG_INTEL_GMA_VBT_FILE)) -vbt.bin-type := raw -vbt.bin-compression := lzma +# add_vbt_to_cbfs, first argument is the filename in cbfs, the second one +# is the filename in the coreboot three. +add_vbt_to_cbfs= \ + $(eval cbfs-files-y += $1) \ + $(eval $1-file := $2) \ + $(eval $1-type := raw) \ + $(eval $1-compression := lzma) + +ifeq ($(CONFIG_INTEL_GMA_ADD_VBT),y) +$(call add_vbt_to_cbfs, vbt.bin, $(call strip_quotes,$(CONFIG_INTEL_GMA_VBT_FILE))) +endif ifeq ($(CONFIG_MAINBOARD_USE_LIBGFXINIT),y) diff --git a/src/mainboard/lenovo/x200/Makefile.inc b/src/mainboard/lenovo/x200/Makefile.inc index 5e9832d..ffd7cf2 100644 --- a/src/mainboard/lenovo/x200/Makefile.inc +++ b/src/mainboard/lenovo/x200/Makefile.inc @@ -20,11 +20,5 @@ ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads -add_vbt_to_cbfs= \ - $(eval cbfs-files-y += $1) \ - $(eval $1-file := $2) \ - $(eval $1-type := raw) \ - $(eval $1-compression := lzma) - $(call add_vbt_to_cbfs, data_ccfl.vbt, data_ccfl.vbt) $(call add_vbt_to_cbfs, data_led.vbt, data_led.vbt) -- To view, visit https://review.coreboot.org/c/coreboot/+/30430 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I80d9b3421f6e539879ad4802119fe81d7ea1e234 Gerrit-Change-Number: 30430 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: sb/intel/bd828x6x: Make CONFIG_ELOG=y compile
by Arthur Heymans (Code Review) 25 Dec '18

25 Dec '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30426 Change subject: sb/intel/bd828x6x: Make CONFIG_ELOG=y compile ...................................................................... sb/intel/bd828x6x: Make CONFIG_ELOG=y compile The function pch_log_state() was overlooked when making the smi relocation code common. Change-Id: I878772f1a93105b828e50f37e105d04988ba0bdf Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/bd82x6x/elog.c M src/southbridge/intel/bd82x6x/pch.h M src/southbridge/intel/common/pmutil.h M src/southbridge/intel/common/smi.c 4 files changed, 5 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/30426/1 diff --git a/src/southbridge/intel/bd82x6x/elog.c b/src/southbridge/intel/bd82x6x/elog.c index 3299d4b..2ccdf83 100644 --- a/src/southbridge/intel/bd82x6x/elog.c +++ b/src/southbridge/intel/bd82x6x/elog.c @@ -21,6 +21,7 @@ #include <stdint.h> #include <string.h> #include <elog.h> +#include <southbridge/intel/common/pmutil.h> #include "pch.h" void pch_log_state(void) diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 280ac7d..ff55c39 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -66,9 +66,6 @@ int pch_silicon_type(void); int pch_silicon_supported(int type, int rev); void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); -#if IS_ENABLED(CONFIG_ELOG) -void pch_log_state(void); -#endif #else /* __PRE_RAM__ */ void enable_smbus(void); void enable_usb_bar(void); diff --git a/src/southbridge/intel/common/pmutil.h b/src/southbridge/intel/common/pmutil.h index 47813f7..2076a3d 100644 --- a/src/southbridge/intel/common/pmutil.h +++ b/src/southbridge/intel/common/pmutil.h @@ -149,5 +149,6 @@ void southbridge_finalize_all(void); void southbridge_smi_monitor(void); em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd); +void pch_log_state(void); #endif /*INTEL_COMMON_PMUTIL_H */ diff --git a/src/southbridge/intel/common/smi.c b/src/southbridge/intel/common/smi.c index 3ce4f40..af9dd5d 100644 --- a/src/southbridge/intel/common/smi.c +++ b/src/southbridge/intel/common/smi.c @@ -23,6 +23,7 @@ #include <cpu/x86/smm.h> #include <cpu/intel/smm/gen1/smi.h> #include <southbridge/intel/common/pmbase.h> +#include <southbridge/intel/common/pmutil.h> #include "pmutil.h" @@ -39,10 +40,9 @@ u16 pm1_en; u32 gpe0_en; -#if IS_ENABLED(CONFIG_ELOG) + if (IS_ENABLED(CONFIG_ELOG)) /* Log events from chipset before clearing */ - pch_log_state(); -#endif + pch_log_state(); printk(BIOS_DEBUG, "Initializing southbridge SMI..."); -- To view, visit https://review.coreboot.org/c/coreboot/+/30426 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I878772f1a93105b828e50f37e105d04988ba0bdf Gerrit-Change-Number: 30426 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/hatch: Enable touch support
by Maulik V Vaghela (Code Review) 25 Dec '18

25 Dec '18

Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30425 Change subject: mb/google/hatch: Enable touch support ...................................................................... mb/google/hatch: Enable touch support This patch will do following to enable touch screen support on hatch 1. Enable I2C1 device at 400Khz 2. Configure GPIO for touch screen Change-Id: I8dab07dad4cb197865bb9cf0e8da240810fcfabe Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/hatch/variants/baseboard/gpio.c 2 files changed, 15 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/30425/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 95dc6a3..731ebba 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -25,6 +25,7 @@ #| | for TPM communication | #| | before memory is up | #| I2C0 | Touchpad | + #| I2C1 | Touch screen | #+-------------------+---------------------------+ register "common_soc_config" = "{ .gspi[0] = { @@ -34,6 +35,9 @@ .i2c[0] = { .speed = I2C_SPEED_FAST, }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, }" # FSP configuration @@ -58,7 +62,7 @@ device i2c 15 on end end end # I2C #0 - device pci 15.1 off end # I2C #1 + device pci 15.1 on end # I2C #1 device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 device pci 16.0 off end # Management Engine Interface 1 diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index 13f5182..0b28442 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -37,6 +37,16 @@ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* PCH_I2C_TRACKPAD_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + /* TOUCHSCREEN_DIS_L */ + PAD_CFG_GPO(GPP_C4, 1, DEEP), + /* PCH_I2C_TOUCHSCREEN_SCL */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + /* PCH_I2C_TOUCHSCREEN_SDA */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + /* TOUCHSCREEN_RST_L */ + PAD_CFG_GPO(GPP_D15, 1, DEEP), + /* TOUCHSCREEN_INT_L */ + PAD_CFG_GPI(GPP_D16, NONE, DEEP), /* H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_C21, NONE, DEEP, LEVEL, INVERT), /* PCH_WP_OD */ -- To view, visit https://review.coreboot.org/c/coreboot/+/30425 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8dab07dad4cb197865bb9cf0e8da240810fcfabe Gerrit-Change-Number: 30425 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/hatch: Enable console UART
by Maulik V Vaghela (Code Review) 25 Dec '18

25 Dec '18

Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30424 Change subject: mb/google/hatch: Enable console UART ...................................................................... mb/google/hatch: Enable console UART This patch incorporates following changes to enable console on UART0 1. update default console number to 0 2. Enable PCI port for UART0 3. Configure TXD and RXD gpio pins for UART0 Change-Id: I735d33674b276b28e2cbb753d3a6d83edbabe89d Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/hatch/variants/baseboard/gpio.c 3 files changed, 8 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/30424/1 diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 6b4e45f..711d2e9 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -45,6 +45,9 @@ config DRIVER_TPM_SPI_BUS default 0x1 +config UART_FOR_CONSOLE + default 0 + config GBB_HWID string depends on CHROMEOS diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 3cdc3e0..95dc6a3 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -85,7 +85,7 @@ device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 device pci 1d.4 off end # PCI Express Port 13 (x4) - device pci 1e.0 off end # UART #0 + device pci 1e.0 on end # UART #0 device pci 1e.1 off end # UART #1 device pci 1e.2 on chip drivers/spi/acpi diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index 489c489..13f5182 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -29,6 +29,10 @@ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* H1_SLAVE_SPI_MOSI_R */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* UART_PCH_RX_DEBUG_TX */ + PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), + /* UART_PCH_TX_DEBUG_RX */ + PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* PCH_I2C_TRACKPAD_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* PCH_I2C_TRACKPAD_SCL */ -- To view, visit https://review.coreboot.org/c/coreboot/+/30424 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I735d33674b276b28e2cbb753d3a6d83edbabe89d Gerrit-Change-Number: 30424 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-MessageType: newchange

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coreboot-gerrit December 2018