coreboot-gerrit December 2018

coreboot-gerrit@coreboot.org

1 participants
1832 discussions

Change in ...coreboot[master]: src/drivers/usb: Make the EHCI debug console work in the bootblock
by Arthur Heymans (Code Review) 28 Dec '18

28 Dec '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30480 Change subject: src/drivers/usb: Make the EHCI debug console work in the bootblock ...................................................................... src/drivers/usb: Make the EHCI debug console work in the bootblock Currently this needlessly initializes the hardware in the both the romstage and the bootblock, but it works. Tested on Google/peppy. Change-Id: Ib77f2fc7f3d8fa524405601bae15cce9f76ffc6f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/device/Makefile.inc M src/drivers/usb/Makefile.inc M src/drivers/usb/ehci_debug.c M src/include/console/usb.h M src/soc/amd/stoneyridge/Makefile.inc M src/soc/intel/broadwell/Makefile.inc M src/southbridge/intel/common/Makefile.inc 7 files changed, 11 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/30480/1 diff --git a/src/device/Makefile.inc b/src/device/Makefile.inc index d1ca356..e6e9f1b 100644 --- a/src/device/Makefile.inc +++ b/src/device/Makefile.inc @@ -27,6 +27,7 @@ verstage-y += device_const.c romstage-y += device_const.c ramstage-y += device_const.c +bootblock-$(CONFIG_PCI) += pci_early.c romstage-$(CONFIG_PCI) += pci_early.c postcar-$(CONFIG_PCI) += pci_early.c diff --git a/src/drivers/usb/Makefile.inc b/src/drivers/usb/Makefile.inc index bc58f32..9495578 100644 --- a/src/drivers/usb/Makefile.inc +++ b/src/drivers/usb/Makefile.inc @@ -1,3 +1,4 @@ +bootblock-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += ehci_debug.c pci_ehci.c console.c gadget.c romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += ehci_debug.c pci_ehci.c console.c gadget.c postcar-$(CONFIG_USBDEBUG) += ehci_debug.c pci_ehci.c console.c gadget.c diff --git a/src/drivers/usb/ehci_debug.c b/src/drivers/usb/ehci_debug.c index bec5164..23aa38c 100644 --- a/src/drivers/usb/ehci_debug.c +++ b/src/drivers/usb/ehci_debug.c @@ -719,7 +719,8 @@ * CBMEM_INIT_HOOKs for postcar and ramstage as we recover state * from CBMEM. */ - if (IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE) && ENV_ROMSTAGE) + if (IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE) + && (ENV_ROMSTAGE || ENV_BOOTBLOCK)) usbdebug_hw_init(); /* USB console init is done early in ramstage if it was @@ -731,4 +732,5 @@ if (!IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE) && ENV_RAMSTAGE && !IS_ENABLED(CONFIG_POSTCAR_STAGE)) usbdebug_hw_init(); + } diff --git a/src/include/console/usb.h b/src/include/console/usb.h index 23f5f7a..d4429e6 100644 --- a/src/include/console/usb.h +++ b/src/include/console/usb.h @@ -28,8 +28,9 @@ int usb_can_rx_byte(int idx); #define __CONSOLE_USB_ENABLE__ (IS_ENABLED(CONFIG_CONSOLE_USB) && \ - ((ENV_ROMSTAGE && IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE)) || \ - ENV_POSTCAR || ENV_RAMSTAGE)) + ((ENV_BOOTBLOCK && IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE)) || \ + (ENV_ROMSTAGE && IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE)) || \ + ENV_POSTCAR || ENV_RAMSTAGE)) #define USB_PIPE_FOR_CONSOLE 0 #define USB_PIPE_FOR_GDB 0 diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index 46f1581..4514dd4 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -42,6 +42,7 @@ bootblock-y += bootblock/bootblock.c bootblock-y += gpio.c bootblock-y += i2c.c +bootblock-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c bootblock-y += monotonic_timer.c bootblock-y += pmutil.c bootblock-y += reset.c diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index 91d2834..20b9fa8 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -61,6 +61,7 @@ ramstage-y += tsc_freq.c romstage-y += tsc_freq.c smm-y += tsc_freq.c +bootblock-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += usb_debug.c romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += usb_debug.c postcar-$(CONFIG_USBDEBUG) += usb_debug.c ramstage-$(CONFIG_USBDEBUG) += usb_debug.c diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index f4d22f7..d76122b 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -29,6 +29,7 @@ postcar-y += pmbase.c smm-y += pmbase.c +bootblock-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += usb_debug.c romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += usb_debug.c postcar-$(CONFIG_USBDEBUG) += usb_debug.c ramstage-$(CONFIG_USBDEBUG) += usb_debug.c -- To view, visit https://review.coreboot.org/c/coreboot/+/30480 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib77f2fc7f3d8fa524405601bae15cce9f76ffc6f Gerrit-Change-Number: 30480 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: drivers/usb: Enable EHCI debug in postcar stage
by Arthur Heymans (Code Review) 28 Dec '18

28 Dec '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30479 Change subject: drivers/usb: Enable EHCI debug in postcar stage ...................................................................... drivers/usb: Enable EHCI debug in postcar stage Tested on google/peppy. Change-Id: I89e1233ccd2cb25a348be95f7c01f5621bd40b84 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/device/Makefile.inc M src/device/pci_early.c M src/drivers/usb/Makefile.inc M src/drivers/usb/ehci_debug.c M src/include/console/usb.h M src/soc/amd/stoneyridge/Makefile.inc M src/soc/intel/broadwell/Makefile.inc M src/southbridge/amd/agesa/hudson/Makefile.inc M src/southbridge/intel/common/Makefile.inc 9 files changed, 13 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/30479/1 diff --git a/src/device/Makefile.inc b/src/device/Makefile.inc index 05dbe74..d1ca356 100644 --- a/src/device/Makefile.inc +++ b/src/device/Makefile.inc @@ -28,6 +28,7 @@ romstage-y += device_const.c ramstage-y += device_const.c romstage-$(CONFIG_PCI) += pci_early.c +postcar-$(CONFIG_PCI) += pci_early.c subdirs-y += oprom dram diff --git a/src/device/pci_early.c b/src/device/pci_early.c index 6baebe0..3c01cb9 100644 --- a/src/device/pci_early.c +++ b/src/device/pci_early.c @@ -20,7 +20,7 @@ #include <device/pci_def.h> #include <delay.h> -#ifdef __PRE_RAM__ +#if !ENV_RAMSTAGE unsigned pci_find_next_capability(pci_devfn_t dev, unsigned cap, unsigned last) { unsigned pos = 0; diff --git a/src/drivers/usb/Makefile.inc b/src/drivers/usb/Makefile.inc index 6c46f04..bc58f32 100644 --- a/src/drivers/usb/Makefile.inc +++ b/src/drivers/usb/Makefile.inc @@ -1,4 +1,4 @@ romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += ehci_debug.c pci_ehci.c console.c gadget.c -postcar-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += ehci_debug.c console.c +postcar-$(CONFIG_USBDEBUG) += ehci_debug.c pci_ehci.c console.c gadget.c ramstage-$(CONFIG_USBDEBUG) += ehci_debug.c pci_ehci.c console.c gadget.c diff --git a/src/drivers/usb/ehci_debug.c b/src/drivers/usb/ehci_debug.c index 52b4bdd..bec5164 100644 --- a/src/drivers/usb/ehci_debug.c +++ b/src/drivers/usb/ehci_debug.c @@ -725,6 +725,10 @@ /* USB console init is done early in ramstage if it was * not done in romstage, this does not require CBMEM. */ - if (!IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE) && ENV_RAMSTAGE) + if (!IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE) && ENV_POSTCAR) + usbdebug_hw_init(); + + if (!IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE) && ENV_RAMSTAGE + && !IS_ENABLED(CONFIG_POSTCAR_STAGE)) usbdebug_hw_init(); } diff --git a/src/include/console/usb.h b/src/include/console/usb.h index 78956d7..23f5f7a 100644 --- a/src/include/console/usb.h +++ b/src/include/console/usb.h @@ -29,8 +29,7 @@ #define __CONSOLE_USB_ENABLE__ (IS_ENABLED(CONFIG_CONSOLE_USB) && \ ((ENV_ROMSTAGE && IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE)) || \ - (ENV_POSTCAR && IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE)) || \ - ENV_RAMSTAGE)) + ENV_POSTCAR || ENV_RAMSTAGE)) #define USB_PIPE_FOR_CONSOLE 0 #define USB_PIPE_FOR_GDB 0 diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index a53984e..46f1581 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -88,6 +88,7 @@ postcar-y += sb_util.c postcar-y += nb_util.c postcar-$(CONFIG_VBOOT_MEASURED_BOOT) += i2c.c +postcar-$(CONFIG_USBDEBUG) += enable_usbdebug.c ramstage-y += BiosCallOuts.c ramstage-y += i2c.c diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index caf963c..91d2834 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -62,6 +62,7 @@ romstage-y += tsc_freq.c smm-y += tsc_freq.c romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += usb_debug.c +postcar-$(CONFIG_USBDEBUG) += usb_debug.c ramstage-$(CONFIG_USBDEBUG) += usb_debug.c ramstage-y += ehci.c ramstage-y += xhci.c diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index 2bf6f02..1fa9ff3 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -17,6 +17,7 @@ ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c ramstage-y += reset.c romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c +postcar-$(CONFIG_USBDEBUG) += enable_usbdebug.c ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c romstage-y += early_setup.c diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index 1a509b1..f4d22f7 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -30,6 +30,7 @@ smm-y += pmbase.c romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += usb_debug.c +postcar-$(CONFIG_USBDEBUG) += usb_debug.c ramstage-$(CONFIG_USBDEBUG) += usb_debug.c romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c -- To view, visit https://review.coreboot.org/c/coreboot/+/30479 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I89e1233ccd2cb25a348be95f7c01f5621bd40b84 Gerrit-Change-Number: 30479 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: mb/google/{auron,jecht}: Remove duplicated HAVE_SMI_HANDLER
by HAOUAS Elyes (Code Review) 28 Dec '18

28 Dec '18

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30478 Change subject: mb/google/{auron,jecht}: Remove duplicated HAVE_SMI_HANDLER ...................................................................... mb/google/{auron,jecht}: Remove duplicated HAVE_SMI_HANDLER HAVE_SMI_HANDLER is selected here: broadwell/Kconfig Change-Id: I50c664198a954f661416c8cb1ced05f8775d8e07 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/google/auron/Kconfig M src/mainboard/google/jecht/Kconfig 2 files changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/30478/1 diff --git a/src/mainboard/google/auron/Kconfig b/src/mainboard/google/auron/Kconfig index b92869b..3f350e8 100644 --- a/src/mainboard/google/auron/Kconfig +++ b/src/mainboard/google/auron/Kconfig @@ -7,7 +7,6 @@ select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME - select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 diff --git a/src/mainboard/google/jecht/Kconfig b/src/mainboard/google/jecht/Kconfig index 0720375..58f3252 100644 --- a/src/mainboard/google/jecht/Kconfig +++ b/src/mainboard/google/jecht/Kconfig @@ -6,7 +6,6 @@ select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME - select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 -- To view, visit https://review.coreboot.org/c/coreboot/+/30478 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50c664198a954f661416c8cb1ced05f8775d8e07 Gerrit-Change-Number: 30478 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: mb/gigabyte/ga-b75m-d3h: Remove duplicated HAVE_SMI_HANDLER
by HAOUAS Elyes (Code Review) 28 Dec '18

28 Dec '18

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30477 Change subject: mb/gigabyte/ga-b75m-d3h: Remove duplicated HAVE_SMI_HANDLER ...................................................................... mb/gigabyte/ga-b75m-d3h: Remove duplicated HAVE_SMI_HANDLER HAVE_SMI_HANDLER is already selected here: bd82x6x/Kconfig Change-Id: I920800bb7c67cb5efd5dac0a9338a76214de2cab Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/gigabyte/ga-b75m-d3h/Kconfig 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/30477/1 diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig index 7aefcfb..360f7d1 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig +++ b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig @@ -13,7 +13,6 @@ select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT select HAVE_ACPI_RESUME - select HAVE_SMI_HANDLER select INTEL_INT15 select SERIRQ_CONTINUOUS_MODE select MAINBOARD_HAS_LIBGFXINIT -- To view, visit https://review.coreboot.org/c/coreboot/+/30477 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I920800bb7c67cb5efd5dac0a9338a76214de2cab Gerrit-Change-Number: 30477 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: mb/google/{glados & variants}: Remove duplicated HAVE_SMI_HANDLER
by HAOUAS Elyes (Code Review) 28 Dec '18

28 Dec '18

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30476 Change subject: mb/google/{glados & variants}: Remove duplicated HAVE_SMI_HANDLER ...................................................................... mb/google/{glados & variants}: Remove duplicated HAVE_SMI_HANDLER HAVE_SMI_HANDLER is already selected in soc/intel/skylake/Kconfig Use "smm-$(CONFIG_HAVE_SMI_HANDLER)" in Makefile.inc files. Change-Id: Ia60e34ee03958b05f2ac0c326632b6dd9f02a2e0 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/google/glados/Kconfig M src/mainboard/google/glados/variants/caroline/Makefile.inc M src/mainboard/google/glados/variants/cave/Makefile.inc M src/mainboard/google/glados/variants/chell/Makefile.inc M src/mainboard/google/glados/variants/glados/Makefile.inc 5 files changed, 4 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/30476/1 diff --git a/src/mainboard/google/glados/Kconfig b/src/mainboard/google/glados/Kconfig index 80cc0f3..05572df 100644 --- a/src/mainboard/google/glados/Kconfig +++ b/src/mainboard/google/glados/Kconfig @@ -12,7 +12,6 @@ select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE - select HAVE_SMI_HANDLER select INTEL_GMA_HAVE_VBT if !BOARD_GOOGLE_GLADOS select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LPC_TPM diff --git a/src/mainboard/google/glados/variants/caroline/Makefile.inc b/src/mainboard/google/glados/variants/caroline/Makefile.inc index 21b20e6..73d7090 100644 --- a/src/mainboard/google/glados/variants/caroline/Makefile.inc +++ b/src/mainboard/google/glados/variants/caroline/Makefile.inc @@ -16,7 +16,7 @@ romstage-y += variant.c ramstage-y += variant.c -smm-y += variant.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += variant.c SPD_BIN = $(obj)/spd.bin diff --git a/src/mainboard/google/glados/variants/cave/Makefile.inc b/src/mainboard/google/glados/variants/cave/Makefile.inc index f3b52c2..5d95e34 100644 --- a/src/mainboard/google/glados/variants/cave/Makefile.inc +++ b/src/mainboard/google/glados/variants/cave/Makefile.inc @@ -16,7 +16,7 @@ romstage-y += variant.c ramstage-y += variant.c -smm-y += variant.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += variant.c SPD_BIN = $(obj)/spd.bin diff --git a/src/mainboard/google/glados/variants/chell/Makefile.inc b/src/mainboard/google/glados/variants/chell/Makefile.inc index 986bdd8..2eff4b1 100644 --- a/src/mainboard/google/glados/variants/chell/Makefile.inc +++ b/src/mainboard/google/glados/variants/chell/Makefile.inc @@ -16,7 +16,7 @@ romstage-y += variant.c ramstage-y += variant.c -smm-y += variant.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += variant.c SPD_BIN = $(obj)/spd.bin diff --git a/src/mainboard/google/glados/variants/glados/Makefile.inc b/src/mainboard/google/glados/variants/glados/Makefile.inc index b6dbbd4..82dbcad 100644 --- a/src/mainboard/google/glados/variants/glados/Makefile.inc +++ b/src/mainboard/google/glados/variants/glados/Makefile.inc @@ -16,7 +16,7 @@ romstage-y += variant.c ramstage-y += variant.c -smm-y += variant.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += variant.c SPD_BIN = $(obj)/spd.bin -- To view, visit https://review.coreboot.org/c/coreboot/+/30476 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia60e34ee03958b05f2ac0c326632b6dd9f02a2e0 Gerrit-Change-Number: 30476 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: agesawrapper.c: check if HOP_COUNT_TABLE exists before AmdInitLate()
by Krystian Hebel (Code Review) 28 Dec '18

28 Dec '18

Krystian Hebel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30475 Change subject: agesawrapper.c: check if HOP_COUNT_TABLE exists before AmdInitLate() ...................................................................... agesawrapper.c: check if HOP_COUNT_TABLE exists before AmdInitLate() If HOP_COUNT_TABLE doesn't exist AmdInitLate() returns error when creating CDIT, which scaries users. This patch checks if mentioned table exists and turns off CDIT generation when it doesn't. After this patch AGESA_UNSUPPORTED is returned due to a bug in AGESA which cannot be walked around without disabling DMI table generation (`AGESA_STATUS Status = TRUE`, present in open source version of AGESA too). Change-Id: I868aa840ad3495a66a9d70b7803af237e7d5f049 Signed-off-by: Krystian Hebel <krystian.hebel(a)3mdeb.com> --- M src/northbridge/amd/pi/agesawrapper.c 1 file changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/30475/1 diff --git a/src/northbridge/amd/pi/agesawrapper.c b/src/northbridge/amd/pi/agesawrapper.c index 3021b81..dfce5b1 100644 --- a/src/northbridge/amd/pi/agesawrapper.c +++ b/src/northbridge/amd/pi/agesawrapper.c @@ -255,12 +255,18 @@ AGESA_STATUS Status; AMD_INTERFACE_PARAMS AmdParamStruct; AMD_LATE_PARAMS *AmdLateParams; + AGESA_BUFFER_PARAMS BufParams; LibAmdMemFill (&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader)); + LibAmdMemFill (&BufParams, + 0, + sizeof(AGESA_BUFFER_PARAMS), + &(BufParams.StdHeader)); + AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; AmdParamStruct.AllocationMethod = PostMemDram; AmdParamStruct.StdHeader.AltImageBasePtr = 0; @@ -274,6 +280,15 @@ AmdLateParams = (AMD_LATE_PARAMS *)AmdParamStruct.NewStructPtr; AmdLateParams->GnbLateConfiguration.GnbIoapicId = CONFIG_MAX_CPUS + 1; AmdLateParams->GnbLateConfiguration.FchIoapicId = CONFIG_MAX_CPUS; + + /* Code for creating CDIT requires hop count table. If it is not + * present AGESA_ERROR is returned, which confuses users. */ + BufParams.BufferHandle = HOP_COUNT_TABLE_HANDLE; + Status = HeapManagerCallout(AGESA_LOCATE_BUFFER, 0, &BufParams); + if (Status != AGESA_SUCCESS) { + AmdLateParams->PlatformConfig.UserOptionCdit = 0; + } + Status = AmdInitLate(AmdLateParams); if (Status != AGESA_SUCCESS) { agesawrapper_amdreadeventlog(AmdLateParams->StdHeader.HeapStatus); -- To view, visit https://review.coreboot.org/c/coreboot/+/30475 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I868aa840ad3495a66a9d70b7803af237e7d5f049 Gerrit-Change-Number: 30475 Gerrit-PatchSet: 1 Gerrit-Owner: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: mb/asus/m2v-mx_se: Allow use of native graphic init
by Arthur Heymans (Code Review) 28 Dec '18

28 Dec '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30473 Change subject: mb/asus/m2v-mx_se: Allow use of native graphic init ...................................................................... mb/asus/m2v-mx_se: Allow use of native graphic init Change-Id: Ib1faee6a71c276f4f9125e39e04aad660fa3ceb8 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/asus/m2v-mx_se/Kconfig M src/southbridge/via/k8t890/Kconfig M src/southbridge/via/k8t890/chrome.c 3 files changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/30473/1 diff --git a/src/mainboard/asus/m2v-mx_se/Kconfig b/src/mainboard/asus/m2v-mx_se/Kconfig index 60ed865..856cbe5 100644 --- a/src/mainboard/asus/m2v-mx_se/Kconfig +++ b/src/mainboard/asus/m2v-mx_se/Kconfig @@ -30,6 +30,7 @@ select VGA select HAVE_ACPI_RESUME select SET_FIDVID + select MAINBOARD_HAS_NATIVE_VGA_INIT config MAINBOARD_DIR string diff --git a/src/southbridge/via/k8t890/Kconfig b/src/southbridge/via/k8t890/Kconfig index f6e51dc..ecbd1d3 100644 --- a/src/southbridge/via/k8t890/Kconfig +++ b/src/southbridge/via/k8t890/Kconfig @@ -23,6 +23,7 @@ depends on SOUTHBRIDGE_VIA_SUBTYPE_K8M890 select VGA select GFXUMA + select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT choice prompt "Framebuffer size" diff --git a/src/southbridge/via/k8t890/chrome.c b/src/southbridge/via/k8t890/chrome.c index 5b6d6d2..ec59715 100644 --- a/src/southbridge/via/k8t890/chrome.c +++ b/src/southbridge/via/k8t890/chrome.c @@ -135,7 +135,7 @@ //k8m890_host_fb_direct_set(fb_address); - if (IS_ENABLED(SOUTHBRIDGE_VIA_K8M890_VGA_EN)) { + if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) { /* Now set up the VGA console */ vga_io_init(); /* Enable full IO access */ -- To view, visit https://review.coreboot.org/c/coreboot/+/30473 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib1faee6a71c276f4f9125e39e04aad660fa3ceb8 Gerrit-Change-Number: 30473 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: mb/foxconn/d41s: Program the subsystemid
by Arthur Heymans (Code Review) 28 Dec '18

28 Dec '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30472 Change subject: mb/foxconn/d41s: Program the subsystemid ...................................................................... mb/foxconn/d41s: Program the subsystemid Change-Id: I4f9d0cfc9a5bfa259d734f194b015e7be1694ceb Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/foxconn/d41s/devicetree.cb 1 file changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/30472/1 diff --git a/src/mainboard/foxconn/d41s/devicetree.cb b/src/mainboard/foxconn/d41s/devicetree.cb index 0fd9e29..21e8762 100644 --- a/src/mainboard/foxconn/d41s/devicetree.cb +++ b/src/mainboard/foxconn/d41s/devicetree.cb @@ -26,6 +26,7 @@ end end device domain 0 on # PCI domain + subsystemid 0x105b 0x0d55 inherit device pci 0.0 on end # Host Bridge device pci 1.0 off end # PEG device pci 2.0 on end # Integrated graphics controller @@ -45,7 +46,9 @@ device pci 1b.0 on end # Audio device pci 1c.0 on end # PCIe 1 - device pci 1c.1 on end # PCIe 2 (NIC) + device pci 1c.1 on # PCIe 2 (NIC) + device pci 00.0 on end + end device pci 1c.2 off end # PCIe 3 device pci 1c.3 off end # PCIe 4 # (PCIe 5 and 6 not on nm10?) -- To view, visit https://review.coreboot.org/c/coreboot/+/30472 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f9d0cfc9a5bfa259d734f194b015e7be1694ceb Gerrit-Change-Number: 30472 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: mb/intel/dg43gt: Program the subsystemid
by Arthur Heymans (Code Review) 28 Dec '18

28 Dec '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30471 Change subject: mb/intel/dg43gt: Program the subsystemid ...................................................................... mb/intel/dg43gt: Program the subsystemid Change-Id: I9f979e63378b1e0090a57849038eaafeb20d7a40 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/intel/dg43gt/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/30471/1 diff --git a/src/mainboard/intel/dg43gt/devicetree.cb b/src/mainboard/intel/dg43gt/devicetree.cb index 70ba6bc..be0b911 100644 --- a/src/mainboard/intel/dg43gt/devicetree.cb +++ b/src/mainboard/intel/dg43gt/devicetree.cb @@ -25,6 +25,7 @@ end end device domain 0 on # PCI domain + subsystemid 0x8086 0x0028 inherit device pci 0.0 on end # Host Bridge device pci 2.0 on end # Integrated graphics controller device pci 2.1 on end # Integrated graphics controller 2 -- To view, visit https://review.coreboot.org/c/coreboot/+/30471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f979e63378b1e0090a57849038eaafeb20d7a40 Gerrit-Change-Number: 30471 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: mb/google/hatch: Enable CSME/PMC/P2SB/SMBus
by Rizwan Qureshi (Code Review) 28 Dec '18

28 Dec '18

Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30465 Change subject: mb/google/hatch: Enable CSME/PMC/P2SB/SMBus ...................................................................... mb/google/hatch: Enable CSME/PMC/P2SB/SMBus * Enable host bridge. * Enable CSME. * Enable Power Management Controller. * Enable Primary to Side Band Bridge Controller. * Enable SmBus Controller. BUG=b:120914069 BRANCH=None TEST= code compiles with the changes Change-Id: I2fbf0ece845a7114ce5ab7f6482a935d9275deee Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb 1 file changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/30465/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index a996a70..e59ccc1 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -41,7 +41,7 @@ register "SkipExtGfxScan" = "1" device domain 0 on - device pci 00.0 off end # Host Bridge + device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device device pci 04.0 off end # SA Thermal device device pci 12.0 off end # Thermal Subsystem @@ -61,7 +61,7 @@ device pci 15.1 off end # I2C #1 device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 - device pci 16.0 off end # Management Engine Interface 1 + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT Redirection @@ -97,10 +97,10 @@ end # GSPI #0 device pci 1e.3 off end # GSPI #1 device pci 1f.0 on end # LPC/eSPI - device pci 1f.1 off end # P2SB - device pci 1f.2 off end # Power Management Controller + device pci 1f.1 on end # P2SB + device pci 1f.2 on end # Power Management Controller device pci 1f.3 off end # Intel HDA - device pci 1f.4 off end # SMBus + device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI device pci 1f.6 off end # GbE end -- To view, visit https://review.coreboot.org/c/coreboot/+/30465 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2fbf0ece845a7114ce5ab7f6482a935d9275deee Gerrit-Change-Number: 30465 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-MessageType: newchange

1 0

← Newer
1
2
3
4
5
6
7
8
9
...
184
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit December 2018