coreboot-gerrit December 2018

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Change in ...coreboot[master]: Makefile.inc: Create a default SMMSTORE region
by Arthur Heymans (Code Review) 06 Feb '19

06 Feb '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30421 Change subject: Makefile.inc: Create a default SMMSTORE region ...................................................................... Makefile.inc: Create a default SMMSTORE region Change-Id: I7b7b75050e0139ea9a0a4f2ad3c0d69a482fb38b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M Makefile.inc M src/drivers/smmstore/Kconfig M util/cbfstool/default-x86.fmd 3 files changed, 26 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/30421/1 diff --git a/Makefile.inc b/Makefile.inc index 8af291f..7dee1d2 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -869,11 +869,27 @@ endif # ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y) # +# X86 SMMSTORE FMAP region +# +# position, size and entry line of SMMSTORE relative to BIOS_BASE, if enabled +ifeq ($(CONFIG_SMMSTORE),y) +FMAP_SMMSTORE_BASE := $(call int-align, $(call int-add, $(FMAP_CONSOLE_BASE) \ + $(FMAP_CONSOLE_SIZE) $(FMAP_MRC_CACHE_SIZE)), 0x10000) +FMAP_SMMSTORE_SIZE := $(CONFIG_SMMSTORE_SIZE) +FMAP_SMMSTORE_ENTRY := SMMSTORE@$(FMAP_SMMSTORE_BASE) $(FMAP_SMMSTORE_SIZE) +else # ifeq ($(CONFIG_SMMSTORE),y) +FMAP_SMMSTORE_BASE := 0 +FMAP_SMMSTORE_SIZE := 0 +FMAP_SMMSTORE_ENTRY := +endif # ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y) + +# # X86 FMAP region # # # position, size -FMAP_FMAP_BASE := $(call int-add, $(FMAP_CONSOLE_SIZE) $(FMAP_MRC_CACHE_SIZE)) +FMAP_FMAP_BASE := $(call int-add, $(FMAP_CONSOLE_BASE) $(FMAP_CONSOLE_SIZE) \ + $(FMAP_MRC_CACHE_SIZE) $(FMAP_SMMSTORE_SIZE)) FMAP_FMAP_SIZE := 0x200 # @@ -947,6 +963,7 @@ -e "s,##FMAP_SIZE##,$(FMAP_FMAP_SIZE)," \ -e "s,##CONSOLE_ENTRY##,$(FMAP_CONSOLE_ENTRY)," \ -e "s,##MRC_CACHE_ENTRY##,$(FMAP_MRC_CACHE_ENTRY)," \ + -e "s,##SMMSTORE_ENTRY##,$(FMAP_SMMSTORE_ENTRY)," \ -e "s,##CBFS_BASE##,$(FMAP_CBFS_BASE)," \ -e "s,##CBFS_SIZE##,$(FMAP_CBFS_SIZE)," \ $(DEFAULT_FLASHMAP) > $@.tmp diff --git a/src/drivers/smmstore/Kconfig b/src/drivers/smmstore/Kconfig index 1ab3a5e..f2c97ab 100644 --- a/src/drivers/smmstore/Kconfig +++ b/src/drivers/smmstore/Kconfig @@ -37,4 +37,11 @@ string "SMM store file name" if SMMSTORE_IN_CBFS default "smm_store" +config SMMSTORE_SIZE + hex "size of the SMMSTORE FMAP region" + depends on !SMMSTORE_IN_CBFS + default 0x40000 + help + Set the size of the default SMMSTORE FMAP region. + endif diff --git a/util/cbfstool/default-x86.fmd b/util/cbfstool/default-x86.fmd index 174db1f..f0143e9 100644 --- a/util/cbfstool/default-x86.fmd +++ b/util/cbfstool/default-x86.fmd @@ -11,6 +11,7 @@ BIOS@##BIOS_BASE## ##BIOS_SIZE## { ##CONSOLE_ENTRY## ##MRC_CACHE_ENTRY## + ##SMMSTORE_ENTRY## FMAP@##FMAP_BASE## ##FMAP_SIZE## COREBOOT(CBFS)@##CBFS_BASE## ##CBFS_SIZE## } -- To view, visit https://review.coreboot.org/c/coreboot/+/30421 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b7b75050e0139ea9a0a4f2ad3c0d69a482fb38b Gerrit-Change-Number: 30421 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

2 7

Change in ...coreboot[master]: Makefile.inc: Make sure the BIOS region is 64K aligned
by Arthur Heymans (Code Review) 06 Feb '19

06 Feb '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30420 Change subject: Makefile.inc: Make sure the BIOS region is 64K aligned ...................................................................... Makefile.inc: Make sure the BIOS region is 64K aligned If a non aligned CONFIG_CBFS_SIZE is used the region RW_MRC_CACHE and CONSOLE could end up non aligned. Currently this is only possible if the user messes with CONFIG_CBFS_SIZE in menuconfig, but better be safe than sorry. Change-Id: Ieb7e3c7112bd4b3f9733c36af21b1d59b3836811 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M Makefile.inc 1 file changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/30420/1 diff --git a/Makefile.inc b/Makefile.inc index 85aa19e..8af291f 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -146,6 +146,7 @@ int-gt=$(if $(filter 1,$(words $1)),$(strip $1),$(shell expr $(call _toint,$(word 1,$1)) \> $(call _toint,$(word 2,$1)))) int-eq=$(if $(filter 1,$(words $1)),$(strip $1),$(shell expr $(call _toint,$(word 1,$1)) = $(call _toint,$(word 2,$1)))) int-align=$(shell A=$(call _toint,$1) B=$(call _toint,$2); expr $$A + $ \( $$B - \( $$A % $$B $ \) % $$B \) ) +int-align-down=$(shell A=$(call _toint,$1) B=$(call _toint,$2); expr $$A - $ $$A % $$B $ ) file-size=$(strip $(shell cat $1 | wc -c)) tolower=$(shell echo '$1' | tr '[:upper:]' '[:lower:]') toupper=$(shell echo '$1' | tr '[:lower:]' '[:upper:]') @@ -835,8 +836,8 @@ FMAP_ROM_SIZE := $(CONFIG_ROM_SIZE) # entire "BIOS" region (everything directly of concern to the host system) # relative to ROM_BASE -FMAP_BIOS_BASE := $(call int-subtract, $(CONFIG_ROM_SIZE) $(CONFIG_CBFS_SIZE)) -FMAP_BIOS_SIZE := $(shell echo $(CONFIG_CBFS_SIZE) | tr A-F a-f) +FMAP_BIOS_BASE := $(call int-align, $(call int-subtract, $(CONFIG_ROM_SIZE) $(CONFIG_CBFS_SIZE)), 0x10000) +FMAP_BIOS_SIZE := $(call int-align-down, $(shell echo $(CONFIG_CBFS_SIZE) | tr A-F a-f), 0x10000) # position and size of flashmap, relative to BIOS_BASE # -- To view, visit https://review.coreboot.org/c/coreboot/+/30420 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb7e3c7112bd4b3f9733c36af21b1d59b3836811 Gerrit-Change-Number: 30420 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

2 2

Change in ...coreboot[master]: Makefile.inc: Optimize generating the default x86 fmap
by Arthur Heymans (Code Review) 06 Feb '19

06 Feb '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30419 Change subject: Makefile.inc: Optimize generating the default x86 fmap ...................................................................... Makefile.inc: Optimize generating the default x86 fmap Put the FMAP FMAP region right above the coreboot region. The other regions like RW_MRC_CACHE and CONSOLE might have alignment requirements so it makes sense to put those on top. This also simplifies the generation code a little. Change-Id: I24fa6c89ecf85fb9002c0357f14aa970ee51b1df Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M Makefile.inc M util/cbfstool/default-x86.fmd 2 files changed, 12 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/30419/1 diff --git a/Makefile.inc b/Makefile.inc index b25ac6b..85aa19e 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -838,19 +838,16 @@ FMAP_BIOS_BASE := $(call int-subtract, $(CONFIG_ROM_SIZE) $(CONFIG_CBFS_SIZE)) FMAP_BIOS_SIZE := $(shell echo $(CONFIG_CBFS_SIZE) | tr A-F a-f) # position and size of flashmap, relative to BIOS_BASE -FMAP_FMAP_BASE := 0 -FMAP_FMAP_SIZE := 0x200 # # X86 CONSOLE FMAP region # # position, size and entry line of CONSOLE relative to BIOS_BASE, if enabled +FMAP_CONSOLE_BASE := 0 ifeq ($(CONFIG_CONSOLE_SPI_FLASH),y) -FMAP_CONSOLE_BASE := $(call int-add, $(FMAP_FMAP_BASE) $(FMAP_FMAP_SIZE)) FMAP_CONSOLE_SIZE := $(CONFIG_CONSOLE_SPI_FLASH_BUFFER_SIZE) FMAP_CONSOLE_ENTRY := CONSOLE@$(FMAP_CONSOLE_BASE) $(FMAP_CONSOLE_SIZE) else # ifeq ($(CONFIG_CONSOLE_SPI_FLASH),y) -FMAP_CONSOLE_BASE := 0 FMAP_CONSOLE_SIZE := 0 FMAP_CONSOLE_ENTRY := endif # ifeq ($(CONFIG_CONSOLE_SPI_FLASH),y) @@ -860,13 +857,8 @@ # # position, size and entry line of MRC_CACHE relative to BIOS_BASE, if enabled ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y) -ifeq ($(CONFIG_CONSOLE_SPI_FLASH),y) -FMAP_MRC_CACHE_BASE := $(call int-align, $(call int-add, $(FMAP_CONSOLE_BASE) \ +FMAP_MRC_CACHE_BASE := $(call int-align, $(call int-add, $(FMAP_CONSOLE_BASE) \ $(FMAP_CONSOLE_SIZE)), 0x10000) -else -FMAP_MRC_CACHE_BASE := $(call int-align, $(call int-add, $(FMAP_FMAP_BASE) \ - $(FMAP_FMAP_SIZE)), 0x10000) -endif FMAP_MRC_CACHE_SIZE := $(CONFIG_MRC_SETTINGS_CACHE_SIZE) FMAP_MRC_CACHE_ENTRY := RW_MRC_CACHE@$(FMAP_MRC_CACHE_BASE) $(FMAP_MRC_CACHE_SIZE) else # ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y) @@ -876,14 +868,18 @@ endif # ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y) # +# X86 FMAP region +# +# +# position, size +FMAP_FMAP_BASE := $(call int-add, $(FMAP_CONSOLE_SIZE) $(FMAP_MRC_CACHE_SIZE)) +FMAP_FMAP_SIZE := 0x200 + +# # X86 COREBOOT default cbfs FMAP region # # position and size of CBFS, relative to BIOS_BASE -ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y) -FMAP_CBFS_BASE := $(call int-add, $(FMAP_MRC_CACHE_BASE) $(FMAP_MRC_CACHE_SIZE)) -else -FMAP_CBFS_BASE := $(call int-add, $(FMAP_CONSOLE_SIZE) $(FMAP_FMAP_SIZE)) -endif +FMAP_CBFS_BASE := $(call int-add, $(FMAP_FMAP_BASE) $(FMAP_FMAP_SIZE)) FMAP_CBFS_SIZE := $(call int-subtract, $(FMAP_BIOS_SIZE) $(FMAP_CBFS_BASE)) else # ifeq ($(CONFIG_ARCH_X86),y) DEFAULT_FLASHMAP:=$(top)/util/cbfstool/default.fmd diff --git a/util/cbfstool/default-x86.fmd b/util/cbfstool/default-x86.fmd index 1f1aa43..174db1f 100644 --- a/util/cbfstool/default-x86.fmd +++ b/util/cbfstool/default-x86.fmd @@ -9,9 +9,9 @@ FLASH@##ROM_BASE## ##ROM_SIZE## { BIOS@##BIOS_BASE## ##BIOS_SIZE## { - FMAP@##FMAP_BASE## ##FMAP_SIZE## ##CONSOLE_ENTRY## ##MRC_CACHE_ENTRY## + FMAP@##FMAP_BASE## ##FMAP_SIZE## COREBOOT(CBFS)@##CBFS_BASE## ##CBFS_SIZE## } } -- To view, visit https://review.coreboot.org/c/coreboot/+/30419 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24fa6c89ecf85fb9002c0357f14aa970ee51b1df Gerrit-Change-Number: 30419 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

2 2

Change in ...coreboot[master]: WIP: mb/qemu-riscv: update to match current qemu version
by Philipp Hug (Code Review) 02 Feb '19

02 Feb '19

Philipp Hug has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30554 Change subject: WIP: mb/qemu-riscv: update to match current qemu version ...................................................................... WIP: mb/qemu-riscv: update to match current qemu version Boots again to payload not found on qemu. Change-Id: Ie107eb882cbaac5a5a06c1ff990e7b9364377640 Signed-off-by: Philipp Hug <philipp(a)hug.cx> --- M src/mainboard/emulation/qemu-riscv/Kconfig M src/mainboard/emulation/qemu-riscv/Makefile.inc M src/mainboard/emulation/qemu-riscv/mainboard.c M src/mainboard/emulation/qemu-riscv/memlayout.ld D src/mainboard/emulation/qemu-riscv/mtime.c M src/mainboard/emulation/qemu-riscv/rom_media.c M src/mainboard/emulation/qemu-riscv/uart.c 7 files changed, 23 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/30554/1 diff --git a/src/mainboard/emulation/qemu-riscv/Kconfig b/src/mainboard/emulation/qemu-riscv/Kconfig index 528b21e..ecaa764 100644 --- a/src/mainboard/emulation/qemu-riscv/Kconfig +++ b/src/mainboard/emulation/qemu-riscv/Kconfig @@ -13,7 +13,8 @@ ## GNU General Public License for more details. # To execute, do: -# qemu-system-arm -M vexpress-a9 -m 1024M -nographic -kernel build/coreboot.rom +# util/riscv/make-spike-elf.sh build/coreboot.rom build/coreboot.elf +# qemu-system-riscv64 -M virt -m 1024M -nographic -kernel build/coreboot.elf if BOARD_EMULATION_QEMU_RISCV diff --git a/src/mainboard/emulation/qemu-riscv/Makefile.inc b/src/mainboard/emulation/qemu-riscv/Makefile.inc index 1d882ac..eb99544 100644 --- a/src/mainboard/emulation/qemu-riscv/Makefile.inc +++ b/src/mainboard/emulation/qemu-riscv/Makefile.inc @@ -14,7 +14,7 @@ bootblock-y += uart.c bootblock-y += rom_media.c -bootblock-y += mtime.c +bootblock-y += clint.c romstage-y += romstage.c romstage-y += uart.c @@ -22,8 +22,10 @@ ramstage-y += uart.c ramstage-y += rom_media.c -ramstage-y += mtime.c +ramstage-y += clint.c bootblock-y += memlayout.ld romstage-y += memlayout.ld ramstage-y += memlayout.ld + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include diff --git a/src/mainboard/emulation/qemu-riscv/mainboard.c b/src/mainboard/emulation/qemu-riscv/mainboard.c index 7061bcf..4b428aa 100644 --- a/src/mainboard/emulation/qemu-riscv/mainboard.c +++ b/src/mainboard/emulation/qemu-riscv/mainboard.c @@ -16,6 +16,7 @@ #include <console/console.h> #include <device/device.h> #include <cbmem.h> +#include <symbols.h> static void mainboard_enable(struct device *dev) { @@ -24,7 +25,7 @@ die("No dev0; die\n"); } - ram_resource(dev, 0, 2048, 32768); + ram_resource(dev, 0, (uintptr_t)_dram / KiB, CONFIG_DRAM_SIZE_MB * KiB); cbmem_recovery(0); } diff --git a/src/mainboard/emulation/qemu-riscv/memlayout.ld b/src/mainboard/emulation/qemu-riscv/memlayout.ld index 615d1f2..032fbdd 100644 --- a/src/mainboard/emulation/qemu-riscv/memlayout.ld +++ b/src/mainboard/emulation/qemu-riscv/memlayout.ld @@ -14,15 +14,16 @@ */ #include <memlayout.h> - #include <arch/header.ld> +#define START 0x80000000 + SECTIONS { - DRAM_START(0x0) - BOOTBLOCK(0x0, 64K) - ROMSTAGE(0x20000, 128K) - STACK(0x40000, 0x3ff00) - PRERAM_CBMEM_CONSOLE(0x80000, 8K) - RAMSTAGE(0x100000, 16M) + DRAM_START(START) + BOOTBLOCK(START, 64K) + STACK(START + 4M, 4K) + ROMSTAGE(START + 4M + 64K, 128K) + PRERAM_CBMEM_CONSOLE(START + 4M + 192K, 8K) + RAMSTAGE(START + 4M + 200K, 16M) } diff --git a/src/mainboard/emulation/qemu-riscv/mtime.c b/src/mainboard/emulation/qemu-riscv/mtime.c deleted file mode 100644 index f8c2717..0000000 --- a/src/mainboard/emulation/qemu-riscv/mtime.c +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 HardenedLinux - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <mcall.h> - -/* FIXME: This is an empty implementation, please improve */ -/* This function is used to initialize HLS()->time/HLS()->timecmp */ -void mtime_init(void) -{ -} diff --git a/src/mainboard/emulation/qemu-riscv/rom_media.c b/src/mainboard/emulation/qemu-riscv/rom_media.c index c171307..bac1984 100644 --- a/src/mainboard/emulation/qemu-riscv/rom_media.c +++ b/src/mainboard/emulation/qemu-riscv/rom_media.c @@ -14,11 +14,12 @@ * GNU General Public License for more details. */ #include <boot_device.h> +#include <symbols.h> -/* This assumes that the CBFS resides at 0x0, which is true for the default - * configuration. */ +/* This assumes that the CBFS resides at start of dram, which is true for the + * default configuration. */ static const struct mem_region_device boot_dev = - MEM_REGION_DEV_RO_INIT(NULL, CONFIG_ROM_SIZE); + MEM_REGION_DEV_RO_INIT(_dram, CONFIG_ROM_SIZE); const struct region_device *boot_device_ro(void) { diff --git a/src/mainboard/emulation/qemu-riscv/uart.c b/src/mainboard/emulation/qemu-riscv/uart.c index 730ef3e..084362a 100644 --- a/src/mainboard/emulation/qemu-riscv/uart.c +++ b/src/mainboard/emulation/qemu-riscv/uart.c @@ -17,8 +17,9 @@ #include <console/uart.h> #include <arch/io.h> #include <boot/coreboot_tables.h> +#include <mainboard/addressmap.h> -static uint8_t *buf = (void *)0x3f8; +static uint8_t *buf = (void *)QEMU_VIRT_UART0; uintptr_t uart_platform_base(int idx) { return (uintptr_t) buf; @@ -47,7 +48,7 @@ { struct lb_serial serial; serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; - serial.baseaddr = 0x3f8; + serial.baseaddr = QEMU_VIRT_UART0; serial.baud = 115200; serial.regwidth = 1; lb_add_serial(&serial, data); -- To view, visit https://review.coreboot.org/c/coreboot/+/30554 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie107eb882cbaac5a5a06c1ff990e7b9364377640 Gerrit-Change-Number: 30554 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-MessageType: newchange

4 5

Change in ...coreboot[master]: drivers/usb: Initialize the HW once in CAR stages
by Arthur Heymans (Code Review) 31 Jan '19

31 Jan '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30481 Change subject: drivers/usb: Initialize the HW once in CAR stages ...................................................................... drivers/usb: Initialize the HW once in CAR stages The EHCI hardware needs to be initialized only once during CAR stages. Some exception need to be made when a blob messes with the EHCI hardware. To achieve this add a fixed location in the car.ld linker script such that the ehci debug information can be shared across CAR stages. Currently this means only romstage and bootblock, but verstage can also be hooked up later on. Tested on google/peppy: Both the bootblock and the romstage properly output console. Change-Id: I78e20a172fd5cc81f366d580f3cce57b9545d7a2 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/car.ld M src/arch/x86/include/arch/symbols.h M src/drivers/usb/ehci_debug.c M src/include/console/usb.h M src/northbridge/intel/sandybridge/raminit_mrc.c M src/soc/intel/fsp_baytrail/romstage/romstage.c M src/soc/intel/fsp_broadwell_de/romstage/romstage.c M src/southbridge/intel/fsp_rangeley/romstage.c 8 files changed, 32 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/30481/1 diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index 8665682..893b31f 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -40,9 +40,9 @@ _car_stack_end = .; #endif /* The pre-ram cbmem console as well as the timestamp region are fixed - * in size. Therefore place them at the beginning .car.data section - * so that multiple stages (romstage and verstage) have a consistent - * link address of these shared objects. */ + * in size. Therefore place them above the car global section so that + * multiple stages (romstage and verstage) have a consistent + * link address of these shared objects. */ PRERAM_CBMEM_CONSOLE(., CONFIG_PRERAM_CBMEM_CONSOLE_SIZE) #if IS_ENABLED(CONFIG_PAGING_IN_CACHE_AS_RAM) . = ALIGN(32); @@ -66,6 +66,9 @@ . += 256; _car_drivers_storage_end = .; #endif + _car_ehci_dbg_info_start = .; + . += 64; + _car_ehci_dbg_info_end = .; /* _car_global_start and _car_global_end provide symbols to per-stage * variables that are not shared like the timestamp and the pre-ram * cbmem console. This is useful for clearing this area on a per-stage diff --git a/src/arch/x86/include/arch/symbols.h b/src/arch/x86/include/arch/symbols.h index 704e3bb..9ef6a3b 100644 --- a/src/arch/x86/include/arch/symbols.h +++ b/src/arch/x86/include/arch/symbols.h @@ -34,6 +34,8 @@ extern char _car_stack_end[]; #define _car_stack_size (_car_stack_end - _car_stack_start) +extern char _car_ehci_dbg_info_start[]; + /* * The _car_relocatable_data_[start|end] symbols cover CAR data which is * relocatable once memory comes online. Variables with CAR_GLOBAL decoration diff --git a/src/drivers/usb/ehci_debug.c b/src/drivers/usb/ehci_debug.c index 23aa38c..c3713d9 100644 --- a/src/drivers/usb/ehci_debug.c +++ b/src/drivers/usb/ehci_debug.c @@ -18,6 +18,7 @@ #include <console/console.h> #include <console/usb.h> #include <arch/io.h> +#include <arch/symbols.h> #include <arch/early_variables.h> #include <string.h> #include <cbmem.h> @@ -27,6 +28,7 @@ #include "ehci.h" struct ehci_debug_info { + bool initialized; void *ehci_base; void *ehci_debug; @@ -61,6 +63,10 @@ static inline struct ehci_debug_info *dbgp_ehci_info(void) { + if (IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE) + && (ENV_ROMSTAGE || ENV_BOOTBLOCK || ENV_VERSTAGE)) + glob_dbg_info_p = + (struct ehci_debug_info *)_car_ehci_dbg_info_start; if (car_get_var(glob_dbg_info_p) == NULL) car_set_var(glob_dbg_info_p, &glob_dbg_info); @@ -569,6 +575,8 @@ goto err; } + info->initialized = true; + return 0; err: /* Things didn't work so remove my claim */ @@ -648,11 +656,14 @@ #endif -static int usbdebug_hw_init(void) +static int usbdebug_hw_init(bool force) { struct ehci_debug_info *dbg_info = dbgp_ehci_info(); unsigned int ehci_base, dbg_offset; + if (dbg_info->initialized && !force) + return -1; + if (ehci_debug_hw_enable(&ehci_base, &dbg_offset)) return -1; return usbdebug_init_(ehci_base, dbg_offset, dbg_info); @@ -686,7 +697,7 @@ * are still not enabled. Should never happen. */ rv = dbgp_enabled() ? 0 : -1; if (!ENV_POSTCAR && rv < 0) - rv = usbdebug_hw_init(); + rv = usbdebug_hw_init(true); if (rv < 0) printk(BIOS_DEBUG, "usbdebug: Failed hardware init\n"); @@ -713,7 +724,7 @@ return &dbgp_ehci_info()->ep_pipe[DBGP_CONSOLE_EPIN]; } -void usbdebug_init(void) +void usbdebug_init(bool force) { /* USB console init is done early in romstage, yet delayed to * CBMEM_INIT_HOOKs for postcar and ramstage as we recover state @@ -721,16 +732,16 @@ */ if (IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE) && (ENV_ROMSTAGE || ENV_BOOTBLOCK)) - usbdebug_hw_init(); + usbdebug_hw_init(force); /* USB console init is done early in ramstage if it was * not done in romstage, this does not require CBMEM. */ if (!IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE) && ENV_POSTCAR) - usbdebug_hw_init(); + usbdebug_hw_init(force); if (!IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE) && ENV_RAMSTAGE && !IS_ENABLED(CONFIG_POSTCAR_STAGE)) - usbdebug_hw_init(); + usbdebug_hw_init(force); } diff --git a/src/include/console/usb.h b/src/include/console/usb.h index d4429e6..ed91cce 100644 --- a/src/include/console/usb.h +++ b/src/include/console/usb.h @@ -20,7 +20,7 @@ #include <rules.h> #include <stdint.h> -void usbdebug_init(void); +void usbdebug_init(bool force); void usb_tx_byte(int idx, unsigned char data); void usb_tx_flush(int idx); @@ -36,7 +36,7 @@ #define USB_PIPE_FOR_GDB 0 #if __CONSOLE_USB_ENABLE__ -static inline void __usbdebug_init(void) { usbdebug_init(); } +static inline void __usbdebug_init(void) { usbdebug_init(false); } static inline void __usb_tx_byte(u8 data) { usb_tx_byte(USB_PIPE_FOR_CONSOLE, data); @@ -52,7 +52,7 @@ #if 0 && IS_ENABLED(CONFIG_GDB_STUB) && \ ((ENV_ROMSTAGE && IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE)) \ || ENV_RAMSTAGE) -static inline void __gdb_hw_init(void) { usbdebug_init(); } +static inline void __gdb_hw_init(void) { usbdebug_init(false); } static inline void __gdb_tx_byte(u8 data) { usb_tx_byte(USB_PIPE_FOR_GDB, data); diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 1975051..46cd201 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -238,10 +238,8 @@ die("UEFI PEI System Agent not found.\n"); } -#if IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE) /* mrc.bin reconfigures USB, so reinit it to have debug */ - usbdebug_init(); -#endif + usbdebug_init(true); /* For reference print the System Agent version * after executing the UEFI PEI stage. diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c index bc49a41..c71b637 100644 --- a/src/soc/intel/fsp_baytrail/romstage/romstage.c +++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c @@ -225,10 +225,8 @@ printk(BIOS_DEBUG, "%s status: %x hob_list_ptr: %x\n", __func__, (u32) status, (u32) hob_list_ptr); -#if IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE) /* FSP reconfigures USB, so reinit it to have debug */ - usbdebug_init(); -#endif /* IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE) */ + usbdebug_init(true); printk(BIOS_DEBUG, "FSP Status: 0x%0x\n", (u32)status); diff --git a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c index 801f9e0..8e837fc 100644 --- a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c +++ b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c @@ -101,10 +101,8 @@ printk(BIOS_DEBUG, "%s status: %x hob_list_ptr: %x\n", __func__, (u32) status, (u32) hob_list_ptr); -#if IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE) /* FSP reconfigures USB, so reinit it to have debug */ - usbdebug_init(); -#endif /* IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE) */ + usbdebug_init(true); printk(BIOS_DEBUG, "FSP Status: 0x%0x\n", (u32)status); diff --git a/src/southbridge/intel/fsp_rangeley/romstage.c b/src/southbridge/intel/fsp_rangeley/romstage.c index f986d79..d001656 100644 --- a/src/southbridge/intel/fsp_rangeley/romstage.c +++ b/src/southbridge/intel/fsp_rangeley/romstage.c @@ -99,10 +99,8 @@ printk(BIOS_DEBUG, "%s status: %x hob_list_ptr: %x\n", __func__, (u32) status, (u32) hob_list_ptr); -#if IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE) /* FSP reconfigures USB, so reinit it to have debug */ - usbdebug_init(); -#endif /* IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE) */ + usbdebug_init(true); printk(BIOS_DEBUG, "FSP Status: 0x%0x\n", (u32)status); -- To view, visit https://review.coreboot.org/c/coreboot/+/30481 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78e20a172fd5cc81f366d580f3cce57b9545d7a2 Gerrit-Change-Number: 30481 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

2 1

Change in ...coreboot[master]: drivers/generic/gpio_keys: Add trigger for wakeup event action
by Karthik Ramasubramanian (Code Review) 24 Jan '19

24 Jan '19

Hello Karthikeyan Ramasubramanian, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/30451 to review the following change. Change subject: drivers/generic/gpio_keys: Add trigger for wakeup event action ...................................................................... drivers/generic/gpio_keys: Add trigger for wakeup event action Currently without any trigger the wakeup event is generated on both the rising and falling edges of the GPIO input. Add support to specify the trigger explicitly so that the configuration can be passed to the kernel. BRANCH=octopus BUG=b:117953118 TEST=Ensure that the system boots to ChromeOS. Ensure that the stylus tools open on pen eject. Ensure that the system wakes on Pen Eject. Ensure that the system enters S0ix and S3 states after the pen is ejected. Ensure that the system enters S0ix and S3 states when the pen remains inserted in its holder. Ensured that the system does not wake when the pen is inserted. Ensure that the suspend_stress_test runs successfully for 25 iterations with the pen placed in its holder and ejected from its holder. Change-Id: Ifb08ba01106031aa2655c1ae2faab284926f1ceb Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> --- M src/drivers/generic/gpio_keys/chip.h M src/drivers/generic/gpio_keys/gpio_keys.c 2 files changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/30451/1 diff --git a/src/drivers/generic/gpio_keys/chip.h b/src/drivers/generic/gpio_keys/chip.h index 818f14c..88a3b35 100644 --- a/src/drivers/generic/gpio_keys/chip.h +++ b/src/drivers/generic/gpio_keys/chip.h @@ -30,6 +30,13 @@ SW_PEN_INSERTED = 0xf, }; +/* Trigger for wakeup event action */ +enum { + EV_ACT_ANY, + EV_ACT_ASSERTED, + EV_ACT_DEASSERTED, +}; + /* Details of the child node defining key */ struct key_info { /* Device name of the child node - Mandatory */ @@ -47,6 +54,8 @@ bool is_wakeup_source; /* Wake GPE */ unsigned int wake; + /* Trigger for Wakeup Event Action */ + unsigned int wakeup_event_action; /* Can this key be disabled? */ bool can_be_disabled; /* Debounce interval time in milliseconds */ diff --git a/src/drivers/generic/gpio_keys/gpio_keys.c b/src/drivers/generic/gpio_keys/gpio_keys.c index 5ecb63e..63f53fe 100644 --- a/src/drivers/generic/gpio_keys/gpio_keys.c +++ b/src/drivers/generic/gpio_keys/gpio_keys.c @@ -45,6 +45,10 @@ key->is_wakeup_source); if (key->wake) acpigen_write_PRW(key->wake, 3); + if (key->wakeup_event_action) + acpi_dp_add_integer(dsd, "wakeup-event-action", + key->wakeup_event_action); + if (key->can_be_disabled) acpi_dp_add_integer(dsd, "linux,can-disable", key->can_be_disabled); -- To view, visit https://review.coreboot.org/c/coreboot/+/30451 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifb08ba01106031aa2655c1ae2faab284926f1ceb Gerrit-Change-Number: 30451 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-MessageType: newchange

3 2

Change in ...coreboot[master]: soc/intel/gpio: Enable configuring GPIO debounce duration
by Karthik Ramasubramanian (Code Review) 24 Jan '19

24 Jan '19

Hello Karthikeyan Ramasubramanian, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/30450 to review the following change. Change subject: soc/intel/gpio: Enable configuring GPIO debounce duration ...................................................................... soc/intel/gpio: Enable configuring GPIO debounce duration Add new helper functions to enable configuring debounce duration for a GPIO input. Also ensure that the debounce configuration is not masked out. BRANCH=octopus BUG=b:117953118 TEST=Ensure that the system boots to ChromeOS. Ensure that the debounce duration is configured as expected. Change-Id: I4e3cd7744867bcfbaed7d3d96fed4e561afb2cec Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> --- M src/soc/intel/common/block/gpio/gpio.c M src/soc/intel/common/block/include/intelblocks/gpio_defs.h 2 files changed, 29 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/30450/1 diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c index c3b0ebf..294218c 100644 --- a/src/soc/intel/common/block/gpio/gpio.c +++ b/src/soc/intel/common/block/gpio/gpio.c @@ -46,7 +46,7 @@ PAD_CFG1_IOSSTATE_MASK) #endif -#define PAD_DW2_MASK (0) +#define PAD_DW2_MASK (PAD_CFG2_DEBOUNCE_MASK) #define PAD_DW3_MASK (0) #define MISCCFG_GPE0_DW0_SHIFT 8 diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h index 153a9da..4d02ecb 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h @@ -108,6 +108,22 @@ #endif /* CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY */ #define PAD_CFG2_NONE 0 +#define PAD_CFG2_DEBEN 1 +/* Debounce Duration = (2 ^ PAD_CFG2_DEBOUNCE_x_RTC) * RTC clock duration */ +#define PAD_CFG2_DEBOUNCE_8_RTC (0x3 << 1) +#define PAD_CFG2_DEBOUNCE_16_RTC (0x4 << 1) +#define PAD_CFG2_DEBOUNCE_32_RTC (0x5 << 1) +#define PAD_CFG2_DEBOUNCE_64_RTC (0x6 << 1) +#define PAD_CFG2_DEBOUNCE_128_RTC (0x7 << 1) +#define PAD_CFG2_DEBOUNCE_256_RTC (0x8 << 1) +#define PAD_CFG2_DEBOUNCE_512_RTC (0x9 << 1) +#define PAD_CFG2_DEBOUNCE_1K_RTC (0xa << 1) +#define PAD_CFG2_DEBOUNCE_2K_RTC (0xb << 1) +#define PAD_CFG2_DEBOUNCE_4K_RTC (0xc << 1) +#define PAD_CFG2_DEBOUNCE_8K_RTC (0xd << 1) +#define PAD_CFG2_DEBOUNCE_16K_RTC (0xe << 1) +#define PAD_CFG2_DEBOUNCE_32K_RTC (0xf << 1) +#define PAD_CFG2_DEBOUNCE_MASK 0x1f /* voltage tolerance 0=3.3V default 1=1.8V tolerant */ #if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL) @@ -352,6 +368,18 @@ #define PAD_CFG_GPI_SCI_HIGH(pad, pull, rst, trig) \ PAD_CFG_GPI_SCI(pad, pull, rst, trig, NONE) +#define PAD_CFG_GPI_SCI_DEBEN(pad, pull, rst, trig, inv, dur) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \ + PAD_IOSSTATE(TxDRxE), PAD_CFG2_DEBEN | PAD_CFG2_##dur) + +#define PAD_CFG_GPI_SCI_LOW_DEBEN(pad, pull, rst, trig, dur) \ + PAD_CFG_GPI_SCI_DEBEN(pad, pull, rst, trig, INVERT, dur) + +#define PAD_CFG_GPI_SCI_HIGH_DEBEN(pad, pull, rst, trig, dur) \ + PAD_CFG_GPI_SCI_DEBEN(pad, pull, rst, trig, NONE, dur) + /* General purpose input, routed to NMI */ #define PAD_CFG_GPI_NMI(pad, pull, rst, trig, inv) \ _PAD_CFG_STRUCT(pad, \ -- To view, visit https://review.coreboot.org/c/coreboot/+/30450 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e3cd7744867bcfbaed7d3d96fed4e561afb2cec Gerrit-Change-Number: 30450 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-MessageType: newchange

3 2

Change in ...coreboot[master]: soc/intel/common/gpio_defs: Enable configuring GPIO_DW2 pad register
by Karthik Ramasubramanian (Code Review) 24 Jan '19

24 Jan '19

Hello Karthikeyan Ramasubramanian, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/30449 to review the following change. Change subject: soc/intel/common/gpio_defs: Enable configuring GPIO_DW2 pad register ...................................................................... soc/intel/common/gpio_defs: Enable configuring GPIO_DW2 pad register Currently all the helpers support configuring GPIO_DW0/1 registers. In some architectures there is an additional configuration GPIO_DW2 register that can be used to configure debounce duration etc. Update the helpers to enable configuring GPIO_DW2 pad register. BRANCH=octopus BUG=b:117953118 TEST=Ensure that the system boots to ChromeOS. Ensure that the current configuration is not disturbed by turning on the GPIO_DEBUG option and verifying the debug output before and after the change. Change-Id: I3e5d259d007fdc83940a43cc4cd4a2b8a547d334 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> --- M src/soc/intel/common/block/include/intelblocks/gpio_defs.h 1 file changed, 42 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/30449/1 diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h index 418b6ab..153a9da 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h @@ -107,6 +107,8 @@ #define PAD_CFG1_IOSSTATE_MASK 0 #endif /* CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY */ +#define PAD_CFG2_NONE 0 + /* voltage tolerance 0=3.3V default 1=1.8V tolerant */ #if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL) #define PAD_CFG1_TOL_MASK (0x1 << 25) @@ -138,17 +140,27 @@ PAD_CFG0_RX_POL_##inv) #endif /* CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT */ -#define _PAD_CFG_STRUCT(__pad, __config0, __config1) \ +#if GPIO_NUM_PAD_CFG_REGS > 2 +#define _PAD_CFG_STRUCT(__pad, __config0, __config1, __config2) \ + { \ + .pad = __pad, \ + .pad_config[0] = __config0, \ + .pad_config[1] = __config1, \ + .pad_config[2] = __config2, \ + } +#else +#define _PAD_CFG_STRUCT(__pad, __config0, __config1, __config2) \ { \ .pad = __pad, \ .pad_config[0] = __config0, \ .pad_config[1] = __config1, \ } +#endif /* Native function configuration */ #define PAD_CFG_NF(pad, pull, rst, func) \ _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \ - PAD_IOSSTATE(TxLASTRxE)) + PAD_IOSSTATE(TxLASTRxE), PAD_CFG2_NONE) #if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL) /* Native 1.8V tolerant pad, only applies to some pads like I2C/I2S @@ -156,55 +168,57 @@ */ #define PAD_CFG_NF_1V8(pad, pull, rst, func) \ _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) |\ - PAD_IOSSTATE(TxLASTRxE) | PAD_CFG1_TOL_1V8) + PAD_IOSSTATE(TxLASTRxE) | PAD_CFG1_TOL_1V8, PAD_CFG2_NONE) #endif /* Native function configuration for standby state */ #define PAD_CFG_NF_IOSSTATE(pad, pull, rst, func, iosstate) \ _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \ - PAD_IOSSTATE(iosstate)) + PAD_IOSSTATE(iosstate), PAD_CFG2_NONE) /* Native function configuration for standby state, also configuring iostandby as masked */ #define PAD_CFG_NF_IOSTANDBY_IGNORE(pad, pull, rst, func) \ _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \ - PAD_IOSSTATE(IGNORE)) + PAD_IOSSTATE(IGNORE), PAD_CFG2_NONE) /* Native function configuration for standby state, also configuring iosstate and iosterm */ #define PAD_CFG_NF_IOSSTATE_IOSTERM(pad, pull, rst, func, iosstate, iosterm) \ _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \ - PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) + PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm), PAD_CFG2_NONE) /* General purpose output, no pullup/down. */ #define PAD_CFG_GPO(pad, val, rst) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_RX_DISABLE | !!val, \ - PAD_PULL(NONE) | PAD_IOSSTATE(TxLASTRxE)) + PAD_PULL(NONE) | PAD_IOSSTATE(TxLASTRxE), PAD_CFG2_NONE) /* General purpose output, with termination specified */ #define PAD_CFG_TERM_GPO(pad, val, pull, rst) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_RX_DISABLE | !!val, \ - PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE)) + PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE), PAD_CFG2_NONE) /* General purpose output, no pullup/down. */ #define PAD_CFG_GPO_GPIO_DRIVER(pad, val, rst, pull) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_RX_DISABLE | !!val, \ - PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE) | PAD_CFG1_GPIO_DRIVER) + PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE) | \ + PAD_CFG1_GPIO_DRIVER, PAD_CFG2_NONE) /* General purpose output. */ #define PAD_CFG_GPO_IOSSTATE_IOSTERM(pad, val, rst, pull, iosstate, ioterm) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_RX_DISABLE | !!val, \ - PAD_PULL(pull) | PAD_IOSSTATE(iosstate) | PAD_IOSTERM(ioterm)) + PAD_PULL(pull) | PAD_IOSSTATE(iosstate) | PAD_IOSTERM(ioterm), \ + PAD_CFG2_NONE) /* General purpose input */ #define PAD_CFG_GPI(pad, pull, rst) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \ - PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE)) + PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE), PAD_CFG2_NONE) /* General purpose input. The following macro sets the * Host Software Pad Ownership to GPIO Driver mode. @@ -212,27 +226,29 @@ #define PAD_CFG_GPI_GPIO_DRIVER(pad, pull, rst) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \ - PAD_PULL(pull) | PAD_CFG1_GPIO_DRIVER | PAD_IOSSTATE(TxDRxE)) + PAD_PULL(pull) | PAD_CFG1_GPIO_DRIVER | PAD_IOSSTATE(TxDRxE), \ + PAD_CFG2_NONE) #define PAD_CFG_GPIO_DRIVER_HI_Z(pad, pull, rst, iosstate, iosterm) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ PAD_CFG0_RX_DISABLE, \ PAD_PULL(pull) | PAD_CFG1_GPIO_DRIVER | \ - PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) + PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm), PAD_CFG2_NONE) #define PAD_CFG_GPIO_HI_Z(pad, pull, rst, iosstate, iosterm) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ PAD_CFG0_RX_DISABLE, PAD_PULL(pull) | \ - PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) + PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm), PAD_CFG2_NONE) /* GPIO Interrupt */ #define PAD_CFG_GPI_INT(pad, pull, rst, trig) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ PAD_CFG0_TRIG_##trig | PAD_CFG0_RX_POL_NONE, \ - PAD_PULL(pull) | PAD_CFG1_GPIO_DRIVER | PAD_IOSSTATE(TxDRxE)) + PAD_PULL(pull) | PAD_CFG1_GPIO_DRIVER | PAD_IOSSTATE(TxDRxE), \ + PAD_CFG2_NONE) /* No Connect configuration for unused pad. * NC should be GPI with Term as PU20K, PD20K, NONE depending upon default Term @@ -244,12 +260,13 @@ #define PAD_CFG_GPI_APIC(pad, pull, rst) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ - PAD_IRQ_CFG(IOAPIC, LEVEL, NONE), PAD_PULL(pull)) + PAD_IRQ_CFG(IOAPIC, LEVEL, NONE), PAD_PULL(pull), PAD_CFG2_NONE) #define PAD_CFG_GPI_APIC_INVERT(pad, pull, rst) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ - PAD_IRQ_CFG(IOAPIC, LEVEL, INVERT), PAD_PULL(pull)) + PAD_IRQ_CFG(IOAPIC, LEVEL, INVERT), PAD_PULL(pull), \ + PAD_CFG2_NONE) #define PAD_CFG_GPI_ACPI_SCI(pad, pull, rst, inv) \ PAD_CFG_GPI_SCI(pad, pull, rst, EDGE_SINGLE, inv) @@ -271,7 +288,7 @@ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ PAD_IRQ_CFG(IOAPIC, trig, inv), PAD_PULL(pull) | \ - PAD_IOSSTATE(TxDRxE)) + PAD_IOSSTATE(TxDRxE), PAD_CFG2_NONE) #endif /* General purpose input, routed to APIC - with IOStandby Config*/ @@ -279,7 +296,7 @@ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ PAD_IRQ_CFG(IOAPIC, trig, inv), PAD_PULL(pull) | \ - PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) + PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm), PAD_CFG2_NONE) /* * The following APIC macros assume the APIC will handle the filtering @@ -300,14 +317,14 @@ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ PAD_IRQ_CFG(SMI, trig, inv), PAD_PULL(pull) | \ - PAD_IOSSTATE(TxDRxE)) + PAD_IOSSTATE(TxDRxE), PAD_CFG2_NONE) /* General purpose input, routed to SMI */ #define PAD_CFG_GPI_SMI_IOS(pad, pull, rst, trig, inv, iosstate, iosterm) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ PAD_IRQ_CFG(SMI, trig, inv), PAD_PULL(pull) | \ - PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) + PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm), PAD_CFG2_NONE) #define PAD_CFG_GPI_SMI_LOW(pad, pull, rst, trig) \ PAD_CFG_GPI_SMI(pad, pull, rst, trig, INVERT) @@ -320,14 +337,14 @@ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \ - PAD_IOSSTATE(TxDRxE)) + PAD_IOSSTATE(TxDRxE), PAD_CFG2_NONE) /* General purpose input, routed to SCI */ #define PAD_CFG_GPI_SCI_IOS(pad, pull, rst, trig, inv, iosstate, iosterm) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \ - PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) + PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm), PAD_CFG2_NONE) #define PAD_CFG_GPI_SCI_LOW(pad, pull, rst, trig) \ PAD_CFG_GPI_SCI(pad, pull, rst, trig, INVERT) @@ -340,14 +357,14 @@ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ PAD_IRQ_CFG(NMI, trig, inv), PAD_PULL(pull) | \ - PAD_IOSSTATE(TxDRxE)) + PAD_IOSSTATE(TxDRxE), PAD_CFG2_NONE) #if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT) #define PAD_CFG_GPI_DUAL_ROUTE(pad, pull, rst, trig, inv, route1, route2) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ PAD_IRQ_CFG_DUAL_ROUTE(route1, route2, trig, inv), \ - PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE)) + PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE), PAD_CFG2_NONE) #define PAD_CFG_GPI_IRQ_WAKE(pad, pull, rst, trig, inv) \ PAD_CFG_GPI_DUAL_ROUTE(pad, pull, rst, trig, inv, IOAPIC, SCI) -- To view, visit https://review.coreboot.org/c/coreboot/+/30449 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e5d259d007fdc83940a43cc4cd4a2b8a547d334 Gerrit-Change-Number: 30449 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-MessageType: newchange

3 2

Change in ...coreboot[master]: mb/google/hatch: Enable PCIe WLAN and BT
by Maulik V Vaghela (Code Review) 24 Jan '19

24 Jan '19

Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30467 Change subject: mb/google/hatch: Enable PCIe WLAN and BT ...................................................................... mb/google/hatch: Enable PCIe WLAN and BT Enable PCIe WLAN for hatch 1. Enable PCI Rp#13 for PCIe WLAN 2. Enable PCI clock source 3 for PCI port 13 3. GPIO pad config for WLAN and BT USB port for BT has already been enabled so not included in this patch BUG=b:120914069 BRANCH=none TEST=check if code compiles correctly and verify GPIO configuration with schematics Change-Id: I4f2a6eb37a467ad8b8cdde8fe6b657fabb383b04 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/hatch/variants/baseboard/gpio.c 2 files changed, 22 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/30467/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 0e80ab3..1ad5589 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -49,7 +49,6 @@ register "SataPortsDevSlp[1]" = "1" register "satapwroptimize" = "1" - # Enable Root port 9(x4) for NVMe. register "PcieRpEnable[8]" = "1" # RP 9 uses CLK SRC 1 @@ -57,6 +56,12 @@ # ClkReq-to-ClkSrc mapping for CLK SRC 1 register "PcieClkSrcClkReq[1]" = "1" + # PCIe port 13 for M.2 E-key WLAN + register "PcieRpEnable[13]" = "1" + # RP 13 uses CLK SRC 3 + register "PcieClkSrcUsage[3]" = "13" + register "PcieClkSrcClkReq[3]" = "3" + device domain 0 on device pci 00.0 off end # Host Bridge device pci 02.0 on end # Integrated Graphics Device @@ -119,7 +124,12 @@ device pci 1d.1 off end # PCI Express Port 10 device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 - device pci 1d.4 off end # PCI Express Port 13 (x4) + device pci 1d.4 on + chip drivers/intel/wifi + register "wake" = "GPE0_DW1_01" + device pci 00.0 on end + end + end # PCI Express Port 13 (x4) device pci 1e.0 on end # UART #0 device pci 1e.1 off end # UART #1 device pci 1e.2 on diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index ce78bb5..4a6341f 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -23,6 +23,8 @@ PAD_CFG_GPI_APIC(GPP_A21, NONE, PLTRST, LEVEL, INVERT), /* SRCCLKREQ1 */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), + /* PCIE_14_WLAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), /* H1_SLAVE_SPI_CS_L */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* H1_SLAVE_SPI_CLK */ @@ -31,12 +33,16 @@ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* H1_SLAVE_SPI_MOSI_R */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* PCIE_14_WLAN_WAKE_ODL */ + PAD_CFG_GPI(GPP_C1, NONE, PLTRST), /* TOUCHSCREEN_DIS_L */ PAD_CFG_GPO(GPP_C4, 1, DEEP), /* GPP_C10_TP */ PAD_NC(GPP_C10, DN_20K), /* GPP_C11_TP */ PAD_NC(GPP_C11, DN_20K), + /* BT_DISABLE_L */ + PAD_CFG_GPO(GPP_C14, 1, DEEP), /* PCH_I2C_TRACKPAD_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* PCH_I2C_TRACKPAD_SCL */ @@ -45,12 +51,14 @@ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* PCH_I2C_TOUCHSCREEN_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), - /* H1_PCH_INT_ODL */ - PAD_CFG_GPI_APIC(GPP_C21, NONE, DEEP, LEVEL, INVERT), /* PCH_WP_OD */ PAD_CFG_GPI(GPP_C20, NONE, DEEP), + /* H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, DEEP, LEVEL, INVERT), /* EC_IN_RW_OD */ PAD_CFG_GPI(GPP_C22, NONE, DEEP), + /* WLAN_PE_RST# */ + PAD_CFG_GPO(GPP_C23, 1, DEEP), /* TOUCHSCREEN_RST_L */ PAD_CFG_GPO(GPP_D15, 1, DEEP), /* TOUCHSCREEN_INT_L */ -- To view, visit https://review.coreboot.org/c/coreboot/+/30467 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f2a6eb37a467ad8b8cdde8fe6b657fabb383b04 Gerrit-Change-Number: 30467 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-MessageType: newchange

5 8

Change in ...coreboot[master]: mb/google/hatch: Enable SD card support for hatch
by Maulik V Vaghela (Code Review) 23 Jan '19

23 Jan '19

Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30545 Change subject: mb/google/hatch: Enable SD card support for hatch ...................................................................... mb/google/hatch: Enable SD card support for hatch Enable support for SD card support for hatch 1. Enable PCI device for SD and also configure SD detect GPIO 2. Configure SD card related GPIOs in gpio.c BUG=b:120914069 BRANCH=none TEST=check if code compiles correctly and verify GPIO configuration with schematics Change-Id: I8ccaa28323b1e1fcc192e245347a96309227660b Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/hatch/variants/baseboard/gpio.c 2 files changed, 24 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/30545/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index dc17559..7978b44 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -80,6 +80,9 @@ register "PcieClkSrcUsage[3]" = "13" register "PcieClkSrcClkReq[3]" = "3" + # GPIO for SD card detect + register "sdcard_cd_gpio" = "GPP_G5" + device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device @@ -168,7 +171,7 @@ register "wake" = "GPE0_PME_B0" device pci 14.3 on end # CNVi wifi end - device pci 14.5 off end # SDCard + device pci 14.5 on end # SDCard device pci 15.0 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index 3d63997..5eeddb0 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -19,6 +19,10 @@ #include <commonlib/helpers.h> static const struct pad_config gpio_table[] = { + /* SD_1P8_SEL => NC */ + PAD_NC(GPP_A16, DN_20K), + /* EN_PP3300_SD_DX */ + PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), /* TRACKPAD_INT_ODL */ PAD_CFG_GPI_APIC(GPP_A21, NONE, PLTRST, LEVEL, INVERT), /* SRCCLKREQ1 */ @@ -103,6 +107,22 @@ PAD_CFG_GPI(GPP_F11, NONE, PLTRST), /* PCH_MEM_STRAP3 */ PAD_CFG_GPI(GPP_F22, NONE, PLTRST), + /* SD_CMD */ + PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), + /* SD_DATA0 */ + PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), + /* SD_DATA1 */ + PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), + /* SD_DATA2 */ + PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1), + /* SD_DATA3 */ + PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), + /* SD_CD# */ + PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), + /* SD_CLK */ + PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), + /* SD_WP => NC */ + PAD_NC(GPP_G7, DN_20K), }; const struct pad_config *__weak variant_gpio_table(size_t *num) -- To view, visit https://review.coreboot.org/c/coreboot/+/30545 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ccaa28323b1e1fcc192e245347a96309227660b Gerrit-Change-Number: 30545 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-MessageType: newchange

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