Change in ...coreboot[master]: WIP: mb/qemu-riscv: update to match current qemu version
Philipp Hug has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30554 Change subject: WIP: mb/qemu-riscv: update to match current qemu version ...................................................................... WIP: mb/qemu-riscv: update to match current qemu version Boots again to payload not found on qemu. Change-Id: Ie107eb882cbaac5a5a06c1ff990e7b9364377640 Signed-off-by: Philipp Hug <philipp@hug.cx> --- M src/mainboard/emulation/qemu-riscv/Kconfig M src/mainboard/emulation/qemu-riscv/Makefile.inc M src/mainboard/emulation/qemu-riscv/mainboard.c M src/mainboard/emulation/qemu-riscv/memlayout.ld D src/mainboard/emulation/qemu-riscv/mtime.c M src/mainboard/emulation/qemu-riscv/rom_media.c M src/mainboard/emulation/qemu-riscv/uart.c 7 files changed, 23 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/30554/1 diff --git a/src/mainboard/emulation/qemu-riscv/Kconfig b/src/mainboard/emulation/qemu-riscv/Kconfig index 528b21e..ecaa764 100644 --- a/src/mainboard/emulation/qemu-riscv/Kconfig +++ b/src/mainboard/emulation/qemu-riscv/Kconfig @@ -13,7 +13,8 @@ ## GNU General Public License for more details. # To execute, do: -# qemu-system-arm -M vexpress-a9 -m 1024M -nographic -kernel build/coreboot.rom +# util/riscv/make-spike-elf.sh build/coreboot.rom build/coreboot.elf +# qemu-system-riscv64 -M virt -m 1024M -nographic -kernel build/coreboot.elf if BOARD_EMULATION_QEMU_RISCV diff --git a/src/mainboard/emulation/qemu-riscv/Makefile.inc b/src/mainboard/emulation/qemu-riscv/Makefile.inc index 1d882ac..eb99544 100644 --- a/src/mainboard/emulation/qemu-riscv/Makefile.inc +++ b/src/mainboard/emulation/qemu-riscv/Makefile.inc @@ -14,7 +14,7 @@ bootblock-y += uart.c bootblock-y += rom_media.c -bootblock-y += mtime.c +bootblock-y += clint.c romstage-y += romstage.c romstage-y += uart.c @@ -22,8 +22,10 @@ ramstage-y += uart.c ramstage-y += rom_media.c -ramstage-y += mtime.c +ramstage-y += clint.c bootblock-y += memlayout.ld romstage-y += memlayout.ld ramstage-y += memlayout.ld + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include diff --git a/src/mainboard/emulation/qemu-riscv/mainboard.c b/src/mainboard/emulation/qemu-riscv/mainboard.c index 7061bcf..4b428aa 100644 --- a/src/mainboard/emulation/qemu-riscv/mainboard.c +++ b/src/mainboard/emulation/qemu-riscv/mainboard.c @@ -16,6 +16,7 @@ #include <console/console.h> #include <device/device.h> #include <cbmem.h> +#include <symbols.h> static void mainboard_enable(struct device *dev) { @@ -24,7 +25,7 @@ die("No dev0; die\n"); } - ram_resource(dev, 0, 2048, 32768); + ram_resource(dev, 0, (uintptr_t)_dram / KiB, CONFIG_DRAM_SIZE_MB * KiB); cbmem_recovery(0); } diff --git a/src/mainboard/emulation/qemu-riscv/memlayout.ld b/src/mainboard/emulation/qemu-riscv/memlayout.ld index 615d1f2..032fbdd 100644 --- a/src/mainboard/emulation/qemu-riscv/memlayout.ld +++ b/src/mainboard/emulation/qemu-riscv/memlayout.ld @@ -14,15 +14,16 @@ */ #include <memlayout.h> - #include <arch/header.ld> +#define START 0x80000000 + SECTIONS { - DRAM_START(0x0) - BOOTBLOCK(0x0, 64K) - ROMSTAGE(0x20000, 128K) - STACK(0x40000, 0x3ff00) - PRERAM_CBMEM_CONSOLE(0x80000, 8K) - RAMSTAGE(0x100000, 16M) + DRAM_START(START) + BOOTBLOCK(START, 64K) + STACK(START + 4M, 4K) + ROMSTAGE(START + 4M + 64K, 128K) + PRERAM_CBMEM_CONSOLE(START + 4M + 192K, 8K) + RAMSTAGE(START + 4M + 200K, 16M) } diff --git a/src/mainboard/emulation/qemu-riscv/mtime.c b/src/mainboard/emulation/qemu-riscv/mtime.c deleted file mode 100644 index f8c2717..0000000 --- a/src/mainboard/emulation/qemu-riscv/mtime.c +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 HardenedLinux - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <mcall.h> - -/* FIXME: This is an empty implementation, please improve */ -/* This function is used to initialize HLS()->time/HLS()->timecmp */ -void mtime_init(void) -{ -} diff --git a/src/mainboard/emulation/qemu-riscv/rom_media.c b/src/mainboard/emulation/qemu-riscv/rom_media.c index c171307..bac1984 100644 --- a/src/mainboard/emulation/qemu-riscv/rom_media.c +++ b/src/mainboard/emulation/qemu-riscv/rom_media.c @@ -14,11 +14,12 @@ * GNU General Public License for more details. */ #include <boot_device.h> +#include <symbols.h> -/* This assumes that the CBFS resides at 0x0, which is true for the default - * configuration. */ +/* This assumes that the CBFS resides at start of dram, which is true for the + * default configuration. */ static const struct mem_region_device boot_dev = - MEM_REGION_DEV_RO_INIT(NULL, CONFIG_ROM_SIZE); + MEM_REGION_DEV_RO_INIT(_dram, CONFIG_ROM_SIZE); const struct region_device *boot_device_ro(void) { diff --git a/src/mainboard/emulation/qemu-riscv/uart.c b/src/mainboard/emulation/qemu-riscv/uart.c index 730ef3e..084362a 100644 --- a/src/mainboard/emulation/qemu-riscv/uart.c +++ b/src/mainboard/emulation/qemu-riscv/uart.c @@ -17,8 +17,9 @@ #include <console/uart.h> #include <arch/io.h> #include <boot/coreboot_tables.h> +#include <mainboard/addressmap.h> -static uint8_t *buf = (void *)0x3f8; +static uint8_t *buf = (void *)QEMU_VIRT_UART0; uintptr_t uart_platform_base(int idx) { return (uintptr_t) buf; @@ -47,7 +48,7 @@ { struct lb_serial serial; serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; - serial.baseaddr = 0x3f8; + serial.baseaddr = QEMU_VIRT_UART0; serial.baud = 115200; serial.regwidth = 1; lb_add_serial(&serial, data); -- To view, visit https://review.coreboot.org/c/coreboot/+/30554 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie107eb882cbaac5a5a06c1ff990e7b9364377640 Gerrit-Change-Number: 30554 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Hug <philipp@hug.cx> Gerrit-MessageType: newchange
ron minnich has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30554 ) Change subject: WIP: mb/qemu-riscv: update to match current qemu version ...................................................................... Patch Set 3: (1 comment) If you can fix this include I think this is fine. https://review.coreboot.org/#/c/30554/3/src/mainboard/emulation/qemu-riscv/c... File src/mainboard/emulation/qemu-riscv/clint.c: https://review.coreboot.org/#/c/30554/3/src/mainboard/emulation/qemu-riscv/c... PS3, Line 23: HLS()->time = (uint64_t *)(QEMU_VIRT_CLINT + 0xbff8);
that's not common for coreboot […] it's a regrettable riscv convention but I think we should accept it.
-- To view, visit https://review.coreboot.org/c/coreboot/+/30554 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie107eb882cbaac5a5a06c1ff990e7b9364377640 Gerrit-Change-Number: 30554 Gerrit-PatchSet: 3 Gerrit-Owner: Philipp Hug <philipp@hug.cx> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Gerrit-Reviewer: Julius Werner <jwerner@chromium.org> Gerrit-Reviewer: Martin Roth <martinroth@google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com> Gerrit-Reviewer: Philipp Hug <philipp@hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-Reviewer: ron minnich <rminnich@gmail.com> Gerrit-CC: Patrick Rudolph <siro@das-labor.org> Gerrit-Comment-Date: Fri, 25 Jan 2019 22:48:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <siro@das-labor.org> Gerrit-MessageType: comment
Hello ron minnich, Julius Werner, Jonathan Neuschäfer, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/30554 to look at the new patch set (#4). Change subject: mb/qemu-riscv: update to match current qemu version ...................................................................... mb/qemu-riscv: update to match current qemu version Boots again to payload not found on qemu. Change-Id: Ie107eb882cbaac5a5a06c1ff990e7b9364377640 Signed-off-by: Philipp Hug <philipp@hug.cx> --- A Documentation/mainboard/emulation/qemu-riscv.md M Documentation/mainboard/index.md M src/mainboard/emulation/qemu-riscv/Kconfig M src/mainboard/emulation/qemu-riscv/Makefile.inc R src/mainboard/emulation/qemu-riscv/clint.c C src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h M src/mainboard/emulation/qemu-riscv/mainboard.c M src/mainboard/emulation/qemu-riscv/memlayout.ld M src/mainboard/emulation/qemu-riscv/rom_media.c M src/mainboard/emulation/qemu-riscv/uart.c 10 files changed, 42 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/30554/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/30554 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie107eb882cbaac5a5a06c1ff990e7b9364377640 Gerrit-Change-Number: 30554 Gerrit-PatchSet: 4 Gerrit-Owner: Philipp Hug <philipp@hug.cx> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Gerrit-Reviewer: Julius Werner <jwerner@chromium.org> Gerrit-Reviewer: Martin Roth <martinroth@google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com> Gerrit-Reviewer: Philipp Hug <philipp@hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-Reviewer: ron minnich <rminnich@gmail.com> Gerrit-CC: Patrick Rudolph <siro@das-labor.org> Gerrit-MessageType: newpatchset
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30554 ) Change subject: mb/qemu-riscv: update to match current qemu version ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/30554 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie107eb882cbaac5a5a06c1ff990e7b9364377640 Gerrit-Change-Number: 30554 Gerrit-PatchSet: 4 Gerrit-Owner: Philipp Hug <philipp@hug.cx> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Gerrit-Reviewer: Julius Werner <jwerner@chromium.org> Gerrit-Reviewer: Martin Roth <martinroth@google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com> Gerrit-Reviewer: Philipp Hug <philipp@hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-Reviewer: ron minnich <rminnich@gmail.com> Gerrit-CC: Patrick Rudolph <siro@das-labor.org> Gerrit-Comment-Date: Sat, 26 Jan 2019 13:40:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30554 ) Change subject: mb/qemu-riscv: update to match current qemu version ...................................................................... mb/qemu-riscv: update to match current qemu version Boots again to payload not found on qemu. Change-Id: Ie107eb882cbaac5a5a06c1ff990e7b9364377640 Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/c/30554 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> --- A Documentation/mainboard/emulation/qemu-riscv.md M Documentation/mainboard/index.md M src/mainboard/emulation/qemu-riscv/Kconfig M src/mainboard/emulation/qemu-riscv/Makefile.inc R src/mainboard/emulation/qemu-riscv/clint.c C src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h M src/mainboard/emulation/qemu-riscv/mainboard.c M src/mainboard/emulation/qemu-riscv/memlayout.ld M src/mainboard/emulation/qemu-riscv/rom_media.c M src/mainboard/emulation/qemu-riscv/uart.c 10 files changed, 42 insertions(+), 25 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved diff --git a/Documentation/mainboard/emulation/qemu-riscv.md b/Documentation/mainboard/emulation/qemu-riscv.md new file mode 100644 index 0000000..3aad816 --- /dev/null +++ b/Documentation/mainboard/emulation/qemu-riscv.md @@ -0,0 +1,8 @@ +# Qemu RISC-V emulator + +## Building coreboot and running it in Qemu + +- Configure coreboot and run `make` as usual +- Run `util/riscv/make-spike-elf.sh build/coreboot.rom build/coreboot.elf` to + convert coreboot to an ELF that Qemu can load +- Run `qemu-system-riscv64 -M virt -m 1024M -nographic -kernel build/coreboot.elf` diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 93ee828..d8d3b76 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -19,6 +19,7 @@ The boards in this section are not real mainboards, but emulators. - [Spike RISC-V emulator](emulation/spike-riscv.md) +- [Qemu RISC-V emulator](emulation/qemu-riscv.md) ## Intel diff --git a/src/mainboard/emulation/qemu-riscv/Kconfig b/src/mainboard/emulation/qemu-riscv/Kconfig index 528b21e..ecaa764 100644 --- a/src/mainboard/emulation/qemu-riscv/Kconfig +++ b/src/mainboard/emulation/qemu-riscv/Kconfig @@ -13,7 +13,8 @@ ## GNU General Public License for more details. # To execute, do: -# qemu-system-arm -M vexpress-a9 -m 1024M -nographic -kernel build/coreboot.rom +# util/riscv/make-spike-elf.sh build/coreboot.rom build/coreboot.elf +# qemu-system-riscv64 -M virt -m 1024M -nographic -kernel build/coreboot.elf if BOARD_EMULATION_QEMU_RISCV diff --git a/src/mainboard/emulation/qemu-riscv/Makefile.inc b/src/mainboard/emulation/qemu-riscv/Makefile.inc index 1d882ac..eb99544 100644 --- a/src/mainboard/emulation/qemu-riscv/Makefile.inc +++ b/src/mainboard/emulation/qemu-riscv/Makefile.inc @@ -14,7 +14,7 @@ bootblock-y += uart.c bootblock-y += rom_media.c -bootblock-y += mtime.c +bootblock-y += clint.c romstage-y += romstage.c romstage-y += uart.c @@ -22,8 +22,10 @@ ramstage-y += uart.c ramstage-y += rom_media.c -ramstage-y += mtime.c +ramstage-y += clint.c bootblock-y += memlayout.ld romstage-y += memlayout.ld ramstage-y += memlayout.ld + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include diff --git a/src/mainboard/emulation/qemu-riscv/mtime.c b/src/mainboard/emulation/qemu-riscv/clint.c similarity index 77% rename from src/mainboard/emulation/qemu-riscv/mtime.c rename to src/mainboard/emulation/qemu-riscv/clint.c index f8c2717..367d48d 100644 --- a/src/mainboard/emulation/qemu-riscv/mtime.c +++ b/src/mainboard/emulation/qemu-riscv/clint.c @@ -14,9 +14,12 @@ */ #include <mcall.h> +#include <mainboard/addressmap.h> -/* FIXME: This is an empty implementation, please improve */ /* This function is used to initialize HLS()->time/HLS()->timecmp */ void mtime_init(void) { + long hart_id = read_csr(mhartid); + HLS()->time = (uint64_t *)(QEMU_VIRT_CLINT + 0xbff8); + HLS()->timecmp = (uint64_t *)(QEMU_VIRT_CLINT + 0x4000 + 8 * hart_id); } diff --git a/src/mainboard/emulation/qemu-riscv/mtime.c b/src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h similarity index 70% copy from src/mainboard/emulation/qemu-riscv/mtime.c copy to src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h index f8c2717..fd8c136 100644 --- a/src/mainboard/emulation/qemu-riscv/mtime.c +++ b/src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 HardenedLinux + * Copyright (C) 2018 Philipp Hug * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -13,10 +13,8 @@ * GNU General Public License for more details. */ -#include <mcall.h> - -/* FIXME: This is an empty implementation, please improve */ -/* This function is used to initialize HLS()->time/HLS()->timecmp */ -void mtime_init(void) -{ -} +#define QEMU_VIRT_CLINT 0x02000000 +#define QEMU_VIRT_PLIC 0x0c000000 +#define QEMU_VIRT_UART0 0x10000000 +#define QEMU_VIRT_VIRTIO 0x10001000 +#define QEMU_VIRT_DRAM 0x80000000 diff --git a/src/mainboard/emulation/qemu-riscv/mainboard.c b/src/mainboard/emulation/qemu-riscv/mainboard.c index 7061bcf..4b428aa 100644 --- a/src/mainboard/emulation/qemu-riscv/mainboard.c +++ b/src/mainboard/emulation/qemu-riscv/mainboard.c @@ -16,6 +16,7 @@ #include <console/console.h> #include <device/device.h> #include <cbmem.h> +#include <symbols.h> static void mainboard_enable(struct device *dev) { @@ -24,7 +25,7 @@ die("No dev0; die\n"); } - ram_resource(dev, 0, 2048, 32768); + ram_resource(dev, 0, (uintptr_t)_dram / KiB, CONFIG_DRAM_SIZE_MB * KiB); cbmem_recovery(0); } diff --git a/src/mainboard/emulation/qemu-riscv/memlayout.ld b/src/mainboard/emulation/qemu-riscv/memlayout.ld index 615d1f2..032fbdd 100644 --- a/src/mainboard/emulation/qemu-riscv/memlayout.ld +++ b/src/mainboard/emulation/qemu-riscv/memlayout.ld @@ -14,15 +14,16 @@ */ #include <memlayout.h> - #include <arch/header.ld> +#define START 0x80000000 + SECTIONS { - DRAM_START(0x0) - BOOTBLOCK(0x0, 64K) - ROMSTAGE(0x20000, 128K) - STACK(0x40000, 0x3ff00) - PRERAM_CBMEM_CONSOLE(0x80000, 8K) - RAMSTAGE(0x100000, 16M) + DRAM_START(START) + BOOTBLOCK(START, 64K) + STACK(START + 4M, 4K) + ROMSTAGE(START + 4M + 64K, 128K) + PRERAM_CBMEM_CONSOLE(START + 4M + 192K, 8K) + RAMSTAGE(START + 4M + 200K, 16M) } diff --git a/src/mainboard/emulation/qemu-riscv/rom_media.c b/src/mainboard/emulation/qemu-riscv/rom_media.c index c171307..bac1984 100644 --- a/src/mainboard/emulation/qemu-riscv/rom_media.c +++ b/src/mainboard/emulation/qemu-riscv/rom_media.c @@ -14,11 +14,12 @@ * GNU General Public License for more details. */ #include <boot_device.h> +#include <symbols.h> -/* This assumes that the CBFS resides at 0x0, which is true for the default - * configuration. */ +/* This assumes that the CBFS resides at start of dram, which is true for the + * default configuration. */ static const struct mem_region_device boot_dev = - MEM_REGION_DEV_RO_INIT(NULL, CONFIG_ROM_SIZE); + MEM_REGION_DEV_RO_INIT(_dram, CONFIG_ROM_SIZE); const struct region_device *boot_device_ro(void) { diff --git a/src/mainboard/emulation/qemu-riscv/uart.c b/src/mainboard/emulation/qemu-riscv/uart.c index 730ef3e..084362a 100644 --- a/src/mainboard/emulation/qemu-riscv/uart.c +++ b/src/mainboard/emulation/qemu-riscv/uart.c @@ -17,8 +17,9 @@ #include <console/uart.h> #include <arch/io.h> #include <boot/coreboot_tables.h> +#include <mainboard/addressmap.h> -static uint8_t *buf = (void *)0x3f8; +static uint8_t *buf = (void *)QEMU_VIRT_UART0; uintptr_t uart_platform_base(int idx) { return (uintptr_t) buf; @@ -47,7 +48,7 @@ { struct lb_serial serial; serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; - serial.baseaddr = 0x3f8; + serial.baseaddr = QEMU_VIRT_UART0; serial.baud = 115200; serial.regwidth = 1; lb_add_serial(&serial, data); -- To view, visit https://review.coreboot.org/c/coreboot/+/30554 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie107eb882cbaac5a5a06c1ff990e7b9364377640 Gerrit-Change-Number: 30554 Gerrit-PatchSet: 5 Gerrit-Owner: Philipp Hug <philipp@hug.cx> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Gerrit-Reviewer: Julius Werner <jwerner@chromium.org> Gerrit-Reviewer: Martin Roth <martinroth@google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com> Gerrit-Reviewer: Philipp Hug <philipp@hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-Reviewer: ron minnich <rminnich@gmail.com> Gerrit-CC: Patrick Rudolph <siro@das-labor.org> Gerrit-MessageType: merged
Jonathan Neuschäfer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30554 ) Change subject: mb/qemu-riscv: update to match current qemu version ...................................................................... Patch Set 5: Code-Review+1 (2 comments) Looks good (haven't tested it, though) https://review.coreboot.org/#/c/30554/5/src/mainboard/emulation/qemu-riscv/K... File src/mainboard/emulation/qemu-riscv/Kconfig: https://review.coreboot.org/#/c/30554/5/src/mainboard/emulation/qemu-riscv/K... PS5, Line 16: # util/riscv/make-spike-elf.sh build/coreboot.rom build/coreboot.elf Unnecessary, because we have Documentation/**/*.md https://review.coreboot.org/#/c/30554/5/src/mainboard/emulation/qemu-riscv/u... File src/mainboard/emulation/qemu-riscv/uart.c: https://review.coreboot.org/#/c/30554/5/src/mainboard/emulation/qemu-riscv/u... PS5, Line 21: : static uint8_t *buf = (void *)QEMU_VIRT_UART0; : uintptr_t uart_platform_base(int idx) : { : Could we use the common driver for memory-mapped 8250 here? -- To view, visit https://review.coreboot.org/c/coreboot/+/30554 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie107eb882cbaac5a5a06c1ff990e7b9364377640 Gerrit-Change-Number: 30554 Gerrit-PatchSet: 5 Gerrit-Owner: Philipp Hug <philipp@hug.cx> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Gerrit-Reviewer: Julius Werner <jwerner@chromium.org> Gerrit-Reviewer: Martin Roth <martinroth@google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com> Gerrit-Reviewer: Philipp Hug <philipp@hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-Reviewer: ron minnich <rminnich@gmail.com> Gerrit-CC: Patrick Rudolph <siro@das-labor.org> Gerrit-Comment-Date: Sat, 02 Feb 2019 17:05:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment
participants (4)
-
Jonathan Neuschäfer (Code Review) -
Patrick Georgi (Code Review)
-
Philipp Hug (Code Review)
-
ron minnich (Code Review)