Philipp Hug has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31201
Change subject: riscv: Show hart id in trap handler ......................................................................
riscv: Show hart id in trap handler
Also show hart id in trap information for easier debugging.
Change-Id: I20acf86e1af111600c158295ae03b2167838d127 Signed-off-by: Philipp Hug philipp@hug.cx --- M src/arch/riscv/trap_handler.c 1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/31201/1
diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c index e072bf7..6ec8e19 100644 --- a/src/arch/riscv/trap_handler.c +++ b/src/arch/riscv/trap_handler.c @@ -57,6 +57,7 @@ { const char *previous_mode; bool mprv = !!(tf->status & MSTATUS_MPRV); + int hart_id = read_csr(mhartid);
/* Leave some space around the trap message */ printk(BIOS_DEBUG, "\n"); @@ -69,6 +70,7 @@ (void *)tf->cause);
previous_mode = mstatus_to_previous_mode(read_csr(mstatus)); + printk(BIOS_DEBUG, "Hart ID: %d\n", hart_id); printk(BIOS_DEBUG, "Previous mode: %s%s\n", previous_mode, mprv? " (MPRV)":""); printk(BIOS_DEBUG, "Bad instruction pc: %p\n", (void *)tf->epc);
ron minnich has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31201 )
Change subject: riscv: Show hart id in trap handler ......................................................................
Patch Set 1: Code-Review+2
ron minnich has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31201 )
Change subject: riscv: Show hart id in trap handler ......................................................................
riscv: Show hart id in trap handler
Also show hart id in trap information for easier debugging.
Change-Id: I20acf86e1af111600c158295ae03b2167838d127 Signed-off-by: Philipp Hug philipp@hug.cx Reviewed-on: https://review.coreboot.org/c/31201 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: ron minnich rminnich@gmail.com --- M src/arch/riscv/trap_handler.c 1 file changed, 2 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified ron minnich: Looks good to me, approved
diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c index e072bf7..6ec8e19 100644 --- a/src/arch/riscv/trap_handler.c +++ b/src/arch/riscv/trap_handler.c @@ -57,6 +57,7 @@ { const char *previous_mode; bool mprv = !!(tf->status & MSTATUS_MPRV); + int hart_id = read_csr(mhartid);
/* Leave some space around the trap message */ printk(BIOS_DEBUG, "\n"); @@ -69,6 +70,7 @@ (void *)tf->cause);
previous_mode = mstatus_to_previous_mode(read_csr(mstatus)); + printk(BIOS_DEBUG, "Hart ID: %d\n", hart_id); printk(BIOS_DEBUG, "Previous mode: %s%s\n", previous_mode, mprv? " (MPRV)":""); printk(BIOS_DEBUG, "Bad instruction pc: %p\n", (void *)tf->epc);
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Philipp Hug (Code Review) -
ron minnich (Code Review)