coreboot-gerrit May 2019

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Change in ...coreboot[master]: ec/quanta/it8518: Use ACPI EC code
by James (Code Review) 07 Aug '23

07 Aug '23

James has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31382 Change subject: ec/quanta/it8518: Use ACPI EC code ...................................................................... ec/quanta/it8518: Use ACPI EC code ec/quanta/it8518 implements its own code for reading and writing the EC. As a result, it cannot be used with ec/acpi. ec/quanta/it8518 contains definitions that are useful for mb/thinkpad/x131e, however, x131e uses ec/acpi. This replaces functions and definitions in ec/quanta/it8518 with their equivalents in ec/acpi. TODO: test on google/stout Change-Id: I7bea7445f34817cef1602843bbded59230bb8d47 Signed-off-by: James Ye <jye836(a)gmail.com> --- M src/ec/quanta/it8518/Kconfig M src/ec/quanta/it8518/ec.c M src/ec/quanta/it8518/ec.h M src/mainboard/google/stout/chromeos.c M src/mainboard/google/stout/ec.c M src/mainboard/google/stout/mainboard.c M src/mainboard/google/stout/mainboard_smi.c M src/mainboard/google/stout/romstage.c 8 files changed, 17 insertions(+), 59 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/31382/1 diff --git a/src/ec/quanta/it8518/Kconfig b/src/ec/quanta/it8518/Kconfig index 24ac36f..caaccd5 100644 --- a/src/ec/quanta/it8518/Kconfig +++ b/src/ec/quanta/it8518/Kconfig @@ -1,4 +1,5 @@ config EC_QUANTA_IT8518 + select EC_ACPI bool help Interface to QUANTA IT8518 Embedded Controller. diff --git a/src/ec/quanta/it8518/ec.c b/src/ec/quanta/it8518/ec.c index e293f7c..a27e7b9 100644 --- a/src/ec/quanta/it8518/ec.c +++ b/src/ec/quanta/it8518/ec.c @@ -19,6 +19,7 @@ #include <delay.h> #include <device/device.h> #include <device/pnp.h> +#include <ec/acpi/ec.h> #include <pc80/keyboard.h> #include <stdlib.h> @@ -93,48 +94,16 @@ * These functions are for accessing the IT8518 device RAM space via 0x66/0x68 */ -u8 ec_read_ob(void) -{ - if (!output_buffer_full(EC_SC)) return 0; - return inb(EC_DATA); -} - -void ec_write_cmd(u8 cmd) -{ - if (!input_buffer_empty(EC_SC)) return; - outb(cmd, EC_SC); -} - -void ec_write_ib(u8 data) -{ - if (!input_buffer_empty(EC_SC)) return; - outb(data, EC_DATA); -} - -u8 ec_read(u16 addr) -{ - ec_write_cmd(RD_EC); - ec_write_ib(addr); - return ec_read_ob(); -} - -void ec_write(u16 addr, u8 data) -{ - ec_write_cmd(WR_EC); - ec_write_ib(addr); - ec_write_ib(data); -} - #ifndef __PRE_RAM__ u8 ec_it8518_get_event(void) { u8 cmd = 0; u8 status = inb(EC_SC); - if (status & SCI_EVT) { - ec_write_cmd(QR_EC); - cmd = ec_read_ob(); - } else if (status & SMI_EVT) { + if (status & EC_SCI_EVT) { + send_ec_command(QR_EC); + cmd = recv_ec_data(); + } else if (status & EC_SMI_EVT) { ec_kbc_write_cmd(EC_KBD_SMI_EVENT); cmd = ec_kbc_read_ob(); } diff --git a/src/ec/quanta/it8518/ec.h b/src/ec/quanta/it8518/ec.h index 6fca3b9..27f9137 100644 --- a/src/ec/quanta/it8518/ec.h +++ b/src/ec/quanta/it8518/ec.h @@ -43,17 +43,6 @@ void ec_kbc_write_cmd(u8 cmd); void ec_kbc_write_ib(u8 data); -// 62h/66h Command Interface -#define EC_DATA 0x62 -#define EC_SC 0x66 // Status & Control Register -#define SMI_EVT (1 << 6) // 1: SMI event was triggered -#define SCI_EVT (1 << 5) // 1: SCI event was triggered - -// EC Commands (defined in ec_function_spec v3.12) -#define RD_EC 0x80 -#define WR_EC 0x81 -#define QR_EC 0x84 - #define EC_CMD_EXIT_BOOT_BLOCK 0x85 #define EC_CMD_NOTIFY_ACPI_ENTER 0x86 #define EC_CMD_NOTIFY_ACPI_EXIT 0x87 @@ -63,13 +52,13 @@ #define EC_PERIPH_CNTL_3 0x0D #define EC_USB_S3_EN 0x26 #define EC_PERIPH_STAT_3 0x35 +#define EC_MBAT_STATUS 0x38 #define EC_THERM_0 0x78 #define EC_WAKE_SRC_ENABLE 0xBF #define EC_FW_VER 0xE8 // 2 Bytes #define EC_IF_MIN_VER 0xEB #define EC_STATUS_REG 0xEC #define EC_IF_MAJ_VER 0xEF -#define EC_MBAT_STATUS 0x0138 // EC 0.83b added status bits: @@ -81,12 +70,6 @@ // EC 0.86a added enable bit: #define EC_LID_WAKE_ENABLE 0x4 -u8 ec_read_ob(void); -void ec_write_cmd(u8 cmd); -void ec_write_ib(u8 data); - -u8 ec_read(u16 addr); -void ec_write(u16 addr, u8 data); u8 ec_it8518_get_event(void); void ec_it8518_enable_wake_events(void); diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c index 5301d30..f7f54c1 100644 --- a/src/mainboard/google/stout/chromeos.c +++ b/src/mainboard/google/stout/chromeos.c @@ -24,6 +24,7 @@ #include <southbridge/intel/common/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> #include "ec.h" +#include <ec/acpi/ec.h> #include <ec/quanta/it8518/ec.h> #ifndef __PRE_RAM__ diff --git a/src/mainboard/google/stout/ec.c b/src/mainboard/google/stout/ec.c index 229f919..11cdc2a 100644 --- a/src/mainboard/google/stout/ec.c +++ b/src/mainboard/google/stout/ec.c @@ -18,6 +18,7 @@ #include <bootmode.h> #include <types.h> #include <console/console.h> +#include <ec/acpi/ec.h> #include <ec/quanta/it8518/ec.h> #include <device/device.h> #include <device/pci.h> diff --git a/src/mainboard/google/stout/mainboard.c b/src/mainboard/google/stout/mainboard.c index b63083f..63cc67b 100644 --- a/src/mainboard/google/stout/mainboard.c +++ b/src/mainboard/google/stout/mainboard.c @@ -29,13 +29,14 @@ #include <southbridge/intel/bd82x6x/pch.h> #include <smbios.h> #include <device/pci.h> +#include <ec/acpi/ec.h> #include <ec/quanta/it8518/ec.h> #include <vendorcode/google/chromeos/chromeos.h> void mainboard_suspend_resume(void) { /* Stout EC needs to be put back in ACPI mode */ - ec_write_cmd(EC_CMD_NOTIFY_ACPI_ENTER); + send_ec_command(EC_CMD_NOTIFY_ACPI_ENTER); } diff --git a/src/mainboard/google/stout/mainboard_smi.c b/src/mainboard/google/stout/mainboard_smi.c index 6a51645..27eae19 100644 --- a/src/mainboard/google/stout/mainboard_smi.c +++ b/src/mainboard/google/stout/mainboard_smi.c @@ -24,6 +24,7 @@ #include <cpu/intel/model_206ax/model_206ax.h> /* Include EC functions */ +#include <ec/acpi/ec.h> #include <ec/quanta/it8518/ec.h> #include "ec.h" @@ -96,13 +97,13 @@ /* * TODO(kimarie) Clear all pending events and enable SCI. */ - ec_write_cmd(EC_CMD_NOTIFY_ACPI_ENTER); + send_ec_command(EC_CMD_NOTIFY_ACPI_ENTER); break; case APMC_ACPI_DIS: /* * TODO(kimarie) Clear all pending events and enable SMI. */ - ec_write_cmd(EC_CMD_NOTIFY_ACPI_EXIT); + send_ec_command(EC_CMD_NOTIFY_ACPI_EXIT); break; } return 0; diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c index d212951..66eb953 100644 --- a/src/mainboard/google/stout/romstage.c +++ b/src/mainboard/google/stout/romstage.c @@ -29,6 +29,7 @@ #include <southbridge/intel/common/gpio.h> #include <halt.h> #include <bootmode.h> +#include <ec/acpi/ec.h> #include <ec/quanta/it8518/ec.h> #include "ec.h" #include "onboard.h" @@ -121,12 +122,12 @@ * Tell EC to exit RO mode */ printk(BIOS_DEBUG, "EC will exit RO mode and boot normally\n"); - ec_write_cmd(EC_CMD_EXIT_BOOT_BLOCK); + send_ec_command(EC_CMD_EXIT_BOOT_BLOCK); die("wait for ec to reset"); } } else { printk(BIOS_DEBUG, "EC Warm Boot Detected\n"); - ec_write_cmd(EC_CMD_WARM_RESET); + send_ec_command(EC_CMD_WARM_RESET); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/31382 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7bea7445f34817cef1602843bbded59230bb8d47 Gerrit-Change-Number: 31382 Gerrit-PatchSet: 1 Gerrit-Owner: James <jye836(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Patch SSDTs into qemu, and add VPD area to the fmap for q35 as a proo...
by John Looney (Code Review) 07 Aug '23

07 Aug '23

John Looney has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32087 Change subject: Patch SSDTs into qemu, and add VPD area to the fmap for q35 as a proof of concept ...................................................................... Patch SSDTs into qemu, and add VPD area to the fmap for q35 as a proof of concept Signed-off-by: John Looney <john.looney(a)gmail.com> Change-Id: I4678b9adc8044a691c818527e2c16205f9b259e2 --- A src/mainboard/emulation/qemu-q35/board.fmd 1 file changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/32087/1 diff --git a/src/mainboard/emulation/qemu-q35/board.fmd b/src/mainboard/emulation/qemu-q35/board.fmd new file mode 100644 index 0000000..a97e218 --- /dev/null +++ b/src/mainboard/emulation/qemu-q35/board.fmd @@ -0,0 +1,16 @@ +# layout for firmware residing at top of 4GB address space +# +-------------+ <-- 4GB - ROM_SIZE / start of flash +# | unspecified | +# +-------------+ <-- 4GB - BIOS_SIZE +# | FMAP | +# +-------------+ <-- 4GB - BIOS_SIZE + FMAP_SIZE +# | CBFS | +# +-------------+ <-- 4GB / end of flash +FLASH@4278190080 0x1000000 { + BIOS@0 0x1000000 { + FMAP@0 0x200 + RO_VPD@0x200 0x10000 + RW_VPD@0x10200 0x1000 + COREBOOT(CBFS)@0x11200 + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/32087 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4678b9adc8044a691c818527e2c16205f9b259e2 Gerrit-Change-Number: 32087 Gerrit-PatchSet: 1 Gerrit-Owner: John Looney <john.looney(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/arch: This is an upgrade of SMBIOS to latest version 3.2
by Francois Toguo Fotso (Code Review) 07 Aug '23

07 Aug '23

Francois Toguo Fotso has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32090 Change subject: src/arch: This is an upgrade of SMBIOS to latest version 3.2 ...................................................................... src/arch: This is an upgrade of SMBIOS to latest version 3.2 This is the second of 2 patches upgrading the SMBIOS interface to the latest 3.2 First patch is in mosys. Newer required fields are added to various types definitions BUG=NONE TEST=Boot to OS on GLK Sparky Change-Id: I1171c20ac85a2231d949d4ac1c3e3c544ba3e5ef Signed-off-by: Francois Toguo <francois.toguo.fotso(a)intel.com> --- M src/arch/x86/smbios.c M src/include/smbios.h 2 files changed, 71 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/32090/1 diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 8cb59df..b82780d 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -328,6 +328,17 @@ t->handle = *handle; *handle += 1; t->length = sizeof(struct smbios_type17) - 2; + t->memory_technology = MEMORY_TECHNOLOGY_UNKNOWN; + t->operating_mode_capability = MEMORY_OPERATING_MODE_CAP_UNKNOWN; + t->fw_version = 0xff; + t->manufacturer_id = dimm->mod_id; + t->product_id = 0x0000; + t->sub_ctrl_manufacturer_id = 0x0000; + t->sub_ctrl_product_id = 0x0000; + t->non_volatile_size = 0xffffffffffffffff; + t->volatile_size = 0xffffffffffffffff; + t->cache_size = 0xffffffffffffffff; + t->logical_size = 0xffffffffffffffff; return t->length + smbios_string_table_len(t->eos); } @@ -547,9 +558,31 @@ return len; } +u16 __weak smbios_processor_core_thread_count(u16 level_type) +{ + u16 count = 0; + int ecx = 0; + + for (ecx = 0 ; ecx < 255 ; ecx++) { + struct cpuid_result leaf_b; + leaf_b = cpuid_ext(0xb, ecx); + if ((cpuid_eax(0) < 0xb) || + !(leaf_b.eax | leaf_b.ebx | leaf_b.ecx | leaf_b.edx)) + return (((cpuid(1).ebx) >> 16) & 0x00ff); + + if ((leaf_b.ecx & 0xff00) == level_type) { + count = leaf_b.ebx & 0xffff; + break; + } + } + + return count; +} + static int smbios_write_type4(unsigned long *current, int handle) { struct cpuid_result res; + u16 core_count = 0, thread_count = 0; struct smbios_type4 *t = (struct smbios_type4 *)*current; int len = sizeof(struct smbios_type4); @@ -570,7 +603,15 @@ t->processor_version = smbios_processor_name(t->eos); t->processor_family = (res.eax > 0) ? 0x0c : 0x6; t->processor_type = 3; /* System Processor */ - t->core_count = (res.ebx >> 16) & 0xff; + + core_count = smbios_processor_core_thread_count(PROC_CORE_TYPE); + thread_count = smbios_processor_core_thread_count(PROC_THREAD_TYPE); + t->core_count2 = core_count; + t->core_count = (core_count > BYTE_LIMIT) ? 0xff : core_count; + t->thread_count2 = thread_count; + t->thread_count = (thread_count > BYTE_LIMIT) ? 0xff : core_count; + t->core_enabled2 = core_count; + t->l1_cache_handle = 0xffff; t->l2_cache_handle = 0xffff; t->l3_cache_handle = 0xffff; diff --git a/src/include/smbios.h b/src/include/smbios.h index af83bfe..e1d71be 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -52,6 +52,10 @@ u8 smbios_mainboard_feature_flags(void); const char *smbios_mainboard_location_in_chassis(void); u8 smbios_mainboard_enclosure_type(void); +u16 smbios_processor_core_thread_count(u16 level_type); +#ifdef CONFIG_MAINBOARD_FAMILY +const char *smbios_mainboard_family(void); +#endif #define BIOS_CHARACTERISTICS_PCI_SUPPORTED (1 << 7) #define BIOS_CHARACTERISTICS_PC_CARD (1 << 8) @@ -100,6 +104,11 @@ #define MEMORY_OPERATING_MODE_CAP_BYTE_ACCESS_PERSISTENT (1 << 4) #define MEMORY_OPERATING_MODE_CAP_BLOCK_ACCESS_PERSISTENT (1 << 5) +#define PROC_THREAD_TYPE 0x1 +#define PROC_CORE_TYPE 0x2 + +#define BYTE_LIMIT 255 + typedef enum { MEMORY_BUS_WIDTH_8 = 0, MEMORY_BUS_WIDTH_16 = 1, @@ -299,6 +308,7 @@ u8 location_in_chassis; u16 chassis_handle; u8 board_type; + u8 num_cont_obj_handles; u8 eos[2]; } __packed; @@ -390,6 +400,9 @@ u8 thread_count; u16 processor_characteristics; u16 processor_family2; + u16 core_count2; + u16 core_enabled2; + u16 thread_count2; u8 eos[2]; } __packed; @@ -401,6 +414,11 @@ u8 eos[2]; } __packed; +typedef struct { + u8 type; + u8 format_descriptor; +} log_type_descriptor; + struct smbios_type15 { u8 type; u8 length; @@ -471,6 +489,17 @@ u16 minimum_voltage; u16 maximum_voltage; u16 configured_voltage; + u8 memory_technology; + u16 operating_mode_capability; + u8 fw_version; + u16 manufacturer_id; + u16 product_id; + u16 sub_ctrl_manufacturer_id; + u16 sub_ctrl_product_id; + u64 non_volatile_size; + u64 volatile_size; + u64 cache_size; + u64 logical_size; u8 eos[2]; } __packed; -- To view, visit https://review.coreboot.org/c/coreboot/+/32090 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1171c20ac85a2231d949d4ac1c3e3c544ba3e5ef Gerrit-Change-Number: 32090 Gerrit-PatchSet: 1 Gerrit-Owner: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Documentation: Document PMH known registers
by Patrick Rudolph (Code Review) 07 Aug '23

07 Aug '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32253 Change subject: Documentation: Document PMH known registers ...................................................................... Documentation: Document PMH known registers Document what is known of Lenovo's PMH. Change-Id: I1891a6370123d9ee29d9e37e4b7b78b677343aed Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M Documentation/mainboard/index.md A Documentation/mainboard/lenovo/pmh.md 2 files changed, 70 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/32253/1 diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index d94c23e..adfe877 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -54,6 +54,7 @@ - [Hardware Maintenance Manual of ThinkPads](lenovo/thinkpad_hmm.md) - [T4xx common](lenovo/t4xx_series.md) - [X2xx common](lenovo/x2xx_series.md) +- [PMH](lenovo/pmh.md) ### Sandy Bridge series diff --git a/Documentation/mainboard/lenovo/pmh.md b/Documentation/mainboard/lenovo/pmh.md new file mode 100644 index 0000000..06c595d --- /dev/null +++ b/Documentation/mainboard/lenovo/pmh.md @@ -0,0 +1,69 @@ +# Lenovo's Power Management Hub + +The *Power Management Hub* or *PMH* originally was a CPLD connected to the EC +to controll power rails and reset lines on the lenovo mainboard. +Starting with Ivy Bridge series, the CPLD was removed and an EC with higher +pincount does the same job. The IO space to configure the PMH is still +the same. + +## PMH access + +The PMH register can be accessed using the IO region: + + IO region address: 0x15e0 + IO region size: 16 + +The IO region has the following layout: + +```eval_rst ++-------------------+---------------------------------------+ +| Offset | Register function | ++-------------------+---------------------------------------+ +| 0xc | ADDR_L: Low address into PMH space | ++-------------------+---------------------------------------+ +| 0xd | ADDR_H: High address into PMH space | ++-------------------+---------------------------------------+ +| 0xe | DATA: The data to read/write in PMH | ++-------------------+---------------------------------------+ +``` + +The PMH register space allows to access 512bytes. +The following registers are known: + +```eval_rst ++-------------------+---------------------------------------+ +| Offset | Register function | ++-------------------+---------------------------------------+ +| 0x50 | BIT3: dGPU power enable | +| +---------------------------------------+ +| | BIT5: Backlight enable | +| +---------------------------------------+ +| | BIT7: dGPU !reset | ++-------------------+---------------------------------------+ +| 0x51 | BIT0: Trackpoint enable | +| +---------------------------------------+ +| | BIT2: Touchpad enable | ++-------------------+---------------------------------------+ +| 0x60 | BIT3: Dock event enable | ++-------------------+---------------------------------------+ +| 0x62 | BIT0: Ultrabay power enable | ++-------------------+---------------------------------------+ +| 0xc2 | ID: ID of PMH | ++-------------------+---------------------------------------+ +| 0xc3 | REV: Revision of PMH | ++-------------------+---------------------------------------+ +``` + +The revision at 0xc3 seems to increment over time: + +```eval_rst ++-------------------+---------------------------------------+ +| Revision | Mainboard generation | ++-------------------+---------------------------------------+ +| 4 | T520 and T420s | ++-------------------+---------------------------------------+ +| 5 | W530 | ++-------------------+---------------------------------------+ +| 6 | T470p | ++-------------------+---------------------------------------+ +``` -- To view, visit https://review.coreboot.org/c/coreboot/+/32253 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1891a6370123d9ee29d9e37e4b7b78b677343aed Gerrit-Change-Number: 32253 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Supplement motherboard name for G41M-GS
by Pixie (Code Review) 07 Aug '23

07 Aug '23

Pixie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32372 Change subject: Supplement motherboard name for G41M-GS ...................................................................... Supplement motherboard name for G41M-GS A few months ago, Arthur Heymans rebased a few patches to add support for the G41M-GS to aid me in testing my G41M-S. The two boards are exact duplicates, save for the -GS having a gigabit LAN chip, and the G41M-S having a 100Mbit one. I did some scant testing, and it worked, but I had a lot of other projects ongoing. Now that I remembered thisagain, I'm here to commit the motherboard name. Signed-off-by: Cheetah Pixie <mayulithsv(a)gmail.com> Change-Id: I97f77ec2c8cbd9c2f13e6890257cb7c5b1c77311 --- M src/mainboard/asrock/g41c-gs/Kconfig.name 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/32372/1 diff --git a/src/mainboard/asrock/g41c-gs/Kconfig.name b/src/mainboard/asrock/g41c-gs/Kconfig.name index 86a41aa..1a090ff3 100644 --- a/src/mainboard/asrock/g41c-gs/Kconfig.name +++ b/src/mainboard/asrock/g41c-gs/Kconfig.name @@ -5,7 +5,7 @@ bool "G41C-GS / G41C-S" config BOARD_ASROCK_G41M_GS - bool "G41M-GS" + bool "G41M-GS / G41M-S" config BOARD_ASROCK_G41M_S3 bool "G41M-S3" -- To view, visit https://review.coreboot.org/c/coreboot/+/32372 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I97f77ec2c8cbd9c2f13e6890257cb7c5b1c77311 Gerrit-Change-Number: 32372 Gerrit-PatchSet: 1 Gerrit-Owner: Pixie <mayulithsv(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: CML: Enable UPDs for PCH SLP_S0 for S0ix entry
by Sumeet R Pawnikar (Code Review) 07 Aug '23

07 Aug '23

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32668 Change subject: CML: Enable UPDs for PCH SLP_S0 for S0ix entry ...................................................................... CML: Enable UPDs for PCH SLP_S0 for S0ix entry Enable PCH SLP S0 UPDs for S0ix entry. BUG=None BRANCH=None TEST=Built and tested on Hatch Change-Id: I57a15746705a726b402431321a45b3257d837faa --- M src/soc/intel/cannonlake/fsp_params.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/32668/1 diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index cc01d10..796b717 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -177,9 +177,9 @@ params->PchLanEnable = dev->enabled; if (config->s0ix_enable) { params->SlpS0WithGbeSupport = 1; - params->PchPmSlpS0VmRuntimeControl = 0; - params->PchPmSlpS0Vm070VSupport = 0; - params->PchPmSlpS0Vm075VSupport = 0; + params->PchPmSlpS0VmRuntimeControl = 1; + params->PchPmSlpS0Vm070VSupport = 1; + params->PchPmSlpS0Vm075VSupport = 1; ignore_gbe_ltr(); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/32668 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I57a15746705a726b402431321a45b3257d837faa Gerrit-Change-Number: 32668 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: WIP: google/flapjack: Add Panels support
by Jerry Han (Code Review) 07 Aug '23

07 Aug '23

Jerry Han has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32840 Change subject: WIP: google/flapjack: Add Panels support ...................................................................... WIP: google/flapjack: Add Panels support Add panel BOE_TV101WUM_NG0, BOE_TV080WUM_NG0, INX_OTA7290D10P, AUO_NT51021D8P for FLAPJACK. Change-Id: I3e50df59de3db9ed6efcccbd01b553c21f793a3f Signed-off-by: Jerry Han <hanxu5(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/kukui/Makefile.inc M src/mainboard/google/kukui/display.c M src/mainboard/google/kukui/display.h A src/mainboard/google/kukui/panel_flapjack.c 4 files changed, 1,112 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/32840/1 diff --git a/src/mainboard/google/kukui/Makefile.inc b/src/mainboard/google/kukui/Makefile.inc index 9576b7d..a91f91e7 100644 --- a/src/mainboard/google/kukui/Makefile.inc +++ b/src/mainboard/google/kukui/Makefile.inc @@ -25,6 +25,7 @@ ramstage-y += display.c ramstage-y += panel_kukui.c ramstage-y += panel_krane.c +ramstage-y += panel_flapjack.c ramstage-y += mainboard.c ramstage-y += memlayout.ld ramstage-y += reset.c diff --git a/src/mainboard/google/kukui/display.c b/src/mainboard/google/kukui/display.c index b0a5026..55e129b 100644 --- a/src/mainboard/google/kukui/display.c +++ b/src/mainboard/google/kukui/display.c @@ -99,6 +99,8 @@ return &kukui_display_intf; else if (CONFIG(BOARD_GOOGLE_KRANE)) return &krane_display_intf; + else if (CONFIG(BOARD_GOOGLE_FLAPJACK)) + return &flapjack_display_intf; else return NULL; } diff --git a/src/mainboard/google/kukui/display.h b/src/mainboard/google/kukui/display.h index 1b184af..bc26c69 100644 --- a/src/mainboard/google/kukui/display.h +++ b/src/mainboard/google/kukui/display.h @@ -41,10 +41,21 @@ PANEL_KRANE_UNINITIALIZED }; +enum flapjack_panel_id { + PANEL_FLAPJACK_FIRST = 0, + PANEL_FLAPJACK_BOE_TV101WUM_NG0, + PANEL_FLAPJACK_BOE_TV080WUM_NG0, + PANEL_FLAPJACK_INX_OTA7290D10P, + PANEL_FLAPJACK_AUO_NT51021D8P, + PANEL_FLAPJACK_UNKNOWN, + PANEL_FLAPJACK_COUNT, + PANEL_FLAPJACK_UNINITIALIZED +}; union panel_id { enum kukui_panel_id kukui_panel; enum krane_panel_id krane_panel; + enum flapjack_panel_id flapjack_panel; int value; }; @@ -100,5 +111,6 @@ */ extern struct board_display_intf kukui_display_intf; extern struct board_display_intf krane_display_intf; +extern struct board_display_intf flapjack_display_intf; #endif diff --git a/src/mainboard/google/kukui/panel_flapjack.c b/src/mainboard/google/kukui/panel_flapjack.c new file mode 100644 index 0000000..1b72e8a --- /dev/null +++ b/src/mainboard/google/kukui/panel_flapjack.c @@ -0,0 +1,1097 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Huaqin Telecom Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <delay.h> +#include <device/device.h> +#include <edid.h> +#include <gpio.h> +#include <soc/auxadc.h> +#include <soc/ddp.h> +#include <soc/dsi.h> +#include <soc/gpio.h> +#include <boardid.h> + +#include "display.h" +#include "gpio.h" + +#define PP3300_LCM_EN GPIO(SIM2_SIO) +#define PP1800_LCM_EN GPIO(SIM2_SRST) + +#define FLAPJACK_PANEL_ADC_ID 2 +#define FLAPJACK_PANEL_ID_BIT_POSITION 16 + +const int tolerance = 30000; /* 30,000 uV */ + +static struct edid flapjack_boe_tv080wum_edid = { + .panel_bits_per_color = 8, + .panel_bits_per_pixel = 24, + .mode = { + .name = "1200x1920@60Hz", + .pixel_clock = 159420, + .lvds_dual_channel = 0, + .refresh = 60, + .ha = 1200, .hbl = 164, .hso = 80, .hspw = 24, .hborder = 0, + .va = 1920, .vbl = 28, .vso = 10, .vspw = 4, .vborder = 0, + .phsync = '-', .pvsync = '-', + .x_mm = 107, .y_mm = 132, + }, +}; + +static struct lcm_init_table boe_tv080wum_lcm_init_cmd[] = { + {INIT_CMD, 1, {0x10} }, + {DELAY_CMD, 0x22, {} }, + {INIT_CMD, 2, {0xB0, 0x05} }, + {INIT_CMD, 2, {0xB1, 0xE5} }, + {INIT_CMD, 2, {0xB3, 0x52} }, + {INIT_CMD, 2, {0xB0, 0x00} }, + {INIT_CMD, 2, {0xB3, 0x88} }, + {INIT_CMD, 2, {0xB0, 0x04} }, + {INIT_CMD, 2, {0xB8, 0x00} }, + {INIT_CMD, 2, {0xB0, 0x00} }, + {INIT_CMD, 2, {0xB2, 0x50} }, + {INIT_CMD, 2, {0xB6, 0x03} }, + {INIT_CMD, 2, {0xBA, 0x8B} }, + {INIT_CMD, 2, {0xBF, 0x15} }, + {INIT_CMD, 2, {0xC0, 0x0F} }, + {INIT_CMD, 2, {0xC2, 0x0C} }, + {INIT_CMD, 2, {0xC3, 0x02} }, + {INIT_CMD, 2, {0xC4, 0x0C} }, + {INIT_CMD, 2, {0xC5, 0x02} }, + {INIT_CMD, 2, {0xB0, 0x01} }, + {INIT_CMD, 2, {0xE0, 0x26} }, + {INIT_CMD, 2, {0xE1, 0x26} }, + {INIT_CMD, 2, {0xDC, 0x00} }, + {INIT_CMD, 2, {0xDD, 0x00} }, + {INIT_CMD, 2, {0xCC, 0x26} }, + {INIT_CMD, 2, {0xCD, 0x26} }, + {INIT_CMD, 2, {0xC8, 0x00} }, + {INIT_CMD, 2, {0xC9, 0x00} }, + {INIT_CMD, 2, {0xD2, 0x04} }, + {INIT_CMD, 2, {0xD3, 0x04} }, + {INIT_CMD, 2, {0xE6, 0x03} }, + {INIT_CMD, 2, {0xE7, 0x03} }, + {INIT_CMD, 2, {0xC4, 0x08} }, + {INIT_CMD, 2, {0xC5, 0x08} }, + {INIT_CMD, 2, {0xD8, 0x07} }, + {INIT_CMD, 2, {0xD9, 0x07} }, + {INIT_CMD, 2, {0xC2, 0x06} }, + {INIT_CMD, 2, {0xC3, 0x06} }, + {INIT_CMD, 2, {0xD6, 0x05} }, + {INIT_CMD, 2, {0xD7, 0x05} }, + {INIT_CMD, 2, {0xC0, 0x0C} }, + {INIT_CMD, 2, {0xC1, 0x0C} }, + {INIT_CMD, 2, {0xD4, 0x0B} }, + {INIT_CMD, 2, {0xD5, 0x0B} }, + {INIT_CMD, 2, {0xCA, 0x0A} }, + {INIT_CMD, 2, {0xCB, 0x0A} }, + {INIT_CMD, 2, {0xDE, 0x09} }, + {INIT_CMD, 2, {0xDF, 0x09} }, + {INIT_CMD, 2, {0xC6, 0x26} }, + {INIT_CMD, 2, {0xC7, 0x26} }, + {INIT_CMD, 2, {0xCE, 0x00} }, + {INIT_CMD, 2, {0xCF, 0x00} }, + {INIT_CMD, 2, {0xDA, 0x26} }, + {INIT_CMD, 2, {0xDB, 0x26} }, + {INIT_CMD, 2, {0xE2, 0x00} }, + {INIT_CMD, 2, {0xE3, 0x00} }, + {INIT_CMD, 2, {0xB0, 0x02} }, + {INIT_CMD, 2, {0xC0, 0x00} }, + {INIT_CMD, 2, {0xC1, 0x07} }, + {INIT_CMD, 2, {0xC2, 0x0D} }, + {INIT_CMD, 2, {0xC3, 0x18} }, + {INIT_CMD, 2, {0xC4, 0x27} }, + {INIT_CMD, 2, {0xC5, 0x28} }, + {INIT_CMD, 2, {0xC6, 0x30} }, + {INIT_CMD, 2, {0xC7, 0x2E} }, + {INIT_CMD, 2, {0xC8, 0x2F} }, + {INIT_CMD, 2, {0xC9, 0x1A} }, + {INIT_CMD, 2, {0xCA, 0x20} }, + {INIT_CMD, 2, {0xCB, 0x29} }, + {INIT_CMD, 2, {0xCC, 0x26} }, + {INIT_CMD, 2, {0xCD, 0x32} }, + {INIT_CMD, 2, {0xCE, 0x33} }, + {INIT_CMD, 2, {0xCF, 0x31} }, + {INIT_CMD, 2, {0xD0, 0x06} }, + {INIT_CMD, 2, {0xD2, 0x00} }, + {INIT_CMD, 2, {0xD3, 0x07} }, + {INIT_CMD, 2, {0xD4, 0x12} }, + {INIT_CMD, 2, {0xD5, 0x26} }, + {INIT_CMD, 2, {0xD6, 0x3D} }, + {INIT_CMD, 2, {0xD7, 0x3F} }, + {INIT_CMD, 2, {0xD8, 0x3F} }, + {INIT_CMD, 2, {0xD9, 0x3F} }, + {INIT_CMD, 2, {0xDA, 0x3F} }, + {INIT_CMD, 2, {0xDB, 0x3F} }, + {INIT_CMD, 2, {0xDC, 0x3F} }, + {INIT_CMD, 2, {0xDD, 0x3F} }, + {INIT_CMD, 2, {0xDE, 0x3F} }, + {INIT_CMD, 2, {0xDF, 0x3A} }, + {INIT_CMD, 2, {0xE0, 0x37} }, + {INIT_CMD, 2, {0xE1, 0x35} }, + {INIT_CMD, 2, {0xE2, 0x07} }, + {INIT_CMD, 2, {0xB0, 0x03} }, + {INIT_CMD, 2, {0xC8, 0x0B} }, + {INIT_CMD, 2, {0xC9, 0x07} }, + {INIT_CMD, 2, {0xC3, 0x00} }, + {INIT_CMD, 2, {0xE7, 0x00} }, + {INIT_CMD, 2, {0xC5, 0x2A} }, + {INIT_CMD, 2, {0xDE, 0x2A} }, + {INIT_CMD, 2, {0xCA, 0x43} }, + {INIT_CMD, 2, {0xC9, 0x07} }, + {INIT_CMD, 2, {0xE4, 0xC0} }, + {INIT_CMD, 2, {0xE5, 0x0D} }, + {INIT_CMD, 2, {0xCB, 0x00} }, + {INIT_CMD, 2, {0xB0, 0x06} }, + {INIT_CMD, 2, {0xB8, 0xA5} }, + {INIT_CMD, 2, {0xC0, 0xA5} }, + {INIT_CMD, 2, {0xC7, 0x0F} }, + {INIT_CMD, 2, {0xD5, 0x32} }, + {INIT_CMD, 2, {0xB8, 0x00} }, + {INIT_CMD, 2, {0xC0, 0x00} }, + {INIT_CMD, 2, {0xBC, 0x00} }, + {INIT_CMD, 2, {0xB0, 0x07} }, + {INIT_CMD, 2, {0xB1, 0x00} }, + {INIT_CMD, 2, {0xB2, 0x09} }, + {INIT_CMD, 2, {0xB3, 0x19} }, + {INIT_CMD, 2, {0xB4, 0x2F} }, + {INIT_CMD, 2, {0xB5, 0x44} }, + {INIT_CMD, 2, {0xB6, 0x52} }, + {INIT_CMD, 2, {0xB7, 0x6A} }, + {INIT_CMD, 2, {0xB8, 0x8A} }, + {INIT_CMD, 2, {0xB9, 0xCA} }, + {INIT_CMD, 2, {0xBA, 0x0C} }, + {INIT_CMD, 2, {0xBB, 0x87} }, + {DELAY_CMD, 0x05, {} }, + {INIT_CMD, 2, {0xBC, 0x06} }, + {INIT_CMD, 2, {0xBD, 0x0A} }, + {INIT_CMD, 2, {0xBE, 0x9B} }, + {INIT_CMD, 2, {0xBF, 0x0C} }, + {INIT_CMD, 2, {0xC0, 0x3D} }, + {INIT_CMD, 2, {0xC1, 0x71} }, + {INIT_CMD, 2, {0xC2, 0x90} }, + {INIT_CMD, 2, {0xC3, 0xA0} }, + {INIT_CMD, 2, {0xC4, 0xA8} }, + {INIT_CMD, 2, {0xC5, 0xB1} }, + {INIT_CMD, 2, {0xC6, 0xBB} }, + {INIT_CMD, 2, {0xC7, 0xC0} }, + {INIT_CMD, 2, {0xC8, 0xC4} }, + {INIT_CMD, 2, {0xC9, 0x00} }, + {INIT_CMD, 2, {0xCA, 0x00} }, + {INIT_CMD, 2, {0xCB, 0x16} }, + {INIT_CMD, 2, {0xCC, 0xAF} }, + {INIT_CMD, 2, {0xCD, 0xFF} }, + {INIT_CMD, 2, {0xCE, 0xFF} }, + {INIT_CMD, 2, {0xB0, 0x08} }, + {INIT_CMD, 2, {0xB1, 0x04} }, + {INIT_CMD, 2, {0xB2, 0x08} }, + {INIT_CMD, 2, {0xB3, 0x19} }, + {INIT_CMD, 2, {0xB4, 0x31} }, + {INIT_CMD, 2, {0xB5, 0x46} }, + {INIT_CMD, 2, {0xB6, 0x55} }, + {INIT_CMD, 2, {0xB7, 0x6E} }, + {INIT_CMD, 2, {0xB8, 0x92} }, + {INIT_CMD, 2, {0xB9, 0xD4} }, + {INIT_CMD, 2, {0xBA, 0x1B} }, + {INIT_CMD, 2, {0xBB, 0x9B} }, + {DELAY_CMD, 0x05, {} }, + {INIT_CMD, 2, {0xBC, 0x28} }, + {INIT_CMD, 2, {0xBD, 0x2D} }, + {INIT_CMD, 2, {0xBE, 0xC3} }, + {INIT_CMD, 2, {0xBF, 0x2F} }, + {INIT_CMD, 2, {0xC0, 0x62} }, + {INIT_CMD, 2, {0xC1, 0x99} }, + {INIT_CMD, 2, {0xC2, 0xAB} }, + {INIT_CMD, 2, {0xC3, 0xBF} }, + {INIT_CMD, 2, {0xC4, 0xCF} }, + {INIT_CMD, 2, {0xC5, 0xDF} }, + {INIT_CMD, 2, {0xC6, 0xF0} }, + {INIT_CMD, 2, {0xC7, 0xF9} }, + {INIT_CMD, 2, {0xC8, 0xFC} }, + {INIT_CMD, 2, {0xC9, 0x00} }, + {INIT_CMD, 2, {0xCA, 0x00} }, + {INIT_CMD, 2, {0xCB, 0x16} }, + {INIT_CMD, 2, {0xCC, 0xAF} }, + {INIT_CMD, 2, {0xCD, 0xFF} }, + {INIT_CMD, 2, {0xCE, 0xFF} }, + {INIT_CMD, 2, {0xB0, 0x09} }, + {INIT_CMD, 2, {0xB1, 0x04} }, + {INIT_CMD, 2, {0xB2, 0x05} }, + {INIT_CMD, 2, {0xB3, 0x17} }, + {INIT_CMD, 2, {0xB4, 0x2E} }, + {INIT_CMD, 2, {0xB5, 0x42} }, + {INIT_CMD, 2, {0xB6, 0x51} }, + {INIT_CMD, 2, {0xB7, 0x69} }, + {INIT_CMD, 2, {0xB8, 0x88} }, + {INIT_CMD, 2, {0xB9, 0xC9} }, + {INIT_CMD, 2, {0xBA, 0x0C} }, + {INIT_CMD, 2, {0xBB, 0x86} }, + {DELAY_CMD, 0x05, {} }, + {INIT_CMD, 2, {0xBC, 0x03} }, + {INIT_CMD, 2, {0xBD, 0x08} }, + {INIT_CMD, 2, {0xBE, 0x95} }, + {INIT_CMD, 2, {0xBF, 0x05} }, + {INIT_CMD, 2, {0xC0, 0x35} }, + {INIT_CMD, 2, {0xC1, 0x62} }, + {INIT_CMD, 2, {0xC2, 0x81} }, + {INIT_CMD, 2, {0xC3, 0x96} }, + {INIT_CMD, 2, {0xC4, 0x9E} }, + {INIT_CMD, 2, {0xC5, 0xA5} }, + {INIT_CMD, 2, {0xC6, 0xAD} }, + {INIT_CMD, 2, {0xC7, 0xB1} }, + {INIT_CMD, 2, {0xC8, 0xB4} }, + {INIT_CMD, 2, {0xC9, 0x00} }, + {INIT_CMD, 2, {0xCA, 0x00} }, + {INIT_CMD, 2, {0xCB, 0x16} }, + {INIT_CMD, 2, {0xCC, 0xAF} }, + {INIT_CMD, 2, {0xCD, 0xFF} }, + {INIT_CMD, 2, {0xCE, 0xFF} }, + {INIT_CMD, 2, {0xB0, 0x0A} }, + {INIT_CMD, 2, {0xB1, 0x00} }, + {INIT_CMD, 2, {0xB2, 0x09} }, + {INIT_CMD, 2, {0xB3, 0x19} }, + {INIT_CMD, 2, {0xB4, 0x2F} }, + {INIT_CMD, 2, {0xB5, 0x44} }, + {INIT_CMD, 2, {0xB6, 0x52} }, + {INIT_CMD, 2, {0xB7, 0x6A} }, + {INIT_CMD, 2, {0xB8, 0x8A} }, + {INIT_CMD, 2, {0xB9, 0xCA} }, + {INIT_CMD, 2, {0xBA, 0x0C} }, + {INIT_CMD, 2, {0xBB, 0x87} }, + {DELAY_CMD, 0x05, {} }, + {INIT_CMD, 2, {0xBC, 0x06} }, + {INIT_CMD, 2, {0xBD, 0x0A} }, + {INIT_CMD, 2, {0xBE, 0x9B} }, + {INIT_CMD, 2, {0xBF, 0x0C} }, + {INIT_CMD, 2, {0xC0, 0x3D} }, + {INIT_CMD, 2, {0xC1, 0x71} }, + {INIT_CMD, 2, {0xC2, 0x90} }, + {INIT_CMD, 2, {0xC3, 0xA0} }, + {INIT_CMD, 2, {0xC4, 0xA8} }, + {INIT_CMD, 2, {0xC5, 0xB1} }, + {INIT_CMD, 2, {0xC6, 0xBB} }, + {INIT_CMD, 2, {0xC7, 0xC0} }, + {INIT_CMD, 2, {0xC8, 0xC4} }, + {INIT_CMD, 2, {0xC9, 0x00} }, + {INIT_CMD, 2, {0xCA, 0x00} }, + {INIT_CMD, 2, {0xCB, 0x16} }, + {INIT_CMD, 2, {0xCC, 0xAF} }, + {INIT_CMD, 2, {0xCD, 0xFF} }, + {INIT_CMD, 2, {0xCE, 0xFF} }, + {INIT_CMD, 2, {0xB0, 0x0B} }, + {INIT_CMD, 2, {0xB1, 0x04} }, + {INIT_CMD, 2, {0xB2, 0x08} }, + {INIT_CMD, 2, {0xB3, 0x19} }, + {INIT_CMD, 2, {0xB4, 0x31} }, + {INIT_CMD, 2, {0xB5, 0x46} }, + {INIT_CMD, 2, {0xB6, 0x55} }, + {INIT_CMD, 2, {0xB7, 0x6E} }, + {INIT_CMD, 2, {0xB8, 0x92} }, + {INIT_CMD, 2, {0xB9, 0xD4} }, + {INIT_CMD, 2, {0xBA, 0x1B} }, + {INIT_CMD, 2, {0xBB, 0x9B} }, + {DELAY_CMD, 0x05, {} }, + {INIT_CMD, 2, {0xBC, 0x28} }, + {INIT_CMD, 2, {0xBD, 0x2D} }, + {INIT_CMD, 2, {0xBE, 0xC3} }, + {INIT_CMD, 2, {0xBF, 0x2F} }, + {INIT_CMD, 2, {0xC0, 0x62} }, + {INIT_CMD, 2, {0xC1, 0x99} }, + {INIT_CMD, 2, {0xC2, 0xAB} }, + {INIT_CMD, 2, {0xC3, 0xBF} }, + {INIT_CMD, 2, {0xC4, 0xCF} }, + {INIT_CMD, 2, {0xC5, 0xDF} }, + {INIT_CMD, 2, {0xC6, 0xF0} }, + {INIT_CMD, 2, {0xC7, 0xF9} }, + {INIT_CMD, 2, {0xC8, 0xFC} }, + {INIT_CMD, 2, {0xC9, 0x00} }, + {INIT_CMD, 2, {0xCA, 0x00} }, + {INIT_CMD, 2, {0xCB, 0x16} }, + {INIT_CMD, 2, {0xCC, 0xAF} }, + {INIT_CMD, 2, {0xCD, 0xFF} }, + {INIT_CMD, 2, {0xCE, 0xFF} }, + {INIT_CMD, 2, {0xB0, 0x0C} }, + {INIT_CMD, 2, {0xB1, 0x04} }, + {INIT_CMD, 2, {0xB2, 0x05} }, + {INIT_CMD, 2, {0xB3, 0x17} }, + {INIT_CMD, 2, {0xB4, 0x2E} }, + {INIT_CMD, 2, {0xB5, 0x42} }, + {INIT_CMD, 2, {0xB6, 0x51} }, + {INIT_CMD, 2, {0xB7, 0x69} }, + {INIT_CMD, 2, {0xB8, 0x88} }, + {INIT_CMD, 2, {0xB9, 0xC9} }, + {INIT_CMD, 2, {0xBA, 0x0C} }, + {INIT_CMD, 2, {0xBB, 0x86} }, + {DELAY_CMD, 0x05, {} }, + {INIT_CMD, 2, {0xBC, 0x03} }, + {INIT_CMD, 2, {0xBD, 0x08} }, + {INIT_CMD, 2, {0xBE, 0x95} }, + {INIT_CMD, 2, {0xBF, 0x05} }, + {INIT_CMD, 2, {0xC0, 0x35} }, + {INIT_CMD, 2, {0xC1, 0x62} }, + {INIT_CMD, 2, {0xC2, 0x81} }, + {INIT_CMD, 2, {0xC3, 0x96} }, + {INIT_CMD, 2, {0xC4, 0x9E} }, + {INIT_CMD, 2, {0xC5, 0xA5} }, + {INIT_CMD, 2, {0xC6, 0xAD} }, + {INIT_CMD, 2, {0xC7, 0xB1} }, + {INIT_CMD, 2, {0xC8, 0xB4} }, + {INIT_CMD, 2, {0xC9, 0x00} }, + {INIT_CMD, 2, {0xCA, 0x00} }, + {INIT_CMD, 2, {0xCB, 0x16} }, + {INIT_CMD, 2, {0xCC, 0xAF} }, + {INIT_CMD, 2, {0xCD, 0xFF} }, + {INIT_CMD, 2, {0xCE, 0xFF} }, + {DELAY_CMD, 0x64, {} }, + {INIT_CMD, 2, {0xB0, 0x00} }, + {INIT_CMD, 2, {0xB3, 0x08} }, + {INIT_CMD, 2, {0xB0, 0x04} }, + {INIT_CMD, 2, {0xB8, 0x68} }, + {DELAY_CMD, 0x0A, {} }, + {INIT_CMD, 1, {0x11} }, + {DELAY_CMD, 0x78, {} }, + {INIT_CMD, 1, {0x29} }, + {DELAY_CMD, 0x14, {} }, + +}; + +/* flapjack C19 BOE tv101wum panel : PANEL_FLAPJACK_BOE_TV101WUM_NG0 */ +static struct edid flapjack_boe_tv101wum_edid = { + .panel_bits_per_color = 8, + .panel_bits_per_pixel = 24, + .mode = { + .name = "1200x1920@60Hz", + .pixel_clock = 159420, + .lvds_dual_channel = 0, + .refresh = 60, + .ha = 1200, .hbl = 164, .hso = 80, .hspw = 24, .hborder = 0, + .va = 1920, .vbl = 28, .vso = 10, .vspw = 4, .vborder = 0, + .phsync = '-', .pvsync = '-', + .x_mm = 135, .y_mm = 216, + }, +}; + +static struct lcm_init_table boe_tv101wum_lcm_init_cmd[] = { + {INIT_CMD, 1, {0x10} }, + {DELAY_CMD, 0x22, {} }, + {INIT_CMD, 2, {0xB0, 0x05} }, + {INIT_CMD, 2, {0xB1, 0xE5} }, + {INIT_CMD, 2, {0xB3, 0x52} }, + {INIT_CMD, 2, {0xB0, 0x00} }, + {INIT_CMD, 2, {0xB3, 0x88} }, + {INIT_CMD, 2, {0xB0, 0x04} }, + {INIT_CMD, 2, {0xB8, 0x00} }, + {INIT_CMD, 2, {0xB0, 0x00} }, + {INIT_CMD, 2, {0xB2, 0x50} }, + {INIT_CMD, 2, {0xB6, 0x03} }, + {INIT_CMD, 2, {0xBA, 0x8B} }, + {INIT_CMD, 2, {0xBF, 0x15} }, + {INIT_CMD, 2, {0xC0, 0x0F} }, + {INIT_CMD, 2, {0xC2, 0x0C} }, + {INIT_CMD, 2, {0xC3, 0x02} }, + {INIT_CMD, 2, {0xC4, 0x0C} }, + {INIT_CMD, 2, {0xC5, 0x02} }, + {INIT_CMD, 2, {0xB0, 0x01} }, + {INIT_CMD, 2, {0xE0, 0x26} }, + {INIT_CMD, 2, {0xE1, 0x26} }, + {INIT_CMD, 2, {0xDC, 0x00} }, + {INIT_CMD, 2, {0xDD, 0x00} }, + {INIT_CMD, 2, {0xCC, 0x26} }, + {INIT_CMD, 2, {0xCD, 0x26} }, + {INIT_CMD, 2, {0xC8, 0x00} }, + {INIT_CMD, 2, {0xC9, 0x00} }, + {INIT_CMD, 2, {0xD2, 0x04} }, + {INIT_CMD, 2, {0xD3, 0x04} }, + {INIT_CMD, 2, {0xE6, 0x03} }, + {INIT_CMD, 2, {0xE7, 0x03} }, + {INIT_CMD, 2, {0xC4, 0x08} }, + {INIT_CMD, 2, {0xC5, 0x08} }, + {INIT_CMD, 2, {0xD8, 0x07} }, + {INIT_CMD, 2, {0xD9, 0x07} }, + {INIT_CMD, 2, {0xC2, 0x06} }, + {INIT_CMD, 2, {0xC3, 0x06} }, + {INIT_CMD, 2, {0xD6, 0x05} }, + {INIT_CMD, 2, {0xD7, 0x05} }, + {INIT_CMD, 2, {0xC0, 0x0C} }, + {INIT_CMD, 2, {0xC1, 0x0C} }, + {INIT_CMD, 2, {0xD4, 0x0B} }, + {INIT_CMD, 2, {0xD5, 0x0B} }, + {INIT_CMD, 2, {0xCA, 0x0A} }, + {INIT_CMD, 2, {0xCB, 0x0A} }, + {INIT_CMD, 2, {0xDE, 0x09} }, + {INIT_CMD, 2, {0xDF, 0x09} }, + {INIT_CMD, 2, {0xC6, 0x26} }, + {INIT_CMD, 2, {0xC7, 0x26} }, + {INIT_CMD, 2, {0xCE, 0x00} }, + {INIT_CMD, 2, {0xCF, 0x00} }, + {INIT_CMD, 2, {0xDA, 0x26} }, + {INIT_CMD, 2, {0xDB, 0x26} }, + {INIT_CMD, 2, {0xE2, 0x00} }, + {INIT_CMD, 2, {0xE3, 0x00} }, + {INIT_CMD, 2, {0xB0, 0x02} }, + {INIT_CMD, 2, {0xC0, 0x00} }, + {INIT_CMD, 2, {0xC1, 0x07} }, + {INIT_CMD, 2, {0xC2, 0x0D} }, + {INIT_CMD, 2, {0xC3, 0x18} }, + {INIT_CMD, 2, {0xC4, 0x27} }, + {INIT_CMD, 2, {0xC5, 0x28} }, + {INIT_CMD, 2, {0xC6, 0x30} }, + {INIT_CMD, 2, {0xC7, 0x2E} }, + {INIT_CMD, 2, {0xC8, 0x2F} }, + {INIT_CMD, 2, {0xC9, 0x1A} }, + {INIT_CMD, 2, {0xCA, 0x20} }, + {INIT_CMD, 2, {0xCB, 0x29} }, + {INIT_CMD, 2, {0xCC, 0x26} }, + {INIT_CMD, 2, {0xCD, 0x32} }, + {INIT_CMD, 2, {0xCE, 0x33} }, + {INIT_CMD, 2, {0xCF, 0x31} }, + {INIT_CMD, 2, {0xD0, 0x06} }, + {INIT_CMD, 2, {0xD2, 0x00} }, + {INIT_CMD, 2, {0xD3, 0x07} }, + {INIT_CMD, 2, {0xD4, 0x12} }, + {INIT_CMD, 2, {0xD5, 0x26} }, + {INIT_CMD, 2, {0xD6, 0x3D} }, + {INIT_CMD, 2, {0xD7, 0x3F} }, + {INIT_CMD, 2, {0xD8, 0x3F} }, + {INIT_CMD, 2, {0xD9, 0x3F} }, + {INIT_CMD, 2, {0xDA, 0x3F} }, + {INIT_CMD, 2, {0xDB, 0x3F} }, + {INIT_CMD, 2, {0xDC, 0x3F} }, + {INIT_CMD, 2, {0xDD, 0x3F} }, + {INIT_CMD, 2, {0xDE, 0x3F} }, + {INIT_CMD, 2, {0xDF, 0x3A} }, + {INIT_CMD, 2, {0xE0, 0x37} }, + {INIT_CMD, 2, {0xE1, 0x35} }, + {INIT_CMD, 2, {0xE2, 0x07} }, + {INIT_CMD, 2, {0xB0, 0x03} }, + {INIT_CMD, 2, {0xC8, 0x0B} }, + {INIT_CMD, 2, {0xC9, 0x07} }, + {INIT_CMD, 2, {0xC3, 0x00} }, + {INIT_CMD, 2, {0xE7, 0x00} }, + {INIT_CMD, 2, {0xC5, 0x2A} }, + {INIT_CMD, 2, {0xDE, 0x2A} }, + {INIT_CMD, 2, {0xCA, 0x43} }, + {INIT_CMD, 2, {0xC9, 0x07} }, + {INIT_CMD, 2, {0xE4, 0xC0} }, + {INIT_CMD, 2, {0xE5, 0x0D} }, + {INIT_CMD, 2, {0xCB, 0x00} }, + {INIT_CMD, 2, {0xB0, 0x06} }, + {INIT_CMD, 2, {0xB8, 0xA5} }, + {INIT_CMD, 2, {0xC0, 0xA5} }, + {INIT_CMD, 2, {0xC7, 0x0F} }, + {INIT_CMD, 2, {0xD5, 0x32} }, + {INIT_CMD, 2, {0xB8, 0x00} }, + {INIT_CMD, 2, {0xC0, 0x00} }, + {INIT_CMD, 2, {0xBC, 0x00} }, + {INIT_CMD, 2, {0xB0, 0x07} }, + {INIT_CMD, 2, {0xB1, 0x00} }, + {INIT_CMD, 2, {0xB2, 0x09} }, + {INIT_CMD, 2, {0xB3, 0x19} }, + {INIT_CMD, 2, {0xB4, 0x2F} }, + {INIT_CMD, 2, {0xB5, 0x44} }, + {INIT_CMD, 2, {0xB6, 0x52} }, + {INIT_CMD, 2, {0xB7, 0x6A} }, + {INIT_CMD, 2, {0xB8, 0x8A} }, + {INIT_CMD, 2, {0xB9, 0xCA} }, + {INIT_CMD, 2, {0xBA, 0x0C} }, + {INIT_CMD, 2, {0xBB, 0x87} }, + {DELAY_CMD, 0x05, {} }, + {INIT_CMD, 2, {0xBC, 0x06} }, + {INIT_CMD, 2, {0xBD, 0x0A} }, + {INIT_CMD, 2, {0xBE, 0x9B} }, + {INIT_CMD, 2, {0xBF, 0x0C} }, + {INIT_CMD, 2, {0xC0, 0x3D} }, + {INIT_CMD, 2, {0xC1, 0x71} }, + {INIT_CMD, 2, {0xC2, 0x90} }, + {INIT_CMD, 2, {0xC3, 0xA0} }, + {INIT_CMD, 2, {0xC4, 0xA8} }, + {INIT_CMD, 2, {0xC5, 0xB1} }, + {INIT_CMD, 2, {0xC6, 0xBB} }, + {INIT_CMD, 2, {0xC7, 0xC0} }, + {INIT_CMD, 2, {0xC8, 0xC4} }, + {INIT_CMD, 2, {0xC9, 0x00} }, + {INIT_CMD, 2, {0xCA, 0x00} }, + {INIT_CMD, 2, {0xCB, 0x16} }, + {INIT_CMD, 2, {0xCC, 0xAF} }, + {INIT_CMD, 2, {0xCD, 0xFF} }, + {INIT_CMD, 2, {0xCE, 0xFF} }, + {INIT_CMD, 2, {0xB0, 0x08} }, + {INIT_CMD, 2, {0xB1, 0x04} }, + {INIT_CMD, 2, {0xB2, 0x08} }, + {INIT_CMD, 2, {0xB3, 0x19} }, + {INIT_CMD, 2, {0xB4, 0x31} }, + {INIT_CMD, 2, {0xB5, 0x46} }, + {INIT_CMD, 2, {0xB6, 0x55} }, + {INIT_CMD, 2, {0xB7, 0x6E} }, + {INIT_CMD, 2, {0xB8, 0x92} }, + {INIT_CMD, 2, {0xB9, 0xD4} }, + {INIT_CMD, 2, {0xBA, 0x1B} }, + {INIT_CMD, 2, {0xBB, 0x9B} }, + {DELAY_CMD, 0x05, {} }, + {INIT_CMD, 2, {0xBC, 0x28} }, + {INIT_CMD, 2, {0xBD, 0x2D} }, + {INIT_CMD, 2, {0xBE, 0xC3} }, + {INIT_CMD, 2, {0xBF, 0x2F} }, + {INIT_CMD, 2, {0xC0, 0x62} }, + {INIT_CMD, 2, {0xC1, 0x99} }, + {INIT_CMD, 2, {0xC2, 0xAB} }, + {INIT_CMD, 2, {0xC3, 0xBF} }, + {INIT_CMD, 2, {0xC4, 0xCF} }, + {INIT_CMD, 2, {0xC5, 0xDF} }, + {INIT_CMD, 2, {0xC6, 0xF0} }, + {INIT_CMD, 2, {0xC7, 0xF9} }, + {INIT_CMD, 2, {0xC8, 0xFC} }, + {INIT_CMD, 2, {0xC9, 0x00} }, + {INIT_CMD, 2, {0xCA, 0x00} }, + {INIT_CMD, 2, {0xCB, 0x16} }, + {INIT_CMD, 2, {0xCC, 0xAF} }, + {INIT_CMD, 2, {0xCD, 0xFF} }, + {INIT_CMD, 2, {0xCE, 0xFF} }, + {INIT_CMD, 2, {0xB0, 0x09} }, + {INIT_CMD, 2, {0xB1, 0x04} }, + {INIT_CMD, 2, {0xB2, 0x05} }, + {INIT_CMD, 2, {0xB3, 0x17} }, + {INIT_CMD, 2, {0xB4, 0x2E} }, + {INIT_CMD, 2, {0xB5, 0x42} }, + {INIT_CMD, 2, {0xB6, 0x51} }, + {INIT_CMD, 2, {0xB7, 0x69} }, + {INIT_CMD, 2, {0xB8, 0x88} }, + {INIT_CMD, 2, {0xB9, 0xC9} }, + {INIT_CMD, 2, {0xBA, 0x0C} }, + {INIT_CMD, 2, {0xBB, 0x86} }, + {DELAY_CMD, 0x05, {} }, + {INIT_CMD, 2, {0xBC, 0x03} }, + {INIT_CMD, 2, {0xBD, 0x08} }, + {INIT_CMD, 2, {0xBE, 0x95} }, + {INIT_CMD, 2, {0xBF, 0x05} }, + {INIT_CMD, 2, {0xC0, 0x35} }, + {INIT_CMD, 2, {0xC1, 0x62} }, + {INIT_CMD, 2, {0xC2, 0x81} }, + {INIT_CMD, 2, {0xC3, 0x96} }, + {INIT_CMD, 2, {0xC4, 0x9E} }, + {INIT_CMD, 2, {0xC5, 0xA5} }, + {INIT_CMD, 2, {0xC6, 0xAD} }, + {INIT_CMD, 2, {0xC7, 0xB1} }, + {INIT_CMD, 2, {0xC8, 0xB4} }, + {INIT_CMD, 2, {0xC9, 0x00} }, + {INIT_CMD, 2, {0xCA, 0x00} }, + {INIT_CMD, 2, {0xCB, 0x16} }, + {INIT_CMD, 2, {0xCC, 0xAF} }, + {INIT_CMD, 2, {0xCD, 0xFF} }, + {INIT_CMD, 2, {0xCE, 0xFF} }, + {INIT_CMD, 2, {0xB0, 0x0A} }, + {INIT_CMD, 2, {0xB1, 0x00} }, + {INIT_CMD, 2, {0xB2, 0x09} }, + {INIT_CMD, 2, {0xB3, 0x19} }, + {INIT_CMD, 2, {0xB4, 0x2F} }, + {INIT_CMD, 2, {0xB5, 0x44} }, + {INIT_CMD, 2, {0xB6, 0x52} }, + {INIT_CMD, 2, {0xB7, 0x6A} }, + {INIT_CMD, 2, {0xB8, 0x8A} }, + {INIT_CMD, 2, {0xB9, 0xCA} }, + {INIT_CMD, 2, {0xBA, 0x0C} }, + {INIT_CMD, 2, {0xBB, 0x87} }, + {DELAY_CMD, 0x05, {} }, + {INIT_CMD, 2, {0xBC, 0x06} }, + {INIT_CMD, 2, {0xBD, 0x0A} }, + {INIT_CMD, 2, {0xBE, 0x9B} }, + {INIT_CMD, 2, {0xBF, 0x0C} }, + {INIT_CMD, 2, {0xC0, 0x3D} }, + {INIT_CMD, 2, {0xC1, 0x71} }, + {INIT_CMD, 2, {0xC2, 0x90} }, + {INIT_CMD, 2, {0xC3, 0xA0} }, + {INIT_CMD, 2, {0xC4, 0xA8} }, + {INIT_CMD, 2, {0xC5, 0xB1} }, + {INIT_CMD, 2, {0xC6, 0xBB} }, + {INIT_CMD, 2, {0xC7, 0xC0} }, + {INIT_CMD, 2, {0xC8, 0xC4} }, + {INIT_CMD, 2, {0xC9, 0x00} }, + {INIT_CMD, 2, {0xCA, 0x00} }, + {INIT_CMD, 2, {0xCB, 0x16} }, + {INIT_CMD, 2, {0xCC, 0xAF} }, + {INIT_CMD, 2, {0xCD, 0xFF} }, + {INIT_CMD, 2, {0xCE, 0xFF} }, + {INIT_CMD, 2, {0xB0, 0x0B} }, + {INIT_CMD, 2, {0xB1, 0x04} }, + {INIT_CMD, 2, {0xB2, 0x08} }, + {INIT_CMD, 2, {0xB3, 0x19} }, + {INIT_CMD, 2, {0xB4, 0x31} }, + {INIT_CMD, 2, {0xB5, 0x46} }, + {INIT_CMD, 2, {0xB6, 0x55} }, + {INIT_CMD, 2, {0xB7, 0x6E} }, + {INIT_CMD, 2, {0xB8, 0x92} }, + {INIT_CMD, 2, {0xB9, 0xD4} }, + {INIT_CMD, 2, {0xBA, 0x1B} }, + {INIT_CMD, 2, {0xBB, 0x9B} }, + {DELAY_CMD, 0x05, {} }, + {INIT_CMD, 2, {0xBC, 0x28} }, + {INIT_CMD, 2, {0xBD, 0x2D} }, + {INIT_CMD, 2, {0xBE, 0xC3} }, + {INIT_CMD, 2, {0xBF, 0x2F} }, + {INIT_CMD, 2, {0xC0, 0x62} }, + {INIT_CMD, 2, {0xC1, 0x99} }, + {INIT_CMD, 2, {0xC2, 0xAB} }, + {INIT_CMD, 2, {0xC3, 0xBF} }, + {INIT_CMD, 2, {0xC4, 0xCF} }, + {INIT_CMD, 2, {0xC5, 0xDF} }, + {INIT_CMD, 2, {0xC6, 0xF0} }, + {INIT_CMD, 2, {0xC7, 0xF9} }, + {INIT_CMD, 2, {0xC8, 0xFC} }, + {INIT_CMD, 2, {0xC9, 0x00} }, + {INIT_CMD, 2, {0xCA, 0x00} }, + {INIT_CMD, 2, {0xCB, 0x16} }, + {INIT_CMD, 2, {0xCC, 0xAF} }, + {INIT_CMD, 2, {0xCD, 0xFF} }, + {INIT_CMD, 2, {0xCE, 0xFF} }, + {INIT_CMD, 2, {0xB0, 0x0C} }, + {INIT_CMD, 2, {0xB1, 0x04} }, + {INIT_CMD, 2, {0xB2, 0x05} }, + {INIT_CMD, 2, {0xB3, 0x17} }, + {INIT_CMD, 2, {0xB4, 0x2E} }, + {INIT_CMD, 2, {0xB5, 0x42} }, + {INIT_CMD, 2, {0xB6, 0x51} }, + {INIT_CMD, 2, {0xB7, 0x69} }, + {INIT_CMD, 2, {0xB8, 0x88} }, + {INIT_CMD, 2, {0xB9, 0xC9} }, + {INIT_CMD, 2, {0xBA, 0x0C} }, + {INIT_CMD, 2, {0xBB, 0x86} }, + {DELAY_CMD, 0x05, {} }, + {INIT_CMD, 2, {0xBC, 0x03} }, + {INIT_CMD, 2, {0xBD, 0x08} }, + {INIT_CMD, 2, {0xBE, 0x95} }, + {INIT_CMD, 2, {0xBF, 0x05} }, + {INIT_CMD, 2, {0xC0, 0x35} }, + {INIT_CMD, 2, {0xC1, 0x62} }, + {INIT_CMD, 2, {0xC2, 0x81} }, + {INIT_CMD, 2, {0xC3, 0x96} }, + {INIT_CMD, 2, {0xC4, 0x9E} }, + {INIT_CMD, 2, {0xC5, 0xA5} }, + {INIT_CMD, 2, {0xC6, 0xAD} }, + {INIT_CMD, 2, {0xC7, 0xB1} }, + {INIT_CMD, 2, {0xC8, 0xB4} }, + {INIT_CMD, 2, {0xC9, 0x00} }, + {INIT_CMD, 2, {0xCA, 0x00} }, + {INIT_CMD, 2, {0xCB, 0x16} }, + {INIT_CMD, 2, {0xCC, 0xAF} }, + {INIT_CMD, 2, {0xCD, 0xFF} }, + {INIT_CMD, 2, {0xCE, 0xFF} }, + {DELAY_CMD, 0x64, {} }, + {INIT_CMD, 2, {0xB0, 0x00} }, + {INIT_CMD, 2, {0xB3, 0x08} }, + {INIT_CMD, 2, {0xB0, 0x04} }, + {INIT_CMD, 2, {0xB8, 0x68} }, + {DELAY_CMD, 0x0A, {} }, + {INIT_CMD, 1, {0x11} }, + {DELAY_CMD, 0x78, {} }, + {INIT_CMD, 1, {0x29} }, + {DELAY_CMD, 0x14, {} }, +}; + +/* flapjack C18 AUO NT51021 panel : PANEL_AUO_NT51021D8P */ +static struct edid flapjack_auo_nt51021d8p_edid = { + .panel_bits_per_color = 8, + .panel_bits_per_pixel = 24, + .mode = { + .name = "1200x1920@60Hz", + .pixel_clock = 159420, + .lvds_dual_channel = 0, + .refresh = 60, + .ha = 1200, .hbl = 141, .hso = 80, .hspw = 1, .hborder = 0, + .va = 1920, .vbl = 61, .vso = 35, .vspw = 1, .vborder = 0, + .phsync = '-', .pvsync = '-', + .x_mm = 107, .y_mm = 132, + }, +}; + +static struct lcm_init_table auo_nt51021d8p_lcm_init_cmd[] = { + {INIT_CMD, 1, {0x11} }, + {DELAY_CMD, 0x78, {} }, + {INIT_CMD, 1, {0x29} }, + {DELAY_CMD, 0x14, {} }, +}; + +/* flapjack C19 INX OTA7290 panel : PANEL_INX_OTA7290D10P */ +static struct edid flapjack_inx_ota7290d10p_edid = { + .panel_bits_per_color = 8, + .panel_bits_per_pixel = 24, + .mode = { + .name = "1200x1920@60Hz", + .pixel_clock = 159420, + .lvds_dual_channel = 0, + .refresh = 60, + .ha = 1200, .hbl = 141, .hso = 80, .hspw = 1, .hborder = 0, + .va = 1920, .vbl = 61, .vso = 35, .vspw = 1, .vborder = 0, + .phsync = '-', .pvsync = '-', + .x_mm = 135, .y_mm = 216, + }, +}; + +static struct lcm_init_table inx_ota7290d10p_lcm_init_cmd[] = { + {INIT_CMD, 2, { 0xB0, 0x5A} }, + {INIT_CMD, 2, { 0xB1, 0x00} }, + {INIT_CMD, 2, { 0x89, 0x01} }, + {INIT_CMD, 2, { 0x91, 0x17} }, + {INIT_CMD, 2, { 0xB1, 0x03} }, + {INIT_CMD, 2, { 0x2C, 0x28} }, + {INIT_CMD, 2, { 0x00, 0xF1} }, + {INIT_CMD, 2, { 0x01, 0x78} }, + {INIT_CMD, 2, { 0x02, 0x3C} }, + {INIT_CMD, 2, { 0x03, 0x1E} }, + {INIT_CMD, 2, { 0x04, 0x8F} }, + {INIT_CMD, 2, { 0x05, 0x01} }, + {INIT_CMD, 2, { 0x06, 0x00} }, + {INIT_CMD, 2, { 0x07, 0x00} }, + {INIT_CMD, 2, { 0x08, 0x00} }, + {INIT_CMD, 2, { 0x09, 0x00} }, + {INIT_CMD, 2, { 0x0A, 0x01} }, + {INIT_CMD, 2, { 0x0B, 0x3C} }, + {INIT_CMD, 2, { 0x0C, 0x00} }, + {INIT_CMD, 2, { 0x0D, 0x00} }, + {INIT_CMD, 2, { 0x0E, 0x24} }, + {INIT_CMD, 2, { 0x0F, 0x1C} }, + {INIT_CMD, 2, { 0x10, 0xC8} }, + {INIT_CMD, 2, { 0x11, 0x60} }, + {INIT_CMD, 2, { 0x12, 0x70} }, + {INIT_CMD, 2, { 0x13, 0x01} }, + {INIT_CMD, 2, { 0x14, 0xE3} }, + {INIT_CMD, 2, { 0x15, 0xFF} }, + {INIT_CMD, 2, { 0x16, 0x3D} }, + {INIT_CMD, 2, { 0x17, 0x0E} }, + {INIT_CMD, 2, { 0x18, 0x01} }, + {INIT_CMD, 2, { 0x19, 0x00} }, + {INIT_CMD, 2, { 0x1A, 0x00} }, + {INIT_CMD, 2, { 0x1B, 0xFC} }, + {INIT_CMD, 2, { 0x1C, 0x0B} }, + {INIT_CMD, 2, { 0x1D, 0xA0} }, + {INIT_CMD, 2, { 0x1E, 0x03} }, + {INIT_CMD, 2, { 0x1F, 0x04} }, + {INIT_CMD, 2, { 0x20, 0x0C} }, + {INIT_CMD, 2, { 0x21, 0x00} }, + {INIT_CMD, 2, { 0x22, 0x04} }, + {INIT_CMD, 2, { 0x23, 0x81} }, + {INIT_CMD, 2, { 0x24, 0x1F} }, + {INIT_CMD, 2, { 0x25, 0x10} }, + {INIT_CMD, 2, { 0x26, 0x9B} }, + {INIT_CMD, 2, { 0x2D, 0x01} }, + {INIT_CMD, 2, { 0x2E, 0x84} }, + {INIT_CMD, 2, { 0x2F, 0x00} }, + {INIT_CMD, 2, { 0x30, 0x02} }, + {INIT_CMD, 2, { 0x31, 0x08} }, + {INIT_CMD, 2, { 0x32, 0x01} }, + {INIT_CMD, 2, { 0x33, 0x1C} }, + {INIT_CMD, 2, { 0x34, 0x70} }, + {INIT_CMD, 2, { 0x35, 0xFF} }, + {INIT_CMD, 2, { 0x36, 0xFF} }, + {INIT_CMD, 2, { 0x37, 0xFF} }, + {INIT_CMD, 2, { 0x38, 0xFF} }, + {INIT_CMD, 2, { 0x39, 0xFF} }, + {INIT_CMD, 2, { 0x3A, 0x05} }, + {INIT_CMD, 2, { 0x3B, 0x00} }, + {INIT_CMD, 2, { 0x3C, 0x00} }, + {INIT_CMD, 2, { 0x3D, 0x00} }, + {INIT_CMD, 2, { 0x3E, 0x0F} }, + {INIT_CMD, 2, { 0x3F, 0xA4} }, + {INIT_CMD, 2, { 0x40, 0x28} }, + {INIT_CMD, 2, { 0x41, 0xFC} }, + {INIT_CMD, 2, { 0x42, 0x01} }, + {INIT_CMD, 2, { 0x43, 0x08} }, + {INIT_CMD, 2, { 0x44, 0x05} }, + {INIT_CMD, 2, { 0x45, 0xF0} }, + {INIT_CMD, 2, { 0x46, 0x01} }, + {INIT_CMD, 2, { 0x47, 0x02} }, + {INIT_CMD, 2, { 0x48, 0x00} }, + {INIT_CMD, 2, { 0x49, 0x58} }, + {INIT_CMD, 2, { 0x4A, 0x00} }, + {INIT_CMD, 2, { 0x4B, 0x05} }, + {INIT_CMD, 2, { 0x4C, 0x03} }, + {INIT_CMD, 2, { 0x4D, 0xD0} }, + {INIT_CMD, 2, { 0x4E, 0x13} }, + {INIT_CMD, 2, { 0x4F, 0xFF} }, + {INIT_CMD, 2, { 0x50, 0x0A} }, + {INIT_CMD, 2, { 0x51, 0x53} }, + {INIT_CMD, 2, { 0x52, 0x26} }, + {INIT_CMD, 2, { 0x53, 0x22} }, + {INIT_CMD, 2, { 0x54, 0x09} }, + {INIT_CMD, 2, { 0x55, 0x22} }, + {INIT_CMD, 2, { 0x56, 0x00} }, + {INIT_CMD, 2, { 0x57, 0x1C} }, + {INIT_CMD, 2, { 0x58, 0x03} }, + {INIT_CMD, 2, { 0x59, 0x3F} }, + {INIT_CMD, 2, { 0x5A, 0x28} }, + {INIT_CMD, 2, { 0x5B, 0x01} }, + {INIT_CMD, 2, { 0x5C, 0xCC} }, + {INIT_CMD, 2, { 0x5D, 0x21} }, + {INIT_CMD, 2, { 0x5E, 0x04} }, + {INIT_CMD, 2, { 0x5F, 0x13} }, + {INIT_CMD, 2, { 0x60, 0x42} }, + {INIT_CMD, 2, { 0x61, 0x08} }, + {INIT_CMD, 2, { 0x62, 0x64} }, + {INIT_CMD, 2, { 0x63, 0xEB} }, + {INIT_CMD, 2, { 0x64, 0x10} }, + {INIT_CMD, 2, { 0x65, 0xA8} }, + {INIT_CMD, 2, { 0x66, 0x84} }, + {INIT_CMD, 2, { 0x67, 0x8E} }, + {INIT_CMD, 2, { 0x68, 0x29} }, + {INIT_CMD, 2, { 0x69, 0x11} }, + {INIT_CMD, 2, { 0x6A, 0x42} }, + {INIT_CMD, 2, { 0x6B, 0x38} }, + {INIT_CMD, 2, { 0x6C, 0x21} }, + {INIT_CMD, 2, { 0x6D, 0x84} }, + {INIT_CMD, 2, { 0x6E, 0x50} }, + {INIT_CMD, 2, { 0x6F, 0xB6} }, + {INIT_CMD, 2, { 0x70, 0x0E} }, + {INIT_CMD, 2, { 0x71, 0xA1} }, + {INIT_CMD, 2, { 0x72, 0xCE} }, + {INIT_CMD, 2, { 0x73, 0xF8} }, + {INIT_CMD, 2, { 0x74, 0xDA} }, + {INIT_CMD, 2, { 0x75, 0x1A} }, + {INIT_CMD, 2, { 0x76, 0x00} }, + {INIT_CMD, 2, { 0x77, 0x00} }, + {INIT_CMD, 2, { 0x78, 0x5F} }, + {INIT_CMD, 2, { 0x79, 0xE0} }, + {INIT_CMD, 2, { 0x7A, 0x01} }, + {INIT_CMD, 2, { 0x7B, 0xFF} }, + {INIT_CMD, 2, { 0x7C, 0xFF} }, + {INIT_CMD, 2, { 0x7D, 0xFF} }, + {INIT_CMD, 2, { 0x7E, 0xFF} }, + {INIT_CMD, 2, { 0x7F, 0xFE} }, + {INIT_CMD, 2, { 0xB1, 0x02} }, + {INIT_CMD, 2, { 0x00, 0xFF} }, + {INIT_CMD, 2, { 0x01, 0x01} }, + {INIT_CMD, 2, { 0x02, 0x00} }, + {INIT_CMD, 2, { 0x03, 0x00} }, + {INIT_CMD, 2, { 0x04, 0x00} }, + {INIT_CMD, 2, { 0x05, 0x00} }, + {INIT_CMD, 2, { 0x06, 0x00} }, + {INIT_CMD, 2, { 0x07, 0x00} }, + {INIT_CMD, 2, { 0x08, 0xC0} }, + {INIT_CMD, 2, { 0x09, 0x00} }, + {INIT_CMD, 2, { 0x0A, 0x00} }, + {INIT_CMD, 2, { 0x0B, 0x04} }, + {INIT_CMD, 2, { 0x0C, 0xE6} }, + {INIT_CMD, 2, { 0x0D, 0x0D} }, + {INIT_CMD, 2, { 0x0F, 0x08} }, + {INIT_CMD, 2, { 0x10, 0xE5} }, + {INIT_CMD, 2, { 0x11, 0xA8} }, + {INIT_CMD, 2, { 0x12, 0xEC} }, + {INIT_CMD, 2, { 0x13, 0x54} }, + {INIT_CMD, 2, { 0x14, 0x5A} }, + {INIT_CMD, 2, { 0x15, 0xD5} }, + {INIT_CMD, 2, { 0x16, 0x23} }, + {INIT_CMD, 2, { 0x17, 0x11} }, + {INIT_CMD, 2, { 0x18, 0x2F} }, + {INIT_CMD, 2, { 0x19, 0x93} }, + {INIT_CMD, 2, { 0x1A, 0xA6} }, + {INIT_CMD, 2, { 0x1B, 0x0F} }, + {INIT_CMD, 2, { 0x1C, 0xFF} }, + {INIT_CMD, 2, { 0x1D, 0xFF} }, + {INIT_CMD, 2, { 0x1E, 0xFF} }, + {INIT_CMD, 2, { 0x1F, 0xFF} }, + {INIT_CMD, 2, { 0x20, 0xFF} }, + {INIT_CMD, 2, { 0x21, 0xFF} }, + {INIT_CMD, 2, { 0x22, 0xFF} }, + {INIT_CMD, 2, { 0x23, 0xFF} }, + {INIT_CMD, 2, { 0x24, 0xFF} }, + {INIT_CMD, 2, { 0x25, 0xFF} }, + {INIT_CMD, 2, { 0x26, 0xFF} }, + {INIT_CMD, 2, { 0x27, 0x1F} }, + {INIT_CMD, 2, { 0x28, 0xC8} }, + {INIT_CMD, 2, { 0x29, 0xFF} }, + {INIT_CMD, 2, { 0x2A, 0xFF} }, + {INIT_CMD, 2, { 0x2B, 0xFF} }, + {INIT_CMD, 2, { 0x2C, 0x07} }, + {INIT_CMD, 2, { 0x2D, 0x03} }, + {INIT_CMD, 2, { 0x33, 0x09} }, + {INIT_CMD, 2, { 0x35, 0x7F} }, + {INIT_CMD, 2, { 0x36, 0x0C} }, + {INIT_CMD, 2, { 0x38, 0x7F} }, + {INIT_CMD, 2, { 0x3A, 0x80} }, + {INIT_CMD, 2, { 0x3B, 0x55} }, + {INIT_CMD, 2, { 0x3C, 0xE2} }, + {INIT_CMD, 2, { 0x3D, 0x32} }, + {INIT_CMD, 2, { 0x3E, 0x00} }, + {INIT_CMD, 2, { 0x3F, 0x58} }, + {INIT_CMD, 2, { 0x40, 0x06} }, + {INIT_CMD, 2, { 0x41, 0x80} }, + {INIT_CMD, 2, { 0x42, 0xCB} }, + {INIT_CMD, 2, { 0x43, 0x2C} }, + {INIT_CMD, 2, { 0x44, 0x61} }, + {INIT_CMD, 2, { 0x45, 0x39} }, + {INIT_CMD, 2, { 0x46, 0x00} }, + {INIT_CMD, 2, { 0x47, 0x00} }, + {INIT_CMD, 2, { 0x48, 0x8B} }, + {INIT_CMD, 2, { 0x49, 0xD2} }, + {INIT_CMD, 2, { 0x4A, 0x01} }, + {INIT_CMD, 2, { 0x4B, 0x00} }, + {INIT_CMD, 2, { 0x4C, 0x10} }, + {INIT_CMD, 2, { 0x4D, 0xC0} }, + {INIT_CMD, 2, { 0x4E, 0x0F} }, + {INIT_CMD, 2, { 0x4F, 0xF1} }, + {INIT_CMD, 2, { 0x50, 0x78} }, + {INIT_CMD, 2, { 0x51, 0x7A} }, + {INIT_CMD, 2, { 0x52, 0x34} }, + {INIT_CMD, 2, { 0x53, 0x99} }, + {INIT_CMD, 2, { 0x54, 0xA2} }, + {INIT_CMD, 2, { 0x55, 0x03} }, + {INIT_CMD, 2, { 0x56, 0x6C} }, + {INIT_CMD, 2, { 0x57, 0x1A} }, + {INIT_CMD, 2, { 0x58, 0x05} }, + {INIT_CMD, 2, { 0x59, 0x30} }, + {INIT_CMD, 2, { 0x5A, 0x1E} }, + {INIT_CMD, 2, { 0x5B, 0x8F} }, + {INIT_CMD, 2, { 0x5C, 0xC7} }, + {INIT_CMD, 2, { 0x5D, 0xE3} }, + {INIT_CMD, 2, { 0x5E, 0xF1} }, + {INIT_CMD, 2, { 0x5F, 0x78} }, + {INIT_CMD, 2, { 0x60, 0x3C} }, + {INIT_CMD, 2, { 0x61, 0x36} }, + {INIT_CMD, 2, { 0x62, 0x1E} }, + {INIT_CMD, 2, { 0x63, 0x1B} }, + {INIT_CMD, 2, { 0x64, 0x8F} }, + {INIT_CMD, 2, { 0x65, 0xC7} }, + {INIT_CMD, 2, { 0x66, 0xE3} }, + {INIT_CMD, 2, { 0x67, 0x31} }, + {INIT_CMD, 2, { 0x68, 0x14} }, + {INIT_CMD, 2, { 0x69, 0x89} }, + {INIT_CMD, 2, { 0x6A, 0x70} }, + {INIT_CMD, 2, { 0x6B, 0x8C} }, + {INIT_CMD, 2, { 0x6C, 0x8D} }, + {INIT_CMD, 2, { 0x6D, 0x8D} }, + {INIT_CMD, 2, { 0x6E, 0x8D} }, + {INIT_CMD, 2, { 0x6F, 0x8D} }, + {INIT_CMD, 2, { 0x70, 0xC7} }, + {INIT_CMD, 2, { 0x71, 0xE3} }, + {INIT_CMD, 2, { 0x72, 0xF1} }, + {INIT_CMD, 2, { 0x73, 0xD8} }, + {INIT_CMD, 2, { 0x74, 0xD8} }, + {INIT_CMD, 2, { 0x75, 0xD8} }, + {INIT_CMD, 2, { 0x76, 0x18} }, + {INIT_CMD, 2, { 0x77, 0x00} }, + {INIT_CMD, 2, { 0x78, 0x00} }, + {INIT_CMD, 2, { 0x79, 0x00} }, + {INIT_CMD, 2, { 0x7A, 0xC6} }, + {INIT_CMD, 2, { 0x7B, 0xC6} }, + {INIT_CMD, 2, { 0x7C, 0xC6} }, + {INIT_CMD, 2, { 0x7D, 0xC6} }, + {INIT_CMD, 2, { 0x7E, 0xC6} }, + {INIT_CMD, 2, { 0x7F, 0xE3} }, + {INIT_CMD, 2, { 0x0B, 0x04} }, + {INIT_CMD, 2, { 0xB1, 0x03} }, + {INIT_CMD, 2, { 0x2C, 0x2C} }, + {INIT_CMD, 2, { 0xB1, 0x00} }, + {INIT_CMD, 2, { 0x89, 0x03} }, + {INIT_CMD, 1, {0x11} }, + {DELAY_CMD, 0x78, {} }, + {INIT_CMD, 1, {0x29} }, + {DELAY_CMD, 0x14, {} }, +}; + +struct panel_info flapjack_panel_info[] = { + PANEL(PANEL_FLAPJACK_BOE_TV101WUM_NG0, + 74000, + flapjack_boe_tv101wum_edid, + boe_tv101wum_lcm_init_cmd), + PANEL(PANEL_FLAPJACK_BOE_TV080WUM_NG0, + 212000, + flapjack_boe_tv080wum_edid, + boe_tv080wum_lcm_init_cmd), + PANEL(PANEL_FLAPJACK_INX_OTA7290D10P, + 1191000, + flapjack_inx_ota7290d10p_edid, + inx_ota7290d10p_lcm_init_cmd), + PANEL(PANEL_FLAPJACK_AUO_NT51021D8P, + 1027000, + flapjack_auo_nt51021d8p_edid, + auo_nt51021d8p_lcm_init_cmd), + {{PANEL_FLAPJACK_UNKNOWN}, "PANEL_FLAPJACK_UNKNOWN", + 0, NULL, NULL, 0}, +}; + +static union panel_id get_panel_id_from_adc(int channel, + struct board_display_intf *intf) +{ + uint32_t ver = board_id(); + + if (ver == BOARD_ID_UNKNOWN || ver < 3) { + int id; + int value = auxadc_get_voltage(channel); + + for (id = 0; id < intf->all_panel_info_size; id++) { + if (ABS(value - intf->all_panel_info[id].voltage) < tolerance) + return intf->all_panel_info[id].disp_id; + } + + return (union panel_id)PANEL_FLAPJACK_UNKNOWN; + } else + return (union panel_id)((sku_id() >> FLAPJACK_PANEL_ID_BIT_POSITION) & 0xf); +} + + +static union panel_id flapjack_get_panel_id(struct board_display_intf *intf) +{ + union panel_id id; + + id = get_panel_id_from_adc(FLAPJACK_PANEL_ADC_ID, + intf); + return id; +}; + +static bool flapjack_is_panel_id_valid(union panel_id id) +{ + if (id.value < PANEL_FLAPJACK_UNKNOWN) + return true; + return false; +}; + +static int flapjack_backlight(struct board_display_intf *intf) +{ + configure_backlight(); + return 0; +}; + +static int flapjack_power(struct board_display_intf *intf) +{ + int result = 0; + switch (intf->cur_panel_info->disp_id.value) { + case PANEL_FLAPJACK_BOE_HIMAX8279D10P: + case PANEL_FLAPJACK_BOE_HIMAX8279D8P: + case PANEL_FLAPJACK_INX_OTA7290D10P: + case PANEL_FLAPJACK_AUO_NT51021D8P: + gpio_output(PP3300_LCM_EN, 1); + gpio_output(PP1800_LCM_EN, 1); + + gpio_output(GPIO(LCM_RST), 0); + mdelay(20); + gpio_output(GPIO(LCM_RST), 1); + mdelay(10); + break; + case PANEL_FLAPJACK_UNKNOWN: + default: + result = ERR; + break; + } + return result; +}; + +struct board_display_intf flapjack_display_intf = { + .board = "flapjack", + .all_panel_info = flapjack_panel_info, + .all_panel_info_size = ARRAY_SIZE(flapjack_panel_info), + .cur_panel_info = NULL, + .get_panel_id = &flapjack_get_panel_id, + .is_panel_id_valid = &flapjack_is_panel_id_valid, + .backlight = &flapjack_backlight, + .power = &flapjack_power, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/32840 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e50df59de3db9ed6efcccbd01b553c21f793a3f Gerrit-Change-Number: 32840 Gerrit-PatchSet: 1 Gerrit-Owner: Jerry Han <hanxu5(a)huaqin.corp-partner.google.com> Gerrit-MessageType: newchange

6 6

Change in ...coreboot[master]: intel/skylake: nhlt: Add 24 bit blobs for Max98373
by Jenny Tc (Code Review) 07 Aug '23

07 Aug '23

Jenny Tc has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31635 Change subject: intel/skylake: nhlt: Add 24 bit blobs for Max98373 ...................................................................... intel/skylake: nhlt: Add 24 bit blobs for Max98373 Enable 24 bit nhlt blobs and remove 16 bit blobs. 16 bit and 24 bit blobs cannot be supported together since the OS NHLT parsing relies on container bit format. The container bit format for 16 and 24 bit capture are same (32) and putting both blobs in configs results in selecting the first blob. To enable 24 and 16 bit blobs together, the core nhlt parsing logic has to be changed which would impact SKL and KBL platforms. In order to minimize the impact, the 16 bit blob is removed considering that the machine driver for max98373 is expected to support only format due to topology configuration for 16 and 24 bit. BUG=b:110795132 BRANCH=none TEST=Verify playback after flashing CQ-DEPEND=*806750 Change-Id: I62cc109fb0aca9269736779a6ce80980b0571b78 Signed-off-by: Jenny TC <jenny.tc(a)intel.com> --- M src/soc/intel/skylake/nhlt/Makefile.inc M src/soc/intel/skylake/nhlt/max98373.c 2 files changed, 6 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/31635/1 diff --git a/src/soc/intel/skylake/nhlt/Makefile.inc b/src/soc/intel/skylake/nhlt/Makefile.inc index 5c8bd80..548747a 100644 --- a/src/soc/intel/skylake/nhlt/Makefile.inc +++ b/src/soc/intel/skylake/nhlt/Makefile.inc @@ -21,7 +21,6 @@ DMIC_4CH_48KHZ_32B = dmic-4ch-48khz-32b.bin NAU88L25 = nau88l25-2ch-48khz-24b.bin MAX98357_RENDER = max98357-render-2ch-48khz-24b.bin -MAX98373_RENDER_16B = max98373-render-2ch-48khz-16b.bin MAX98373_RENDER_24B = max98373-render-2ch-48khz-24b.bin MAX98927_RENDER_24B = max98927-render-2ch-48khz-24b.bin MAX98927_RENDER_16B = max98927-render-2ch-48khz-16b.bin diff --git a/src/soc/intel/skylake/nhlt/max98373.c b/src/soc/intel/skylake/nhlt/max98373.c index 0e3a413..a781943 100644 --- a/src/soc/intel/skylake/nhlt/max98373.c +++ b/src/soc/intel/skylake/nhlt/max98373.c @@ -25,35 +25,26 @@ .speaker_mask = SPEAKER_FRONT_LEFT | SPEAKER_FRONT_RIGHT, .settings_file = "max98373-render-2ch-48khz-24b.bin", }, - /* 48 KHz 16-bits per sample. */ - { - .num_channels = 2, - .sample_freq_khz = 48, - .container_bits_per_sample = 16, - .valid_bits_per_sample = 16, - .speaker_mask = SPEAKER_FRONT_LEFT | SPEAKER_FRONT_RIGHT, - .settings_file = "max98373-render-2ch-48khz-16b.bin", - } }; static const struct nhlt_format_config max98373_capture_formats[] = { - /* 48 KHz 16-bits per sample - Quad Channel. */ + /* 48 KHz 24-bits per sample - Quad Channel. */ { .num_channels = 4, .sample_freq_khz = 48, .container_bits_per_sample = 32, - .valid_bits_per_sample = 16, + .valid_bits_per_sample = 24, .speaker_mask = SPEAKER_FRONT_LEFT | SPEAKER_FRONT_RIGHT, - .settings_file = "max98373-render-2ch-48khz-16b.bin", + .settings_file = "max98373-render-2ch-48khz-24b.bin", }, - /* 48 KHz 16-bits per sample - Stereo Channel */ + /* 48 KHz 24-bits per sample - Stereo Channel */ { .num_channels = 2, .sample_freq_khz = 48, .container_bits_per_sample = 32, - .valid_bits_per_sample = 16, + .valid_bits_per_sample = 24, .speaker_mask = SPEAKER_FRONT_LEFT | SPEAKER_FRONT_RIGHT, - .settings_file = "max98373-render-2ch-48khz-16b.bin", + .settings_file = "max98373-render-2ch-48khz-24b.bin", }, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/31635 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62cc109fb0aca9269736779a6ce80980b0571b78 Gerrit-Change-Number: 31635 Gerrit-PatchSet: 1 Gerrit-Owner: Jenny Tc <jenny.tc(a)intel.com> Gerrit-MessageType: newchange

9 29

Change in ...coreboot[master]: mb/pcengines/apu2: describe serial ports in ACPI
by Michał Żygowski (Code Review) 03 Aug '23

03 Aug '23

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32989 Change subject: mb/pcengines/apu2: describe serial ports in ACPI ...................................................................... mb/pcengines/apu2: describe serial ports in ACPI FreeBSD users had to manually configure serial ports on their installations. Defining serial ports in ACPI save that effort. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I0de4172a1884abbe9d625060a9045c9d71469e27 --- A src/mainboard/pcengines/apu2/acpi/superio.asl M src/mainboard/pcengines/apu2/dsdt.asl 2 files changed, 68 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/32989/1 diff --git a/src/mainboard/pcengines/apu2/acpi/superio.asl b/src/mainboard/pcengines/apu2/acpi/superio.asl new file mode 100644 index 0000000..c61e3d7 --- /dev/null +++ b/src/mainboard/pcengines/apu2/acpi/superio.asl @@ -0,0 +1,65 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 PC Engines Gmbh + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB.PCI0.LIBR) { + + Device (COM1) { + Name (_HID, EISAID ("PNP0501")) + Name (_UID, 1) + + Method (_STA, 0, NotSerialized) { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x03F8, 0x3F8, 0x08, 0x08) + IRQNoFlags () {4} + }) + + Name (_PRS, ResourceTemplate () + { + StartDependentFn (0, 0) { + IO (Decode16, 0x03F8, 0x3F8, 0x08, 0x08) + IRQNoFlags () {4} + } + EndDependentFn () + }) + } + + Device (COM2) { + Name (_HID, EISAID ("PNP0501")) + Name (_UID, 2) + + Method (_STA, 0, NotSerialized) { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x02F8, 0x2F8, 0x08, 0x08) + IRQNoFlags () {3} + }) + + Name (_PRS, ResourceTemplate () + { + StartDependentFn (0, 0) { + IO (Decode16, 0x02F8, 0x2F8, 0x08, 0x08) + IRQNoFlags () {3} + } + EndDependentFn () + }) + } +} \ No newline at end of file diff --git a/src/mainboard/pcengines/apu2/dsdt.asl b/src/mainboard/pcengines/apu2/dsdt.asl index 3bf0ed6..409f03d 100644 --- a/src/mainboard/pcengines/apu2/dsdt.asl +++ b/src/mainboard/pcengines/apu2/dsdt.asl @@ -81,5 +81,8 @@ /* Define the System Indicators for the platform */ #include "acpi/si.asl" + + /* Super IO devices (COM ports) */ + #include "acpi/superio.asl" } /* End of ASL file */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32989 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0de4172a1884abbe9d625060a9045c9d71469e27 Gerrit-Change-Number: 32989 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

6 12

Change in ...libgfxinit[master]: [WIP] gma: Add Gemini Lake support
by Nico Huber (Code Review) 02 Aug '23

02 Aug '23

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/libgfxinit/+/31611 Change subject: [WIP] gma: Add Gemini Lake support ...................................................................... [WIP] gma: Add Gemini Lake support Change-Id: I84347130fc3fcaf33d9f3d84fab47c67899c792d Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M common/Makefile.inc M common/broxton/hw-gfx-gma-ddi_phy.ads M common/broxton/hw-gfx-gma-plls.adb M common/broxton/hw-gfx-gma-power_and_clocks.adb M common/hw-gfx-gma-config.ads.template M common/hw-gfx-gma-registers.ads M common/hw-gfx-gma.ads R configs/apollolake C configs/geminilake 9 files changed, 109 insertions(+), 42 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/11/31611/1 diff --git a/common/Makefile.inc b/common/Makefile.inc index 61955eb..cfb2dfa 100644 --- a/common/Makefile.inc +++ b/common/Makefile.inc @@ -68,7 +68,7 @@ subdirs-y += ironlake else ifneq ($(filter Haswell Broadwell,$(CONFIG_GFX_GMA_CPU)),) subdirs-y += haswell_shared haswell -else ifneq ($(filter Broxton,$(CONFIG_GFX_GMA_CPU)),) +else ifneq ($(filter Apollolake Geminilake,$(CONFIG_GFX_GMA_CPU)),) subdirs-y += haswell_shared broxton else ifneq ($(filter Skylake Kabylake,$(CONFIG_GFX_GMA_CPU)),) subdirs-y += haswell_shared skylake diff --git a/common/broxton/hw-gfx-gma-ddi_phy.ads b/common/broxton/hw-gfx-gma-ddi_phy.ads index fc6cacf..e6301bf 100644 --- a/common/broxton/hw-gfx-gma-ddi_phy.ads +++ b/common/broxton/hw-gfx-gma-ddi_phy.ads @@ -16,7 +16,7 @@ private package HW.GFX.GMA.DDI_Phy is - type T is (BC, A); + type T is (BC, A, C); procedure Power_On (Phy : T); procedure Power_Off (Phy : T); diff --git a/common/broxton/hw-gfx-gma-plls.adb b/common/broxton/hw-gfx-gma-plls.adb index 087ff12..f7ecc05 100644 --- a/common/broxton/hw-gfx-gma-plls.adb +++ b/common/broxton/hw-gfx-gma-plls.adb @@ -170,6 +170,8 @@ PLL_10 : Registers_Index; PCS_DW12_LN01 : Registers_Index; PCS_DW12_GRP : Registers_Index; + TX_DW5_LN0 : Registers_Index; + TX_DW5_GRP : Registers_Index; end record; type Port_PLL_Array is array (Valid_PLLs) of Port_PLL_Regs; @@ -187,7 +189,9 @@ PLL_9 => BXT_PORT_PLL_9_A, PLL_10 => BXT_PORT_PLL_10_A, PCS_DW12_LN01 => BXT_PORT_PCS_DW12_01_A, - PCS_DW12_GRP => BXT_PORT_PCS_DW12_GRP_A), + PCS_DW12_GRP => BXT_PORT_PCS_DW12_GRP_A, + TX_DW5_LN0 => BXT_PORT_TX_DW5_LN0_A, + TX_DW5_GRP => BXT_PORT_TX_DW5_GRP_A), DPLL_B => (PLL_ENABLE => BXT_PORT_PLL_ENABLE_B, PLL_EBB_0 => BXT_PORT_PLL_EBB_0_B, @@ -201,7 +205,9 @@ PLL_9 => BXT_PORT_PLL_9_B, PLL_10 => BXT_PORT_PLL_10_B, PCS_DW12_LN01 => BXT_PORT_PCS_DW12_01_B, - PCS_DW12_GRP => BXT_PORT_PCS_DW12_GRP_B), + PCS_DW12_GRP => BXT_PORT_PCS_DW12_GRP_B, + TX_DW5_LN0 => BXT_PORT_TX_DW5_LN0_B, + TX_DW5_GRP => BXT_PORT_TX_DW5_GRP_B), DPLL_C => (PLL_ENABLE => BXT_PORT_PLL_ENABLE_C, PLL_EBB_0 => BXT_PORT_PLL_EBB_0_C, @@ -215,11 +221,15 @@ PLL_9 => BXT_PORT_PLL_9_C, PLL_10 => BXT_PORT_PLL_10_C, PCS_DW12_LN01 => BXT_PORT_PCS_DW12_01_C, - PCS_DW12_GRP => BXT_PORT_PCS_DW12_GRP_C)); + PCS_DW12_GRP => BXT_PORT_PCS_DW12_GRP_C, + TX_DW5_LN0 => BXT_PORT_TX_DW5_LN0_C, + TX_DW5_GRP => BXT_PORT_TX_DW5_GRP_C)); PORT_PLL_ENABLE : constant := 1 * 2 ** 31; PORT_PLL_ENABLE_LOCK : constant := 1 * 2 ** 30; PORT_PLL_ENABLE_REF_SEL : constant := 1 * 2 ** 27; + PORT_PLL_POWER_ENABLE : constant := 1 * 2 ** 26; + PORT_PLL_POWER_STATE : constant := 1 * 2 ** 25; PORT_PLL_EBB0_P1_SHIFT : constant := 13; PORT_PLL_EBB0_P1_MASK : constant := 16#07# * 2 ** 13; @@ -336,8 +346,17 @@ begin pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity)); - Set_Mask (PORT (P).PLL_ENABLE, PORT_PLL_ENABLE_REF_SEL); -- non-SSC ref - Unset_Mask (PORT (P).PLL_EBB_4, PORT_PLL_EBB4_10BIT_CLK_ENABLE); + Set_Mask (PORT (P).PLL_ENABLE, PORT_PLL_ENABLE_REF_SEL); -- non-SSC ref + + if Config.Has_Port_PLL_Pwr_En then + Set_Mask (PORT (P).PLL_ENABLE, PORT_PLL_POWER_ENABLE); + Wait_Set_Mask + (Register => PORT (P).PLL_ENABLE, + Mask => PORT_PLL_POWER_STATE, + TOut_MS => 1); -- 200us + end if; + + Unset_Mask (PORT (P).PLL_EBB_4, PORT_PLL_EBB4_10BIT_CLK_ENABLE); Unset_And_Set_Mask (Register => PORT (P).PLL_EBB_0, @@ -388,7 +407,16 @@ Wait_Set_Mask (Register => PORT (P).PLL_ENABLE, Mask => PORT_PLL_ENABLE_LOCK, - TOut_MS => 1); -- 100us + TOut_MS => 1); -- 200us + + if (Config.Has_DCC_Delay_Range) then + declare + Delay_Range : Word32; + begin + Read (PORT (P).DW5_LN0, Delay_Range); + Delay_Range := Delay_Range or PORT_TX_DW5_DCC_DELAY_RANGE_2; + Write (PORT (P).DW5_GRP, Delay_Range); + end if; Read (PORT (P).PCS_DW12_LN01, PCS); PCS := PCS and not PORT_PCS_LANE_STAGGER_MASK; @@ -471,6 +499,13 @@ begin if PLL in Valid_PLLs then Unset_Mask (PORT (PLL).PLL_ENABLE, PORT_PLL_ENABLE); + if Config.Has_Port_PLL_Pwr_En then + Unset_Mask (PORT (P).PLL_ENABLE, PORT_PLL_POWER_ENABLE); + Wait_Unset_Mask + (Register => PORT (P).PLL_ENABLE, + Mask => PORT_PLL_POWER_STATE, + TOut_MS => 1); -- 200us + end if; end if; end Free; diff --git a/common/broxton/hw-gfx-gma-power_and_clocks.adb b/common/broxton/hw-gfx-gma-power_and_clocks.adb index 8aa9a21..4e3fbc3 100644 --- a/common/broxton/hw-gfx-gma-power_and_clocks.adb +++ b/common/broxton/hw-gfx-gma-power_and_clocks.adb @@ -214,22 +214,12 @@ ---------------------------------------------------------------------------- - CDClk_Ref : constant := 19_200_000; - procedure Set_CDClk (Freq : Frequency_Type) with - Pre => - Freq = CDClk_Ref or Freq = 144_000_000 or Freq = 288_000_000 or - Freq = 384_000_000 or Freq = 576_000_000 or Freq = 624_000_000 + Pre => Config.Valid_CDClk (Freq) is VCO : constant Int64 := - CDClk_Ref * - (if Freq = CDClk_Ref then - 0 - elsif Freq = 624_000_000 then - 65 - else - 60); + Config.Broxton_CDClk_Ref * Config.CDClk_Ratio (Freq); CDCLK_CD2X_Div_Sel : constant Word32 := (case VCO / Freq is -- CDClk = VCO / 2 / Div when 2 => CDCLK_CD2X_DIV_SEL_1, @@ -255,7 +245,8 @@ Unset_And_Set_Mask (Register => BXT_DE_PLL_CTL, Mask_Unset => BXT_DE_PLL_RATIO_MASK, - Mask_Set => Word32 (VCO / CDClk_Ref)); + Mask_Set => (if Freq = Config.Broxton_CDClk_Ref then 0 else + Word32 (VCO / Config.Broxton_CDClk_Ref))); Write (Register => BXT_DE_PLL_ENABLE, Value => BXT_DE_PLL_PLL_ENABLE); @@ -297,7 +288,7 @@ -- Linux' i915 never keeps the PLL disabled but runs it -- at a "ratio" of 0 with CDClk at its reference clock. - Set_CDClk (CDClk_Ref); + Set_CDClk (Config.Broxton_CDClk_Ref); PW_Off (PW1); end Post_All_Off; diff --git a/common/hw-gfx-gma-config.ads.template b/common/hw-gfx-gma-config.ads.template index 4653ae9..972cfa8 100644 --- a/common/hw-gfx-gma-config.ads.template +++ b/common/hw-gfx-gma-config.ads.template @@ -40,7 +40,8 @@ Has_Internal_Display : constant Boolean := Internal_Display /= None; Internal_Is_EDP : constant Boolean := Internal_Display = DP; Have_DVI_I : constant Boolean := Analog_I2C_Port /= PCH_DAC; - Has_Presence_Straps : constant Boolean := CPU /= Broxton; + Is_Broxton : constant Boolean := CPU in Apollolake..Geminilake; + Has_Presence_Straps : constant Boolean := not Is_Broxton; Is_ULT : constant Boolean := CPU_Var = ULT; Is_ULX : constant Boolean := CPU_Var = ULX; Is_LP : constant Boolean := Is_ULT or Is_ULX; @@ -57,7 +58,7 @@ Has_Pipe_MSA_Misc : constant Boolean := CPU >= Haswell; Has_Pipeconf_Misc : constant Boolean := CPU >= Broadwell; Has_Pipeconf_BPC : constant Boolean := CPU /= Haswell; - Has_Plane_Control : constant Boolean := CPU >= Broxton; + Has_Plane_Control : constant Boolean := CPU >= Apollolake; Has_DSP_Linoff : constant Boolean := CPU <= Ivybridge; Has_PF_Pipe_Select : constant Boolean := CPU in Ivybridge .. Haswell; Has_Cursor_FBC_Control : constant Boolean := CPU >= Ivybridge; @@ -73,7 +74,7 @@ Has_PCH_Panel_Power : constant Boolean := CPU >= Ironlake; ----- PCH/FDI: --------- - Has_PCH : constant Boolean := CPU /= Broxton and CPU /= G45; + Has_PCH : constant Boolean := not Is_Broxton and CPU /= G45; Has_PCH_DAC : constant Boolean := CPU in Ironlake .. Ivybridge or (CPU in Haswell .. Broadwell and not Is_LP); @@ -103,7 +104,9 @@ and Is_LP) or CPU >= Skylake; - Has_DDI_PHYs : constant Boolean := CPU = Broxton; + Has_DDI_PHYs : constant Boolean := Is_Broxton; + Has_Dual_DDI_Phy_BC : constant Boolean := CPU = Apollolake; + Has_Port_PLL_Pwr_En : constant Boolean := CPU = Geminilake; Has_DDI_D : constant Boolean := CPU >= Haswell and not Is_LP and @@ -112,8 +115,8 @@ Has_DDI_D; Has_DDI_Buffer_Trans : constant Boolean := CPU >= Haswell and - CPU /= Broxton; - Has_Low_Voltage_Swing : constant Boolean := CPU >= Broxton; + not Is_Broxton; + Has_Low_Voltage_Swing : constant Boolean := CPU >= Apollolake; Has_Iboost_Config : constant Boolean := CPU >= Skylake; Use_KBL_DDI_Buf_Trans : constant Boolean := CPU = Kabylake; @@ -126,7 +129,7 @@ ----- GMBUS: ----------- Ungate_GMBUS_Unit_Level : constant Boolean := CPU >= Skylake; - GMBUS_Alternative_Pins : constant Boolean := CPU = Broxton; + GMBUS_Alternative_Pins : constant Boolean := Is_Broxton; Has_PCH_GMBUS : constant Boolean := CPU >= Ironlake; ----- Power: ----------- @@ -178,7 +181,8 @@ DP3 => CPU_Var = Normal, Analog => CPU_Var = Normal, others => True), - Broxton => + Apollolake | + Geminilake => (Internal => Config.Internal_Display = DP, DP1 => True, DP2 => True, @@ -234,11 +238,12 @@ Default_DDI_HDMI_Buffer_Translation : constant DDI_HDMI_Buf_Trans_Range := (case CPU is - when Haswell => 6, - when Broadwell => 7, - when Broxton => 8, - when Skylake => 8, - when others => 0); + when Haswell => 6, + when Broadwell => 7, + when Apollolake | + Geminilake => 8, + when Skylake => 8, + when others => 0); ---------------------------------------------------------------------------- @@ -250,7 +255,8 @@ Ivybridge => 400_000_000, when Haswell | Broadwell => (if Is_ULX then 337_500_000 else 450_000_000), - when Broxton => 288_000_000, + when Apollolake => 288_000_000, + when Geminilake => 158_400_000, when Skylake | Kabylake => 337_500_000); @@ -262,13 +268,34 @@ Ivybridge => 125_000_000, when Haswell | Broadwell => (if Is_LP then 24_000_000 else 125_000_000), - when Broxton => Frequency_Type'First, -- none needed + when Apollolake | + Geminilake => Frequency_Type'First, -- none needed when Skylake | Kabylake => 24_000_000); Raw_Clock : Frequency_Type := Default_RawClk_Freq with Part_Of => GMA.Config_State; + Broxton_CDClk_Ref : constant := 19_200_000; + + function Valid_CDClk (Freq : Frequency_Type) return Boolean is + (case CPU is + when Geminilake => + Freq = Broxton_CDClk_Ref or Freq = 79_200_000 or + Freq = 158_400_000 or Freq = 316_800_000, + when Apollolake => + Freq = Broxton_CDClk_Ref or Freq = 144_000_000 or + Freq = 288_000_000 or Freq = 384_000_000 or + Freq = 576_000_000 or Freq = 624_000_000, + when others => + True); + + function CDClk_Ratio (Freq : Frequency_Type) return Int64 is + (case CPU is + when Geminilake => 33, + when Apollolake => if Freq = 624_000_000 then 65 else 60, + when others => 1); + ---------------------------------------------------------------------------- -- Maximum source width with enabled scaler. This only accounts @@ -414,7 +441,8 @@ when Normal => Is_Broadwell (Device_Id), when ULT => Is_Broadwell_U (Device_Id), when ULX => Is_Broadwell_Y (Device_Id)), - when Broxton => (Device_Id and 16#fffe#) = 16#5a84#, + when Apollolake => (Device_Id and 16#fffe#) = 16#5a84#, + when Geminilake => (Device_Id and 16#fffe#) = 16#3184#, when Skylake => (case CPU_Var is when Normal => Is_Skylake (Device_Id), when ULT => Is_Skylake_U (Device_Id), diff --git a/common/hw-gfx-gma-registers.ads b/common/hw-gfx-gma-registers.ads index 1220d1a..b14194b 100644 --- a/common/hw-gfx-gma-registers.ads +++ b/common/hw-gfx-gma-registers.ads @@ -413,6 +413,7 @@ BXT_PORT_TX_DW2_LN0_B, BXT_PORT_TX_DW3_LN0_B, BXT_PORT_TX_DW4_LN0_B, + BXT_PORT_TX_DW5_LN0_B, BXT_PORT_TX_DW14_LN0_B, BXT_PORT_TX_DW14_LN1_B, BXT_PORT_TX_DW14_LN2_B, @@ -422,6 +423,7 @@ BXT_PORT_TX_DW2_LN0_C, BXT_PORT_TX_DW3_LN0_C, BXT_PORT_TX_DW4_LN0_C, + BXT_PORT_TX_DW5_LN0_C, BXT_PORT_TX_DW14_LN0_C, BXT_PORT_TX_DW14_LN1_C, BXT_PORT_TX_DW14_LN2_C, @@ -431,11 +433,13 @@ BXT_PORT_TX_DW2_GRP_B, BXT_PORT_TX_DW3_GRP_B, BXT_PORT_TX_DW4_GRP_B, + BXT_PORT_TX_DW5_GRP_B, BXT_PORT_PCS_DW10_GRP_C, BXT_PORT_PCS_DW12_GRP_C, BXT_PORT_TX_DW2_GRP_C, BXT_PORT_TX_DW3_GRP_C, BXT_PORT_TX_DW4_GRP_C, + BXT_PORT_TX_DW5_GRP_C, BXT_DE_PLL_CTL, HTOTAL_EDP, HBLANK_EDP, @@ -722,6 +726,7 @@ BXT_PORT_TX_DW2_LN0_A, BXT_PORT_TX_DW3_LN0_A, BXT_PORT_TX_DW4_LN0_A, + BXT_PORT_TX_DW5_LN0_A, BXT_PORT_TX_DW14_LN0_A, BXT_PORT_TX_DW14_LN1_A, BXT_PORT_TX_DW14_LN2_A, @@ -730,7 +735,8 @@ BXT_PORT_PCS_DW12_GRP_A, BXT_PORT_TX_DW2_GRP_A, BXT_PORT_TX_DW3_GRP_A, - BXT_PORT_TX_DW4_GRP_A); + BXT_PORT_TX_DW4_GRP_A, + BXT_PORT_TX_DW5_GRP_A); pragma Warnings (GNATprove, Off, "pragma ""KEEP_NAMES"" ignored *(not yet supported)", @@ -1351,6 +1357,7 @@ BXT_PORT_TX_DW2_LN0_A => 16#16_2508# / Register_Width, BXT_PORT_TX_DW3_LN0_A => 16#16_250c# / Register_Width, BXT_PORT_TX_DW4_LN0_A => 16#16_2510# / Register_Width, + BXT_PORT_TX_DW5_LN0_A => 16#16_2514# / Register_Width, BXT_PORT_TX_DW14_LN0_A => 16#16_2538# / Register_Width, BXT_PORT_TX_DW14_LN1_A => 16#16_25b8# / Register_Width, BXT_PORT_TX_DW14_LN2_A => 16#16_2738# / Register_Width, @@ -1358,9 +1365,11 @@ BXT_PORT_TX_DW2_GRP_A => 16#16_2d08# / Register_Width, BXT_PORT_TX_DW3_GRP_A => 16#16_2d0c# / Register_Width, BXT_PORT_TX_DW4_GRP_A => 16#16_2d10# / Register_Width, + BXT_PORT_TX_DW5_GRP_A => 16#16_2d14# / Register_Width, BXT_PORT_TX_DW2_LN0_B => 16#06_c508# / Register_Width, BXT_PORT_TX_DW3_LN0_B => 16#06_c50c# / Register_Width, BXT_PORT_TX_DW4_LN0_B => 16#06_c510# / Register_Width, + BXT_PORT_TX_DW5_LN0_B => 16#06_c514# / Register_Width, BXT_PORT_TX_DW14_LN0_B => 16#06_c538# / Register_Width, BXT_PORT_TX_DW14_LN1_B => 16#06_c5b8# / Register_Width, BXT_PORT_TX_DW14_LN2_B => 16#06_c738# / Register_Width, @@ -1368,9 +1377,11 @@ BXT_PORT_TX_DW2_GRP_B => 16#06_cd08# / Register_Width, BXT_PORT_TX_DW3_GRP_B => 16#06_cd0c# / Register_Width, BXT_PORT_TX_DW4_GRP_B => 16#06_cd10# / Register_Width, + BXT_PORT_TX_DW5_GRP_B => 16#06_cd14# / Register_Width, BXT_PORT_TX_DW2_LN0_C => 16#06_c908# / Register_Width, BXT_PORT_TX_DW3_LN0_C => 16#06_c90c# / Register_Width, BXT_PORT_TX_DW4_LN0_C => 16#06_c910# / Register_Width, + BXT_PORT_TX_DW5_LN0_C => 16#06_c914# / Register_Width, BXT_PORT_TX_DW14_LN0_C => 16#06_c938# / Register_Width, BXT_PORT_TX_DW14_LN1_C => 16#06_c9b8# / Register_Width, BXT_PORT_TX_DW14_LN2_C => 16#06_cb38# / Register_Width, @@ -1378,6 +1389,7 @@ BXT_PORT_TX_DW2_GRP_C => 16#06_cf08# / Register_Width, BXT_PORT_TX_DW3_GRP_C => 16#06_cf0c# / Register_Width, BXT_PORT_TX_DW4_GRP_C => 16#06_cf10# / Register_Width, + BXT_PORT_TX_DW5_GRP_C => 16#06_cf14# / Register_Width, -- Broxton DDI PHY ref registers BXT_PORT_REF_DW3_A => 16#16_218c# / Register_Width, diff --git a/common/hw-gfx-gma.ads b/common/hw-gfx-gma.ads index 7ca0ca1..c282935 100644 --- a/common/hw-gfx-gma.ads +++ b/common/hw-gfx-gma.ads @@ -41,7 +41,8 @@ Ivybridge, Haswell, Broadwell, - Broxton, + Apollolake, + Geminilake, Skylake, Kabylake); diff --git a/configs/broxton b/configs/apollolake similarity index 83% rename from configs/broxton rename to configs/apollolake index b5f1f9a..24e0847 100644 --- a/configs/broxton +++ b/configs/apollolake @@ -1,4 +1,4 @@ -CONFIG_GFX_GMA_CPU = Broxton +CONFIG_GFX_GMA_CPU = Apollolake CONFIG_GFX_GMA_CPU_VARIANT = Normal # N/A CONFIG_GFX_GMA_INTERNAL_PORT = DP CONFIG_GFX_GMA_ANALOG_I2C_PORT = PCH_DAC # N/A diff --git a/configs/broxton b/configs/geminilake similarity index 83% copy from configs/broxton copy to configs/geminilake index b5f1f9a..be34de7 100644 --- a/configs/broxton +++ b/configs/geminilake @@ -1,4 +1,4 @@ -CONFIG_GFX_GMA_CPU = Broxton +CONFIG_GFX_GMA_CPU = Geminilake CONFIG_GFX_GMA_CPU_VARIANT = Normal # N/A CONFIG_GFX_GMA_INTERNAL_PORT = DP CONFIG_GFX_GMA_ANALOG_I2C_PORT = PCH_DAC # N/A -- To view, visit https://review.coreboot.org/c/libgfxinit/+/31611 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I84347130fc3fcaf33d9f3d84fab47c67899c792d Gerrit-Change-Number: 31611 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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