coreboot-gerrit May 2019

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Change in ...coreboot[master]: for review d945gclf/Kconig and devicetree.cb . these files are modif...
by junaid (Code Review) 10 Jun '23

10 Jun '23

junaid has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30798 Change subject: for review d945gclf/Kconig and devicetree.cb . these files are modified according to the superIO chip Winbond w83627DHG ...................................................................... for review d945gclf/Kconig and devicetree.cb . these files are modified according to the superIO chip Winbond w83627DHG Change-Id: I1449d9351bd1b76ecad16e6d81c501c1d4dd80f5 Signed-off-by: junaid <junaidimpex(a)gmail.com> --- M src/mainboard/intel/d945gclf/Kconfig M src/mainboard/intel/d945gclf/devicetree.cb 2 files changed, 37 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/30798/1 diff --git a/src/mainboard/intel/d945gclf/Kconfig b/src/mainboard/intel/d945gclf/Kconfig index 70fa848..906dd01 100644 --- a/src/mainboard/intel/d945gclf/Kconfig +++ b/src/mainboard/intel/d945gclf/Kconfig @@ -20,7 +20,8 @@ select NORTHBRIDGE_INTEL_I945 select NORTHBRIDGE_INTEL_SUBTYPE_I945GC select SOUTHBRIDGE_INTEL_I82801GX - select SUPERIO_SMSC_LPC47M15X +## changed as per Advantech SOM 4461 + select SUPERIO_WINBOND_W83627DHG select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT select HAVE_PIRQ_TABLE diff --git a/src/mainboard/intel/d945gclf/devicetree.cb b/src/mainboard/intel/d945gclf/devicetree.cb index 90c517f..864775a 100644 --- a/src/mainboard/intel/d945gclf/devicetree.cb +++ b/src/mainboard/intel/d945gclf/devicetree.cb @@ -65,44 +65,42 @@ device pci 1d.1 on end # USB UHCI device pci 1d.2 on end # USB UHCI device pci 1d.3 off end # USB UHCI - device pci 1d.7 on end # USB2 EHCI - device pci 1e.0 on end # PCI bridge - device pci 1e.2 off end # AC'97 Audio + device pci 1d.7 on end # USB2 EHCI + device pci 1e.0 on end # PCI bridge + device pci 1e.2 off end # AC'97 Audio device pci 1e.3 off end # AC'97 Modem device pci 1f.0 on # LPC bridge - chip superio/smsc/lpc47m15x - device pnp 2e.0 off # Floppy - end - device pnp 2e.3 off # Parport - end - device pnp 2e.4 on - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.5 on - io 0x60 = 0x2f8 - irq 0x70 = 3 - irq 0xf1 = 4 # set IRMODE 0 # XXX not an irq - end - device pnp 2e.7 on # Keyboard+Mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - irq 0xf0 = 0x82 # HW accel A20. - end - device pnp 2e.8 on # GAME - # all default - end - device pnp 2e.a on # PME - end - device pnp 2e.b on # MPU - end - end - end + chip superio/winbond/w83627dhg + device pnp 2e.0 off end # Floppy + device pnp 2e.1 off end # Parallel Port + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard,Mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + #device pnp 2e.6 off end # SPI + device pnp 2e.307 off end # GPIO6 + device pnp 2e.8 off end # WDTO, PLED + device pnp 2e.009 off end # GPIO2 + device pnp 2e.109 off end # GPIO3 + device pnp 2e.209 off end # GPIO4 + device pnp 2e.309 off end # GPIO5 + device pnp 2e.A off end # ACPI + device pnp 2e.B off end # HW Monitor + end # w83627dhg + end device pci 1f.1 off end # IDE - device pci 1f.2 on end # SATA - device pci 1f.3 on end # SMBus - end - end + device pci 1f.2 on end # SATA + device pci 1f.3 on end # SMBus + end + end end -- To view, visit https://review.coreboot.org/c/coreboot/+/30798 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1449d9351bd1b76ecad16e6d81c501c1d4dd80f5 Gerrit-Change-Number: 30798 Gerrit-PatchSet: 1 Gerrit-Owner: junaid <junaidimpex(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: [WIP]device/pci_rom: Add ATRM method
by Patrick Rudolph (Code Review) 10 Jun '23

10 Jun '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31502 Change subject: [WIP]device/pci_rom: Add ATRM method ...................................................................... [WIP]device/pci_rom: Add ATRM method Add ATRM method for AMD GPUs, which is similar to _ROM. As both functions seem to have identical arguments and return values, redirect ATRM to _ROM. Don't depend on VGA devices, but display devices, as some AMD dGPUs identify themself as PCI_CLASS_DISPLAY_OTHER. Needs test on platforms with AMD display devices. Change-Id: Id2212f29f0de051f6cbd59f8332e86696c1166ab Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/device/pci_rom.c 1 file changed, 15 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/31502/1 diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index 82d9a30..86c839c 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -272,8 +272,8 @@ { static size_t ngfx; - /* Only handle VGA devices */ - if ((device->class >> 8) != PCI_CLASS_DISPLAY_VGA) + /* Only handle display devices */ + if ((device->class >> 16) != PCI_BASE_CLASS_DISPLAY) return; /* Only handle enabled devices */ @@ -319,9 +319,21 @@ memcpy(cbrom, rom, cbrom_length); - /* write _ROM method */ + /* write ACPI methods */ acpigen_write_scope(scope); + + /* Nvidia uses _ROM */ acpigen_write_rom(cbrom, cbrom_length); + + /* AMD uses ATRM. Redirect ATRM to _ROM */ + acpigen_write_method_serialized("ATRM", 2); + acpigen_write_to_integer(ARG1_OP, LOCAL0_OP); + acpigen_emit_byte(RETURN_OP); + acpigen_emit_namestring("_ROM"); + acpigen_emit_byte(ARG0_OP); + acpigen_emit_byte(LOCAL0_OP); + acpigen_pop_len(); /* pop method */ + acpigen_pop_len(); /* pop scope */ } #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/31502 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id2212f29f0de051f6cbd59f8332e86696c1166ab Gerrit-Change-Number: 31502 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/hatch:[DEBUG ONLY] Assert DEVSLP in S3
by Rizwan Qureshi (Code Review) 10 Jun '23

10 Jun '23

Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32078 Change subject: mb/google/hatch:[DEBUG ONLY] Assert DEVSLP in S3 ...................................................................... mb/google/hatch:[DEBUG ONLY] Assert DEVSLP in S3 It was obsevred that the DEVSLP is keeping low in S3, and SDD is drawing some power, assert DEVSLP in S3 to indicate SSD to go into low power mode. Change-Id: I001781fd0e1e5763f6865966658fc9fccc3edff8 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- M src/mainboard/google/hatch/variants/baseboard/gpio.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/32078/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index 5987abc..15038b5 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -410,6 +410,7 @@ /* Default GPIO settings before entering sleep. */ static const struct pad_config default_sleep_gpio_table[] = { + PAD_CFG_GPO(GPP_E5, 1, DEEP), }; /* -- To view, visit https://review.coreboot.org/c/coreboot/+/32078 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I001781fd0e1e5763f6865966658fc9fccc3edff8 Gerrit-Change-Number: 32078 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Updated and converted to markdown doc from wiki on porting motherboards.
by Calvin (Code Review) 10 Jun '23

10 Jun '23

Calvin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31849 Change subject: Updated and converted to markdown doc from wiki on porting motherboards. ...................................................................... Updated and converted to markdown doc from wiki on porting motherboards. Some of the documentation from the wiki (https://www.coreboot.org/Motherboard_Porting_Guide) has been ported to markdown and updated as I was able to figure things out. Still a work in progress as there is more data from that page that I will need to convert as I work through it. If I get anywhere in my project of porting coreboot to an older Chromebook, I will document more of this process as I go. Signed-off-by: calvinrempel <calvin.rempel(a)gmail.com> Change-Id: Ie3b8a99c10808c7e7ebc826b4d2f992774cc9a75 --- M Documentation/index.md A Documentation/porting/index.md A Documentation/porting/motherboard_probe.md 3 files changed, 135 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/31849/1 diff --git a/Documentation/index.md b/Documentation/index.md index dd8714c..32635f9 100644 --- a/Documentation/index.md +++ b/Documentation/index.md @@ -164,6 +164,7 @@ * [Rookie Guide](lessons/index.md) * [Coding Style](coding_style.md) * [Project Ideas](contributing/project_ideas.md) +* [Porting](porting/index.md) * [Code of Conduct](community/code_of_conduct.md) * [Community forums](community/forums.md) * [coreboot at conferences](community/conferences.md) diff --git a/Documentation/porting/index.md b/Documentation/porting/index.md new file mode 100644 index 0000000..ed282e8 --- /dev/null +++ b/Documentation/porting/index.md @@ -0,0 +1,3 @@ +# Porting New Boards + +* [Motherboard Probing](motherboard_probe.md) diff --git a/Documentation/porting/motherboard_probe.md b/Documentation/porting/motherboard_probe.md new file mode 100644 index 0000000..7562f7c --- /dev/null +++ b/Documentation/porting/motherboard_probe.md @@ -0,0 +1,131 @@ +Motherboard Porting Guide +========================= + +Please note that this guide is very much a work in progress. + +Finding out What You Have +------------------------- + +### Tools +To begin the process of porting a motherboard to coreboot, you first +need to determine what all is on it: the chipset (ie, North and South +Bridge), Flash Rom, etc. To do this, you will need a suite of +tools provided by the coreboot project, as well as some that can be +found more readily in various repositories. + +For the sake of this page, it will be assumed you are using Debian or +Ubuntu. + +#### Build Environment +If you have not already done so, get your basic build environment +installed: + + $ sudo apt install build-essential git cvs subversion + +#### Probing Utilities - From Repos +Next, a number of utilities will need to be installed which will be used +later for probing the system as well as some dev libraries which will be +used in building some of the tools in the next step.These should be +available in your distro's repo: + + $ sudo apt install pciutils pciutils-dev flashrom acpitool \ + usbutils acpidump + +#### Probing Utilities - From Source +Once the base build system in place and what utilities along with what +libraries you can glean from your distro's repositories, it is time to +build some tools from source. If you have not already done so, checkout +the git repo as described in "[Rookie Guide: Lesson 1]". + +Once you have synced the coreboot repo, cd into the utilities folder: + + $cd coreboot/util + +##### superiotool + + $ cd ./superiotool + $ make + $ sudo make install + $ cd .. + +##### inteltool + + $ cd ./inteltool + $ make + $ sudo make install + $ cd .. + +##### ectool + + $ cd ./ectool + $ make + $ make install + $ cd .. + +##### dmidecode + + $ cvs -z3 -d:pserver:anonymous@cvs.savannah.nongnu.org:/sources/dmidecode \ + co dmidecode + $ cd dmidecode + $ make + $ sudo make install + $ cd .. + +##### msrtool + + $ cd ./msrtool + $ ./configure + $ make + $ sudo make install + $ cd .. + +##### nvramtool + + $ cd ./nvramtool + $ make + $ sudo make install + +##### acpica-unix + + $ wget http://deb.debian.org/debian/pool/main/a/acpica-unix/acpica-unix_20181213.o… + $ tar -xaf acpica-unix_20181213.orig.tar.gz + $ cd ./acpica-unix-2018-12-13/ + $ make + $ sudo make install + +### Probe the Board +Now we will begin to probe the board to see what we can find out about +it. First, become root: + + $ sudo su + +Then load the msr module into the kernel: + + $ sudo modprobe msr + +Finally, we probe the board: + + $ lspci -nnvvvxxxx > lspci.log 2> lspci.err.log + $ lsusb -vvv > lsusb.log 2> lsusb.err.log + $ superiotool -deV > superiotool.log 2> superiotool.err.log + $ inteltool -a > inteltool.log 2> inteltool.err.log + $ ectool -i > ectool.log 2> ectool.err.log + $ msrtool > msrtool.log 2> msrtool.err.log + $ dmidecode > dmidecode.log 2> dmidecode.err.log + $ biosdecode > biosdecode.log 2> biosdecode.err.log + $ nvramtool -x > nvramtool.log 2> nvramtool.err.log + $ dmesg > dmesg.log 2> dmesg.err.log + $ acpidump > acpidump.log 2> acpidump.err.log + $ for x in /sys/class/sound/card0/hw*; do cat "$x/init_pin_configs" \ + > pin_"$(basename "$x")"; done + $ for x in /proc/asound/card0/codec#*; do cat "$x" > \ + "$(basename "$x")"; done + $ cat /proc/cpuinfo > cpuinfo.log 2> cpuinfo.err.log + $ cat /proc/ioports > ioports.log 2> ioports.err.log + $ cat /sys/class/input/input*/id/bustype > input_bustypes.log + $flashrom -V -p internal:laptop=force_I_want_a_brick > \ + flashrom_info.log 2> flashrom_info.err.log + $ flashrom -V -p internal:laptop=force_I_want_a_brick -r rom.bin > \ + flashrom_read.log 2> flashrom_read.err.log + +[Rookie Guide: Lesson 1]: https://doc.coreboot.org/lessons/lesson1.html -- To view, visit https://review.coreboot.org/c/coreboot/+/31849 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie3b8a99c10808c7e7ebc826b4d2f992774cc9a75 Gerrit-Change-Number: 31849 Gerrit-PatchSet: 1 Gerrit-Owner: Calvin <calvin.rempel(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Add default boards for qemu, that has VPD partitions.
by John Looney (Code Review) 10 Jun '23

10 Jun '23

John Looney has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32144 Change subject: Add default boards for qemu, that has VPD partitions. ...................................................................... Add default boards for qemu, that has VPD partitions. Tested with https://review.coreboot.org/c/coreboot/+/31984 and the 'vpd' command to add VPD variables to those partitions, then checked that they were exported to userspace. Change-Id: I2aca55543cb3bdbdb77c8b421cbbafad2405d3cc --- A src/mainboard/emulation/qemu-i440fx/board.fmd A src/mainboard/emulation/qemu-q35/board.fmd 2 files changed, 32 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/32144/1 diff --git a/src/mainboard/emulation/qemu-i440fx/board.fmd b/src/mainboard/emulation/qemu-i440fx/board.fmd new file mode 100644 index 0000000..a97e218 --- /dev/null +++ b/src/mainboard/emulation/qemu-i440fx/board.fmd @@ -0,0 +1,16 @@ +# layout for firmware residing at top of 4GB address space +# +-------------+ <-- 4GB - ROM_SIZE / start of flash +# | unspecified | +# +-------------+ <-- 4GB - BIOS_SIZE +# | FMAP | +# +-------------+ <-- 4GB - BIOS_SIZE + FMAP_SIZE +# | CBFS | +# +-------------+ <-- 4GB / end of flash +FLASH@4278190080 0x1000000 { + BIOS@0 0x1000000 { + FMAP@0 0x200 + RO_VPD@0x200 0x10000 + RW_VPD@0x10200 0x1000 + COREBOOT(CBFS)@0x11200 + } +} diff --git a/src/mainboard/emulation/qemu-q35/board.fmd b/src/mainboard/emulation/qemu-q35/board.fmd new file mode 100644 index 0000000..a97e218 --- /dev/null +++ b/src/mainboard/emulation/qemu-q35/board.fmd @@ -0,0 +1,16 @@ +# layout for firmware residing at top of 4GB address space +# +-------------+ <-- 4GB - ROM_SIZE / start of flash +# | unspecified | +# +-------------+ <-- 4GB - BIOS_SIZE +# | FMAP | +# +-------------+ <-- 4GB - BIOS_SIZE + FMAP_SIZE +# | CBFS | +# +-------------+ <-- 4GB / end of flash +FLASH@4278190080 0x1000000 { + BIOS@0 0x1000000 { + FMAP@0 0x200 + RO_VPD@0x200 0x10000 + RW_VPD@0x10200 0x1000 + COREBOOT(CBFS)@0x11200 + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/32144 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2aca55543cb3bdbdb77c8b421cbbafad2405d3cc Gerrit-Change-Number: 32144 Gerrit-PatchSet: 1 Gerrit-Owner: John Looney <john.looney(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util/mtkheader: Add a tool to extract bootload header from binary files.
by You-Cheng Syu (Code Review) 10 Jun '23

10 Jun '23

You-Cheng Syu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32333 Change subject: util/mtkheader: Add a tool to extract bootload header from binary files. ...................................................................... util/mtkheader: Add a tool to extract bootload header from binary files. Add a tool, extract-bl-img.py, which can extract MTK bootload header from binary files. This could be useful for boards (e.g., Kukui) which put the bootblock in other places (e.g., Chrome EC). Change-Id: Ib744c80bdc2adfe27d4287365e161096e3fe08c7 Signed-off-by: You-Cheng Syu <youcheng(a)google.com> --- A util/mtkheader/extract-bl-img.py 1 file changed, 55 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/32333/1 diff --git a/util/mtkheader/extract-bl-img.py b/util/mtkheader/extract-bl-img.py new file mode 100755 index 0000000..21bf9eb --- /dev/null +++ b/util/mtkheader/extract-bl-img.py @@ -0,0 +1,55 @@ +#!/usr/bin/env python +# This file is part of the coreboot project. +# +# Copyright 2019 Google LLC +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. + +import argparse +import struct +import sys + + +_DESCRIPTION = 'Extract MTK bootload header from a binary file.' + + +def parse_args(): + parser = argparse.ArgumentParser(description=_DESCRIPTION) + parser.add_argument('input_path', metavar='INPUT_FILE') + parser.add_argument('output_path', metavar='OUTPUT_FILE') + return parser.parse_args() + + +def main(): + args = parse_args() + + with open(args.input_path, 'rb') as f: + data = f.read() + + header = struct.pack('<8sII', 'BRLYT', 1, 2048) + + start = -1 + while True: + start = data.find(header, start + 1) + if start < 0: + raise RuntimeError('Cannot find MTK bootload header') + offset = start + len(header) + buf = struct.unpack('<II', data[offset:offset+8]) + if buf[1] == 0x42424242: + break + size = buf[0] + offset = start - 512 + + with open(args.output_path, 'wb') as f: + f.write(data[offset:offset+size]) + + +if __name__ == '__main__': + main() -- To view, visit https://review.coreboot.org/c/coreboot/+/32333 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib744c80bdc2adfe27d4287365e161096e3fe08c7 Gerrit-Change-Number: 32333 Gerrit-PatchSet: 1 Gerrit-Owner: You-Cheng Syu <youcheng(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Patch SSDTs into qemu, and add VPD area to the fmap for q35 as a proo...
by John Looney (Code Review) 10 Jun '23

10 Jun '23

John Looney has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32082 Change subject: Patch SSDTs into qemu, and add VPD area to the fmap for q35 as a proof of concept ...................................................................... Patch SSDTs into qemu, and add VPD area to the fmap for q35 as a proof of concept Change-Id: I8c31fa79e13be237a752f47e72a6a7025fe9dffd reformatting Change-Id: I4e1b161a89d860c350d4735f843f6bee42313378 --- M src/arch/x86/acpi.c M src/mainboard/emulation/qemu-i440fx/fw_cfg.c M src/mainboard/emulation/qemu-q35/Kconfig 3 files changed, 20 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/32082/1 diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index f08a401..7bbbd2f 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -38,7 +38,6 @@ */ #include <console/console.h> -#include <string.h> #include <arch/acpi.h> #include <arch/acpi_ivrs.h> #include <arch/acpigen.h> diff --git a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c index 3acb11e..af5dddd 100644 --- a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c +++ b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c @@ -225,6 +225,8 @@ BiosLinkerLoaderEntry *s; unsigned long *addrs, current; uint8_t *ptr; + acpi_rsdp_t *rsdp = NULL; + acpi_header_t *ssdt; int i, j, src, dst, max; if (fw_cfg_check_file(&f, "etc/table-loader")) @@ -251,6 +253,10 @@ printk(BIOS_DEBUG, "QEMU: loading \"%s\" to 0x%lx (len %d)\n", s[i].alloc.file, current, f.size); + if (!strncmp(s[i].alloc.file, "etc/acpi/rsdp", 13)) { + printk(BIOS_DEBUG, "Found RSDP at 0x%lx\n", current); + rsdp = (acpi_rsdp_t *) current; + } fw_cfg_get(f.select, (void *)current, f.size); addrs[i] = current; current += f.size; @@ -322,6 +328,16 @@ }; } + if (rsdp) { + ssdt = (acpi_header_t *)current; + acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); + if (ssdt->length > sizeof(acpi_header_t)) { + current += ssdt->length; + acpi_add_table(rsdp, ssdt); + current = acpi_align_current(current); + } + } + printk(BIOS_DEBUG, "QEMU: loaded ACPI tables from fw_cfg.\n"); free(s); free(addrs); diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig index 815b93b..0672092 100644 --- a/src/mainboard/emulation/qemu-q35/Kconfig +++ b/src/mainboard/emulation/qemu-q35/Kconfig @@ -54,4 +54,8 @@ hex default 0x4000 +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd" + endif # BOARD_EMULATION_QEMU_X86_Q35 -- To view, visit https://review.coreboot.org/c/coreboot/+/32082 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e1b161a89d860c350d4735f843f6bee42313378 Gerrit-Change-Number: 32082 Gerrit-PatchSet: 1 Gerrit-Owner: John Looney <john.looney(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Enable acoustic noise mitgation for arcada platform, the slow slew ra...
by Nathan Chen (Code Review) 10 Jun '23

10 Jun '23

Nathan Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32520 Change subject: Enable acoustic noise mitgation for arcada platform, the slow slew rates for Ia and Gt are fast time dived by 8. ...................................................................... Enable acoustic noise mitgation for arcada platform, the slow slew rates for Ia and Gt are fast time dived by 8. BUG=b:131144464 TEST=waveform test and hardware validation result pass. Signed-off-by: nathan chen <nathan_chen(a)wistron.corp-partner.google.com> Change-Id: I2ebcca803deb04737bfb5b2c134b164971f3688e --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/32520/1 diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index cf64c4b..77bd82a 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -37,10 +37,10 @@ register "tdp_pl2_override" = "51" register "Device4Enable" = "1" register "AcousticNoiseMitigation" = "1" - register "SlowSlewRateForIa" = "0" - register "SlowSlewRateForGt" = "0" + register "SlowSlewRateForIa" = "2" + register "SlowSlewRateForGt" = "2" register "SlowSlewRateForSa" = "0" - register "SlowSlewRateForFivr" = "0" + register "SlowSlewRateForFivr" = "2" # Enable eDP device register "DdiPortEdp" = "1" # Enable HPD for DDI ports B/C -- To view, visit https://review.coreboot.org/c/coreboot/+/32520 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2ebcca803deb04737bfb5b2c134b164971f3688e Gerrit-Change-Number: 32520 Gerrit-PatchSet: 1 Gerrit-Owner: Nathan Chen <nathan_chen(a)wistron.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/lenovo/t520: Add MRC settings in devicetree
by Patrick Rudolph (Code Review) 10 Jun '23

10 Jun '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32500 Change subject: mb/lenovo/t520: Add MRC settings in devicetree ...................................................................... mb/lenovo/t520: Add MRC settings in devicetree Add support for MRC raminit using devicetree settings. Tested on Lenovo T520. Change-Id: I58198f3f177a7639675f8a408c1f4e02fcebc50a --- M src/mainboard/lenovo/t520/Kconfig M src/mainboard/lenovo/t520/romstage.c M src/mainboard/lenovo/t520/variants/t520/devicetree.cb 3 files changed, 30 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/32500/1 diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig index 06f296b..d61f651 100644 --- a/src/mainboard/lenovo/t520/Kconfig +++ b/src/mainboard/lenovo/t520/Kconfig @@ -2,7 +2,6 @@ def_bool n select SYSTEM_TYPE_LAPTOP select NORTHBRIDGE_INTEL_SANDYBRIDGE - select USE_NATIVE_RAMINIT select SOUTHBRIDGE_INTEL_BD82X6X select EC_LENOVO_PMH7 select EC_LENOVO_H8 diff --git a/src/mainboard/lenovo/t520/romstage.c b/src/mainboard/lenovo/t520/romstage.c index 96d07fe..8566200 100644 --- a/src/mainboard/lenovo/t520/romstage.c +++ b/src/mainboard/lenovo/t520/romstage.c @@ -20,6 +20,7 @@ #include <device/pci_ops.h> #include <device/pci_def.h> #include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit.h> #include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h> @@ -95,3 +96,12 @@ void mainboard_config_superio(void) { } + +void mainboard_fill_pei_data(struct pei_data *pei_data) +{ +} + +int mainboard_should_reset_usb(int s3resume) +{ + return !s3resume; +} diff --git a/src/mainboard/lenovo/t520/variants/t520/devicetree.cb b/src/mainboard/lenovo/t520/variants/t520/devicetree.cb index cf8e7ce..22db921 100644 --- a/src/mainboard/lenovo/t520/variants/t520/devicetree.cb +++ b/src/mainboard/lenovo/t520/variants/t520/devicetree.cb @@ -36,6 +36,26 @@ register "pci_mmio_size" = "2048" + # PEI data + register "spd_addresses" = "{ 0xa0, 0x00, 0xa2, 0x00 }" + register "ts_addresses" = "{ 0x00, 0x00, 0x00, 0x00 }" + + register "dimm_channel0_disabled" = "2" + register "dimm_channel1_disabled" = "2" + + register "max_mem_clock_mhz" = "666" # DDR3-1333 + + register "usb_port_config" = "{ + { 1, 0, 0x0040 }, /* back, towards HDMI plugs */ + { 1, 0, 0x0040 }, /* back, towards power plug */ + { 1, 1, 0x0040 }, /* half-width miniPCIe */ + { 1, 1, 0x0040 }, /* full-width miniPCIe */ + { 1, 2, 0x0040 }, /* front-panel header */ + { 1, 2, 0x0040 }, /* front-panel header */ + { 1, 3, 0x0040 }, /* front connector */ + }" + + device domain 0 on device pci 00.0 on end # host bridge device pci 01.0 on end # NVIDIA Corporation GF119M [NVS 4200M] -- To view, visit https://review.coreboot.org/c/coreboot/+/32500 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I58198f3f177a7639675f8a408c1f4e02fcebc50a Gerrit-Change-Number: 32500 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/*/devicetree.cb: Add more smbios_slot_desc
by Patrick Rudolph (Code Review) 10 Jun '23

10 Jun '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32684 Change subject: mb/*/devicetree.cb: Add more smbios_slot_desc ...................................................................... mb/*/devicetree.cb: Add more smbios_slot_desc Add smbios_slot_desc for desktop and serverboards. Fill in PCIe, PCI and Mini PCIe slots. Change-Id: I829de30c50212bb90cb51470af91518fd9b9e41c Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/asrock/b75pro3-m/devicetree.cb M src/mainboard/asrock/h110m/devicetree.cb M src/mainboard/asrock/h81m-hds/devicetree.cb M src/mainboard/asus/h61m-cs/devicetree.cb M src/mainboard/asus/kcma-d8/devicetree.cb M src/mainboard/asus/kgpe-d16/devicetree.cb M src/mainboard/asus/maximus_iv_gene-z/devicetree.cb M src/mainboard/asus/p8h61-m_lx/devicetree.cb M src/mainboard/asus/p8h61-m_pro/devicetree.cb M src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb M src/mainboard/gigabyte/ga-b75m-d3v/devicetree.cb M src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb M src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb M src/mainboard/kontron/ktqm77/devicetree.cb M src/mainboard/msi/ms7707/devicetree.cb M src/mainboard/pcengines/apu1/devicetree.cb M src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb M src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb M src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb M src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb M src/mainboard/sapphire/pureplatinumh61/devicetree.cb M src/mainboard/supermicro/x10slm-f/devicetree.cb 22 files changed, 100 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/32684/1 diff --git a/src/mainboard/asrock/b75pro3-m/devicetree.cb b/src/mainboard/asrock/b75pro3-m/devicetree.cb index 9eba6fc..18c0c12 100644 --- a/src/mainboard/asrock/b75pro3-m/devicetree.cb +++ b/src/mainboard/asrock/b75pro3-m/devicetree.cb @@ -48,6 +48,7 @@ end device pci 01.0 on subsystemid 0x1849 0x0151 + smbios_slot_desc "0xb6" "4" "PCI Express x16" "0xd" end device pci 02.0 on subsystemid 0x1849 0x0152 @@ -92,6 +93,7 @@ end device pci 1c.0 on # PCIe Port #1 subsystemid 0x1849 0x1e10 + smbios_slot_desc "0xb0" "4" "PCI Express x16" "0xa" end device pci 1c.1 off # PCIe Port #2 end @@ -114,6 +116,7 @@ end device pci 1e.0 on # PCI bridge subsystemid 0x1849 0x244e + smbios_slot_desc "0x6" "3" "PCI slot" "0x5" end device pci 1f.0 on # LPC bridge subsystemid 0x1849 0x1e49 diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index 158801f..1e4d6bc 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -267,6 +267,7 @@ end device pci 01.0 on # PEG subsystemid 0x1849 0x1901 + smbios_slot_desc "0xb6" "4" "PCI Express x16" "0xd" end device pci 02.0 on # Integrated Graphics Device subsystemid 0x1849 0x1912 @@ -295,7 +296,9 @@ device pci 19.0 off end # UART #2 device pci 19.1 off end # I2C #5 device pci 19.2 off end # I2C #4 - device pci 1c.0 on end # PCI Express Port 1 + device pci 1c.0 on + smbios_slot_desc "0xac" "4" "PCI Express x1" "8" + end # PCI Express Port 1 device pci 1c.1 off end # PCI Express Port 2 device pci 1c.2 off end # PCI Express Port 3 device pci 1c.3 off end # PCI Express Port 4 diff --git a/src/mainboard/asrock/h81m-hds/devicetree.cb b/src/mainboard/asrock/h81m-hds/devicetree.cb index 58a319d..a25a57e 100644 --- a/src/mainboard/asrock/h81m-hds/devicetree.cb +++ b/src/mainboard/asrock/h81m-hds/devicetree.cb @@ -38,6 +38,7 @@ device pci 01.0 on # PCIe graphics subsystemid 0x1849 0x0c01 + smbios_slot_desc "0xb6" "4" "PCI Express x16" "0xd" end device pci 02.0 on # VGA controller @@ -101,6 +102,7 @@ end device pci 1c.5 on # PCIe 1x slot subsystemid 0x1849 0x8c1a + smbios_slot_desc "0xac" "4" "PCI Express x1" "8" end device pci 1d.0 on # EHCI controller #1 subsystemid 0x1849 0x8c26 diff --git a/src/mainboard/asus/h61m-cs/devicetree.cb b/src/mainboard/asus/h61m-cs/devicetree.cb index 9a4c6fe..118e435 100644 --- a/src/mainboard/asus/h61m-cs/devicetree.cb +++ b/src/mainboard/asus/h61m-cs/devicetree.cb @@ -30,7 +30,9 @@ device domain 0x0 on subsystemid 0x1043 0x844d inherit device pci 00.0 on end # Host bridge - device pci 01.0 on end # PCIe Bridge for discrete graphics + device pci 01.0 on + smbios_slot_desc "0xb6" "4" "PCI Express x16" "0xd" + end # PCIe Bridge for discrete graphics device pci 02.0 on end # Internal graphics chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "c2_latency" = "0x0065" diff --git a/src/mainboard/asus/kcma-d8/devicetree.cb b/src/mainboard/asus/kcma-d8/devicetree.cb index f8a2d83..49bb8b2 100644 --- a/src/mainboard/asus/kcma-d8/devicetree.cb +++ b/src/mainboard/asus/kcma-d8/devicetree.cb @@ -17,6 +17,7 @@ device pci 0.2 on end # IOMMU device pci 2.0 on # PCIE P2P bridge 0x9603 (GPP1 Port0) # Slot # PCI E 1 / PCI E 2 + smbios_slot_desc "0xb0" "4" "PCI Express x16" "0xd" end device pci 3.0 off end # PCIE P2P bridge 0x960b (GPP1 Port1) device pci 4.0 on # PCIE P2P bridge 0x9604 (GPP3a Port0) @@ -211,12 +212,15 @@ device pci 14.4 on # Bridge device pci 1.0 on # Slot # Slot # PCI 0 + smbios_slot_desc "6" "3" "PCI slot 0" "5" end device pci 2.0 on # Slot # Slot # PCI 1 + smbios_slot_desc "6" "3" "PCI slot 1" "5" end device pci 3.0 on # Slot # Slot # PCI 2 + smbios_slot_desc "6" "3" "PCI slot 2" "5" end device pci 5.0 on end # VGA end diff --git a/src/mainboard/asus/kgpe-d16/devicetree.cb b/src/mainboard/asus/kgpe-d16/devicetree.cb index 0ea4216..5710521 100644 --- a/src/mainboard/asus/kgpe-d16/devicetree.cb +++ b/src/mainboard/asus/kgpe-d16/devicetree.cb @@ -18,6 +18,7 @@ device pci 0.2 on end # IOMMU device pci 2.0 on # PCIE P2P bridge 0x9603 (GPP1 Port0) # Slot # PCI E 1 / PCI E 2 + smbios_slot_desc "0xb0" "4" "PCI Express x16" "0xd" end device pci 3.0 off end # PCIE P2P bridge 0x960b (GPP1 Port1) device pci 4.0 on # PCIE P2P bridge 0x9604 (GPP3a Port0) @@ -35,12 +36,15 @@ end device pci b.0 on # Bridge (GPP2 Port0) # Slot # PCI E 4 + smbios_slot_desc "0xb0" "4" "PCI Express x16" "0xb" end device pci c.0 on # Bridge (GPP2 Port1) # Slot # PCI E 5 + smbios_slot_desc "0xb0" "4" "PCI Express x16" "0xb" end device pci d.0 on # Bridge (GPP3b Port0) # Slot # PCI E 3 + smbios_slot_desc "0xaf" "4" "PCI Express x8" "0xa" end register "gpp1_configuration" = "0" # Configuration 16:0 default register "gpp2_configuration" = "1" # Configuration 8:8 @@ -226,6 +230,7 @@ device pci 2.0 on end # FireWire device pci 3.0 on # Slot # Slot # PCI 0 + smbios_slot_desc "6" "3" "PCI slot" "5" end end device pci 14.5 on end # USB OHCI2 0x4399 diff --git a/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb b/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb index 4b80f39..915b67a 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb +++ b/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb @@ -34,7 +34,9 @@ subsystemid 0x1043 0x844d inherit device pci 00.0 on end # Host bridge - device pci 01.0 on end # PCIe bridge for discrete graphics + device pci 01.0 on + smbios_slot_desc "0xb0" "4" "PCI Express x16" "0xd" + end # PCIe bridge for discrete graphics device pci 02.0 on end # VGA controller chip southbridge/intel/bd82x6x diff --git a/src/mainboard/asus/p8h61-m_lx/devicetree.cb b/src/mainboard/asus/p8h61-m_lx/devicetree.cb index ef8071f..80cd2e9 100644 --- a/src/mainboard/asus/p8h61-m_lx/devicetree.cb +++ b/src/mainboard/asus/p8h61-m_lx/devicetree.cb @@ -34,7 +34,9 @@ subsystemid 0x1043 0x844d inherit device pci 00.0 on end # Host bridge - device pci 01.0 on end # PCIe bridge for discrete graphics + device pci 01.0 on + smbios_slot_desc "0xb0" "4" "PCI Express x16" "0xd" + end # PCIe bridge for discrete graphics device pci 02.0 on end # VGA controller chip southbridge/intel/bd82x6x diff --git a/src/mainboard/asus/p8h61-m_pro/devicetree.cb b/src/mainboard/asus/p8h61-m_pro/devicetree.cb index f853452..d3706d5 100644 --- a/src/mainboard/asus/p8h61-m_pro/devicetree.cb +++ b/src/mainboard/asus/p8h61-m_pro/devicetree.cb @@ -119,7 +119,9 @@ device pci 1f.6 off end # Thermal end device pci 00.0 on end # Host bridge - device pci 01.0 on end # PCIe bridge for discrete graphics (PCIEX16_1) + device pci 01.0 on + smbios_slot_desc "0xb6" "4" "PCI Express x16" "0xd" + end # PCIe bridge for discrete graphics (PCIEX16_1) device pci 02.0 on end # Internal graphics VGA controller end end diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb index 7a3568a..409314e 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb +++ b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb @@ -24,7 +24,9 @@ device pci 00.0 on # host bridge subsystemid 0x1458 0x5000 end - device pci 01.0 on end # PCIe Bridge for discrete graphics + device pci 01.0 on + smbios_slot_desc "0xb6" "4" "PCI Express x16" "0xd" + end # PCIe Bridge for discrete graphics device pci 02.0 on # vga controller subsystemid 0x1458 0xd000 end @@ -73,7 +75,9 @@ device pci 1d.0 on # USB2 EHCI #1 subsystemid 0x1458 0x5006 end - device pci 1e.0 on end # PCI bridge + device pci 1e.0 on + smbios_slot_desc "0x6" "3" "PCI slot" "0x5" + end # PCI bridge device pci 1f.0 on # ISA/LPC bridge subsystemid 0x1458 0x5001 chip superio/ite/it8728f diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/devicetree.cb b/src/mainboard/gigabyte/ga-b75m-d3v/devicetree.cb index a00e2ee..faf05a2 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3v/devicetree.cb +++ b/src/mainboard/gigabyte/ga-b75m-d3v/devicetree.cb @@ -23,7 +23,9 @@ device pci 00.0 on # host bridge subsystemid 0x1458 0x5000 end - device pci 01.0 on end # PCIe Bridge for discrete graphics + device pci 01.0 on + smbios_slot_desc "0xb6" "4" "PCI Express x16" "0xd" + end # PCIe Bridge for discrete graphics device pci 02.0 on # vga controller subsystemid 0x1458 0xd000 end diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb b/src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb index e382cbd..72d064c 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb @@ -31,7 +31,9 @@ register "pci_mmio_size" = "2048" device domain 0x0 on device pci 00.0 on end # Host bridge - device pci 01.0 on end # PCIe Bridge for discrete graphics (PCIEX16) + device pci 01.0 on + smbios_slot_desc "0xb0" "4" "PCI Express x16" "0xd" + end # PCIe Bridge for discrete graphics (PCIEX16) device pci 02.0 on end # Internal graphics VGA controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "c2_latency" = "0x0065" diff --git a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb index 95659be..1c97750 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb +++ b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb @@ -72,6 +72,7 @@ end device pci 1c.0 on # PCIe Port #1 subsystemid 0x103c 0x1495 + smbios_slot_desc "0xb0" "4" "PCI Express x4" "0xa" end device pci 1c.1 off # PCIe Port #2 end @@ -81,6 +82,7 @@ end device pci 1c.4 on # PCIe Port #5 subsystemid 0x103c 0x1495 + smbios_slot_desc "0xac" "4" "PCI Express x1" "0x8" end device pci 1c.5 off # PCIe Port #6 end @@ -95,6 +97,7 @@ end device pci 1e.0 on # PCI bridge subsystemid 0x103c 0x1495 + smbios_slot_desc "0x6" "3" "PCI slot" "0x5" end device pci 1f.0 on # LPC bridge PCI-LPC bridge subsystemid 0x103c 0x1495 @@ -214,6 +217,7 @@ end device pci 01.0 on # PCIe Bridge for discrete graphics subsystemid 0x103c 0x1495 + smbios_slot_desc "0xb6" "4" "PCI Express x16" "0xd" end device pci 02.0 on # Internal graphics VGA controller subsystemid 0x103c 0x1495 diff --git a/src/mainboard/kontron/ktqm77/devicetree.cb b/src/mainboard/kontron/ktqm77/devicetree.cb index fad139a..3feb4e7 100644 --- a/src/mainboard/kontron/ktqm77/devicetree.cb +++ b/src/mainboard/kontron/ktqm77/devicetree.cb @@ -21,7 +21,8 @@ device domain 0 on device pci 00.0 on end # host bridge - device pci 01.0 on end # PCIe Bridge x16 + device pci 01.0 on + end # PCIe Bridge x16 device pci 02.0 on end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH @@ -56,13 +57,19 @@ # Disabling 1c.0 might break IRQ settings as it enables port coalescing # There are two mini PCIe x1 sockets, so one PCIe port is unrouted - device pci 1c.0 on end # PCIe Port #1 mini PCIe x1? - device pci 1c.1 on end # PCIe Port #2 mini PCIe x1? + device pci 1c.0 on + smbios_slot_desc "0x22" "4" "PCI Express Mini" "8" + end # PCIe Port #1 mini PCIe x1? + device pci 1c.1 on + smbios_slot_desc "0x22" "4" "PCI Express Mini" "8" + end # PCIe Port #2 mini PCIe x1? device pci 1c.2 on end # PCIe Port #3 second Ethernet NIC device pci 1c.3 on end # PCIe Port #4 third Ethernet NIC device pci 1c.4 on end # PCIe Port #5 first Ethernet PHY device pci 1c.5 on end # PCIe Port #6 FireWire - device pci 1c.6 on end # PCIe Port #7 PCIe x1 + device pci 1c.6 on + smbios_slot_desc "0xac" "4" "PCI Express x1" "8" + end # PCIe Port #7 PCIe x1 device pci 1c.7 on end # PCIe Port #8 mini PCIe x1? device pci 1d.0 on end # USB2 EHCI #1 diff --git a/src/mainboard/msi/ms7707/devicetree.cb b/src/mainboard/msi/ms7707/devicetree.cb index 4db2536..58e6942 100644 --- a/src/mainboard/msi/ms7707/devicetree.cb +++ b/src/mainboard/msi/ms7707/devicetree.cb @@ -35,13 +35,17 @@ device pci 19.0 on end # Intel Gigabit Ethernet device pci 1a.0 on end # USB2 EHCI #2 device pci 1b.0 on end # High Definition Audio Audio controller - device pci 1c.0 on end # PCIe Port #1 + device pci 1c.0 on + smbios_slot_desc "0xac" "4" "PCI Express x1" "8" + end # PCIe Port #1 device pci 1c.1 off end # PCIe Port #2 device pci 1c.2 off end # PCIe Port #3 device pci 1c.3 off end # PCIe Port #4 device pci 1c.4 off end # PCIe Port #5 device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 on end # PCIe Port #7 + device pci 1c.6 on + smbios_slot_desc "0xac" "4" "PCI Express x1" "8" + end # PCIe Port #7 device pci 1c.7 off end # PCIe Port #8 device pci 1d.0 on end # USB2 EHCI #1 device pci 1e.0 off end # PCI bridge @@ -111,7 +115,9 @@ device pci 1f.6 off end # Thermal end device pci 00.0 on end # Host bridge - device pci 01.0 on end # PCIe Bridge for discrete graphics + device pci 01.0 on + smbios_slot_desc "0xb0" "4" "PCI Express x16" "0xd" + end # PCIe Bridge for discrete graphics device pci 02.0 off end # Internal graphics end end diff --git a/src/mainboard/pcengines/apu1/devicetree.cb b/src/mainboard/pcengines/apu1/devicetree.cb index 2e8b8f4..4074e82 100644 --- a/src/mainboard/pcengines/apu1/devicetree.cb +++ b/src/mainboard/pcengines/apu1/devicetree.cb @@ -27,7 +27,9 @@ device pci 4.0 on end # PCIE P2P bridge on-board NIC 3 device pci 5.0 on end # PCIE P2P bridge on-board NIC 2 device pci 6.0 on end # PCIE P2P bridge on-board NIC 1 - device pci 7.0 on end # PCIE P2P bridge miniPCIe slot 1 + device pci 7.0 on + smbios_slot_desc "0x22" "4" "mPCIe 1" "8" + end # PCIE P2P bridge miniPCIe slot 1 device pci 8.0 on end # NB/SB Link P2P bridge end # agesa northbridge @@ -77,7 +79,9 @@ device pci 14.4 on end # PCIB 0x4384 always active; pins remapped to gpio by disconnect_pcib = 1 device pci 14.5 off end # OHCI FS/LS USB #device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699) - device pci 15.0 on end # PCIe PortA miniPCIe slot 2 + device pci 15.0 on + smbios_slot_desc "0x22" "4" "mPCIe 2" "8" + end # PCIe PortA miniPCIe slot 2 device pci 15.1 off end # PCIe PortB device pci 15.2 off end # PCIe PortC device pci 15.3 off end # PCIe PortD diff --git a/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb index 6728228..e37dc20 100644 --- a/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb @@ -28,11 +28,15 @@ device pci 1.0 off end # Internal Graphics P2P bridge 0x9804 device pci 1.1 off end # Internal Multimedia device pci 2.0 on end # PCIe Host Bridge - device pci 2.1 on end # mPCIe slot 2 (on GFX lane) + device pci 2.1 on + smbios_slot_desc "0x22" "4" "mPCIe 2" "8" + end # mPCIe slot 2 (on GFX lane) device pci 2.2 on end # LAN3 device pci 2.3 on end # LAN2 device pci 2.4 on end # LAN1 - device pci 2.5 on end # mPCIe slot 1 + device pci 2.5 on + smbios_slot_desc "0x22" "4" "mPCIe 1" "8" + end # mPCIe slot 1 device pci 8.0 on end # Platform Security Processor end #chip northbridge/amd/pi/00730F01 diff --git a/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb index 0c0c21e..2c2900c 100644 --- a/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb @@ -28,11 +28,15 @@ device pci 1.0 off end # Internal Graphics P2P bridge 0x9804 device pci 1.1 off end # Internal Multimedia device pci 2.0 on end # PCIe Host Bridge - device pci 2.1 on end # mPCIe slot 2 (on GFX lane) + device pci 2.1 on + smbios_slot_desc "0x22" "4" "mPCIe 2" "8" + end # mPCIe slot 2 (on GFX lane) device pci 2.2 on end # LAN3 device pci 2.3 on end # LAN2 device pci 2.4 on end # LAN1 - device pci 2.5 on end # mPCIe slot 1 + device pci 2.5 on + smbios_slot_desc "0x22" "4" "mPCIe 1" "8" + end # mPCIe slot 1 device pci 8.0 on end # Platform Security Processor end #chip northbridge/amd/pi/00730F01 diff --git a/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb index c93c04f..95a6920 100644 --- a/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb @@ -32,7 +32,9 @@ device pci 2.2 on end # LAN2 device pci 2.3 on end # LAN3 device pci 2.4 on end # LAN4 - device pci 2.5 on end # mPCIe slot 1 + device pci 2.5 on + smbios_slot_desc "0x22" "4" "mPCIe 1" "8" + end # mPCIe slot 1 device pci 8.0 on end # Platform Security Processor end #chip northbridge/amd/pi/00730F01 diff --git a/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb index b6b22cf..dac8c50 100644 --- a/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb @@ -28,11 +28,15 @@ device pci 1.0 off end # Internal Graphics P2P bridge 0x9804 device pci 1.1 off end # Internal Multimedia device pci 2.0 on end # PCIe Host Bridge - device pci 2.1 on end # mPCIe slot 2 (on GFX lane) + device pci 2.1 on + smbios_slot_desc "0x22" "4" "mPCIe 2" "8" + end # mPCIe slot 2 (on GFX lane) device pci 2.2 on end # LAN3 device pci 2.3 on end # LAN2 device pci 2.4 on end # LAN1 - device pci 2.5 on end # mPCIe slot 1 + device pci 2.5 on + smbios_slot_desc "0x22" "4" "mPCIe 1" "8" + end # mPCIe slot 1 device pci 8.0 on end # Platform Security Processor end #chip northbridge/amd/pi/00730F01 diff --git a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb index 95c59df..05dec1b 100644 --- a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb +++ b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb @@ -157,6 +157,7 @@ end device pci 01.0 on # PCIe Bridge for discrete graphics subsystemid 0x174b 0x1007 + smbios_slot_desc "0xb6" "4" "PCI Express x16" "0xd" end device pci 02.0 on # Internal graphics VGA controller subsystemid 0x8086 0x2010 diff --git a/src/mainboard/supermicro/x10slm-f/devicetree.cb b/src/mainboard/supermicro/x10slm-f/devicetree.cb index 434fb59..5784fe0 100644 --- a/src/mainboard/supermicro/x10slm-f/devicetree.cb +++ b/src/mainboard/supermicro/x10slm-f/devicetree.cb @@ -34,7 +34,9 @@ subsystemid 0x15d9 0x0803 inherit device pci 00.0 on end # Host bridge - device pci 01.0 on end # PEG 10 + device pci 01.0 on + smbios_slot_desc "0xb6" "4" "PCI Express x16" "0xb" + end # PEG 10 device pci 01.1 on end # PEG 11 device pci 02.0 off end # IGD device pci 03.0 off end # Mini-HD audio @@ -78,7 +80,9 @@ subsystemid 0x15d9 0x1533 end end - device pci 1c.4 on end # PCIe root port 5 + device pci 1c.4 on + smbios_slot_desc "0xaf" "4" "PCI Express x8" "0xa" + end # PCIe root port 5 device pci 1c.5 off end # PCIe root port 6 device pci 1c.6 off end # PCIe root port 7 device pci 1c.7 off end # PCIe root port 8 -- To view, visit https://review.coreboot.org/c/coreboot/+/32684 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I829de30c50212bb90cb51470af91518fd9b9e41c Gerrit-Change-Number: 32684 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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coreboot-gerrit May 2019