coreboot-gerrit May 2019

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Change in ...coreboot[master]: mb/lenovo/t520: Add MRC settings in devicetree
by Patrick Rudolph (Code Review) 10 Jun '23

10 Jun '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32500 Change subject: mb/lenovo/t520: Add MRC settings in devicetree ...................................................................... mb/lenovo/t520: Add MRC settings in devicetree Add support for MRC raminit using devicetree settings. Tested on Lenovo T520. Change-Id: I58198f3f177a7639675f8a408c1f4e02fcebc50a --- M src/mainboard/lenovo/t520/Kconfig M src/mainboard/lenovo/t520/romstage.c M src/mainboard/lenovo/t520/variants/t520/devicetree.cb 3 files changed, 30 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/32500/1 diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig index 06f296b..d61f651 100644 --- a/src/mainboard/lenovo/t520/Kconfig +++ b/src/mainboard/lenovo/t520/Kconfig @@ -2,7 +2,6 @@ def_bool n select SYSTEM_TYPE_LAPTOP select NORTHBRIDGE_INTEL_SANDYBRIDGE - select USE_NATIVE_RAMINIT select SOUTHBRIDGE_INTEL_BD82X6X select EC_LENOVO_PMH7 select EC_LENOVO_H8 diff --git a/src/mainboard/lenovo/t520/romstage.c b/src/mainboard/lenovo/t520/romstage.c index 96d07fe..8566200 100644 --- a/src/mainboard/lenovo/t520/romstage.c +++ b/src/mainboard/lenovo/t520/romstage.c @@ -20,6 +20,7 @@ #include <device/pci_ops.h> #include <device/pci_def.h> #include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit.h> #include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h> @@ -95,3 +96,12 @@ void mainboard_config_superio(void) { } + +void mainboard_fill_pei_data(struct pei_data *pei_data) +{ +} + +int mainboard_should_reset_usb(int s3resume) +{ + return !s3resume; +} diff --git a/src/mainboard/lenovo/t520/variants/t520/devicetree.cb b/src/mainboard/lenovo/t520/variants/t520/devicetree.cb index cf8e7ce..22db921 100644 --- a/src/mainboard/lenovo/t520/variants/t520/devicetree.cb +++ b/src/mainboard/lenovo/t520/variants/t520/devicetree.cb @@ -36,6 +36,26 @@ register "pci_mmio_size" = "2048" + # PEI data + register "spd_addresses" = "{ 0xa0, 0x00, 0xa2, 0x00 }" + register "ts_addresses" = "{ 0x00, 0x00, 0x00, 0x00 }" + + register "dimm_channel0_disabled" = "2" + register "dimm_channel1_disabled" = "2" + + register "max_mem_clock_mhz" = "666" # DDR3-1333 + + register "usb_port_config" = "{ + { 1, 0, 0x0040 }, /* back, towards HDMI plugs */ + { 1, 0, 0x0040 }, /* back, towards power plug */ + { 1, 1, 0x0040 }, /* half-width miniPCIe */ + { 1, 1, 0x0040 }, /* full-width miniPCIe */ + { 1, 2, 0x0040 }, /* front-panel header */ + { 1, 2, 0x0040 }, /* front-panel header */ + { 1, 3, 0x0040 }, /* front connector */ + }" + + device domain 0 on device pci 00.0 on end # host bridge device pci 01.0 on end # NVIDIA Corporation GF119M [NVS 4200M] -- To view, visit https://review.coreboot.org/c/coreboot/+/32500 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I58198f3f177a7639675f8a408c1f4e02fcebc50a Gerrit-Change-Number: 32500 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Enable acoustic noise mitgation for arcada platform, the slow slew ra...
by Nathan Chen (Code Review) 10 Jun '23

10 Jun '23

Nathan Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32520 Change subject: Enable acoustic noise mitgation for arcada platform, the slow slew rates for Ia and Gt are fast time dived by 8. ...................................................................... Enable acoustic noise mitgation for arcada platform, the slow slew rates for Ia and Gt are fast time dived by 8. BUG=b:131144464 TEST=waveform test and hardware validation result pass. Signed-off-by: nathan chen <nathan_chen(a)wistron.corp-partner.google.com> Change-Id: I2ebcca803deb04737bfb5b2c134b164971f3688e --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/32520/1 diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index cf64c4b..77bd82a 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -37,10 +37,10 @@ register "tdp_pl2_override" = "51" register "Device4Enable" = "1" register "AcousticNoiseMitigation" = "1" - register "SlowSlewRateForIa" = "0" - register "SlowSlewRateForGt" = "0" + register "SlowSlewRateForIa" = "2" + register "SlowSlewRateForGt" = "2" register "SlowSlewRateForSa" = "0" - register "SlowSlewRateForFivr" = "0" + register "SlowSlewRateForFivr" = "2" # Enable eDP device register "DdiPortEdp" = "1" # Enable HPD for DDI ports B/C -- To view, visit https://review.coreboot.org/c/coreboot/+/32520 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2ebcca803deb04737bfb5b2c134b164971f3688e Gerrit-Change-Number: 32520 Gerrit-PatchSet: 1 Gerrit-Owner: Nathan Chen <nathan_chen(a)wistron.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: sb/intel/lynxpoint: Fix flashconsole after lockdown
by Daniel Maslowski (Code Review) 10 Jun '23

10 Jun '23

Daniel Maslowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33008 Change subject: sb/intel/lynxpoint: Fix flashconsole after lockdown ...................................................................... sb/intel/lynxpoint: Fix flashconsole after lockdown Same as with sb/intel/bd82x6x: SMM final locks the SPI BAR, which causes flashconsole to hang. Re-init it like SMM does with CONFIG_SPI_FLASH_SMM. Change-Id: Ie35af9610ebbba5c66351e9668e9a55cae3c7520 Signed-off-by: Daniel Maslowski <dan(a)orangecms.org> --- M src/southbridge/intel/lynxpoint/lpc.c 1 file changed, 9 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/33008/1 diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index b0f57c1..714c696 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -965,8 +965,16 @@ RCBA32(0x3898) = SPI_OPMENU_LOWER; RCBA32(0x389c) = SPI_OPMENU_UPPER; - if (acpi_is_wakeup_s3() || CONFIG(INTEL_CHIPSET_LOCKDOWN)) + if (acpi_is_wakeup_s3() || CONFIG(INTEL_CHIPSET_LOCKDOWN)) { outb(APM_CNT_FINALIZE, APM_CNT); + if (CONFIG(CONSOLE_SPI_FLASH)) { + /* Re-init SPI driver to handle locked BAR. + This prevents flashconsole from hanging. + If other code needs to use SPI during + ramstage, whitelist it here. */ + spi_init(); + } + } } static struct pci_operations pci_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/33008 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie35af9610ebbba5c66351e9668e9a55cae3c7520 Gerrit-Change-Number: 33008 Gerrit-PatchSet: 1 Gerrit-Owner: Daniel Maslowski <info(a)orangecms.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: nb/intel/sandybridge: Use understandable values for PWM backlight
by Arthur Heymans (Code Review) 10 Jun '23

10 Jun '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30567 Change subject: nb/intel/sandybridge: Use understandable values for PWM backlight ...................................................................... nb/intel/sandybridge: Use understandable values for PWM backlight This gets rid of setting the register values from the devicetree and makes it possible to use sensible values in the devicetree. TODO update autoport. Untested Change-Id: I7eb69d9efdccede02fdd3771b3deab536050bfa4 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/apple/macbookair4_2/devicetree.cb M src/mainboard/asrock/b75pro3-m/devicetree.cb M src/mainboard/google/link/devicetree.cb M src/mainboard/google/parrot/devicetree.cb M src/mainboard/google/stout/devicetree.cb M src/mainboard/hp/2570p/devicetree.cb M src/mainboard/hp/2760p/devicetree.cb M src/mainboard/hp/8460p/devicetree.cb M src/mainboard/hp/8470p/devicetree.cb M src/mainboard/hp/folio_9470m/devicetree.cb M src/mainboard/hp/revolve_810_g1/devicetree.cb M src/mainboard/lenovo/l520/devicetree.cb M src/mainboard/lenovo/s230u/devicetree.cb M src/mainboard/lenovo/t420/devicetree.cb M src/mainboard/lenovo/t420s/devicetree.cb M src/mainboard/lenovo/t430/devicetree.cb M src/mainboard/lenovo/t430s/devicetree.cb M src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb M src/mainboard/lenovo/t520/variants/t520/devicetree.cb M src/mainboard/lenovo/t520/variants/w520/devicetree.cb M src/mainboard/lenovo/t530/variants/t530/devicetree.cb M src/mainboard/lenovo/t530/variants/w530/devicetree.cb M src/mainboard/lenovo/x131e/devicetree.cb M src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb M src/mainboard/lenovo/x220/devicetree.cb M src/mainboard/lenovo/x230/devicetree.cb M src/mainboard/roda/rv11/variants/rv11/devicetree.cb M src/mainboard/roda/rv11/variants/rw11/devicetree.cb M src/mainboard/sapphire/pureplatinumh61/devicetree.cb M src/northbridge/intel/sandybridge/chip.h M src/northbridge/intel/sandybridge/gma.c 31 files changed, 93 insertions(+), 64 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/30567/1 diff --git a/src/mainboard/apple/macbookair4_2/devicetree.cb b/src/mainboard/apple/macbookair4_2/devicetree.cb index 226ec04..4a7edc9 100644 --- a/src/mainboard/apple/macbookair4_2/devicetree.cb +++ b/src/mainboard/apple/macbookair4_2/devicetree.cb @@ -3,7 +3,6 @@ register "gfx.link_frequency_270_mhz" = "0" register "gfx.ndid" = "2" register "gfx.use_spread_spectrum_clock" = "1" - register "gpu_cpu_backlight" = "0x00001312" register "gpu_dp_b_hotplug" = "4" register "gpu_dp_c_hotplug" = "4" register "gpu_dp_d_hotplug" = "4" @@ -13,7 +12,8 @@ register "gpu_panel_power_cycle_delay" = "6" register "gpu_panel_power_down_delay" = "500" register "gpu_panel_power_up_delay" = "2000" - register "gpu_pch_backlight" = "0x13121312" + register "pwm_freq" = "200" + register "duty_cycle" = "100" device cpu_cluster 0x0 on chip cpu/intel/socket_rPGA989 device lapic 0x0 on diff --git a/src/mainboard/asrock/b75pro3-m/devicetree.cb b/src/mainboard/asrock/b75pro3-m/devicetree.cb index def3d1d..24cfe9a 100644 --- a/src/mainboard/asrock/b75pro3-m/devicetree.cb +++ b/src/mainboard/asrock/b75pro3-m/devicetree.cb @@ -19,7 +19,6 @@ register "gfx.link_frequency_270_mhz" = "0" register "gfx.ndid" = "3" register "gfx.use_spread_spectrum_clock" = "0" - register "gpu_cpu_backlight" = "0x00000000" register "gpu_dp_b_hotplug" = "4" register "gpu_dp_c_hotplug" = "4" register "gpu_dp_d_hotplug" = "4" @@ -29,7 +28,6 @@ register "gpu_panel_power_cycle_delay" = "4" register "gpu_panel_power_down_delay" = "0" register "gpu_panel_power_up_delay" = "0" - register "gpu_pch_backlight" = "0x00000000" device cpu_cluster 0x0 on chip cpu/intel/socket_rPGA989 device lapic 0x0 on diff --git a/src/mainboard/google/link/devicetree.cb b/src/mainboard/google/link/devicetree.cb index 07be8e7..05d7b34 100644 --- a/src/mainboard/google/link/devicetree.cb +++ b/src/mainboard/google/link/devicetree.cb @@ -15,8 +15,9 @@ register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms # Set backlight PWM values for eDP - register "gpu_cpu_backlight" = "0x00000200" - register "gpu_pch_backlight" = "0x04000000" + register "pwm_freq" = "953" + register "duty_cycle" = "50" + register "max_mem_clock_mhz" = "666" diff --git a/src/mainboard/google/parrot/devicetree.cb b/src/mainboard/google/parrot/devicetree.cb index eacfe57..d47684c 100644 --- a/src/mainboard/google/parrot/devicetree.cb +++ b/src/mainboard/google/parrot/devicetree.cb @@ -17,6 +17,9 @@ # Set backlight PWM values register "gpu_cpu_backlight" = "0x000001d4" register "gpu_pch_backlight" = "0x03aa0000" + register "pwm_freq" = "1041" + register "duty_cycle" = "50" + register "max_mem_clock_mhz" = "666" diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb index 0fdb55e..446c822 100644 --- a/src/mainboard/google/stout/devicetree.cb +++ b/src/mainboard/google/stout/devicetree.cb @@ -17,8 +17,8 @@ # For native gfx register "gfx.use_spread_spectrum_clock" = "0" register "gfx.link_frequency_270_mhz" = "1" - register "gpu_cpu_backlight" = "0x1155" - register "gpu_pch_backlight" = "0x06100610" + register "pwm_freq" = "629" + register "duty_cycle" = "100" register "max_mem_clock_mhz" = "666" diff --git a/src/mainboard/hp/2570p/devicetree.cb b/src/mainboard/hp/2570p/devicetree.cb index 753d286..bf3f03f 100644 --- a/src/mainboard/hp/2570p/devicetree.cb +++ b/src/mainboard/hp/2570p/devicetree.cb @@ -19,7 +19,6 @@ register "gfx.link_frequency_270_mhz" = "1" register "gfx.ndid" = "3" register "gfx.use_spread_spectrum_clock" = "1" - register "gpu_cpu_backlight" = "0x00000437" register "gpu_dp_b_hotplug" = "4" register "gpu_dp_c_hotplug" = "4" register "gpu_dp_d_hotplug" = "4" @@ -29,7 +28,8 @@ register "gpu_panel_power_cycle_delay" = "5" register "gpu_panel_power_down_delay" = "230" register "gpu_panel_power_up_delay" = "300" - register "gpu_pch_backlight" = "0x0d9c0d9c" + register "pwm_freq" = "280" + register "duty_cycle" = "30" device cpu_cluster 0x0 on chip cpu/intel/socket_rPGA989 device lapic 0x0 on diff --git a/src/mainboard/hp/2760p/devicetree.cb b/src/mainboard/hp/2760p/devicetree.cb index 041b5e8..6bd4885 100644 --- a/src/mainboard/hp/2760p/devicetree.cb +++ b/src/mainboard/hp/2760p/devicetree.cb @@ -19,7 +19,6 @@ register "gfx.link_frequency_270_mhz" = "1" register "gfx.ndid" = "3" register "gfx.use_spread_spectrum_clock" = "1" - register "gpu_cpu_backlight" = "0x00000129" register "gpu_dp_b_hotplug" = "4" register "gpu_dp_c_hotplug" = "4" register "gpu_dp_d_hotplug" = "4" @@ -29,7 +28,8 @@ register "gpu_panel_power_cycle_delay" = "5" register "gpu_panel_power_down_delay" = "230" register "gpu_panel_power_up_delay" = "300" - register "gpu_pch_backlight" = "0x02880288" + register "pwm_freq" = "1507" + register "duty_cycle" = "45" device cpu_cluster 0x0 on chip cpu/intel/socket_rPGA989 device lapic 0x0 on diff --git a/src/mainboard/hp/8460p/devicetree.cb b/src/mainboard/hp/8460p/devicetree.cb index 9f9efbb..adacbd9 100644 --- a/src/mainboard/hp/8460p/devicetree.cb +++ b/src/mainboard/hp/8460p/devicetree.cb @@ -19,7 +19,6 @@ register "gfx.link_frequency_270_mhz" = "1" register "gfx.ndid" = "3" register "gfx.use_spread_spectrum_clock" = "1" - register "gpu_cpu_backlight" = "0x00000129" register "gpu_dp_b_hotplug" = "4" register "gpu_dp_c_hotplug" = "4" register "gpu_dp_d_hotplug" = "4" @@ -29,7 +28,9 @@ register "gpu_panel_power_cycle_delay" = "5" register "gpu_panel_power_down_delay" = "230" register "gpu_panel_power_up_delay" = "300" - register "gpu_pch_backlight" = "0x02880288" + register "pwm_freq" = "1507" + register "duty_cycle" = "45" + device cpu_cluster 0x0 on chip cpu/intel/socket_rPGA989 device lapic 0x0 on diff --git a/src/mainboard/hp/8470p/devicetree.cb b/src/mainboard/hp/8470p/devicetree.cb index 9d6fe3f..c9151fc 100644 --- a/src/mainboard/hp/8470p/devicetree.cb +++ b/src/mainboard/hp/8470p/devicetree.cb @@ -19,7 +19,6 @@ register "gfx.link_frequency_270_mhz" = "1" register "gfx.ndid" = "3" register "gfx.use_spread_spectrum_clock" = "1" - register "gpu_cpu_backlight" = "0x00000385" register "gpu_dp_b_hotplug" = "4" register "gpu_dp_c_hotplug" = "4" register "gpu_dp_d_hotplug" = "4" @@ -29,7 +28,9 @@ register "gpu_panel_power_cycle_delay" = "5" register "gpu_panel_power_down_delay" = "230" register "gpu_panel_power_up_delay" = "300" - register "gpu_pch_backlight" = "0x0d9c0d9c" + register "pwm_freq" = "280" + register "duty_cycle" = "26" + device cpu_cluster 0x0 on chip cpu/intel/socket_rPGA989 device lapic 0x0 on diff --git a/src/mainboard/hp/folio_9470m/devicetree.cb b/src/mainboard/hp/folio_9470m/devicetree.cb index 56d90d3..c8fb413 100644 --- a/src/mainboard/hp/folio_9470m/devicetree.cb +++ b/src/mainboard/hp/folio_9470m/devicetree.cb @@ -19,7 +19,6 @@ register "gfx.link_frequency_270_mhz" = "1" register "gfx.ndid" = "3" register "gfx.use_spread_spectrum_clock" = "1" - register "gpu_cpu_backlight" = "0x00000d9c" register "gpu_dp_b_hotplug" = "4" register "gpu_dp_c_hotplug" = "4" register "gpu_dp_d_hotplug" = "4" @@ -29,7 +28,9 @@ register "gpu_panel_power_cycle_delay" = "5" register "gpu_panel_power_down_delay" = "230" register "gpu_panel_power_up_delay" = "300" - register "gpu_pch_backlight" = "0x0d9c0d9c" + register "pwm_freq" = "280" + register "duty_cycle" = "30" + device cpu_cluster 0x0 on chip cpu/intel/socket_rPGA989 device lapic 0x0 on diff --git a/src/mainboard/hp/revolve_810_g1/devicetree.cb b/src/mainboard/hp/revolve_810_g1/devicetree.cb index 2384e71..604d4bc 100644 --- a/src/mainboard/hp/revolve_810_g1/devicetree.cb +++ b/src/mainboard/hp/revolve_810_g1/devicetree.cb @@ -19,7 +19,6 @@ register "gfx.link_frequency_270_mhz" = "1" register "gfx.ndid" = "3" register "gfx.use_spread_spectrum_clock" = "1" - register "gpu_cpu_backlight" = "0x00000263" register "gpu_dp_b_hotplug" = "4" register "gpu_dp_c_hotplug" = "4" register "gpu_dp_d_hotplug" = "4" @@ -29,7 +28,9 @@ register "gpu_panel_power_cycle_delay" = "5" register "gpu_panel_power_down_delay" = "230" register "gpu_panel_power_up_delay" = "300" - register "gpu_pch_backlight" = "0x02880288" + register "pwm_freq" = "1507" + register "duty_cycle" = "94" + device cpu_cluster 0x0 on chip cpu/intel/socket_rPGA989 device lapic 0x0 on diff --git a/src/mainboard/lenovo/l520/devicetree.cb b/src/mainboard/lenovo/l520/devicetree.cb index 3e1f308..af14415 100644 --- a/src/mainboard/lenovo/l520/devicetree.cb +++ b/src/mainboard/lenovo/l520/devicetree.cb @@ -3,7 +3,6 @@ register "gfx.link_frequency_270_mhz" = "0" register "gfx.ndid" = "3" register "gfx.use_spread_spectrum_clock" = "0" - register "gpu_cpu_backlight" = "0x00000000" register "gpu_dp_b_hotplug" = "0" register "gpu_dp_c_hotplug" = "0" register "gpu_dp_d_hotplug" = "0" @@ -13,7 +12,6 @@ register "gpu_panel_power_cycle_delay" = "0" register "gpu_panel_power_down_delay" = "0" register "gpu_panel_power_up_delay" = "0" - register "gpu_pch_backlight" = "0x00000000" device cpu_cluster 0x0 on chip cpu/intel/socket_rPGA989 diff --git a/src/mainboard/lenovo/s230u/devicetree.cb b/src/mainboard/lenovo/s230u/devicetree.cb index 35135a9..ddf7baa 100644 --- a/src/mainboard/lenovo/s230u/devicetree.cb +++ b/src/mainboard/lenovo/s230u/devicetree.cb @@ -3,7 +3,6 @@ register "gfx.link_frequency_270_mhz" = "1" register "gfx.ndid" = "3" register "gfx.use_spread_spectrum_clock" = "1" - register "gpu_cpu_backlight" = "0x00000060" register "gpu_dp_b_hotplug" = "4" register "gpu_dp_c_hotplug" = "4" register "gpu_dp_d_hotplug" = "4" @@ -13,7 +12,9 @@ register "gpu_panel_power_cycle_delay" = "5" register "gpu_panel_power_down_delay" = "500" register "gpu_panel_power_up_delay" = "600" - register "gpu_pch_backlight" = "0x041e041e" + register "pwm_freq" = "926" + register "duty_cycle" = "10" + device cpu_cluster 0x0 on chip cpu/intel/socket_rPGA989 device lapic 0x0 on diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb index bed406a..0b7722e 100644 --- a/src/mainboard/lenovo/t420/devicetree.cb +++ b/src/mainboard/lenovo/t420/devicetree.cb @@ -15,8 +15,8 @@ register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms register "gfx.use_spread_spectrum_clock" = "1" register "gfx.link_frequency_270_mhz" = "1" - register "gpu_cpu_backlight" = "0x1155" - register "gpu_pch_backlight" = "0x06100610" + register "pwm_freq" = "629" + register "duty_cycle" = "100" device cpu_cluster 0 on chip cpu/intel/socket_rPGA988B diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb index a090308..809fee2 100644 --- a/src/mainboard/lenovo/t420s/devicetree.cb +++ b/src/mainboard/lenovo/t420s/devicetree.cb @@ -14,8 +14,8 @@ register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms register "gfx.use_spread_spectrum_clock" = "1" register "gfx.link_frequency_270_mhz" = "1" - register "gpu_cpu_backlight" = "0x1155" - register "gpu_pch_backlight" = "0x06100610" + register "pwm_freq" = "629" + register "duty_cycle" = "100" device cpu_cluster 0 on chip cpu/intel/socket_rPGA988B diff --git a/src/mainboard/lenovo/t430/devicetree.cb b/src/mainboard/lenovo/t430/devicetree.cb index 5eb92bc..ddd4289 100644 --- a/src/mainboard/lenovo/t430/devicetree.cb +++ b/src/mainboard/lenovo/t430/devicetree.cb @@ -14,8 +14,8 @@ register "gpu_panel_power_backlight_off_delay" = "2100" # T4: 210ms register "gfx.use_spread_spectrum_clock" = "1" register "gfx.link_frequency_270_mhz" = "1" - register "gpu_cpu_backlight" = "0x1155" - register "gpu_pch_backlight" = "0x11551155" + register "pwm_freq" = "629" + register "duty_cycle" = "100" device cpu_cluster 0x0 on chip cpu/intel/socket_rPGA989 diff --git a/src/mainboard/lenovo/t430s/devicetree.cb b/src/mainboard/lenovo/t430s/devicetree.cb index 56e7f63..69e104a 100644 --- a/src/mainboard/lenovo/t430s/devicetree.cb +++ b/src/mainboard/lenovo/t430s/devicetree.cb @@ -14,8 +14,8 @@ register "gpu_panel_power_backlight_off_delay" = "2100" # T4: 210ms register "gfx.use_spread_spectrum_clock" = "1" register "gfx.link_frequency_270_mhz" = "1" - register "gpu_cpu_backlight" = "0x1155" - register "gpu_pch_backlight" = "0x11551155" + register "pwm_freq" = "629" + register "duty_cycle" = "100" device cpu_cluster 0 on chip cpu/intel/socket_rPGA989 diff --git a/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb b/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb index e69f727..3abf890 100644 --- a/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb +++ b/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb @@ -10,7 +10,8 @@ register "gpu_panel_power_down_delay" = "500" # 50ms register "gpu_panel_power_backlight_on_delay" = "1" # 0.1ms register "gpu_panel_power_backlight_off_delay" = "1" # 0.1ms - register "gpu_cpu_backlight" = "0x03d2" + register "duty_cycle" = "63" + device domain 0 on device pci 00.0 on diff --git a/src/mainboard/lenovo/t520/variants/t520/devicetree.cb b/src/mainboard/lenovo/t520/variants/t520/devicetree.cb index 97350f3..671b45d 100644 --- a/src/mainboard/lenovo/t520/variants/t520/devicetree.cb +++ b/src/mainboard/lenovo/t520/variants/t520/devicetree.cb @@ -15,8 +15,8 @@ register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms register "gfx.use_spread_spectrum_clock" = "1" register "gfx.link_frequency_270_mhz" = "1" - register "gpu_cpu_backlight" = "0x1155" - register "gpu_pch_backlight" = "0x06100610" + register "pwm_freq" = "629" + register "duty_cycle" = "100" device cpu_cluster 0 on chip cpu/intel/socket_rPGA988B diff --git a/src/mainboard/lenovo/t520/variants/w520/devicetree.cb b/src/mainboard/lenovo/t520/variants/w520/devicetree.cb index 33b9368..3df91b9 100644 --- a/src/mainboard/lenovo/t520/variants/w520/devicetree.cb +++ b/src/mainboard/lenovo/t520/variants/w520/devicetree.cb @@ -15,8 +15,8 @@ register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms register "gfx.use_spread_spectrum_clock" = "1" register "gfx.link_frequency_270_mhz" = "1" - register "gpu_cpu_backlight" = "0x1155" - register "gpu_pch_backlight" = "0x06100610" + register "pwm_freq" = "629" + register "duty_cycle" = "100" device cpu_cluster 0 on chip cpu/intel/socket_rPGA988B diff --git a/src/mainboard/lenovo/t530/variants/t530/devicetree.cb b/src/mainboard/lenovo/t530/variants/t530/devicetree.cb index 4dcdc9d..20404c0 100644 --- a/src/mainboard/lenovo/t530/variants/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/variants/t530/devicetree.cb @@ -15,8 +15,8 @@ register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms register "gfx.use_spread_spectrum_clock" = "1" register "gfx.link_frequency_270_mhz" = "1" - register "gpu_cpu_backlight" = "0x1155" - register "gpu_pch_backlight" = "0x11551155" + register "pwm_freq" = "629" + register "duty_cycle" = "100" device cpu_cluster 0 on chip cpu/intel/socket_rPGA989 diff --git a/src/mainboard/lenovo/t530/variants/w530/devicetree.cb b/src/mainboard/lenovo/t530/variants/w530/devicetree.cb index 7a72b26..4af6c42 100644 --- a/src/mainboard/lenovo/t530/variants/w530/devicetree.cb +++ b/src/mainboard/lenovo/t530/variants/w530/devicetree.cb @@ -18,8 +18,8 @@ register "gpu_panel_power_backlight_on_delay" = "2000" # T3: 200ms register "gfx.use_spread_spectrum_clock" = "1" register "gfx.link_frequency_270_mhz" = "1" - register "gpu_cpu_backlight" = "0x1155" - register "gpu_pch_backlight" = "0x11551155" + register "pwm_freq" = "220" + register "duty_cycle" = "100" device cpu_cluster 0x0 on chip cpu/intel/socket_rPGA989 diff --git a/src/mainboard/lenovo/x131e/devicetree.cb b/src/mainboard/lenovo/x131e/devicetree.cb index ccdff7c..2a3a30f 100644 --- a/src/mainboard/lenovo/x131e/devicetree.cb +++ b/src/mainboard/lenovo/x131e/devicetree.cb @@ -14,8 +14,8 @@ register "gpu_panel_power_backlight_off_delay" = "2000" register "gfx.use_spread_spectrum_clock" = "1" register "gfx.link_frequency_270_mhz" = "1" - register "gpu_cpu_backlight" = "0x1155" - register "gpu_pch_backlight" = "0x11551155" + register "pwm_freq" = "220" + register "duty_cycle" = "100" device cpu_cluster 0x0 on chip cpu/intel/socket_rPGA989 diff --git a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb index cb88a7f..c60ac62 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb +++ b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb @@ -3,7 +3,6 @@ register "gfx.link_frequency_270_mhz" = "1" register "gfx.ndid" = "3" register "gfx.use_spread_spectrum_clock" = "1" - register "gpu_cpu_backlight" = "0x00001155" register "gpu_dp_b_hotplug" = "4" register "gpu_dp_c_hotplug" = "4" register "gpu_dp_d_hotplug" = "4" @@ -13,7 +12,9 @@ register "gpu_panel_power_cycle_delay" = "6" register "gpu_panel_power_down_delay" = "300" register "gpu_panel_power_up_delay" = "300" - register "gpu_pch_backlight" = "0x11551155" + register "pwm_freq" = "220" + register "duty_cycle" = "100" + device cpu_cluster 0 on chip cpu/intel/socket_rPGA989 diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index 969ae38..85f3fbc 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -15,8 +15,8 @@ register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms register "gfx.use_spread_spectrum_clock" = "1" register "gfx.link_frequency_270_mhz" = "1" - register "gpu_cpu_backlight" = "0x1155" - register "gpu_pch_backlight" = "0x06100610" + register "pwm_freq" = "629" + register "duty_cycle" = "100" device cpu_cluster 0 on chip cpu/intel/socket_rPGA989 diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index a31be72..9a4866d 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -15,8 +15,8 @@ register "gpu_panel_power_backlight_off_delay" = "2100" # T4: 210ms register "gfx.use_spread_spectrum_clock" = "1" register "gfx.link_frequency_270_mhz" = "1" - register "gpu_cpu_backlight" = "0x1155" - register "gpu_pch_backlight" = "0x11551155" + register "pwm_freq" = "220" + register "duty_cycle" = "100" device cpu_cluster 0 on chip cpu/intel/socket_rPGA989 diff --git a/src/mainboard/roda/rv11/variants/rv11/devicetree.cb b/src/mainboard/roda/rv11/variants/rv11/devicetree.cb index 4455fdb..eab2401 100644 --- a/src/mainboard/roda/rv11/variants/rv11/devicetree.cb +++ b/src/mainboard/roda/rv11/variants/rv11/devicetree.cb @@ -27,8 +27,9 @@ register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms # Set backlight PWM values for eDP - register "gpu_cpu_backlight" = "0x0000001a" - register "gpu_pch_backlight" = "0x002e0000" + register "pwm_freq" = "21229" + register "duty_cycle" = "57" + device cpu_cluster 0 on chip cpu/intel/socket_rPGA989 diff --git a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb index b51c86e..ffc8b2e 100644 --- a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb +++ b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb @@ -27,8 +27,9 @@ register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms # Set backlight PWM values for eDP - register "gpu_cpu_backlight" = "0x00000ac8" - register "gpu_pch_backlight" = "0x13120000" + register "pwm_freq" = "200" + register "duty_cycle" = "57" + device cpu_cluster 0 on chip cpu/intel/socket_rPGA989 diff --git a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb index ed0d997..617e69d 100644 --- a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb +++ b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb @@ -19,7 +19,6 @@ register "gfx.link_frequency_270_mhz" = "0" register "gfx.ndid" = "3" register "gfx.use_spread_spectrum_clock" = "0" - register "gpu_cpu_backlight" = "0x00000000" register "gpu_dp_b_hotplug" = "0" register "gpu_dp_c_hotplug" = "0" register "gpu_dp_d_hotplug" = "0" @@ -29,7 +28,6 @@ register "gpu_panel_power_cycle_delay" = "0" register "gpu_panel_power_down_delay" = "0" register "gpu_panel_power_up_delay" = "0" - register "gpu_pch_backlight" = "0x00000000" device cpu_cluster 0x0 on chip cpu/intel/socket_LGA1155 device lapic 0x0 on diff --git a/src/northbridge/intel/sandybridge/chip.h b/src/northbridge/intel/sandybridge/chip.h index d002824..ebead59 100644 --- a/src/northbridge/intel/sandybridge/chip.h +++ b/src/northbridge/intel/sandybridge/chip.h @@ -37,8 +37,8 @@ u16 gpu_panel_power_backlight_on_delay; /* T5 time sequence */ u16 gpu_panel_power_backlight_off_delay; /* Tx time sequence */ - u32 gpu_cpu_backlight; /* CPU Backlight PWM value */ - u32 gpu_pch_backlight; /* PCH Backlight PWM value */ + u32 pwm_freq; + u8 duty_cycle; /* * Maximum memory clock. diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index cd8f7b9..c5cdd41 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -528,6 +528,17 @@ gtt_write(0xe4f24, 0x0ff803cf); } +static uint32_t get_raw_freq_mhz(void) +{ + uint32_t pp_divisor = (gtt_read(PCH_PP_DIVISOR) >> 8) & 0xffffff; + return (pp_divisor + 1) * 2 / 100; +} + +static uin32_t pwm_freq_to_reg(uint32_t pwm_freq) +{ + return get_raw_freq_mhz * 1000000 / (pwm_freq * 128); +} + static void gma_pm_init_post_vbios(struct device *dev) { struct northbridge_intel_sandybridge_config *conf = dev->chip_info; @@ -582,14 +593,25 @@ gtt_write(0xc7210, reg32); } - /* Enable Backlight if needed */ - if (conf->gpu_cpu_backlight) { - gtt_write(0x48250, (1 << 31)); - gtt_write(0x48254, conf->gpu_cpu_backlight); - } - if (conf->gpu_pch_backlight) { + if (conf->pwm_freq) + { + uint32_t pwm_reg = pwm_freq_to_reg(conf->pwm_freq); + /* Set the pwm frequency */ gtt_write(0xc8250, (1 << 31)); - gtt_write(0xc8254, conf->gpu_pch_backlight); + reg = pwm_reg << 16; + /* PCH PWM freq override */ + uint8_t duty_cycle = conf->duty_cycle; + if (duty_cycle == 0 || duty_cycle > 100) { + printk(BIOS_WARNING, "GMA: Invalid duty cycle, using 100%\n"); + duty_cycle = 100; + } + if (gtt_read(0xc8250) & (1 << 30)) + reg |= pwm_reg * duty_cycle / 100; + /* PCH PWM backlight freq + duty cycle*/ + gtt_write(0xc8254, reg); + /* CPU PWM backlight duty cycle */ + gtt_write(0x48250, (1 << 31)); + gtt_write(0x48254, pwm_reg * duty_cycle / 100); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/30567 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7eb69d9efdccede02fdd3771b3deab536050bfa4 Gerrit-Change-Number: 30567 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

4 3

Change in ...coreboot[master]: superio/smsc/smscsuperio: Add SCH5317
by Daniel Maslowski (Code Review) 10 Jun '23

10 Jun '23

Daniel Maslowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33009 Change subject: superio/smsc/smscsuperio: Add SCH5317 ...................................................................... superio/smsc/smscsuperio: Add SCH5317 According to the Linux kernel docs (Documentation/hwmon/smsc47b397), this EC is compatible with the SMSC LPC47B397-NC. No public datasheet is available. Found on a Gigabyte P34V2 board. Change-Id: Ib3227213f6a0fe4a02c5f53471f67089a8e5b4be Signed-off-by: Daniel Maslowski <dan(a)orangecms.org> --- M src/superio/smsc/smscsuperio/superio.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/33009/1 diff --git a/src/superio/smsc/smscsuperio/superio.c b/src/superio/smsc/smscsuperio/superio.c index 4ce006d..523bcc1 100644 --- a/src/superio/smsc/smscsuperio/superio.c +++ b/src/superio/smsc/smscsuperio/superio.c @@ -56,6 +56,7 @@ #define SCH3112 0x7c #define SCH3114 0x7d #define SCH5307 0x81 /* Rebranded LPC47B397(?) */ +#define SCH5317 0x85 /* compatible with LPC47B397 */ #define SCH5027D 0x89 #define SCH4304 0x90 /* SCH4304, SCH4307 */ #define SCH5147 0xc1 @@ -136,6 +137,7 @@ {SCH3112, {0, 3, 4, 5, -1, 7, -1, -1, -1, -1, -1, -1, 10, -1, -1}}, {SCH3114, {0, 3, 4, 5, -1, 7, -1, -1, -1, -1, -1, -1, 10, -1, -1}}, {SCH5307, {0, 3, 4, 5, -1, 7, -1, -1, 8, -1, -1, -1, 10, -1, -1}}, + {SCH5317, {0, 3, 4, 5, -1, 7, -1, -1, 8, -1, -1, -1, 10, -1, -1}}, // TODO: check correctness {SCH5027D, {0, 3, 4, 5, -1, 7, -1, -1, -1, -1, -1, -1, 10, -1, 11}}, {SCH4304, {0, 3, 4, 5, -1, 7, -1, 11, -1, -1, -1, -1, 10, -1, -1}}, {SCH5147, {0, 3, 4, 5, -1, 7, -1, -1, -1, -1, -1, -1, 10, -1, -1}}, -- To view, visit https://review.coreboot.org/c/coreboot/+/33009 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib3227213f6a0fe4a02c5f53471f67089a8e5b4be Gerrit-Change-Number: 33009 Gerrit-PatchSet: 1 Gerrit-Owner: Daniel Maslowski <info(a)orangecms.org> Gerrit-MessageType: newchange

3 2

Change in ...coreboot[master]: cbmem_top: Change the return value to uintptr_t
by Arthur Heymans (Code Review) 10 Jun '23

10 Jun '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30693 Change subject: cbmem_top: Change the return value to uintptr_t ...................................................................... cbmem_top: Change the return value to uintptr_t This avoid a lot of casts. Change-Id: Iecec1cffba9dba02d06b10fe88aec173dbc08093 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/cbmem.c M src/cpu/allwinner/a10/cbmem.c M src/cpu/allwinner/a10/ram_segs.h M src/cpu/amd/family_10h-family_15h/ram_calc.c M src/cpu/intel/haswell/romstage.c M src/cpu/intel/haswell/stage_cache.c M src/cpu/intel/model_206ax/stage_cache.c M src/cpu/ti/am335x/cbmem.c M src/drivers/amd/agesa/mtrr_fixme.c M src/drivers/intel/fsp1_0/fsp_util.c M src/drivers/intel/fsp2_0/hob_verify.c M src/include/cbmem.h M src/include/imd.h M src/lib/ext_stage_cache.c M src/lib/imd.c M src/mainboard/emulation/qemu-armv7/cbmem.c M src/mainboard/emulation/qemu-i440fx/memory.c M src/mainboard/emulation/qemu-power8/cbmem.c M src/northbridge/intel/e7505/memmap.c M src/northbridge/intel/fsp_rangeley/raminit.c M src/northbridge/intel/gm45/ram_calc.c M src/northbridge/intel/haswell/ram_calc.c M src/northbridge/intel/i440bx/ram_calc.c M src/northbridge/intel/i945/ram_calc.c M src/northbridge/intel/nehalem/ram_calc.c M src/northbridge/intel/pineview/ram_calc.c M src/northbridge/intel/sandybridge/ram_calc.c M src/northbridge/intel/x4x/ram_calc.c M src/northbridge/via/vx900/memmap.c M src/soc/amd/stoneyridge/northbridge.c M src/soc/amd/stoneyridge/ramtop.c M src/soc/amd/stoneyridge/romstage.c M src/soc/cavium/cn81xx/cbmem.c M src/soc/imgtec/pistachio/cbmem.c M src/soc/intel/apollolake/memmap.c M src/soc/intel/apollolake/romstage.c M src/soc/intel/baytrail/memmap.c M src/soc/intel/baytrail/romstage/romstage.c M src/soc/intel/braswell/memmap.c M src/soc/intel/broadwell/memmap.c M src/soc/intel/broadwell/romstage/romstage.c D src/soc/intel/cannonlake/cbmem.c M src/soc/intel/cannonlake/memmap.c M src/soc/intel/cannonlake/romstage/romstage.c M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/denverton_ns/memmap.c M src/soc/intel/denverton_ns/romstage.c M src/soc/intel/fsp_baytrail/memmap.c M src/soc/intel/fsp_broadwell_de/memmap.c D src/soc/intel/icelake/cbmem.c M src/soc/intel/icelake/memmap.c M src/soc/intel/icelake/romstage/romstage.c M src/soc/intel/quark/memmap.c M src/soc/intel/quark/romstage/fsp2_0.c M src/soc/intel/skylake/memmap.c M src/soc/intel/skylake/romstage/romstage_fsp20.c M src/soc/mediatek/common/cbmem.c M src/soc/nvidia/tegra124/cbmem.c M src/soc/nvidia/tegra210/cbmem.c M src/soc/qualcomm/ipq40xx/cbmem.c M src/soc/qualcomm/ipq806x/cbmem.c M src/soc/qualcomm/sdm845/cbmem.c M src/soc/rockchip/common/cbmem.c M src/soc/samsung/exynos5250/cbmem.c M src/soc/samsung/exynos5420/cbmem.c M src/soc/sifive/fu540/cbmem.c M src/soc/ucb/riscv/cbmem.c 67 files changed, 133 insertions(+), 176 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/30693/1 diff --git a/src/arch/x86/cbmem.c b/src/arch/x86/cbmem.c index 73967e1..bb3c1ef 100644 --- a/src/arch/x86/cbmem.c +++ b/src/arch/x86/cbmem.c @@ -17,16 +17,16 @@ #if IS_ENABLED(CONFIG_CBMEM_TOP_BACKUP) -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - static void *cbmem_top_backup; - void *top_backup; + static uintptr_t cbmem_top_backup; + uintptr_t top_backup; if (ENV_RAMSTAGE && cbmem_top_backup != NULL) return cbmem_top_backup; /* Top of CBMEM is at highest usable DRAM address below 4GiB. */ - top_backup = (void *)restore_top_of_low_cacheable(); + top_backup = restore_top_of_low_cacheable(); if (ENV_RAMSTAGE) cbmem_top_backup = top_backup; diff --git a/src/cpu/allwinner/a10/cbmem.c b/src/cpu/allwinner/a10/cbmem.c index a4c563a3..42331a6 100644 --- a/src/cpu/allwinner/a10/cbmem.c +++ b/src/cpu/allwinner/a10/cbmem.c @@ -20,7 +20,7 @@ #include "ram_segs.h" #include <cbmem.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { return a1x_get_cbmem_top(); } diff --git a/src/cpu/allwinner/a10/ram_segs.h b/src/cpu/allwinner/a10/ram_segs.h index fa915cd..4b4f0e5 100644 --- a/src/cpu/allwinner/a10/ram_segs.h +++ b/src/cpu/allwinner/a10/ram_segs.h @@ -22,21 +22,21 @@ /* * Put CBMEM at top of RAM */ -static inline void *a1x_get_cbmem_top(void) +static inline uintptr_t a1x_get_cbmem_top(void) { - return _dram + (CONFIG_DRAM_SIZE_MB << 20); + return (uintptr_t)_dram + (CONFIG_DRAM_SIZE_MB << 20); } /* * By CBFS cache, we mean a cached copy, in RAM, of the entire CBFS region. */ -static inline void *a1x_get_cbfs_cache_top(void) +static inline uintptr_t a1x_get_cbfs_cache_top(void) { /* Arbitrary 16 MiB gap for cbmem tables and bouncebuffer */ return a1x_get_cbmem_top() - (16 << 20); } -static inline void *a1x_get_cbfs_cache_base(void) +static inline uintptr_t a1x_get_cbfs_cache_base(void) { return a1x_get_cbfs_cache_top() - CONFIG_ROM_SIZE; } diff --git a/src/cpu/amd/family_10h-family_15h/ram_calc.c b/src/cpu/amd/family_10h-family_15h/ram_calc.c index 57bd2fc..7d62064 100644 --- a/src/cpu/amd/family_10h-family_15h/ram_calc.c +++ b/src/cpu/amd/family_10h-family_15h/ram_calc.c @@ -89,9 +89,9 @@ return cc6_size; } -void *cbmem_top(void) +uintptr_t cbmem_top(void) { uint32_t topmem = rdmsr(TOP_MEM).lo; - return (void *) topmem - get_uma_memory_size(topmem) - get_cc6_memory_size(); + return topmem - get_uma_memory_size(topmem) - get_cc6_memory_size(); } diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 688f357..8d39892 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -65,7 +65,7 @@ * above top of the ram. This satisfies MTRR alignment requirement * with different TSEG size configurations. */ - top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); + top_of_ram = ALIGN_DOWN(cbmem_top(), 8*MiB); postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 16*MiB, MTRR_TYPE_WRBACK); diff --git a/src/cpu/intel/haswell/stage_cache.c b/src/cpu/intel/haswell/stage_cache.c index 009cc09..82cb95d 100644 --- a/src/cpu/intel/haswell/stage_cache.c +++ b/src/cpu/intel/haswell/stage_cache.c @@ -22,5 +22,5 @@ /* The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. * The top of RAM is defined to be the TSEG base address. */ *size = RESERVED_SMM_SIZE; - *base = (void *)((uint32_t)cbmem_top() + RESERVED_SMM_OFFSET); + *base = (void *)(cbmem_top() + RESERVED_SMM_OFFSET); } diff --git a/src/cpu/intel/model_206ax/stage_cache.c b/src/cpu/intel/model_206ax/stage_cache.c index 26dc5e0..4dcd6b4 100644 --- a/src/cpu/intel/model_206ax/stage_cache.c +++ b/src/cpu/intel/model_206ax/stage_cache.c @@ -24,5 +24,5 @@ * The top of RAM is defined to be the TSEG base address. */ *size = RESERVED_SMM_SIZE; - *base = (void *)((uintptr_t)cbmem_top() + RESERVED_SMM_OFFSET); + *base = (void *)(cbmem_top() + RESERVED_SMM_OFFSET); } diff --git a/src/cpu/ti/am335x/cbmem.c b/src/cpu/ti/am335x/cbmem.c index a626ec6..116d82d 100644 --- a/src/cpu/ti/am335x/cbmem.c +++ b/src/cpu/ti/am335x/cbmem.c @@ -15,7 +15,7 @@ #include <cbmem.h> #include <symbols.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return _dram + (CONFIG_DRAM_SIZE_MB << 20); + return (uintptr_t)_dram + (CONFIG_DRAM_SIZE_MB << 20); } diff --git a/src/drivers/amd/agesa/mtrr_fixme.c b/src/drivers/amd/agesa/mtrr_fixme.c index 1fbb553..49db504 100644 --- a/src/drivers/amd/agesa/mtrr_fixme.c +++ b/src/drivers/amd/agesa/mtrr_fixme.c @@ -56,7 +56,7 @@ * writeback possible. */ - uintptr_t top_of_ram = (uintptr_t) cbmem_top(); + uintptr_t top_of_ram = cbmem_top(); top_of_ram = ALIGN_UP(top_of_ram, 4 * MiB); set_range_uc(top_of_ram - 4 * MiB, 4 * MiB); @@ -89,7 +89,7 @@ * speed make them WB after CAR teardown. */ if (s3resume) { - uintptr_t top_of_ram = (uintptr_t) cbmem_top(); + uintptr_t top_of_ram = cbmem_top(); top_of_ram = ALIGN_DOWN(top_of_ram, 4*MiB); postcar_frame_add_mtrr(pcf, top_of_ram - 4*MiB, 4*MiB, diff --git a/src/drivers/intel/fsp1_0/fsp_util.c b/src/drivers/intel/fsp1_0/fsp_util.c index 71f6416..e0dfddb 100644 --- a/src/drivers/intel/fsp1_0/fsp_util.c +++ b/src/drivers/intel/fsp1_0/fsp_util.c @@ -199,7 +199,7 @@ * @param hob_list_ptr pointer to the start of the hob list * @return pointer to the start of the FSP reserved memory or NULL if not found. */ -void *find_fsp_reserved_mem(void *hob_list_ptr) +uintptr_t find_fsp_reserved_mem(void *hob_list_ptr) { EFI_GUID fsp_reserved_guid = FSP_HOB_RESOURCE_OWNER_FSP_GUID; EFI_HOB_RESOURCE_DESCRIPTOR *fsp_reserved_mem = @@ -209,7 +209,7 @@ if (fsp_reserved_mem == NULL) return NULL; - return (void *)((uintptr_t)fsp_reserved_mem->PhysicalStart); + return ((uintptr_t)fsp_reserved_mem->PhysicalStart); } #endif /* FSP_RESERVE_MEMORY_SIZE */ diff --git a/src/drivers/intel/fsp2_0/hob_verify.c b/src/drivers/intel/fsp2_0/hob_verify.c index 317b2c9..a3c878e 100644 --- a/src/drivers/intel/fsp2_0/hob_verify.c +++ b/src/drivers/intel/fsp2_0/hob_verify.c @@ -61,7 +61,7 @@ die("Space between FSP reserved region and BIOS TOLUM!\n"); } - if (range_entry_end(&tolum) != (uintptr_t)cbmem_top()) { + if (range_entry_end(&tolum) != cbmem_top()) { printk(BIOS_CRIT, "TOLUM end: 0x%08llx != 0x%p: cbmem_top\n", range_entry_end(&tolum), cbmem_top()); die("Space between cbmem_top and BIOS TOLUM!\n"); diff --git a/src/include/cbmem.h b/src/include/cbmem.h index ad48e35..e7f04cc 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -74,7 +74,7 @@ * below 4GiB. * x86 boards or chipsets must return NULL before the cbmem backing store has * been initialized. */ -void *cbmem_top(void); +uintptr_t cbmem_top(void); /* Add a cbmem entry of a given size and id. These return NULL on failure. The * add function performs a find first and do not check against the original diff --git a/src/include/imd.h b/src/include/imd.h index 6575312..cd2d297 100644 --- a/src/include/imd.h +++ b/src/include/imd.h @@ -59,7 +59,7 @@ * to be called at least once before any other imd related functions * can be used. */ -void imd_handle_init(struct imd *imd, void *upper_limit); +void imd_handle_init(struct imd *imd, uintptr_t upper_limit); /* * Initialize a handle with a shallow recovery. This function doesn't diff --git a/src/lib/ext_stage_cache.c b/src/lib/ext_stage_cache.c index c3d4aee..f353681 100644 --- a/src/lib/ext_stage_cache.c +++ b/src/lib/ext_stage_cache.c @@ -32,12 +32,12 @@ static void stage_cache_create_empty(void) { struct imd *imd; - void *base; + uintptr_t base; size_t size; imd = imd_get(); stage_cache_external_region(&base, &size); - imd_handle_init(imd, (void *)(size + (uintptr_t)base)); + imd_handle_init(imd, size + base); printk(BIOS_DEBUG, "External stage cache:\n"); imd_create_tiered_empty(imd, 4096, 4096, 1024, 32); @@ -48,12 +48,12 @@ static void stage_cache_recover(void) { struct imd *imd; - void *base; + uintptr_t base; size_t size; imd = imd_get(); stage_cache_external_region(&base, &size); - imd_handle_init(imd, (void *)(size + (uintptr_t)base)); + imd_handle_init(imd, size + base); if (imd_recover(imd)) printk(BIOS_DEBUG, "Unable to recover external stage cache.\n"); } diff --git a/src/lib/imd.c b/src/lib/imd.c index 17ec2d9..143f617 100644 --- a/src/lib/imd.c +++ b/src/lib/imd.c @@ -132,11 +132,10 @@ e->id = id; } -static void imdr_init(struct imdr *ir, void *upper_limit) +static void imdr_init(struct imdr *ir, uintptr_t upper_limit) { - uintptr_t limit = (uintptr_t)upper_limit; /* Upper limit is aligned down to 4KiB */ - ir->limit = ALIGN_DOWN(limit, LIMIT_ALIGN); + ir->limit = ALIGN_DOWN(upper_limit, LIMIT_ALIGN); ir->r = NULL; } @@ -396,10 +395,10 @@ } /* Initialize imd handle. */ -void imd_handle_init(struct imd *imd, void *upper_limit) +void imd_handle_init(struct imd *imd, uintptr_t upper_limit) { imdr_init(&imd->lg, upper_limit); - imdr_init(&imd->sm, NULL); + imdr_init(&imd->sm, 0); } void imd_handle_init_partial_recovery(struct imd *imd) @@ -411,7 +410,7 @@ if (imd->lg.limit == 0) return; - imd_handle_init(imd, (void *)imd->lg.limit); + imd_handle_init(imd, imd->lg.limit); /* Initialize root pointer for the large regions. */ imdr = &imd->lg; @@ -468,7 +467,7 @@ return 0; fail: - imd_handle_init(imd, (void *)imdr->limit); + imd_handle_init(imd, imdr->limit); return -1; } @@ -495,7 +494,7 @@ /* Tear down any changes on failure. */ if (imdr_recover(&imd->sm) != 0) { - imd_handle_init(imd, (void *)imd->lg.limit); + imd_handle_init(imd, imd->lg.limit); return -1; } diff --git a/src/mainboard/emulation/qemu-armv7/cbmem.c b/src/mainboard/emulation/qemu-armv7/cbmem.c index f26ca6c..6c3ac57 100644 --- a/src/mainboard/emulation/qemu-armv7/cbmem.c +++ b/src/mainboard/emulation/qemu-armv7/cbmem.c @@ -59,7 +59,7 @@ return discovered; } -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return _dram + (probe_ramsize() << 20); + return (uintptr_t)_dram + (probe_ramsize() << 20); } diff --git a/src/mainboard/emulation/qemu-i440fx/memory.c b/src/mainboard/emulation/qemu-i440fx/memory.c index dea96f2..973eecd 100644 --- a/src/mainboard/emulation/qemu-i440fx/memory.c +++ b/src/mainboard/emulation/qemu-i440fx/memory.c @@ -50,7 +50,7 @@ return tomk; } -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return (void *) (qemu_get_memory_size() * 1024); + return qemu_get_memory_size() * 1024; } diff --git a/src/mainboard/emulation/qemu-power8/cbmem.c b/src/mainboard/emulation/qemu-power8/cbmem.c index 3df6b80..4391cdb 100644 --- a/src/mainboard/emulation/qemu-power8/cbmem.c +++ b/src/mainboard/emulation/qemu-power8/cbmem.c @@ -15,10 +15,9 @@ #include <cbmem.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { /* Top of cbmem is at lowest usable DRAM address below 4GiB. */ /* For now, last 1M of 4G */ - void *ptr = (void *) ((1ULL << 32) - 1048576); - return ptr; + return (1ULL << 32) - 1048576; } diff --git a/src/northbridge/intel/e7505/memmap.c b/src/northbridge/intel/e7505/memmap.c index 1b86012..f16cf9a 100644 --- a/src/northbridge/intel/e7505/memmap.c +++ b/src/northbridge/intel/e7505/memmap.c @@ -23,7 +23,7 @@ #include <program_loading.h> #include "e7505.h" -void *cbmem_top(void) +uintptr_t cbmem_top(void) { pci_devfn_t mch = PCI_DEV(0, 0, 0); uintptr_t tolm; @@ -32,7 +32,7 @@ tolm = pci_read_config16(mch, TOLM) >> 11; tolm <<= 27; - return (void *)tolm; + return tolm; } #define ROMSTAGE_RAM_STACK_SIZE 0x5000 @@ -59,7 +59,7 @@ postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); /* Cache CBMEM region as WB. */ - top_of_ram = (uintptr_t)cbmem_top(); + top_of_ram = cbmem_top(); postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); diff --git a/src/northbridge/intel/fsp_rangeley/raminit.c b/src/northbridge/intel/fsp_rangeley/raminit.c index 675a6f4..771d331 100644 --- a/src/northbridge/intel/fsp_rangeley/raminit.c +++ b/src/northbridge/intel/fsp_rangeley/raminit.c @@ -37,7 +37,7 @@ return tom; } -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return (void *) (smm_region_start() - FSP_RESERVE_MEMORY_SIZE); + return smm_region_start() - FSP_RESERVE_MEMORY_SIZE; } diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c index af1a46d..1bb2031 100644 --- a/src/northbridge/intel/gm45/ram_calc.c +++ b/src/northbridge/intel/gm45/ram_calc.c @@ -117,10 +117,10 @@ * 1 MiB alignment. As this may cause very greedy MTRR setup, push * CBMEM top downwards to 4 MiB boundary. */ -void *cbmem_top(void) +uintptr_t cbmem_top(void) { uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); - return (void *) top_of_ram; + return top_of_ram; } #define ROMSTAGE_RAM_STACK_SIZE 0x5000 @@ -145,7 +145,7 @@ /* Cache 8 MiB region below the top of ram and 2 MiB above top of * ram to cover both cbmem as the TSEG region. */ - top_of_ram = (uintptr_t)cbmem_top(); + top_of_ram = cbmem_top(); postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); postcar_frame_add_mtrr(&pcf, northbridge_get_tseg_base(), diff --git a/src/northbridge/intel/haswell/ram_calc.c b/src/northbridge/intel/haswell/ram_calc.c index d3e88f2..2c8217e 100644 --- a/src/northbridge/intel/haswell/ram_calc.c +++ b/src/northbridge/intel/haswell/ram_calc.c @@ -30,7 +30,7 @@ return tom & ~((1 << 20) - 1); } -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return (void *)smm_region_start(); + return smm_region_start(); } diff --git a/src/northbridge/intel/i440bx/ram_calc.c b/src/northbridge/intel/i440bx/ram_calc.c index 3362d93..1c09857 100644 --- a/src/northbridge/intel/i440bx/ram_calc.c +++ b/src/northbridge/intel/i440bx/ram_calc.c @@ -24,7 +24,7 @@ #include <program_loading.h> #include "i440bx.h" -void *cbmem_top(void) +uintptr_t cbmem_top(void) { /* Base of TSEG is top of usable DRAM */ /* @@ -64,7 +64,7 @@ int tseg_size = 128 * KiB * (1 << (tseg >> 1)); tom -= tseg_size; } - return (void *)tom; + return tom; } #define ROMSTAGE_RAM_STACK_SIZE 0x5000 @@ -88,7 +88,7 @@ postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); /* Cache CBMEM region as WB. */ - top_of_ram = (uintptr_t)cbmem_top(); + top_of_ram = cbmem_top(); postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); diff --git a/src/northbridge/intel/i945/ram_calc.c b/src/northbridge/intel/i945/ram_calc.c index fd37aea..b58b3c6 100644 --- a/src/northbridge/intel/i945/ram_calc.c +++ b/src/northbridge/intel/i945/ram_calc.c @@ -70,10 +70,10 @@ * 1 MiB alignment. As this may cause very greedy MTRR setup, push * CBMEM top downwards to 4 MiB boundary. */ -void *cbmem_top(void) +uintptr_t cbmem_top(void) { uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); - return (void *) top_of_ram; + return top_of_ram; } /** Decodes used Graphics Mode Select (GMS) to kilobytes. */ @@ -110,7 +110,7 @@ /* Cache 8 MiB region below the top of ram and 2 MiB above top of * ram to cover both cbmem as the TSEG region. */ - top_of_ram = (uintptr_t)cbmem_top(); + top_of_ram = cbmem_top(); postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); postcar_frame_add_mtrr(&pcf, northbridge_get_tseg_base(), diff --git a/src/northbridge/intel/nehalem/ram_calc.c b/src/northbridge/intel/nehalem/ram_calc.c index baf087e..d80ba07 100644 --- a/src/northbridge/intel/nehalem/ram_calc.c +++ b/src/northbridge/intel/nehalem/ram_calc.c @@ -32,9 +32,9 @@ return tom; } -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return (void *) smm_region_start(); + return smm_region_start(); } #define ROMSTAGE_RAM_STACK_SIZE 0x5000 @@ -60,7 +60,7 @@ * above top of the ram. This satisfies MTRR alignment requirement * with different TSEG size configurations. */ - top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); + top_of_ram = ALIGN_DOWN(cbmem_top(), 8*MiB); postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); postcar_frame_add_mtrr(&pcf, top_of_ram, 8*MiB, MTRR_TYPE_WRBACK); diff --git a/src/northbridge/intel/pineview/ram_calc.c b/src/northbridge/intel/pineview/ram_calc.c index 21b926b..bfdfd60 100644 --- a/src/northbridge/intel/pineview/ram_calc.c +++ b/src/northbridge/intel/pineview/ram_calc.c @@ -130,10 +130,10 @@ * 1 MiB alignment. As this may cause very greedy MTRR setup, push * CBMEM top downwards to 4 MiB boundary. */ -void *cbmem_top(void) +uintptr_t cbmem_top(void) { uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); - return (void *) top_of_ram; + return top_of_ram; } @@ -159,7 +159,7 @@ /* Cache 8 MiB region below the top of ram and 2 MiB above top of * ram to cover both cbmem as the TSEG region. */ - top_of_ram = (uintptr_t)cbmem_top(); + top_of_ram = cbmem_top(); postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); postcar_frame_add_mtrr(&pcf, northbridge_get_tseg_base(), diff --git a/src/northbridge/intel/sandybridge/ram_calc.c b/src/northbridge/intel/sandybridge/ram_calc.c index 00e3e78..4fc4407 100644 --- a/src/northbridge/intel/sandybridge/ram_calc.c +++ b/src/northbridge/intel/sandybridge/ram_calc.c @@ -38,9 +38,9 @@ return tom; } -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return (void *) smm_region_start(); + return smm_region_start(); } #define ROMSTAGE_RAM_STACK_SIZE 0x5000 @@ -62,7 +62,7 @@ /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); - top_of_ram = (uintptr_t)cbmem_top(); + top_of_ram = cbmem_top(); /* Cache 8MiB below the top of ram. On sandybridge systems the top of * ram under 4GiB is the start of the TSEG region. It is required to * be 8MiB aligned. Set this area as cacheable so it can be used later diff --git a/src/northbridge/intel/x4x/ram_calc.c b/src/northbridge/intel/x4x/ram_calc.c index 6484326..6537427 100644 --- a/src/northbridge/intel/x4x/ram_calc.c +++ b/src/northbridge/intel/x4x/ram_calc.c @@ -128,10 +128,10 @@ * 1 MiB alignment. As this may cause very greedy MTRR setup, push * CBMEM top downwards to 4 MiB boundary. */ -void *cbmem_top(void) +uintptr_t cbmem_top(void) { uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); - return (void *) top_of_ram; + return top_of_ram; } #define ROMSTAGE_RAM_STACK_SIZE 0x5000 @@ -156,7 +156,7 @@ /* Cache 8 MiB region below the top of ram and 2 MiB above top of * ram to cover both cbmem as the TSEG region. */ - top_of_ram = (uintptr_t)cbmem_top(); + top_of_ram = cbmem_top(); postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); postcar_frame_add_mtrr(&pcf, northbridge_get_tseg_base(), diff --git a/src/northbridge/via/vx900/memmap.c b/src/northbridge/via/vx900/memmap.c index 8cc7607..e255265 100644 --- a/src/northbridge/via/vx900/memmap.c +++ b/src/northbridge/via/vx900/memmap.c @@ -113,7 +113,7 @@ return (pci_read_config16(MCU, 0x84) & 0xfff0) >> 4; } -void *cbmem_top(void) +uintptr_t cbmem_top(void) { uintptr_t tolm; uintptr_t fb_size; @@ -122,7 +122,7 @@ fb_size = vx900_get_chrome9hd_fb_size (); if (tolm > 0xfc0 || tolm <= 0x3ff || fb_size == 0x0) - return NULL; + return 0; - return (void *)((tolm - fb_size) << 20); + return ((tolm - fb_size) << 20); } diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 4a856a9..8172a76 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -398,7 +398,7 @@ { uint64_t uma_base = get_uma_base(); uint32_t uma_size = get_uma_size(); - uint32_t mem_useable = (uintptr_t)cbmem_top(); + uint32_t mem_useable = cbmem_top(); msr_t tom = rdmsr(TOP_MEM); msr_t high_tom = rdmsr(TOP_MEM2); uint64_t high_mem_useable; diff --git a/src/soc/amd/stoneyridge/ramtop.c b/src/soc/amd/stoneyridge/ramtop.c index 15968ab..4302811 100644 --- a/src/soc/amd/stoneyridge/ramtop.c +++ b/src/soc/amd/stoneyridge/ramtop.c @@ -57,7 +57,7 @@ *size = BERT_REGION_MAX_SIZE; } -void *cbmem_top(void) +uintptr_t cbmem_top(void) { msr_t tom = rdmsr(TOP_MEM); @@ -65,14 +65,14 @@ return 0; /* 8MB alignment to keep MTRR usage low */ - return (void *)ALIGN_DOWN(restore_top_of_low_cacheable() + return ALIGN_DOWN(restore_top_of_low_cacheable() - CONFIG_SMM_TSEG_SIZE - BERT_REGION_MAX_SIZE, 8*MiB); } static uintptr_t smm_region_start(void) { - return (uintptr_t)cbmem_top() + BERT_REGION_MAX_SIZE; + return cbmem_top() + BERT_REGION_MAX_SIZE; } static size_t smm_region_size(void) diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 9f8aed8..35a9ba9 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -160,7 +160,7 @@ * location of ramstage in cbmem is not known. Instruct postcar to cache * 16 megs under cbmem top which is a safe bet to cover ramstage. */ - top_of_ram = (uintptr_t) cbmem_top(); + top_of_ram = cbmem_top(); postcar_frame_add_mtrr(&pcf, top_of_ram - 16*MiB, 16*MiB, MTRR_TYPE_WRBACK); diff --git a/src/soc/cavium/cn81xx/cbmem.c b/src/soc/cavium/cn81xx/cbmem.c index 397fd26..a44ad5c 100644 --- a/src/soc/cavium/cn81xx/cbmem.c +++ b/src/soc/cavium/cn81xx/cbmem.c @@ -19,9 +19,9 @@ #include <stdlib.h> #include <symbols.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { /* Make sure not to overlap with reserved ATF scratchpad */ - return (void *)min((uintptr_t)_dram + (sdram_size_mb() - 1) * MiB, + return min((uintptr_t)_dram + (sdram_size_mb() - 1) * MiB, 4ULL * GiB); } diff --git a/src/soc/imgtec/pistachio/cbmem.c b/src/soc/imgtec/pistachio/cbmem.c index 112df7c..af76722 100644 --- a/src/soc/imgtec/pistachio/cbmem.c +++ b/src/soc/imgtec/pistachio/cbmem.c @@ -18,7 +18,7 @@ #include <stdlib.h> #include <symbols.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return _dram + (CONFIG_DRAM_SIZE_MB << 20); + return (uintptr_t)_dram + (CONFIG_DRAM_SIZE_MB << 20); } diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c index be15e16..4f7a9e8 100644 --- a/src/soc/intel/apollolake/memmap.c +++ b/src/soc/intel/apollolake/memmap.c @@ -25,11 +25,11 @@ #include <soc/systemagent.h> #include <soc/pci_devs.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { const struct device *dev; const config_t *config; - void *tolum = (void *)sa_get_tseg_base(); + uintptr_t tolum = sa_get_tseg_base(); if (!IS_ENABLED(CONFIG_SOC_INTEL_GLK)) return tolum; diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 4f4f9f5..9db1c99 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -252,7 +252,7 @@ * location of ramstage in cbmem is not known. Instruct postcar to cache * 16 megs under cbmem top which is a safe bet to cover ramstage. */ - top_of_ram = (uintptr_t) cbmem_top(); + top_of_ram = cbmem_top(); /* cbmem_top() needs to be at least 16 MiB aligned */ assert(ALIGN_DOWN(top_of_ram, 16*MiB) == top_of_ram); postcar_frame_add_mtrr(&pcf, top_of_ram - 16*MiB, 16*MiB, diff --git a/src/soc/intel/baytrail/memmap.c b/src/soc/intel/baytrail/memmap.c index f1131f6..7d3a98b 100644 --- a/src/soc/intel/baytrail/memmap.c +++ b/src/soc/intel/baytrail/memmap.c @@ -23,7 +23,7 @@ return (iosf_bunit_read(BUNIT_SMRRL) << 20); } -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return (void *) smm_region_start(); + return smm_region_start(); } diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index a52d3b1..6596fdf 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -252,7 +252,7 @@ * above top of the ram. This satisfies MTRR alignment requirement * with different TSEG size configurations. */ - top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); + top_of_ram = ALIGN_DOWN(cbmem_top(), 8*MiB); postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 16*MiB, MTRR_TYPE_WRBACK); diff --git a/src/soc/intel/braswell/memmap.c b/src/soc/intel/braswell/memmap.c index d7c9952..03371b5 100644 --- a/src/soc/intel/braswell/memmap.c +++ b/src/soc/intel/braswell/memmap.c @@ -81,7 +81,7 @@ return 0; } -void *cbmem_top(void) +uintptr_t cbmem_top(void) { char *smm_base; size_t smm_size; @@ -115,5 +115,5 @@ */ smm_region((void **)&smm_base, &smm_size); - return (void *)smm_base; + return smm_base; } diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c index 175c20c..3166627 100644 --- a/src/soc/intel/broadwell/memmap.c +++ b/src/soc/intel/broadwell/memmap.c @@ -36,7 +36,7 @@ return tom; } -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return (void *) dpr_region_start(); + return dpr_region_start(); } diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index afc8216..bd3cdc4 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -56,7 +56,7 @@ * above top of the ram. This satisfies MTRR alignment requirement * with different TSEG size configurations. */ - top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); + top_of_ram = ALIGN_DOWN(cbmem_top(), 8*MiB); postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 16*MiB, MTRR_TYPE_WRBACK); diff --git a/src/soc/intel/cannonlake/cbmem.c b/src/soc/intel/cannonlake/cbmem.c deleted file mode 100644 index 300556a..0000000 --- a/src/soc/intel/cannonlake/cbmem.c +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2017 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <cbmem.h> - -void *cbmem_top(void) -{ - /* not implemented yet */ - return (void *) NULL; -} diff --git a/src/soc/intel/cannonlake/memmap.c b/src/soc/intel/cannonlake/memmap.c index 64e07be..c2caa93 100644 --- a/src/soc/intel/cannonlake/memmap.c +++ b/src/soc/intel/cannonlake/memmap.c @@ -294,7 +294,7 @@ * | | * +-------------------------+ */ -void *cbmem_top(void) +uintptr_t cbmem_top(void) { struct ebda_config ebda_cfg; @@ -309,5 +309,5 @@ retrieve_ebda_object(&ebda_cfg); - return (void *)(uintptr_t)ebda_cfg.tolum_base; + return (uintptr_t)ebda_cfg.tolum_base; } diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index 246e0ea..33bc256 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -136,7 +136,7 @@ * Instruct postcar to cache 16 megs under cbmem top which is * a safe bet to cover ramstage. */ - top_of_ram = (uintptr_t) cbmem_top(); + top_of_ram = cbmem_top(); printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); top_of_ram -= 16*MiB; postcar_frame_add_mtrr(&pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 9608359..0d55357 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -157,7 +157,7 @@ /* Get SoC reserve memory size as per user selection */ reserved_mmio_size = soc_reserved_mmio_size(); - top_of_ram = (uintptr_t)cbmem_top(); + top_of_ram = cbmem_top(); /* 0 - > 0xa0000 */ base_k = 0; diff --git a/src/soc/intel/denverton_ns/memmap.c b/src/soc/intel/denverton_ns/memmap.c index a42d861..6c38f30 100644 --- a/src/soc/intel/denverton_ns/memmap.c +++ b/src/soc/intel/denverton_ns/memmap.c @@ -59,7 +59,10 @@ power_of_2(iqat_region_size + tseg_region_size); } -void *cbmem_top(void) { return (void *)top_of_32bit_ram(); } +uintptr_t cbmem_top(void) +{ + return top_of_32bit_ram(); +} static inline uintptr_t smm_region_start(void) { diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c index 34fd7bb..f19505e 100644 --- a/src/soc/intel/denverton_ns/romstage.c +++ b/src/soc/intel/denverton_ns/romstage.c @@ -166,7 +166,7 @@ * location of ramstage in cbmem is not known. Instruct postcar to cache * 16 megs under cbmem top which is a safe bet to cover ramstage. */ - top_of_ram = (uintptr_t)cbmem_top(); + top_of_ram = cbmem_top(); postcar_frame_add_mtrr(&pcf, top_of_ram - 16 * MiB, 16 * MiB, MTRR_TYPE_WRBACK); diff --git a/src/soc/intel/fsp_baytrail/memmap.c b/src/soc/intel/fsp_baytrail/memmap.c index 1886c6f..ff9ce5d 100644 --- a/src/soc/intel/fsp_baytrail/memmap.c +++ b/src/soc/intel/fsp_baytrail/memmap.c @@ -35,7 +35,7 @@ * @return pointer to the first byte of reserved memory */ -void *cbmem_top(void) +uintptr_t cbmem_top(void) { return find_fsp_reserved_mem(*(void **)CBMEM_FSP_HOB_PTR); } diff --git a/src/soc/intel/fsp_broadwell_de/memmap.c b/src/soc/intel/fsp_broadwell_de/memmap.c index 7510094..8ec6d99 100644 --- a/src/soc/intel/fsp_broadwell_de/memmap.c +++ b/src/soc/intel/fsp_broadwell_de/memmap.c @@ -17,7 +17,7 @@ #include <cbmem.h> #include <drivers/intel/fsp1_0/fsp_util.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { return find_fsp_reserved_mem(*(void **)CBMEM_FSP_HOB_PTR); } diff --git a/src/soc/intel/icelake/cbmem.c b/src/soc/intel/icelake/cbmem.c deleted file mode 100644 index 4f44777..0000000 --- a/src/soc/intel/icelake/cbmem.c +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <cbmem.h> - -void *cbmem_top(void) -{ - /* not implemented yet */ - return (void *) NULL; -} diff --git a/src/soc/intel/icelake/memmap.c b/src/soc/intel/icelake/memmap.c index 027b8b0..8e1d4d6 100644 --- a/src/soc/intel/icelake/memmap.c +++ b/src/soc/intel/icelake/memmap.c @@ -293,7 +293,7 @@ * | | * +-------------------------+ */ -void *cbmem_top(void) +uintptr_t cbmem_top(void) { struct ebda_config ebda_cfg; @@ -308,5 +308,5 @@ retrieve_ebda_object(&ebda_cfg); - return (void *)(uintptr_t)ebda_cfg.tolum_base; + return ebda_cfg.tolum_base; } diff --git a/src/soc/intel/icelake/romstage/romstage.c b/src/soc/intel/icelake/romstage/romstage.c index 432cae5..9968b3d 100644 --- a/src/soc/intel/icelake/romstage/romstage.c +++ b/src/soc/intel/icelake/romstage/romstage.c @@ -136,7 +136,7 @@ * Instruct postcar to cache 16 megs under cbmem top which is * a safe bet to cover ramstage. */ - top_of_ram = (uintptr_t) cbmem_top(); + top_of_ram = cbmem_top(); printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); top_of_ram -= 16*MiB; postcar_frame_add_mtrr(&pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); diff --git a/src/soc/intel/quark/memmap.c b/src/soc/intel/quark/memmap.c index d67856c..9a2706d 100644 --- a/src/soc/intel/quark/memmap.c +++ b/src/soc/intel/quark/memmap.c @@ -16,7 +16,7 @@ #include <cbmem.h> #include <soc/reg_access.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { uint32_t top_of_memory; @@ -30,5 +30,5 @@ top_of_memory -= 0x10000; /* Return the top of memory */ - return (void *)top_of_memory; + return top_of_memory; } diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c index 23051bd..52962be 100644 --- a/src/soc/intel/quark/romstage/fsp2_0.c +++ b/src/soc/intel/quark/romstage/fsp2_0.c @@ -65,7 +65,7 @@ die("Unable to initialize postcar frame.\n"); /* Locate the top of RAM */ - top_of_low_usable_memory = (uintptr_t) cbmem_top(); + top_of_low_usable_memory = cbmem_top(); top_of_ram = ALIGN(top_of_low_usable_memory, 16 * MiB); /* Cache postcar and ramstage */ diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c index f0ccb1d..e464bdc 100644 --- a/src/soc/intel/skylake/memmap.c +++ b/src/soc/intel/skylake/memmap.c @@ -335,7 +335,7 @@ * | | * +-------------------------+ */ -void *cbmem_top(void) +uintptr_t cbmem_top(void) { struct ebda_config ebda_cfg; @@ -350,5 +350,5 @@ retrieve_ebda_object(&ebda_cfg); - return (void *)(uintptr_t)ebda_cfg.tolum_base; + return ebda_cfg.tolum_base; } diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index 2a60158..5030eb8 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -161,7 +161,7 @@ * Instruct postcar to cache 16 megs under cbmem top which is * a safe bet to cover ramstage. */ - top_of_ram = (uintptr_t) cbmem_top(); + top_of_ram = cbmem_top(); printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); top_of_ram -= 16*MiB; postcar_frame_add_mtrr(&pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); diff --git a/src/soc/mediatek/common/cbmem.c b/src/soc/mediatek/common/cbmem.c index 8906565..7d0aad6 100644 --- a/src/soc/mediatek/common/cbmem.c +++ b/src/soc/mediatek/common/cbmem.c @@ -21,7 +21,7 @@ #define MAX_DRAM_ADDRESS ((uintptr_t)4 * GiB) -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return (void *)min((uintptr_t)_dram + sdram_size(), MAX_DRAM_ADDRESS); + return min((uintptr_t)_dram + sdram_size(), MAX_DRAM_ADDRESS); } diff --git a/src/soc/nvidia/tegra124/cbmem.c b/src/soc/nvidia/tegra124/cbmem.c index 4b52a51..d11816a 100644 --- a/src/soc/nvidia/tegra124/cbmem.c +++ b/src/soc/nvidia/tegra124/cbmem.c @@ -17,7 +17,7 @@ #include <soc/display.h> #include <soc/sdram.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return (void *)((sdram_max_addressable_mb() - FB_SIZE_MB) << 20UL); + return ((sdram_max_addressable_mb() - FB_SIZE_MB) << 20UL); } diff --git a/src/soc/nvidia/tegra210/cbmem.c b/src/soc/nvidia/tegra210/cbmem.c index 63ae497..21f8819 100644 --- a/src/soc/nvidia/tegra210/cbmem.c +++ b/src/soc/nvidia/tegra210/cbmem.c @@ -16,7 +16,7 @@ #include <cbmem.h> #include <soc/addressmap.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { static uintptr_t addr; @@ -32,5 +32,5 @@ addr = end_mib << 20; } - return (void *)addr; + return addr; } diff --git a/src/soc/qualcomm/ipq40xx/cbmem.c b/src/soc/qualcomm/ipq40xx/cbmem.c index 05325cc..db859e8 100644 --- a/src/soc/qualcomm/ipq40xx/cbmem.c +++ b/src/soc/qualcomm/ipq40xx/cbmem.c @@ -23,7 +23,7 @@ cbmem_backing_store_ready = 1; } -void *cbmem_top(void) +uintptr_t cbmem_top(void) { /* * In romstage, make sure that cbmem backing store is ready before @@ -34,5 +34,5 @@ if (ENV_ROMSTAGE && (cbmem_backing_store_ready == 0)) return NULL; - return _memlayout_cbmem_top; + return (uintptr_t)_memlayout_cbmem_top; } diff --git a/src/soc/qualcomm/ipq806x/cbmem.c b/src/soc/qualcomm/ipq806x/cbmem.c index 9674db6..d86b113 100644 --- a/src/soc/qualcomm/ipq806x/cbmem.c +++ b/src/soc/qualcomm/ipq806x/cbmem.c @@ -23,7 +23,7 @@ cbmem_backing_store_ready = 1; } -void *cbmem_top(void) +uintptr_t cbmem_top(void) { /* * In romstage, make sure that cbmem backing store is ready before @@ -35,5 +35,5 @@ if (ENV_ROMSTAGE && (cbmem_backing_store_ready == 0)) return NULL; - return _memlayout_cbmem_top; + return (uintptr_t)_memlayout_cbmem_top; } diff --git a/src/soc/qualcomm/sdm845/cbmem.c b/src/soc/qualcomm/sdm845/cbmem.c index 3b9ad4a..5897f18 100644 --- a/src/soc/qualcomm/sdm845/cbmem.c +++ b/src/soc/qualcomm/sdm845/cbmem.c @@ -15,7 +15,7 @@ #include <cbmem.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return (void *)((uintptr_t)4 * GiB); + return ((uintptr_t)4 * GiB); } diff --git a/src/soc/rockchip/common/cbmem.c b/src/soc/rockchip/common/cbmem.c index 401f8b2..105e178 100644 --- a/src/soc/rockchip/common/cbmem.c +++ b/src/soc/rockchip/common/cbmem.c @@ -19,8 +19,8 @@ #include <stdlib.h> #include <symbols.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return (void *)min((uintptr_t)_dram + sdram_size_mb() * MiB, + return min((uintptr_t)_dram + sdram_size_mb() * MiB, MAX_DRAM_ADDRESS); } diff --git a/src/soc/samsung/exynos5250/cbmem.c b/src/soc/samsung/exynos5250/cbmem.c index 1874495..dc02577 100644 --- a/src/soc/samsung/exynos5250/cbmem.c +++ b/src/soc/samsung/exynos5250/cbmem.c @@ -17,7 +17,7 @@ #include <cbmem.h> #include <soc/cpu.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return (void *)(get_fb_base_kb() * KiB); + return get_fb_base_kb() * KiB; } diff --git a/src/soc/samsung/exynos5420/cbmem.c b/src/soc/samsung/exynos5420/cbmem.c index e1999e8..4606c19 100644 --- a/src/soc/samsung/exynos5420/cbmem.c +++ b/src/soc/samsung/exynos5420/cbmem.c @@ -17,7 +17,7 @@ #include <soc/cpu.h> #include <stddef.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return (void *)(get_fb_base_kb() * KiB); + return (get_fb_base_kb() * KiB); } diff --git a/src/soc/sifive/fu540/cbmem.c b/src/soc/sifive/fu540/cbmem.c index 1c68de8..523e62c 100644 --- a/src/soc/sifive/fu540/cbmem.c +++ b/src/soc/sifive/fu540/cbmem.c @@ -19,8 +19,8 @@ #include <stdlib.h> #include <symbols.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return (void *)min((uintptr_t)_dram + sdram_size_mb() * MiB, + return min((uintptr_t)_dram + sdram_size_mb() * MiB, FU540_MAXDRAM); } diff --git a/src/soc/ucb/riscv/cbmem.c b/src/soc/ucb/riscv/cbmem.c index 2ee400a..7e0c4d5 100644 --- a/src/soc/ucb/riscv/cbmem.c +++ b/src/soc/ucb/riscv/cbmem.c @@ -13,7 +13,7 @@ #include <cbmem.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { uintptr_t base; size_t size; @@ -23,5 +23,5 @@ base = 0x80000000; size = 128 * MiB; - return (void *)(base + size); + return (base + size); } -- To view, visit https://review.coreboot.org/c/coreboot/+/30693 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iecec1cffba9dba02d06b10fe88aec173dbc08093 Gerrit-Change-Number: 30693 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

2 1

Change in ...coreboot[master]: mb/google/sarien/variants: Add DPTF based charge control
by Sumeet R Pawnikar (Code Review) 10 Jun '23

10 Jun '23

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30723 Change subject: mb/google/sarien/variants: Add DPTF based charge control ...................................................................... mb/google/sarien/variants: Add DPTF based charge control Add DPTF based input chargning current throttling based on temperature. BRANCH=None BUG=b:122483425 TEST=Built for sarien Change-Id: If01fea731926ec29ca5a0595b875acce9b1f5a2f Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl M src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl 2 files changed, 18 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/30723/1 diff --git a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl index 2d35878..8f8cde5 100644 --- a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl @@ -27,7 +27,15 @@ #define DPTF_TSR1_CRITICAL 80 #undef DPTF_ENABLE_FAN_CONTROL -#undef DPTF_ENABLE_CHARGER +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ +}) Name (DTRT, Package () { /* CPU Throttle Effect on CPU */ diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl index 2d35878..8f8cde5 100644 --- a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl @@ -27,7 +27,15 @@ #define DPTF_TSR1_CRITICAL 80 #undef DPTF_ENABLE_FAN_CONTROL -#undef DPTF_ENABLE_CHARGER +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ +}) Name (DTRT, Package () { /* CPU Throttle Effect on CPU */ -- To view, visit https://review.coreboot.org/c/coreboot/+/30723 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If01fea731926ec29ca5a0595b875acce9b1f5a2f Gerrit-Change-Number: 30723 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newchange

2 1

Change in ...coreboot[master]: [RFC] src/device/smbus: add extended addressing functions
by Michał Żygowski (Code Review) 10 Jun '23

10 Jun '23

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30757 Change subject: [RFC] src/device/smbus: add extended addressing functions ...................................................................... [RFC] src/device/smbus: add extended addressing functions Found this on one of private repositories I have access to. Do not have any use case for it yet. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I5dcfc6bf33ef7baaa619f84b2ce0ab8e179a44b3 --- M src/device/smbus_ops.c M src/include/device/smbus.h M src/include/device/smbus_def.h 3 files changed, 64 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/30757/1 diff --git a/src/device/smbus_ops.c b/src/device/smbus_ops.c index c91f415..26cd956 100644 --- a/src/device/smbus_ops.c +++ b/src/device/smbus_ops.c @@ -90,3 +90,20 @@ return ops_smbus_bus(get_pbus_smbus(dev))->block_write(dev, cmd, bytes, buffer); } + +int smbus_extended_read_byte(struct device *dev, u16 addr) +{ + CHECK_PRESENCE(extended_read_byte); + + return ops_smbus_bus(get_pbus_smbus(dev))->extended_read_byte(dev, + addr); +} + +int smbus_extended_write_byte(struct device *dev, u16 addr, u8 val) +{ + CHECK_PRESENCE(extended_write_byte); + + return ops_smbus_bus(get_pbus_smbus(dev))->extended_write_byte(dev, + addr, + val); +} \ No newline at end of file diff --git a/src/include/device/smbus.h b/src/include/device/smbus.h index de6cf40..cb3f826 100644 --- a/src/include/device/smbus.h +++ b/src/include/device/smbus.h @@ -1,3 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + #ifndef DEVICE_SMBUS_H #define DEVICE_SMBUS_H @@ -15,6 +34,8 @@ int (*block_read)(struct device *dev, u8 cmd, u8 bytes, u8 *buffer); int (*block_write)(struct device *dev, u8 cmd, u8 bytes, const u8 *buffer); + int (*extended_read_byte)(struct device *dev, u16 addr); + int (*extended_write_byte)(struct device *dev, u16 addr, u8 value); }; static inline const struct smbus_bus_operations *ops_smbus_bus(struct bus *bus) @@ -54,6 +75,10 @@ int smbus_block_read(struct device *dev, u8 cmd, u8 bytes, u8 *buffer); int smbus_block_write(struct device *dev, u8 cmd, u8 bytes, const u8 *buffer); +int smbus_extended_read_byte(struct device *dev, u16 addr); +int smbus_extended_write_byte(struct device *dev, u16 addr, u8 val); + + #if IS_ENABLED(CONFIG_SMBUS_HAS_AUX_CHANNELS) void smbus_switch_to_channel(uint8_t channel_number); uint8_t smbus_get_current_channel(void); diff --git a/src/include/device/smbus_def.h b/src/include/device/smbus_def.h index 61d7861..cac08cc 100644 --- a/src/include/device/smbus_def.h +++ b/src/include/device/smbus_def.h @@ -1,10 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + + #ifndef DEVICE_SMBUS_DEF_H #define DEVICE_SMBUS_DEF_H #include <types.h> /* Error results are negative success is >= 0 */ -#define SMBUS_ERROR CB_ERR +#define SMBUS_SUCCESS CB_SUCCESS +#define SMBUS_ERROR CB_ERR #define SMBUS_WAIT_UNTIL_READY_TIMEOUT CB_I2C_BUSY #define SMBUS_WAIT_UNTIL_DONE_TIMEOUT CB_I2C_TIMEOUT #define SMBUS_WAIT_UNTIL_ACTIVE_TIMEOUT CB_I2C_NO_DEVICE -- To view, visit https://review.coreboot.org/c/coreboot/+/30757 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5dcfc6bf33ef7baaa619f84b2ce0ab8e179a44b3 Gerrit-Change-Number: 30757 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

2 1

Change in ...coreboot[master]: [RFC] src/soc/intel/fsp_baytrail/smbus: extended addressing support f...
by Michał Żygowski (Code Review) 10 Jun '23

10 Jun '23

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30758 Change subject: [RFC] src/soc/intel/fsp_baytrail/smbus: extended addressing support for BayTrail ...................................................................... [RFC] src/soc/intel/fsp_baytrail/smbus: extended addressing support for BayTrail Found it on one of private repositories I have access to. Do not have any use case for it for now. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I39178776ef8ccae785ec5f6edb2824929cd103e9 --- A src/soc/intel/fsp_baytrail/include/soc/smbus.h A src/soc/intel/fsp_baytrail/smbus.c A src/soc/intel/fsp_baytrail/smbus_access.c 3 files changed, 956 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/30758/1 diff --git a/src/soc/intel/fsp_baytrail/include/soc/smbus.h b/src/soc/intel/fsp_baytrail/include/soc/smbus.h new file mode 100644 index 0000000..c97423e --- /dev/null +++ b/src/soc/intel/fsp_baytrail/include/soc/smbus.h @@ -0,0 +1,145 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + + +#define FULL_RW 0x48 +#define QUICK_RW 0x44 +#define IGNORED_BYTE 0x00 +#define READ_BIT 0x01 +#define ADDRESS_16_BIT 0x10000000ul + +#define SMBUS_IO_ROUTINES 0x01 +#define SMB_IO_BASE 0x20 +#define I2C_MEM_BASE 0x10 +#define HOSTCFG 0x40 + +/* HOSTCFG bits */ +#define HST_EN (1 << 0) +#define SMB_SMI_EN (1 << 1) +#define I2C_EN (1 << 2) +#define SSRT (1 << 3) +#define SPD_WD (1 << 4) + +/* SMBus I/O bits. */ +#define SMBHSTSTAT 0x0 +#define SMBHSTCTL 0x2 +#define SMBHSTCMD 0x3 +#define SMBXMITADD 0x4 +#define SMBHSTDAT0 0x5 +#define SMBHSTDAT1 0x6 +#define SMBBLKDAT 0x7 +#define SMBTRNSADD 0x9 +#define SMBSLVDATA 0xa +#define SMLINK_PIN_CTL 0xe +#define SMBUS_PIN_CTL 0xf + +#define SMBUS_TIMEOUT (10 * 1000 * 100) + +#define HSTSTS_HOST_BUSY (1 << 0) +#define HSTSTS_INTR (1 << 1) +#define HSTSTS_DEV_ERR (1 << 2) +#define HSTSTS_BUS_ERR (1 << 3) +#define HSTSTS_FAILED (1 << 4) +#define HSTSTS_SMBALERT_STS (1 << 5) +#define HSTSTS_INUSE_STS (1 << 6) +#define HSTSTS_BYTE_DONE_STS (1 << 7) + +/* SIO I2C memory mapped registers */ +#define IC_CON 0x00 +# define IC_CON_MASTER_MODE (1 << 0) +# define IC_CON_10BITADDR_MASTER (1 << 4) +# define IC_CON_7BITADDR_MASTER 0 +# define IC_CON_RESTART_EN (1 << 5) +# define IC_CON_SLAVE_DISABLE (1 << 6) +#define IC_TAR 0x04 +# define IC_TAR_10BITADDR_MASTER (1 << 12) +# define IC_TAR_7BITADDR_MASTER 0 +#define IC_HS_MADDR 0x0C +#define IC_DATA_CMD 0x10 +#define IC_SS_SCL_HCNT 0x14 +#define IC_SS_SCL_LCNT 0x18 +# define IC_DATA_CMD_WRITE 0 +# define IC_DATA_CMD_READ (1 << 8) +# define IC_DATA_CMD_STOP (1 << 9) +#define IC_RAW_INTR_STAT 0x34 +# define IC_STAT_RX_UNDER (1 << 0) +# define IC_STAT_RX_OVER (1 << 1) +# define IC_STAT_RX_FULL (1 << 2) +# define IC_STAT_TX_OVER (1 << 3) +# define IC_STAT_TX_EMPTY (1 << 4) +# define IC_STAT_RD_REQ (1 << 5) +# define IC_STAT_TX_ABRT (1 << 6) +# define IC_STAT_RX_DONE (1 << 7) +# define IC_STAT_ACTIVITY (1 << 8) +# define IC_STAT_STOP_DET (1 << 9) +# define IC_STAT_START_DET (1 << 10) +# define IC_STAT_GEN_CALL (1 << 11) +#define IC_CLR_INTR 0x40 +# define IC_CLR_INTR_CLR_INTR (1 << 0) +#define IC_STATUS 0x70 +# define IC_STATUS_ACTIVITY (1 << 0) +# define IC_STATUS_TFNF (1 << 1) +# define IC_STATUS_TFE (1 << 2) +# define IC_STATUS_RFNE (1 << 3) +# define IC_STATUS_RFF (1 << 4) +# define IC_STATUS_MST_ACTIVITY (1 << 5) +# define IC_STATUS_SLV_ACTIVITY (1 << 6) +#define IC_ENABLE 0x6C +# define IC_ENABLE_ENABLE (1 << 0) +# define IC_ENABLE_DISABLE 0 +# define IC_ENABLE_ABORT (1 << 1) +#define IC_RXFLR 0x78 +#define IC_TX_ABRT_SOURCE 0x80 +# define ABRT_7B_ADDR_NOACK (1 << 0) +# define ABRT_10ADDR1_NOACK (1 << 1) +# define ABRT_10ADDR2_NOACK (1 << 2) +# define ABRT_TXDATA_NOACK (1 << 3) +# define ABRT_GCALL_NOAC (1 << 4) +# define ABRT_GCALL_READ (1 << 5) +# define ABRT_HS_ACKDET (1 << 6) +# define ABRT_SBYTE_ACKDET (1 << 7) +# define ABRT_HS_NORSTRT (1 << 8) +# define ABRT_SBYTE_NORSTRT (1 << 9) +# define ABRT_10B_RD_NORSTRT (1 << 10) +# define ABRT_MASTER_DIS (1 << 11) +# define ARB_LOST (1 << 12) +# define ABRT_SLVFLUSH_TXFIFO (1 << 13) +# define ABRT_SLV_ARBLOST (1 << 14) +# define ABRT_SLVRD_INTX (1 << 15) +# define ABRT_USER_ABRT (1 << 16) + +#define SET_IOSF_REG(name_) \ + case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC): \ + *iosf_reg = LPSS_ ## name_ ## _CTL; \ + *nvs_index = LPSS_NVS_ ## name_ + +#define CASE_I2C(name_) \ + case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC) + +#ifdef __PRE_RAM__ +void enable_smbus(device_t dev, u16 smbus_io_base); +#endif + +s16 baytrail_smbus_write_byte(u16 smbus_base, u8 device, u8 address, u8 data); +s16 baytrail_smbus_read_byte(u32 smbus_base, u8 device, u8 address); +s16 baytrail_smbus_quick_write(u32 smbus_base, u8 device, u8 data); +s16 baytrail_smbus_quick_read(u32 smbus_base, u8 device); +s16 baytrail_smbus_extended_write_byte(u32 smbus_base, u8 device, u16 address, u8 data); +s16 baytrail_smbus_extended_read_byte(u32 smbus_base, u8 device, u16 address); + diff --git a/src/soc/intel/fsp_baytrail/smbus.c b/src/soc/intel/fsp_baytrail/smbus.c new file mode 100644 index 0000000..83da6f5 --- /dev/null +++ b/src/soc/intel/fsp_baytrail/smbus.c @@ -0,0 +1,319 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <console/console.h> +#include <device/pci_def.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <device/smbus.h> +#include <device/smbus_def.h> +#include <soc/gpio.h> +#include <soc/pci_devs.h> +#include <soc/iomap.h> +#include <soc/iosf.h> +#include <soc/smbus.h> +#include <soc/iosf.h> +#include <soc/nvs.h> +#include <reg_script.h> + +static void dev_enable_snoop_and_pm(struct device * dev, int iosf_reg) +{ + struct reg_script ops[] = { + REG_SCRIPT_SET_DEV(dev), + REG_IOSF_RMW(IOSF_PORT_LPSS, iosf_reg, + ~(LPSS_CTL_SNOOP | LPSS_CTL_NOSNOOP), + LPSS_CTL_SNOOP | LPSS_CTL_PM_CAP_PRSNT), + REG_SCRIPT_END, }; + + reg_script_run(ops); +} + +static void dev_ctl_reg(struct device * dev, int *iosf_reg, int *nvs_index) +{ + *iosf_reg = -1; + *nvs_index = -1; + + switch (dev->path.pci.devfn) { + SET_IOSF_REG(I2C1); + break; + SET_IOSF_REG(I2C2); + break; + SET_IOSF_REG(I2C3); + break; + SET_IOSF_REG(I2C4); + break; + SET_IOSF_REG(I2C5); + break; + SET_IOSF_REG(I2C6); + break; + SET_IOSF_REG(I2C7); + break; + } +} + +static void i2c_set_pins(struct device *dev) +{ +#define PIN_SET_FOR_I2C 0x2003C881 + switch (dev->path.pci.devfn) { + CASE_I2C(I2C1) : + write32((volatile void *)(IO_BASE_ADDRESS + 0x0210), + PIN_SET_FOR_I2C); + write32((volatile void *)(IO_BASE_ADDRESS + 0x0200), + PIN_SET_FOR_I2C); + break; + CASE_I2C(I2C2) : + write32((volatile void *)(IO_BASE_ADDRESS + 0x01F0), + PIN_SET_FOR_I2C); + write32((volatile void *)(IO_BASE_ADDRESS + 0x01E0), + PIN_SET_FOR_I2C); + break; + CASE_I2C(I2C3) : + write32((volatile void *)(IO_BASE_ADDRESS + 0x01D0), + PIN_SET_FOR_I2C); + write32((volatile void *)(IO_BASE_ADDRESS + 0x01B0), + PIN_SET_FOR_I2C); + break; + CASE_I2C(I2C4) : + write32((volatile void *)(IO_BASE_ADDRESS + 0x0190), + PIN_SET_FOR_I2C); + write32((volatile void *)(IO_BASE_ADDRESS + 0x01C0), + PIN_SET_FOR_I2C); + break; + CASE_I2C(I2C5) : + write32((volatile void *)(IO_BASE_ADDRESS + 0x01A0), + PIN_SET_FOR_I2C); + write32((volatile void *)(IO_BASE_ADDRESS + 0x0170), + PIN_SET_FOR_I2C); + break; + CASE_I2C(I2C6) : + write32((volatile void *)(IO_BASE_ADDRESS + 0x0150), + PIN_SET_FOR_I2C); + write32((volatile void *)(IO_BASE_ADDRESS + 0x0140), + PIN_SET_FOR_I2C); + break; + CASE_I2C(I2C7) : + write32((volatile void *)(IO_BASE_ADDRESS + 0x0180), + PIN_SET_FOR_I2C); + write32((volatile void *)(IO_BASE_ADDRESS + 0x0160), + PIN_SET_FOR_I2C); + break; + } +} + +static void i2c_disable_resets(struct device * dev) +{ + /* Release the I2C devices from reset. */ + struct reg_script ops[] = { + REG_SCRIPT_SET_DEV(dev), + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x804, 0x3), + REG_SCRIPT_END, }; + + reg_script_run(ops); +} + +static void baytrail_smbus_init(struct device *dev) +{ + int iosf_reg, nvs_index; + + printk(BIOS_DEBUG, "Initializing I2c/SMBus at %s\n", dev_path(dev)); + + switch (dev->path.pci.devfn) { + CASE_I2C(I2C1) : + CASE_I2C(I2C2) : + CASE_I2C(I2C3) : + CASE_I2C(I2C4) : + CASE_I2C(I2C5) : + CASE_I2C(I2C6) : + CASE_I2C(I2C7) : + dev_ctl_reg(dev, &iosf_reg, &nvs_index); + + if (iosf_reg < 0) { + int slot = PCI_SLOT(dev->path.pci.devfn); + int func = PCI_FUNC(dev->path.pci.devfn); + printk(BIOS_DEBUG, + "Could not find iosf_reg for %02x.%01x\n", slot, + func); + return; + } + + dev_enable_snoop_and_pm(dev, iosf_reg); + i2c_disable_resets(dev); + i2c_set_pins(dev); + break; + default: + return; + } +} + +/** + * \brief - get required information about the PCI bus device that an SMBus/I2c + * device is attached to. + * + * @param dev - pointer to SMBus/I2c device - not the PCI SMBus device, + * but the device attached to the SMBus + * @param device - returns the 7/10 bit SMBus chip address + * @param pbus - returns the PCI SMBus/I2c device that the chip is attached to + * @param res - IO or memory base address of the SMBus or I2c PCI device + */ +static void get_smbus_device_info(struct device * dev, u16 *device, + struct bus **pbus, struct resource **res) +{ + *device = dev->path.i2c.device; + *pbus = get_pbus_smbus(dev); + if (dev->device == SMBUS_DEVID) { + *res = find_resource((*pbus)->dev, SMB_IO_BASE); + (*res)->base |= SMBUS_IO_ROUTINES; + } else + *res = find_resource((*pbus)->dev, I2C_MEM_BASE); +} + +/** + * \brief read a byte from an SMBus device that requires a 2 byte address + * @param dev - pointer to SMBus/I2c device + * @param address - the 16 bit address of the byte to read from the device + * @return byte - value read from SMBUS or value < 0 for error + */ +static int lsmbus_extended_read_byte(struct device * dev, u16 address) +{ + u16 device; + struct resource *res; + struct bus *pbus; + u16 retval; + + get_smbus_device_info(dev, &device, &pbus, &res); + retval = baytrail_smbus_extended_read_byte(res->base, device, address); + + return retval; +} + +/** + * \brief write a byte to an SMBus device that requires a 2 byte address + * @param dev - pointer to SMBus/I2c device + * @param address - the 16 bit address of the byte to write to the device + * @return byte - 0 for success or value < 0 for error + */ +static int lsmbus_extended_write_byte(struct device * dev, u16 address, u8 val) +{ + u16 device; + struct resource *res; + struct bus *pbus; + u16 retval; + + get_smbus_device_info(dev, &device, &pbus, &res); + + retval = baytrail_smbus_extended_write_byte(res->base, device, address, + val); + + return retval; +} + +static int lsmbus_read_byte(struct device * dev, u8 address) +{ + u16 device; + struct resource *res; + struct bus *pbus; + + get_smbus_device_info(dev, &device, &pbus, &res); + + return baytrail_smbus_read_byte(res->base, device, address); +} + +static int lsmbus_quick_read_byte(struct device * dev) +{ + u16 device; + struct resource *res; + struct bus *pbus; + + get_smbus_device_info(dev, &device, &pbus, &res); + + return baytrail_smbus_quick_read(res->base, device); +} + +static int lsmbus_write_byte(struct device * dev, u8 address, u8 val) +{ + u16 device; + struct resource *res; + struct bus *pbus; + + get_smbus_device_info(dev, &device, &pbus, &res); + + return baytrail_smbus_write_byte(res->base, device, address, val); +} + +static int lsmbus_quick_write_byte(struct device * dev, u8 value) +{ + u16 device; + struct resource *res; + struct bus *pbus; + + get_smbus_device_info(dev, &device, &pbus, &res); + + return baytrail_smbus_quick_write(res->base, device, value); +} + +const struct smbus_bus_operations baytrail_smbus_bus_ops = { + .read_byte = lsmbus_read_byte, + .write_byte = lsmbus_write_byte, + .recv_byte = lsmbus_quick_read_byte, + .send_byte = lsmbus_quick_write_byte, + .extended_read_byte = lsmbus_extended_read_byte, + .extended_write_byte = lsmbus_extended_write_byte, + +}; + +static void smbus_set_subsystem(struct device * dev, unsigned vendor, unsigned device) +{ + if (!vendor || !device) { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + pci_read_config32(dev, PCI_VENDOR_ID)); + } else { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + ((device & 0xffff) << 16) | (vendor & 0xffff)); + } +} + +static struct pci_operations baytrail_smbus_pci_ops = { + .set_subsystem = smbus_set_subsystem, }; + +struct device_operations baytrail_smbus_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = baytrail_smbus_init, + .scan_bus = 0, + .ops_smbus_bus = &baytrail_smbus_bus_ops, + .ops_pci = &baytrail_smbus_pci_ops, }; + +static const unsigned short pci_device_ids[] = { + I2C1_DEVID, + I2C2_DEVID, + I2C3_DEVID, + I2C4_DEVID, + I2C5_DEVID, + I2C6_DEVID, + I2C7_DEVID, + SMBUS_DEVID, + 0, +}; + +static const struct pci_driver baytrail_smbus __pci_driver = { .ops = + &baytrail_smbus_ops, .vendor = PCI_VENDOR_ID_INTEL, .devices = + pci_device_ids, }; diff --git a/src/soc/intel/fsp_baytrail/smbus_access.c b/src/soc/intel/fsp_baytrail/smbus_access.c new file mode 100644 index 0000000..0db2557 --- /dev/null +++ b/src/soc/intel/fsp_baytrail/smbus_access.c @@ -0,0 +1,492 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2012-2014 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <device/pci_ids.h> +#include <device/pci_def.h> +#include <device/smbus_def.h> +#include <soc/smbus.h> +#include <delay.h> + +/** \brief block until the SMBus is no longer busy, or it times out + * + * \param smbus_base IO base address of the SMBus + */ +static int smbus_wait_until_ready(u16 smbus_base) +{ + u32 loops = SMBUS_TIMEOUT; + u8 byte; + + do { + udelay(1); + if (--loops == 0) + break; + byte = inb(smbus_base + SMBHSTSTAT); + } while (byte & HSTSTS_HOST_BUSY); + return loops ? 0 : -1; +} + +/** \brief block until the SMBus is no longer busy, in use, or it times out + * + * \param smbus_base IO base address of the SMBus + */ +static int smbus_wait_until_done(u16 smbus_base) +{ + u32 loops = SMBUS_TIMEOUT; + u8 byte; + + do { + udelay(1); + if (--loops == 0) + break; + byte = inb(smbus_base + SMBHSTSTAT); + } while ((byte & HSTSTS_HOST_BUSY) + || (byte & ~(HSTSTS_INUSE_STS | HSTSTS_HOST_BUSY)) == 0); + return loops ? 0 : -1; +} + +/** \brief clear the smbus in-use status bit + * + * @param smbus_base IO base address of the SMBus + */ +static void smbus_clear_inuse(u16 smbus_base) +{ + /* Clear INUSE_STS */ + outb((u16)smbus_base + SMBHSTSTAT, HSTSTS_INUSE_STS); +} + +#ifdef __PRE_RAM__ +/** \brief Sets the SMBus BAR, and configures it to run + * + */ +void enable_smbus(device_t dev, u16 smbus_base) +{ + /* TODO: Make this work for all SMBUS and I2c devices on baytrail */ + /* Set SMBus I/O base. */ + pci_write_config32(dev, SMB_IO_BASE, smbus_base | + PCI_BASE_ADDRESS_SPACE_IO); + + /* Set SMBus enable. */ + pci_write_config8(dev, HOSTCFG, HST_EN); + + /* Set SMBus I/O space enable. */ + pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO); + + /* Disable interrupt generation. */ + outb(0, smbus_base + SMBHSTCTL); + + /* Clear any lingering errors, so transactions can run. */ + outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT); + print_debug("SMBus controller enabled.\n"); + smbus_clear_inuse(smbus_base); +} +#endif + +/* + * The functions for setting the speed, along with the timings used were + * pulled from the linux source tree. + * Linux/drivers/i2c/busses/i2c-designware-core.c + * This is the module that is used for the Bay Trail I2c hardware + * + * The two functions are i2c_dw_scl_hcnt() and i2c_dw_scl_lcnt() + * The timing code is i2c_rw_byte() calling the two functions. + * + */ +static u32 i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, + int offset) +{ + /* + * DesignWare I2C core doesn't seem to have solid strategy to meet + * the tHD;STA timing spec. Configuring _HCNT based on tHIGH spec + * will result in violation of the tHD;STA spec. + */ + if (cond) + /* + * Conditional expression: + * + * IC_[FS]S_SCL_HCNT + (1+4+3) >= IC_CLK * tHIGH + * + * This is based on the DW manuals, and represents an ideal + * configuration. The resulting I2C bus speed will be + * faster than any of the others. + * + * If your hardware is free from tHD;STA issue, try this one. + */ + return (ic_clk * tSYMBOL + 5000) / 10000 - 8 + offset; + else + /* + * Conditional expression: + * + * IC_[FS]S_SCL_HCNT + 3 >= IC_CLK * (tHD;STA + tf) + * + * This is just experimental rule; the tHD;STA period turned + * out to be proportional to (_HCNT + 3). With this setting, + * we could meet both tHIGH and tHD;STA timing specs. + * + * If unsure, you'd better to take this alternative. + * + * The reason why we need to take into account "tf" here, + * is the same as described in i2c_dw_scl_lcnt(). + */ + return (ic_clk * (tSYMBOL + tf) + 5000) / 10000 - 3 + offset; +} + +static u32 i2c_dw_scl_lcnt(u32 ic_clk, u32 tLOW, u32 tf, int offset) +{ + /* + * Conditional expression: + * + * IC_[FS]S_SCL_LCNT + 1 >= IC_CLK * (tLOW + tf) + * + * DW I2C core starts counting the SCL CNTs for the LOW period + * of the SCL clock (tLOW) as soon as it pulls the SCL line. + * In order to meet the tLOW timing spec, we need to take into + * account the fall time of SCL signal (tf). Default tf value + * should be 0.3 us, for safety. + */ + return ((ic_clk * (tLOW + tf) + 5000) / 10000) - 1 + offset; +} + +/** \brief block until the i2c bus is no longer active, or it times out + * + * \param i2c_base IO base address of the i2c controller + */ +static int i2c_wait_until_ready(u32 i2c_base) +{ + u32 loops = SMBUS_TIMEOUT; + + do { + udelay(1); + if (--loops == 0) + break; + } while (read32((const volatile void *)(i2c_base + IC_STATUS)) & + IC_STATUS_ACTIVITY); + + return loops ? 0 : -1; +} + +/** + * \brief read or write to the i2c mmio addresses + * + * @param i2c_base mmio base address + * @param device 8 bit i2c device address + * @param addr_dat 8 or 16-bit address within the i2c device plus 8/16 bit flag + * @param data value to write to the register if this is a write + * @param command full or quick read/write command + * @return 8-bit value read from the device or negative value on error + */ +static s16 i2c_rw_byte(u32 i2c_base, u8 device, u32 addr_dat, u8 data, + u8 command) +{ + u32 input_clock_khz = 400; + + if (i2c_wait_until_ready(i2c_base) < 0) + return SMBUS_WAIT_UNTIL_READY_TIMEOUT; + + /*** Set up transaction ***/ + /* Disable i2c controller */ + write32((volatile void *)(i2c_base + IC_ENABLE), IC_ENABLE_DISABLE); + + /* + * set Standard-mode timings for high/low periods + * code from Linux/drivers/i2c/busses/i2c-designware-core.c + */ + write32((volatile void *)(i2c_base + IC_SS_SCL_HCNT), + i2c_dw_scl_hcnt( + input_clock_khz, + 40, /* tHD;STA = tHIGH = 4.0 us */ + 3, /* tf = 0.3 us */ + 0, /* 0: DW default, 1: Ideal */ + 0)); /* No offset */ + write32((volatile void *)(i2c_base + IC_SS_SCL_LCNT), + i2c_dw_scl_lcnt( + input_clock_khz, + 47, /* tLOW = 4.7 us */ + 3, /* tf = 0.3 us */ + 0)); /* No offset */ + + write32((volatile void *)(i2c_base + IC_CON), IC_CON_MASTER_MODE | + IC_CON_RESTART_EN | IC_CON_SLAVE_DISABLE | + IC_CON_7BITADDR_MASTER); + + /* Set the 7-bit i2c device address */ + write32((volatile void *)(i2c_base + IC_TAR), device >> 1 | + IC_TAR_7BITADDR_MASTER); + + /* Enable i2c controller */ + write32((volatile void *)(i2c_base + IC_ENABLE), IC_ENABLE_ENABLE); + + if (i2c_wait_until_ready(i2c_base) < 0) + return SMBUS_WAIT_UNTIL_READY_TIMEOUT; + + /* Set the address if this isn't a 'quick' transaction */ + if (command == FULL_RW) { + /* Set the address and data bytes */ + + if (addr_dat & ADDRESS_16_BIT) { + write32((volatile void *)(i2c_base + IC_DATA_CMD), + ((addr_dat >> 8) & 0x3f) | IC_DATA_CMD_WRITE); + + write32((volatile void *)(i2c_base + IC_DATA_CMD), + ((addr_dat & 0xff) | IC_DATA_CMD_WRITE)); + } else { + write32((volatile void *)(i2c_base + IC_DATA_CMD), + ((addr_dat & 0xff) | IC_DATA_CMD_WRITE)); + } + } + + /* send the data & write or the read command and set the stop bit */ + if (device & READ_BIT) + write32((volatile void *)(i2c_base + IC_DATA_CMD), + IC_DATA_CMD_READ | IC_DATA_CMD_STOP); + else + write32((volatile void *)(i2c_base + IC_DATA_CMD), data | + IC_DATA_CMD_WRITE | IC_DATA_CMD_STOP); + + if (i2c_wait_until_ready(i2c_base) < 0) + return SMBUS_WAIT_UNTIL_READY_TIMEOUT; + + if (device & READ_BIT) + return (read32((const volatile void *)(i2c_base + IC_DATA_CMD)) + & 0xff); + else + return SMBUS_SUCCESS; +} + +/** \brief generic smbus helper function to read & write to the smbus + * + * \details Configures the SMBus for the transaction, sets up the address + * and data bytes, starts the command, waits for the command to + * finish, and returns data if the command is a read. + * + * \param smbus_base The base address of the SMBUS controller + * + * \param device The 8-bit i2c device address, with the read / write bit already + * configured. + * + * \param addr_dat For full reads/writes, this contains the address within + * the device of the byte being read/written. For quick writes, + * this contains the data to write. + * + * \param data For full writes, this contains the Data to write to the + * device. For all other transactions, this is ignored. + * + * \param command Contains the command for a full read/write (0x48) or the + * command for a quick read/write (0x44) + * + * \return Data read from the device, or -1 if there was an error + */ +static s16 smbus_rw_byte(u16 smbus_base, u8 device, u32 addr_dat, u8 data, u8 command) +{ + u8 global_status_register; + + if (smbus_wait_until_ready(smbus_base) < 0) { + smbus_clear_inuse(smbus_base); + return SMBUS_WAIT_UNTIL_READY_TIMEOUT; + } + /*** Set up transaction ***/ + + /* Disable interrupts */ + outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL); + + /* Set the device being talked to using supplied device address*/ + outb(device, smbus_base + SMBXMITADD); + + /* Set the address and data bytes */ + outb(addr_dat & 0xff, smbus_base + SMBHSTCMD); + if (addr_dat & ADDRESS_16_BIT) { + outb((addr_dat >> 8) & 0xff, smbus_base + SMBHSTDAT0); + outb(data, smbus_base + SMBHSTDAT1); + } else { + outb(data, smbus_base + SMBHSTDAT0); + } + + /* Clear any lingering errors, so the transaction will run */ + outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT); + + /* Start the command */ + outb(command, smbus_base + SMBHSTCTL); + + /* Poll for transaction completion */ + if (smbus_wait_until_done(smbus_base) < 0) { + smbus_clear_inuse(smbus_base); + return SMBUS_WAIT_UNTIL_DONE_TIMEOUT; + } + + global_status_register = inb(smbus_base + SMBHSTSTAT); + + /* Ignore the "In Use" status... */ + global_status_register &= ~(HSTSTS_SMBALERT_STS | HSTSTS_INUSE_STS); + + /* + * Read results + * INTR gets set when a command is completed successfully + */ + data = inb(smbus_base + SMBHSTDAT0); + if (global_status_register != HSTSTS_INTR) { + smbus_clear_inuse(smbus_base); + return SMBUS_ERROR; + } + + smbus_clear_inuse(smbus_base); + + return data; +} + +/** \brief Sends an address and writes one byte of data + * + * \param smbus_base The base address of the SMBUS controller + * + * \param device The 7-bit address of the device being written to + * + * \param address The address within the device to write the data to + * + * \param data The data value to write to the device + * + * \return negative value if there was an error + */ +s16 baytrail_smbus_write_byte(u16 smbus_base, u8 device, u8 address, u8 data) +{ + if (smbus_base & SMBUS_IO_ROUTINES) { + return (smbus_rw_byte((u16)(smbus_base & 0xfff0), device << 1, + address, data, FULL_RW)); + } else { + return (i2c_rw_byte(smbus_base, device << 1, address, data, + FULL_RW)); + } +} + +/** \brief Sends an address and reads one byte of data + * + * \param smbus_base The base address of the SMBUS controller + * + * \param device The 7-bit address of the device being written to + * + * \param address The address within the device to write the data to + * + * \return Data read from the device, or negative value if there was an error + */ +s16 baytrail_smbus_read_byte(u32 smbus_base, u8 device, u8 address) +{ + if (smbus_base & SMBUS_IO_ROUTINES) { + return (smbus_rw_byte((u16)(smbus_base & 0xfff0), + (device << 1) | READ_BIT, address, IGNORED_BYTE, + FULL_RW)); + } else { + return (i2c_rw_byte(smbus_base, (device << 1) | READ_BIT, + address, IGNORED_BYTE, FULL_RW)); + } +} + +/** \brief Sends one byte of data with no address byte + * + * \param smbus_base The base address of the SMBUS controller + * + * \param device The 7-bit address of the device being written to + * + * \param data The data value to write to the device + * + * \return negative value if there was an error + */ +s16 baytrail_smbus_quick_write(u32 smbus_base, u8 device, u8 data) +{ + if (smbus_base & SMBUS_IO_ROUTINES) { + return (smbus_rw_byte((u16)(smbus_base & 0xfff0), device << 1, + data, IGNORED_BYTE, QUICK_RW)); + } else { + return (i2c_rw_byte(smbus_base, device << 1, data, IGNORED_BYTE, + QUICK_RW)); + } + +} + +/** \brief Reads one byte of data without sending an address byte + * + * \param smbus_base The base address of the SMBUS controller + * + * \param device The 7-bit address of the device being written to + * + * \return Data read from the device, or negative value if there was an error + */ +s16 baytrail_smbus_quick_read(u32 smbus_base, u8 device) +{ + if (smbus_base & SMBUS_IO_ROUTINES) { + return (smbus_rw_byte((u16)(smbus_base & 0xfff0), + (device << 1) | READ_BIT, + IGNORED_BYTE, IGNORED_BYTE, QUICK_RW)); + } else { + return (i2c_rw_byte(smbus_base, (device << 1) | READ_BIT, + IGNORED_BYTE, IGNORED_BYTE, QUICK_RW)); + } + +} + +/** \brief Sends a 2-byte address and writes one byte of data + * + * \param smbus_base The base address of the SMBUS controller + * + * \param device The 7-bit address of the device being written to + * + * \param address The address within the device to write the data to + * + * \param data The data value to write to the device + * + * \return negative value if there was an error + */ +s16 baytrail_smbus_extended_write_byte(u32 smbus_base, u8 device, u16 address, + u8 data) +{ + u32 addr_dat = ADDRESS_16_BIT | address; + + if (smbus_base & SMBUS_IO_ROUTINES) + return (smbus_rw_byte((u16)(smbus_base & 0xfff0), device << 1, + addr_dat, data, FULL_RW)); + else + return (i2c_rw_byte(smbus_base, (device << 1), addr_dat, data, + FULL_RW)); +} + +/** \brief Sends a 2-byte address and reads one byte of data + * + * \param smbus_base The base address of the SMBUS controller + * + * \param device The 7-bit address of the device being written to + * + * \param address The address within the device to write the data to + * + * \return Data read from the device, or negative value if there was an error + */ +s16 baytrail_smbus_extended_read_byte(u32 smbus_base, u8 device, u16 address) +{ + s16 retval = 0; + u32 addr_dat = ADDRESS_16_BIT | address; + + if (smbus_base & SMBUS_IO_ROUTINES) { + retval = smbus_rw_byte((u16)(smbus_base & 0xfff0), + (device << 1) | READ_BIT, addr_dat, + IGNORED_BYTE, FULL_RW); + } else { + retval = i2c_rw_byte(smbus_base, (device << 1) | READ_BIT, + addr_dat, IGNORED_BYTE, FULL_RW); + } + return retval; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/30758 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I39178776ef8ccae785ec5f6edb2824929cd103e9 Gerrit-Change-Number: 30758 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: x86/acpi_s3: Clarify debug message *Normal boot*
by Paul Menzel (Code Review) 10 Jun '23

10 Jun '23

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30807 Change subject: x86/acpi_s3: Clarify debug message *Normal boot* ...................................................................... x86/acpi_s3: Clarify debug message *Normal boot* To avoid confusing with the normal/fallback mechanism, clarify the debug message *Normal boot*. Change-Id: I3435b4f5b78290a964d1e1bf0894885ed1ec56a4 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/arch/x86/acpi_s3.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/30807/1 diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c index 07c0332..9e48e6a 100644 --- a/src/arch/x86/acpi_s3.c +++ b/src/arch/x86/acpi_s3.c @@ -37,7 +37,7 @@ printk(BIOS_DEBUG, "S3 Resume\n"); acpi_slp_type = ACPI_S3; } else { - printk(BIOS_DEBUG, "Normal boot\n"); + printk(BIOS_DEBUG, "Normal boot (not resuming from S3)\n"); acpi_slp_type = ACPI_S0; } } -- To view, visit https://review.coreboot.org/c/coreboot/+/30807 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3435b4f5b78290a964d1e1bf0894885ed1ec56a4 Gerrit-Change-Number: 30807 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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