coreboot-gerrit May 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: soc/intel/common: Set RX_DISABLE for pads configured as NC
by Furquan Shaikh (Code Review) 01 May '19

01 May '19

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32514 Change subject: soc/intel/common: Set RX_DISABLE for pads configured as NC ...................................................................... soc/intel/common: Set RX_DISABLE for pads configured as NC For GPIO pads that are configured as no-connect (PAD_NC), setting it as GPI (with Rx enabled) leads to GPE0_STS being set incorrectly. Though this is not an issue in practice (GPE0_EN is not set, so no events triggered), it can confuse users when debugging GPE related issues. This change configures PAD_NC to have Rx disabled along with Tx to ensure that it does not end up setting GPE0_STS bits for unwanted GPIO pads. P.S.: IOSSTATE config does not have a TxDRxD setting, so leaving that configuration as is. BUG=b:129235068 TEST=Verified that GPE0_STS bits are not set for pads that are marked as PAD_NC. Change-Id: I726cc7b86a94e7449352cd8a8806d4d775c593dc Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/intel/common/block/include/intelblocks/gpio_defs.h 1 file changed, 9 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/32514/1 diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h index 0ad3e5c..91d8f00 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h @@ -264,10 +264,16 @@ PAD_CFG0_TRIG_##trig | PAD_CFG0_RX_POL_NONE, \ PAD_PULL(pull) | PAD_CFG1_GPIO_DRIVER | PAD_IOSSTATE(TxDRxE)) -/* No Connect configuration for unused pad. - * NC should be GPI with Term as PU20K, PD20K, NONE depending upon default Term +/* + * No Connect configuration for unused pad. + * Both TX and RX are disabled. RX disabling is done to avoid unnecessary + * setting of GPI_STS. */ -#define PAD_NC(pad, pull) PAD_CFG_GPI(pad, pull, DEEP) +#define PAD_NC(pad, pull) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | \ + PAD_CFG0_TX_DISABLE | PAD_CFG0_RX_DISABLE, \ + PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE)) #if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS) -- To view, visit https://review.coreboot.org/c/coreboot/+/32514 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I726cc7b86a94e7449352cd8a8806d4d775c593dc Gerrit-Change-Number: 32514 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: sdm845: Port I2C driver
by Julius Werner (Code Review) 01 May '19

01 May '19

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29104 ) Change subject: sdm845: Port I2C driver ...................................................................... Patch Set 31: (8 comments) https://review.coreboot.org/#/c/29104/31/src/soc/qualcomm/sdm845/i2c.c File src/soc/qualcomm/sdm845/i2c.c: https://review.coreboot.org/#/c/29104/31/src/soc/qualcomm/sdm845/i2c.c@44 PS31, Line 44: struct qup_i2c_clk_fld *itr = qup_i2c_clk_map + idx; When you rewrite this to use the generic enum (see other file), I'd write this stuff like this instead: int clk_div, t_high, t_low, t_cycle; switch (speed) { case I2C_SPEED_STANDARD: clk_div = 7; t_high = 10; t_low = 11; t_cycle = 26; case I2C_SPEED_FAST: ... default: die("Unsupported I2C speed"); } https://review.coreboot.org/#/c/29104/31/src/soc/qualcomm/sdm845/i2c.c@89 PS31, Line 89: (BITS_PER_WORD >> 4)); What about rewriting this to log2(BITS_PER_WORD) - 3? You said "Done" to that, but it looks like you didn't actually do it. https://review.coreboot.org/#/c/29104/31/src/soc/qualcomm/sdm845/i2c.c@130 PS31, Line 130: segment.buf, segment.buf Note that if you combine the three size parameters into one like I'm suggesting in the other file, you can't pass both din and dout here. You'd have to do something like void *din = NULL, *dout = NULL; if (!(segment.flags & I2C_M_RD)) { dout = segment.buf; ... } else { din = segment.buf; ... } https://review.coreboot.org/#/c/29104/31/src/soc/qualcomm/sdm845/include/so… File src/soc/qualcomm/sdm845/include/soc/i2c.h: https://review.coreboot.org/#/c/29104/31/src/soc/qualcomm/sdm845/include/so… PS31, Line 23: }; Actually, looks like we have an existing enum for this in <device/i2c.h> (I2C_SPEED_FAST, etc.), can you use that instead? https://review.coreboot.org/#/c/29104/31/src/soc/qualcomm/sdm845/qcom_qup_s… File src/soc/qualcomm/sdm845/qcom_qup_se.c: https://review.coreboot.org/#/c/29104/31/src/soc/qualcomm/sdm845/qcom_qup_s… PS31, Line 101: u32 wait_till_irq_set(unsigned int bus) I think all of these functions other than qup_isr_handle() could be static? If you do want to export them, they should probably be better namespaced (e.g. qup_wait_for_irq, qup_handle_tx, etc.). https://review.coreboot.org/#/c/29104/31/src/soc/qualcomm/sdm845/qcom_qup_s… PS31, Line 118: Please fix indentation. https://review.coreboot.org/#/c/29104/31/src/soc/qualcomm/sdm845/qcom_qup_s… PS31, Line 184: qup_isr_handle "ISR handle" sounds a bit weird for that this function actually does (which is handle a full transfer except for the setup part). Maybe qup_handle_transfer() or qup_finish_transfer() would be better? https://review.coreboot.org/#/c/29104/31/src/soc/qualcomm/sdm845/qcom_qup_s… PS31, Line 185: unsigned int tx_rem_bytes, unsigned int rx_rem_bytes) You shouldn't need to pass all of size, tx_rem_bytes and rx_rem_bytes. They should all be the same (unless one of the transfer directions is NULL). You should only have a size, and then set up local variables for the other two: unsigned int rx_rem_bytes = din ? size : 0; unsigned int tx_rem_bytes = dout ? size : 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/29104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifb76564d8a11427423dd14d8ba7c8c7d500ef346 Gerrit-Change-Number: 29104 Gerrit-PatchSet: 31 Gerrit-Owner: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: Akash Asthana <akashast(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: T Michael Turney <mturney(a)codeaurora.org> Gerrit-Reviewer: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 01 May 2019 00:52:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: sdm845: Add SPI QUP driver
by Julius Werner (Code Review) 01 May '19

01 May '19

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27483 ) Change subject: sdm845: Add SPI QUP driver ...................................................................... Patch Set 51: (4 comments) Thanks, this looks good now... but it is interdependent with the I2C patch. This patch adds the underlying qcom_qup_se.c stuff, but the I2C patch adds qup_isr_handle() which this patch relies on, so they don't depend on each other. Patches always need to be atomic, so please pull all the shared stuff from the I2C patch into this one. https://review.coreboot.org/#/c/27483/51/src/mainboard/google/cheza/bootblo… File src/mainboard/google/cheza/bootblock.c: https://review.coreboot.org/#/c/27483/51/src/mainboard/google/cheza/bootblo… PS51, Line 19: #include <soc/qcom_qup_se.h> nit: please order alphabetically https://review.coreboot.org/#/c/27483/51/src/soc/qualcomm/sdm845/qspi.c File src/soc/qualcomm/sdm845/qspi.c: https://review.coreboot.org/#/c/27483/51/src/soc/qualcomm/sdm845/qspi.c@19 PS51, Line 19: arch No, this is supposed to be <device/mmio.h> https://review.coreboot.org/#/c/27483/51/src/soc/qualcomm/sdm845/spi_qup.c File src/soc/qualcomm/sdm845/spi_qup.c: https://review.coreboot.org/#/c/27483/51/src/soc/qualcomm/sdm845/spi_qup.c@… PS51, Line 150: /n" I think this is supposed to be a \n? https://review.coreboot.org/#/c/27483/51/src/soc/qualcomm/sdm845/spi_qup.c@… PS51, Line 153: } You should actually return an error value here which you can then pass out of qup_spi_claim_bus(). -- To view, visit https://review.coreboot.org/c/coreboot/+/27483 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35061727d5ccc550eaeb06caef4524bc4cf25b54 Gerrit-Change-Number: 27483 Gerrit-PatchSet: 51 Gerrit-Owner: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mukesh Savaliya <msavaliy(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: T Michael Turney <mturney(a)codeaurora.org> Gerrit-Reviewer: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: Vin Kamath <vink(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Akash Asthana <akashast(a)qualcomm.corp-partner.google.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Wed, 01 May 2019 00:32:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: Mainboard: Add MSI MS-7707
by Bluemax (Code Review) 01 May '19

01 May '19

Bluemax has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32235 Change subject: Mainboard: Add MSI MS-7707 ...................................................................... Mainboard: Add MSI MS-7707 MSI MS-7707 V1.1 (Medion OEM Akoya P4385D MSN10014555) SandyBridge Intel P67 (BD82x6x) Winbond 25Q32BV (4MB) Fintek F71808A Intel 82579V Gigabit NEC uPD720200 USB 3.0 Host Controller IME 7.0.4.1197 Working: * Tested on Arch Linux 5.0.5 * PCIe gfx adapter * PS/2 Keyboard * USB3.0 * coreboot 4.9 (TianoCore) * S0/S5 states * H/W FAN control (proper HWM function not checked) Known issues: * S0/S5 states work properly as long as the board gets powered. After power cut the system is dead. Needs battery removal and CMOSCLR to revive. SuperIO is supposed to be in an unknown state as current coreboot SuperIO initialization isn't able to set all registers. (see cbmem.log - skipping PNP: 004e.a@e0 fixed resource, size=0!) * Logs in ${doc} folder Change-Id: I999149bb95d553ed217b2288cc34bce4fe88abb3 Signed-off-by: Bluemax <1403092+BlueMax(a)users.noreply.github.com> --- A src/mainboard/medion/Kconfig A src/mainboard/medion/Kconfig.name A src/mainboard/medion/ms_7707/Kconfig A src/mainboard/medion/ms_7707/Kconfig.name A src/mainboard/medion/ms_7707/Makefile.inc A src/mainboard/medion/ms_7707/acpi/ec.asl A src/mainboard/medion/ms_7707/acpi/platform.asl A src/mainboard/medion/ms_7707/acpi/superio.asl A src/mainboard/medion/ms_7707/acpi_tables.c A src/mainboard/medion/ms_7707/board_info.txt A src/mainboard/medion/ms_7707/devicetree.cb A src/mainboard/medion/ms_7707/dsdt.asl A src/mainboard/medion/ms_7707/gpio.c A src/mainboard/medion/ms_7707/hda_verb.c A src/mainboard/medion/ms_7707/mainboard.c A src/mainboard/medion/ms_7707/romstage.c 16 files changed, 717 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/32235/1 diff --git a/src/mainboard/medion/Kconfig b/src/mainboard/medion/Kconfig new file mode 100644 index 0000000..16f8bad --- /dev/null +++ b/src/mainboard/medion/Kconfig @@ -0,0 +1,16 @@ +if VENDOR_MEDION + +choice + prompt "Mainboard model" + +source "src/mainboard/medion/*/Kconfig.name" + +endchoice + +source "src/mainboard/medion/*/Kconfig" + +config MAINBOARD_VENDOR + string + default "MEDION" + +endif # VENDOR_MEDION diff --git a/src/mainboard/medion/Kconfig.name b/src/mainboard/medion/Kconfig.name new file mode 100644 index 0000000..4c4ae07 --- /dev/null +++ b/src/mainboard/medion/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_MEDION + bool "MEDION" diff --git a/src/mainboard/medion/ms_7707/Kconfig b/src/mainboard/medion/ms_7707/Kconfig new file mode 100644 index 0000000..f66c55e --- /dev/null +++ b/src/mainboard/medion/ms_7707/Kconfig @@ -0,0 +1,44 @@ +if BOARD_MEDION_MS_7707 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select ARCH_X86 + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select USE_NATIVE_RAMINIT + select SOUTHBRIDGE_INTEL_BD82X6X + select SUPERIO_FINTEK_F71808A + select BOARD_ROMSIZE_KB_4096 + select HAVE_ACPI_TABLES + select HAVE_ACPI_RESUME + select MAINBOARD_USES_IFD_GBE_REGION + select NO_UART_ON_SUPERIO + select SERIRQ_CONTINUOUS_MODE + +config MAINBOARD_DIR + string + default medion/ms_7707 + +config MAINBOARD_PART_NUMBER + string + default "MS-7707" + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x7707 + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x1462 + +config DRAM_RESET_GATE_GPIO + int + default 60 + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX # FIXME: check this + int + default 2 +endif diff --git a/src/mainboard/medion/ms_7707/Kconfig.name b/src/mainboard/medion/ms_7707/Kconfig.name new file mode 100644 index 0000000..5dd9011 --- /dev/null +++ b/src/mainboard/medion/ms_7707/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_MEDION_MS_7707 + bool "MS-7707" diff --git a/src/mainboard/medion/ms_7707/Makefile.inc b/src/mainboard/medion/ms_7707/Makefile.inc new file mode 100644 index 0000000..3dae61e --- /dev/null +++ b/src/mainboard/medion/ms_7707/Makefile.inc @@ -0,0 +1 @@ +romstage-y += gpio.c diff --git a/src/mainboard/medion/ms_7707/acpi/ec.asl b/src/mainboard/medion/ms_7707/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/medion/ms_7707/acpi/ec.asl diff --git a/src/mainboard/medion/ms_7707/acpi/platform.asl b/src/mainboard/medion/ms_7707/acpi/platform.asl new file mode 100644 index 0000000..7c3b3c6 --- /dev/null +++ b/src/mainboard/medion/ms_7707/acpi/platform.asl @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Tristan Corrick <tristan(a)corrick.kiwi> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method(_WAK,1) +{ + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ +} diff --git a/src/mainboard/medion/ms_7707/acpi/superio.asl b/src/mainboard/medion/ms_7707/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/medion/ms_7707/acpi/superio.asl diff --git a/src/mainboard/medion/ms_7707/acpi_tables.c b/src/mainboard/medion/ms_7707/acpi_tables.c new file mode 100644 index 0000000..7d634a0 --- /dev/null +++ b/src/mainboard/medion/ms_7707/acpi_tables.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/bd82x6x/nvs.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + // the lid is open by default. + gnvs->lids = 1; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/medion/ms_7707/board_info.txt b/src/mainboard/medion/ms_7707/board_info.txt new file mode 100644 index 0000000..eebec48 --- /dev/null +++ b/src/mainboard/medion/ms_7707/board_info.txt @@ -0,0 +1,6 @@ +Category: desktop +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2011 diff --git a/src/mainboard/medion/ms_7707/devicetree.cb b/src/mainboard/medion/ms_7707/devicetree.cb new file mode 100644 index 0000000..b8df731 --- /dev/null +++ b/src/mainboard/medion/ms_7707/devicetree.cb @@ -0,0 +1,185 @@ +chip northbridge/intel/sandybridge + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" + register "gfx.link_frequency_270_mhz" = "0" + register "gfx.ndid" = "3" + register "gfx.use_spread_spectrum_clock" = "0" + register "gpu_cpu_backlight" = "0x00000000" + register "gpu_dp_b_hotplug" = "0" + register "gpu_dp_c_hotplug" = "0" + register "gpu_dp_d_hotplug" = "0" + register "gpu_panel_port_select" = "0" + register "gpu_panel_power_backlight_off_delay" = "0" + register "gpu_panel_power_backlight_on_delay" = "0" + register "gpu_panel_power_cycle_delay" = "0" + register "gpu_panel_power_down_delay" = "0" + register "gpu_panel_power_up_delay" = "0" + register "gpu_pch_backlight" = "0x00000000" + device cpu_cluster 0x0 on + chip cpu/intel/model_206ax + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0x0 on end + device lapic 0xacac off end + end + end + device domain 0x0 on + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "0" + register "gen1_dec" = "0x00fc0295" + register "gen2_dec" = "0x00000000" + register "gen3_dec" = "0x00000000" + register "gen4_dec" = "0x00000000" + register "p_cnt_throttling_supported" = "1" + register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0xc" + register "spi_lvscc" = "0x0" + register "spi_uvscc" = "0x0" + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x1462 0x7707 + end + device pci 16.1 off # Management Engine Interface 2 + end + device pci 16.2 off # Management Engine IDE-R + end + device pci 16.3 off # Management Engine KT + end + device pci 19.0 on # Intel Gigabit Ethernet + subsystemid 0x1462 0x7707 + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x1462 0x7707 + end + device pci 1b.0 on # High Definition Audio Audio controller + subsystemid 0x1462 0x7707 + end + device pci 1c.0 on # PCIe Port #1 + subsystemid 0x1462 0x7707 + end + device pci 1c.1 off # PCIe Port #2 + end + device pci 1c.2 off # PCIe Port #3 + end + device pci 1c.3 off # PCIe Port #4 + end + device pci 1c.4 off # PCIe Port #5 + end + device pci 1c.5 off # PCIe Port #6 + end + device pci 1c.6 on # PCIe Port #7 + subsystemid 0x1462 0x7707 + end + device pci 1c.7 off # PCIe Port #8 + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x1462 0x7707 + end + device pci 1e.0 off # PCI bridge + end + device pci 1f.0 on # LPC bridge PCI-LPC bridge + subsystemid 0x1462 0x7707 + chip superio/fintek/f71808a + register "multi_function_register_0" = "0x00" + register "multi_function_register_1" = "0xc4" + register "multi_function_register_2" = "0x21" + register "multi_function_register_3" = "0x2f" + register "multi_function_register_4" = "0x5c" + register "hwm_peci_tsi_ctrl" = "0x02" # PECI enabled, 1.23 V + register "hwm_tcc_temp" = "0x66" # TCC temperature = 102 °C + register "hwm_fan1_seg1_speed" = "0xff" # Fan 1 segment 1 = 100% + register "hwm_fan1_seg2_speed" = "0xdb" # Fan 1 segment 2 = 86% + register "hwm_fan1_seg3_speed" = "0xbc" # Fan 1 segment 3 = 74% + register "hwm_fan1_seg4_speed" = "0x9e" # Fan 1 segment 4 = 62% + register "hwm_fan1_seg5_speed" = "0x7f" # Fan 1 segment 5 = 50% + register "hwm_fan1_temp_src" = "0x18" # Fan 1 source = PECI + register "hwm_fan2_seg1_speed" = "0xff" # Fan 2 segment 1 = 100% + register "hwm_fan2_seg2_speed" = "0xdb" # Fan 2 segment 2 = 86% + register "hwm_fan2_seg3_speed" = "0xbc" # Fan 2 segment 3 = 74% + register "hwm_fan2_seg4_speed" = "0x9e" # Fan 2 segment 4 = 62% + register "hwm_fan2_seg5_speed" = "0x7f" # Fan 2 segment 5 = 50% + register "hwm_fan2_temp_src" = "0x1e" # Fan 2 source = temperature 2 + device pnp 4e.1 off end # Serial Port + device pnp 4e.4 on # Hardware monitor + io 0x60 = 0x295 + irq 0x70 = 0 + end + device pnp 4e.5 on # Keyboard + io 0x60 = 0x060 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 4e.6 on # GPIO + irq 0x70 = 0 + # don't get accepted (see ${docs}/cbmem.log) + irq 0xc1 = 0x3f + irq 0xc5 = 0x1f + irq 0xce = 0xe0 + irq 0xcf = 0x40 + irq 0xd0 = 0x20 + irq 0xd1 = 0x20 + irq 0xd3 = 0x20 + irq 0xe1 = 0x1f + irq 0xf1 = 0xff + end + device pnp 4e.7 on # WDT + io 0x60 = 0xa00 + io 0xf6 = 0xa00 + irq 0x30 = 0x00 + irq 0xf0 = 0x03 # (superiotool.log) + end + device pnp 4e.8 off end # CIR + device pnp 4e.a on # PME, ACPI, Power Saving Registers + # don't get accepted (see ${docs}/cbmem.log) + irq 0x30 = 0x01 # PME Enabled + irq 0xe0 = 0x10 # EuP Enabled + # irq 0xe1 = 0xcc # EuP control register + # irq 0xe2 = 0x0c # EuP control register + # irq 0xe3 = 0x13 # EuP PSIN deb-register + # irq 0xe4 = 0x09 # EuP RSMRST deb-register + # irq 0xe5 = 0xc7 # EuP PSOUT deb-register + # irq 0xe6 = 0x09 # EuP PSON deb-register + # irq 0xe7 = 0x63 # EuP S5 deb-register + # irq 0xe8 = 0x00 # EuP Wakeup Event Enable Register + # irq 0xe9 = 0x0f # EuP S3 Delay register + # irq 0xec = 0x00 # EuP Wakeup Event Enable Register 2 + # irq 0xed = 0xc0 # EuP Watchdog Control Register + # irq 0xee = 0x00 # EuP Watchdog Time Register + # irq 0xf0 = 0x00 # PME Event Enable Register 1 + # irq 0xf2 = 0x00 # PME Event Status Register + irq 0xf4 = 0x04 # Keep Last State Select (06=always.off, 04=always.on, 00=last) + # irq 0xf5 = 0x3c # VDDOK Delay Register + # irq 0xf6 = 0x1f # PCIRST Control Register + # irq 0xf7 = 0x00 # Power Sequence Control Register + irq 0xf8 = 0x00 # LED VCC Mode Select + irq 0xf9 = 0x09 # LED VSB Mode Select + irq 0xfa = 0x00 # LED Mode Select Add + end + end + end + device pci 1f.2 on # SATA Controller 1 + subsystemid 0x1462 0x7707 + end + device pci 1f.3 on # SMBus + subsystemid 0x1462 0x7707 + end + device pci 1f.5 off # SATA Controller 2 + end + device pci 1f.6 off # Thermal + end + end + device pci 00.0 on # Host bridge Host bridge + subsystemid 0x1462 0x7707 + end + device pci 01.0 on # PCIe Bridge for discrete graphics + subsystemid 0x1462 0x7707 + end + device pci 02.0 off # Internal graphics + end + end +end diff --git a/src/mainboard/medion/ms_7707/dsdt.asl b/src/mainboard/medion/ms_7707/dsdt.asl new file mode 100644 index 0000000..8808539 --- /dev/null +++ b/src/mainboard/medion/ms_7707/dsdt.asl @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Tristan Corrick <tristan(a)corrick.kiwi> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI 2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 // OEM revision +) +{ + /* Some generic macros */ + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + /* global NVS and variables. */ + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } +} diff --git a/src/mainboard/medion/ms_7707/gpio.c b/src/mainboard/medion/ms_7707/gpio.c new file mode 100644 index 0000000..8fd8e44 --- /dev/null +++ b/src/mainboard/medion/ms_7707/gpio.c @@ -0,0 +1,189 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_OUTPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_LOW, + .gpio20 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_HIGH, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = {}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = {}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_NATIVE, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_OUTPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio45 = GPIO_LEVEL_HIGH, + .gpio57 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = {}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = {}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = {}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/medion/ms_7707/hda_verb.c b/src/mainboard/medion/ms_7707/hda_verb.c new file mode 100644 index 0000000..6a6cf41 --- /dev/null +++ b/src/mainboard/medion/ms_7707/hda_verb.c @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0887, /* Codec Vendor / Device ID: Realtek */ + 0x14627707, /* Subsystem ID */ + + 0x0000000f, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x0, 0x14627707), + + /* NID 0x11. */ + AZALIA_PIN_CFG(0x0, 0x11, 0x411111f0), + + /* NID 0x12. */ + AZALIA_PIN_CFG(0x0, 0x12, 0x411111f0), + + /* NID 0x14. */ + AZALIA_PIN_CFG(0x0, 0x14, 0x01014410), + + /* NID 0x15. */ + AZALIA_PIN_CFG(0x0, 0x15, 0x01011412), + + /* NID 0x16. */ + AZALIA_PIN_CFG(0x0, 0x16, 0x01016411), + + /* NID 0x17. */ + AZALIA_PIN_CFG(0x0, 0x17, 0x01012414), + + /* NID 0x18. */ + AZALIA_PIN_CFG(0x0, 0x18, 0x01813c40), + + /* NID 0x19. */ + AZALIA_PIN_CFG(0x0, 0x19, 0x02a19c50), + + /* NID 0x1a. */ + AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0), + + /* NID 0x1b. */ + AZALIA_PIN_CFG(0x0, 0x1b, 0x02214c20), + + /* NID 0x1c. */ + AZALIA_PIN_CFG(0x0, 0x1c, 0x411111f0), + + /* NID 0x1d. */ + AZALIA_PIN_CFG(0x0, 0x1d, 0x411111f0), + + /* NID 0x1e. */ + AZALIA_PIN_CFG(0x0, 0x1e, 0x01454130), + + /* NID 0x1f. */ + AZALIA_PIN_CFG(0x0, 0x1f, 0x411111f0), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/medion/ms_7707/mainboard.c b/src/mainboard/medion/ms_7707/mainboard.c new file mode 100644 index 0000000..4e03879 --- /dev/null +++ b/src/mainboard/medion/ms_7707/mainboard.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Tristan Corrick <tristan(a)corrick.kiwi> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <southbridge/intel/bd82x6x/pch.h> + +static void mainboard_enable(struct device *dev) +{ + /* install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); */ +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/medion/ms_7707/romstage.c b/src/mainboard/medion/ms_7707/romstage.c new file mode 100644 index 0000000..5426db4 --- /dev/null +++ b/src/mainboard/medion/ms_7707/romstage.c @@ -0,0 +1,69 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <arch/byteorder.h> +#include <device/pci_ops.h> +#include <device/pci_def.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> + +void pch_enable_lpc(void) +{ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f07); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x00fc0295); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x00000000); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00000000); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000000); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); +} + +void mainboard_rcba_config(void) +{ +} + +const struct southbridge_usb_port mainboard_usb_ports[] = { + {1, 0, 0}, + {1, 0, 0}, + {1, 0, 1}, + {1, 0, 1}, + {1, 0, 2}, + {1, 0, 2}, + {1, 0, 3}, + {1, 0, 3}, + {1, 0, 4}, + {1, 0, 4}, + {1, 0, 6}, + {1, 0, 5}, + {1, 0, 5}, + {1, 0, 6}, +}; + +void mainboard_early_init(int s3resume) +{ +} + +void mainboard_config_superio(void) +{ +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[2], 0x52, id_only); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/32235 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I999149bb95d553ed217b2288cc34bce4fe88abb3 Gerrit-Change-Number: 32235 Gerrit-PatchSet: 1 Gerrit-Owner: Bluemax Gerrit-MessageType: newchange

6 27

Change in ...coreboot[master]: superio/fintek/f71808a: Add more optional ramstage registers
by Max Blau (Code Review) 01 May '19

01 May '19

Max Blau has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32376 Change subject: superio/fintek/f71808a: Add more optional ramstage registers ...................................................................... superio/fintek/f71808a: Add more optional ramstage registers More registers added and made optional so they keep untouched/default if ommitted. Change-Id: I5d8008176d2972976b387c558658b8e70b50af8e Signed-off-by: Max Blau <tripleshiftone(a)gmail.com> --- M src/superio/fintek/f71808a/Makefile.inc M src/superio/fintek/f71808a/chip.h M src/superio/fintek/f71808a/f71808a_hwm.c M src/superio/fintek/f71808a/f71808a_multifunc.c A src/superio/fintek/f71808a/f71808a_pme.c M src/superio/fintek/f71808a/fintek_internal.h 6 files changed, 329 insertions(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/32376/1 diff --git a/src/superio/fintek/f71808a/Makefile.inc b/src/superio/fintek/f71808a/Makefile.inc index f43e602..2bc27b5 100644 --- a/src/superio/fintek/f71808a/Makefile.inc +++ b/src/superio/fintek/f71808a/Makefile.inc @@ -16,4 +16,5 @@ ramstage-$(CONFIG_SUPERIO_FINTEK_F71808A) += f71808a_multifunc.c ramstage-$(CONFIG_SUPERIO_FINTEK_F71808A) += f71808a_hwm.c +ramstage-$(CONFIG_SUPERIO_FINTEK_F71808A) += f71808a_pme.c ramstage-$(CONFIG_SUPERIO_FINTEK_F71808A) += superio.c diff --git a/src/superio/fintek/f71808a/chip.h b/src/superio/fintek/f71808a/chip.h index f4e80ff..6c4a8db 100644 --- a/src/superio/fintek/f71808a/chip.h +++ b/src/superio/fintek/f71808a/chip.h @@ -22,6 +22,10 @@ struct superio_fintek_f71808a_config { + /* Global */ + uint8_t configuration_port_select_0x27; + uint8_t wakeup_control_0x2d; + /* Multi function registers */ uint8_t multi_function_register_0; uint8_t multi_function_register_1; @@ -31,9 +35,16 @@ /* Intel Ibex Peak/PECI/AMD TSI */ uint8_t hwm_peci_tsi_ctrl; + uint8_t hwm_domain1_en_0x0b; uint8_t hwm_tcc_temp; /* Fan 1 control */ + uint8_t hwm_fan1_boundary_hysteresis_0x98; + uint8_t hwm_vt1_boundary_1_temperature_0xa6; + uint8_t hwm_vt1_boundary_2_temperature_0xa7; + uint8_t hwm_vt1_boundary_3_temperature_0xa8; + uint8_t hwm_vt1_boundary_4_temperature_0xa9; + uint8_t hwm_fan1_seg1_speed; uint8_t hwm_fan1_seg2_speed; uint8_t hwm_fan1_seg3_speed; @@ -48,6 +59,34 @@ uint8_t hwm_fan2_seg4_speed; uint8_t hwm_fan2_seg5_speed; uint8_t hwm_fan2_temp_src; + + /* PME */ + uint8_t eup_enable_0xe0; + uint8_t eup_control1_0xe1; + uint8_t eup_control2_0xe2; + uint8_t eup_psin_deb_0xe3; + uint8_t eup_rsmrst_deb_0xe4; + uint8_t eup_psout_deb_0xe5; + uint8_t eup_pson_deb_0xe6; + uint8_t eup_s5_deb_0xe7; + uint8_t eup_wakeup_event_enable1_0xe8; + uint8_t eup_s3_delay_0xe9; + uint8_t eup_wakeup_event_enable2_0xec; + uint8_t eup_watchdog_control_0xed; + uint8_t eup_watchdog_time_0xee; + uint8_t pme_event_enable1_0xf0; + uint8_t pme_event_enable2_0xf1; + uint8_t pme_event_status1_0xf2; + uint8_t pme_event_status2_0xf3; + uint8_t keep_last_state_select_0xf4; + uint8_t vddok_delay_0xf5; + uint8_t pcirst_control_0xf6; + uint8_t power_sequence_control_0xf7; + uint8_t led_vcc_mode_select_0xf8; + uint8_t led_vsb_mode_select_0xf9; + uint8_t led_mode_select_add_0xfa; + uint8_t intel_dsw_delay_select_0xfc; + uint8_t ri_debounce_select_0xfe; }; #endif /* SUPERIO_FINTEK_F71808A_CHIP_H */ diff --git a/src/superio/fintek/f71808a/f71808a_hwm.c b/src/superio/fintek/f71808a/f71808a_hwm.c index a370219..aec6af8 100644 --- a/src/superio/fintek/f71808a/f71808a_hwm.c +++ b/src/superio/fintek/f71808a/f71808a_hwm.c @@ -22,24 +22,30 @@ #include "chip.h" /* Intel Ibex Peak/PECI/AMD TSI */ -#define HWM_PECI_TSI_CTRL_REG 0x0a -#define HWM_TCC_TEMPERATURE_REG 0x0c +#define HWM_PECI_TSI_CTRL_REG 0x0a +#define HWM_DOMAIN1_EN 0x0b +#define HWM_TCC_TEMPERATURE_REG 0x0c /* Fan 1 control */ -#define HWM_FAN1_SEG1_SPEED_REG 0xaa -#define HWM_FAN1_SEG2_SPEED_REG 0xab -#define HWM_FAN1_SEG3_SPEED_REG 0xac -#define HWM_FAN1_SEG4_SPEED_REG 0xad -#define HWM_FAN1_SEG5_SPEED_REG 0xae -#define HWM_FAN1_TEMP_SRC_REG 0xaf +#define HWM_FAN1_BOUNDARY_HYSTERESIS 0x98 +#define HWM_VT1_BOUNDARY_1_TEMPERATURE 0xa6 +#define HWM_VT1_BOUNDARY_2_TEMPERATURE 0xa7 +#define HWM_VT1_BOUNDARY_3_TEMPERATURE 0xa8 +#define HWM_VT1_BOUNDARY_4_TEMPERATURE 0xa9 +#define HWM_FAN1_SEG1_SPEED_REG 0xaa +#define HWM_FAN1_SEG2_SPEED_REG 0xab +#define HWM_FAN1_SEG3_SPEED_REG 0xac +#define HWM_FAN1_SEG4_SPEED_REG 0xad +#define HWM_FAN1_SEG5_SPEED_REG 0xae +#define HWM_FAN1_TEMP_SRC_REG 0xaf /* Fan 2 control */ -#define HWM_FAN2_SEG1_SPEED_REG 0xba -#define HWM_FAN2_SEG2_SPEED_REG 0xbb -#define HWM_FAN2_SEG3_SPEED_REG 0xbc -#define HWM_FAN2_SEG4_SPEED_REG 0xbd -#define HWM_FAN2_SEG5_SPEED_REG 0xbe -#define HWM_FAN2_TEMP_SRC_REG 0xbf +#define HWM_FAN2_SEG1_SPEED_REG 0xba +#define HWM_FAN2_SEG2_SPEED_REG 0xbb +#define HWM_FAN2_SEG3_SPEED_REG 0xbc +#define HWM_FAN2_SEG4_SPEED_REG 0xbd +#define HWM_FAN2_SEG5_SPEED_REG 0xbe +#define HWM_FAN2_TEMP_SRC_REG 0xbf void f71808a_hwm_init(struct device *dev) { @@ -55,32 +61,92 @@ pnp_enter_conf_mode(dev); - pnp_write_index(port, HWM_PECI_TSI_CTRL_REG, reg->hwm_peci_tsi_ctrl); - pnp_write_index(port, HWM_TCC_TEMPERATURE_REG, reg->hwm_tcc_temp); + if (reg->hwm_peci_tsi_ctrl) { + pnp_write_index(port, HWM_PECI_TSI_CTRL_REG, + reg->hwm_peci_tsi_ctrl); + } + if (reg->hwm_tcc_temp) { + pnp_write_index(port, HWM_TCC_TEMPERATURE_REG, + reg->hwm_tcc_temp); + } + if (reg->hwm_domain1_en_0x0b) { + pnp_write_index(port, HWM_DOMAIN1_EN, + reg->hwm_domain1_en_0x0b); + } - pnp_write_index(port, HWM_FAN1_SEG1_SPEED_REG, + /* fan1_speed */ + if (reg->hwm_fan1_seg1_speed) { + pnp_write_index(port, HWM_FAN1_SEG1_SPEED_REG, reg->hwm_fan1_seg1_speed); - pnp_write_index(port, HWM_FAN1_SEG2_SPEED_REG, + } + if (reg->hwm_fan1_seg2_speed) { + pnp_write_index(port, HWM_FAN1_SEG2_SPEED_REG, reg->hwm_fan1_seg2_speed); - pnp_write_index(port, HWM_FAN1_SEG3_SPEED_REG, + } + if (reg->hwm_fan1_seg3_speed) { + pnp_write_index(port, HWM_FAN1_SEG3_SPEED_REG, reg->hwm_fan1_seg3_speed); - pnp_write_index(port, HWM_FAN1_SEG4_SPEED_REG, + } + if (reg->hwm_fan1_seg4_speed) { + pnp_write_index(port, HWM_FAN1_SEG4_SPEED_REG, reg->hwm_fan1_seg4_speed); - pnp_write_index(port, HWM_FAN1_SEG5_SPEED_REG, + } + if (reg->hwm_fan1_seg5_speed) { + pnp_write_index(port, HWM_FAN1_SEG5_SPEED_REG, reg->hwm_fan1_seg5_speed); - pnp_write_index(port, HWM_FAN1_TEMP_SRC_REG, reg->hwm_fan1_temp_src); + } + if (reg->hwm_fan1_temp_src) { + pnp_write_index(port, HWM_FAN1_TEMP_SRC_REG, + reg->hwm_fan1_temp_src); + } - pnp_write_index(port, HWM_FAN2_SEG1_SPEED_REG, + /* fan2_speed */ + if (reg->hwm_fan2_seg1_speed) { + pnp_write_index(port, HWM_FAN2_SEG1_SPEED_REG, reg->hwm_fan2_seg1_speed); - pnp_write_index(port, HWM_FAN2_SEG2_SPEED_REG, + } + if (reg->hwm_fan2_seg2_speed) { + pnp_write_index(port, HWM_FAN2_SEG2_SPEED_REG, reg->hwm_fan2_seg2_speed); - pnp_write_index(port, HWM_FAN2_SEG3_SPEED_REG, + } + if (reg->hwm_fan2_seg3_speed) { + pnp_write_index(port, HWM_FAN2_SEG3_SPEED_REG, reg->hwm_fan2_seg3_speed); - pnp_write_index(port, HWM_FAN2_SEG4_SPEED_REG, + } + if (reg->hwm_fan2_seg4_speed) { + pnp_write_index(port, HWM_FAN2_SEG4_SPEED_REG, reg->hwm_fan2_seg4_speed); - pnp_write_index(port, HWM_FAN2_SEG5_SPEED_REG, + } + if (reg->hwm_fan2_seg5_speed) { + pnp_write_index(port, HWM_FAN2_SEG5_SPEED_REG, reg->hwm_fan2_seg5_speed); - pnp_write_index(port, HWM_FAN2_TEMP_SRC_REG, reg->hwm_fan2_temp_src); + } + if (reg->hwm_fan2_temp_src) { + pnp_write_index(port, HWM_FAN2_TEMP_SRC_REG, + reg->hwm_fan2_temp_src); + } + + /* fan1_boundary_temperatures */ + if (reg->hwm_fan1_boundary_hysteresis_0x98) { + pnp_write_index(port, HWM_FAN1_BOUNDARY_HYSTERESIS, + reg->hwm_fan1_boundary_hysteresis_0x98); + } + if (reg->hwm_vt1_boundary_1_temperature_0xa6) { + pnp_write_index(port, HWM_VT1_BOUNDARY_1_TEMPERATURE, + reg->hwm_vt1_boundary_1_temperature_0xa6); + } + if (reg->hwm_vt1_boundary_2_temperature_0xa7) { + pnp_write_index(port, HWM_VT1_BOUNDARY_2_TEMPERATURE, + reg->hwm_vt1_boundary_2_temperature_0xa7); + } + if (reg->hwm_vt1_boundary_3_temperature_0xa8) { + pnp_write_index(port, HWM_VT1_BOUNDARY_3_TEMPERATURE, + reg->hwm_vt1_boundary_3_temperature_0xa8); + } + if (reg->hwm_vt1_boundary_4_temperature_0xa9) { + pnp_write_index(port, HWM_VT1_BOUNDARY_4_TEMPERATURE, + reg->hwm_vt1_boundary_4_temperature_0xa9); + } pnp_exit_conf_mode(dev); } diff --git a/src/superio/fintek/f71808a/f71808a_multifunc.c b/src/superio/fintek/f71808a/f71808a_multifunc.c index 32119e2..0abb81d 100644 --- a/src/superio/fintek/f71808a/f71808a_multifunc.c +++ b/src/superio/fintek/f71808a/f71808a_multifunc.c @@ -20,11 +20,13 @@ #include "chip.h" #include "fintek_internal.h" +#define CONFIGURATION_PORT_SELECT 0x27 #define MULTI_FUNC_SEL_REG0 0x28 #define MULTI_FUNC_SEL_REG1 0x29 #define MULTI_FUNC_SEL_REG2 0x2A #define MULTI_FUNC_SEL_REG3 0x2B #define MULTI_FUNC_SEL_REG4 0x2C +#define WAKEUP_CONTROL 0x2D void f71808a_multifunc_init(struct device *dev) { @@ -32,25 +34,40 @@ pnp_enter_conf_mode(dev); - /* multi-func select reg0 */ - pnp_write_config(dev, MULTI_FUNC_SEL_REG0, - conf->multi_function_register_0); + if (conf->configuration_port_select_0x27) { + pnp_write_config(dev, CONFIGURATION_PORT_SELECT, + conf->configuration_port_select_0x27); + } - /* multi-func select reg1 */ - pnp_write_config(dev, MULTI_FUNC_SEL_REG1, - conf->multi_function_register_1); + if (conf->wakeup_control_0x2d) { + pnp_write_config(dev, WAKEUP_CONTROL, + conf->wakeup_control_0x2d); + } - /* multi-func select reg2 */ - pnp_write_config(dev, MULTI_FUNC_SEL_REG2, - conf->multi_function_register_2); + if (conf->multi_function_register_0) { + pnp_write_config(dev, MULTI_FUNC_SEL_REG0, + conf->multi_function_register_0); + } - /* multi-func select reg3 */ - pnp_write_config(dev, MULTI_FUNC_SEL_REG3, - conf->multi_function_register_3); + if (conf->multi_function_register_1) { + pnp_write_config(dev, MULTI_FUNC_SEL_REG1, + conf->multi_function_register_1); + } - /* multi-func select reg4 */ - pnp_write_config(dev, MULTI_FUNC_SEL_REG4, - conf->multi_function_register_4); + if (conf->multi_function_register_2) { + pnp_write_config(dev, MULTI_FUNC_SEL_REG2, + conf->multi_function_register_2); + } + + if (conf->multi_function_register_3) { + pnp_write_config(dev, MULTI_FUNC_SEL_REG3, + conf->multi_function_register_3); + } + + if (conf->multi_function_register_4) { + pnp_write_config(dev, MULTI_FUNC_SEL_REG4, + conf->multi_function_register_4); + } pnp_exit_conf_mode(dev); } diff --git a/src/superio/fintek/f71808a/f71808a_pme.c b/src/superio/fintek/f71808a/f71808a_pme.c new file mode 100644 index 0000000..5ce1b67 --- /dev/null +++ b/src/superio/fintek/f71808a/f71808a_pme.c @@ -0,0 +1,162 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * Copyright (C) 2017 Nicola Corna <nicola(a)corna.info> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <device/pnp.h> +#include "chip.h" +#include "fintek_internal.h" + +#define EUP_ENABLE 0xE0 +#define EUP_CONTROL1 0xE1 +#define EUP_CONTROL2 0xE2 +#define EUP_PSIN_DEB 0xE3 +#define EUP_RSMRST_DEB 0xE4 +#define EUP_PSOUT_DEB 0xE5 +#define EUP_PSON_DEB 0xE6 +#define EUP_S5_DEB 0xE7 +#define EUP_WAKEUP_EVENT_ENABLE1 0xE8 +#define EUP_S3_DELAY 0xE9 +#define EUP_WAKEUP_EVENT_ENABLE2 0xEC +#define EUP_WATCHDOG_CONTROL 0xED +#define EUP_WATCHDOG_TIME 0xEE +#define PME_EVENT_ENABLE1 0xF0 +#define PME_EVENT_ENABLE2 0xF1 +#define PME_EVENT_STATUS1 0xF2 +#define PME_EVENT_STATUS2 0xF3 +#define KEEP_LAST_STATE_SELECT 0xF4 +#define VDDOK_DELAY 0xF5 +#define PCIRST_CONTROL 0xF6 +#define POWER_SEQUENCE_CONTROL 0xF7 +#define LED_VCC_MODE_SELECT 0xF8 +#define LED_VSB_MODE_SELECT 0xF9 +#define LED_MODE_SELECT_ADD 0xFA +#define INTEL_DSW_DELAY_SELECT 0xFC +#define RI_DEBOUNCE_SELECT 0xFE + +void f71808a_pme_init(struct device *dev) +{ + const struct superio_fintek_f71808a_config *conf = dev->chip_info; + + pnp_enter_conf_mode(dev); + + if (conf->eup_enable_0xe0) { + pnp_write_config(dev, EUP_ENABLE, + conf->eup_enable_0xe0); + } + if (conf->eup_control1_0xe1) { + pnp_write_config(dev, EUP_CONTROL1, + conf->eup_control1_0xe1); + } + if (conf->eup_control2_0xe2) { + pnp_write_config(dev, EUP_CONTROL2, + conf->eup_control2_0xe2); + } + if (conf->eup_psin_deb_0xe3) { + pnp_write_config(dev, EUP_PSIN_DEB, + conf->eup_psin_deb_0xe3); + } + if (conf->eup_rsmrst_deb_0xe4) { + pnp_write_config(dev, EUP_RSMRST_DEB, + conf->eup_rsmrst_deb_0xe4); + } + if (conf->eup_psout_deb_0xe5) { + pnp_write_config(dev, EUP_PSOUT_DEB, + conf->eup_psout_deb_0xe5); + } + if (conf->eup_pson_deb_0xe6) { + pnp_write_config(dev, EUP_PSON_DEB, + conf->eup_pson_deb_0xe6); + } + if (conf->eup_s5_deb_0xe7) { + pnp_write_config(dev, EUP_S5_DEB, + conf->eup_s5_deb_0xe7); + } + if (conf->eup_wakeup_event_enable1_0xe8) { + pnp_write_config(dev, EUP_WAKEUP_EVENT_ENABLE1, + conf->eup_wakeup_event_enable1_0xe8); + } + if (conf->eup_s3_delay_0xe9) { + pnp_write_config(dev, EUP_S3_DELAY, + conf->eup_s3_delay_0xe9); + } + if (conf->eup_wakeup_event_enable2_0xec) { + pnp_write_config(dev, EUP_WAKEUP_EVENT_ENABLE2, + conf->eup_wakeup_event_enable2_0xec); + } + if (conf->eup_watchdog_control_0xed) { + pnp_write_config(dev, EUP_WATCHDOG_CONTROL, + conf->eup_watchdog_control_0xed); + } + if (conf->eup_watchdog_time_0xee) { + pnp_write_config(dev, EUP_WATCHDOG_TIME, + conf->eup_watchdog_time_0xee); + } + if (conf->pme_event_enable1_0xf0) { + pnp_write_config(dev, PME_EVENT_ENABLE1, + conf->pme_event_enable1_0xf0); + } + if (conf->pme_event_enable2_0xf1) { + pnp_write_config(dev, PME_EVENT_ENABLE2, + conf->pme_event_enable2_0xf1); + } + if (conf->pme_event_status1_0xf2) { + pnp_write_config(dev, PME_EVENT_STATUS1, + conf->pme_event_status1_0xf2); + } + if (conf->pme_event_status2_0xf3) { + pnp_write_config(dev, PME_EVENT_STATUS2, + conf->pme_event_status2_0xf3); + } + if (conf->keep_last_state_select_0xf4) { + pnp_write_config(dev, KEEP_LAST_STATE_SELECT, + conf->keep_last_state_select_0xf4); + } + if (conf->vddok_delay_0xf5) { + pnp_write_config(dev, VDDOK_DELAY, + conf->vddok_delay_0xf5); + } + if (conf->pcirst_control_0xf6) { + pnp_write_config(dev, PCIRST_CONTROL, + conf->pcirst_control_0xf6); + } + if (conf->power_sequence_control_0xf7) { + pnp_write_config(dev, POWER_SEQUENCE_CONTROL, + conf->power_sequence_control_0xf7); + } + if (conf->led_vcc_mode_select_0xf8) { + pnp_write_config(dev, LED_VCC_MODE_SELECT, + conf->led_vcc_mode_select_0xf8); + } + if (conf->led_vsb_mode_select_0xf9) { + pnp_write_config(dev, LED_VSB_MODE_SELECT, + conf->led_vsb_mode_select_0xf9); + } + if (conf->led_mode_select_add_0xfa) { + pnp_write_config(dev, LED_MODE_SELECT_ADD, + conf->led_mode_select_add_0xfa); + } + if (conf->intel_dsw_delay_select_0xfc) { + pnp_write_config(dev, INTEL_DSW_DELAY_SELECT, + conf->intel_dsw_delay_select_0xfc); + } + if (conf->ri_debounce_select_0xfe) { + pnp_write_config(dev, RI_DEBOUNCE_SELECT, + conf->ri_debounce_select_0xfe); + } + + pnp_exit_conf_mode(dev); +} diff --git a/src/superio/fintek/f71808a/fintek_internal.h b/src/superio/fintek/f71808a/fintek_internal.h index 7bdb94d..28a77a0 100644 --- a/src/superio/fintek/f71808a/fintek_internal.h +++ b/src/superio/fintek/f71808a/fintek_internal.h @@ -22,5 +22,6 @@ void f71808a_multifunc_init(struct device *dev); void f71808a_hwm_init(struct device *dev); +void f71808a_pme_init(struct device *dev); #endif /* SUPERIO_FINTEK_F71808A_INTERNAL_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32376 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5d8008176d2972976b387c558658b8e70b50af8e Gerrit-Change-Number: 32376 Gerrit-PatchSet: 1 Gerrit-Owner: Max Blau Gerrit-MessageType: newchange

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coreboot-gerrit May 2019