coreboot-gerrit May 2019

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Change in ...coreboot[master]: soc/intel/icelake: Clear PMCON status bits
by Subrata Banik (Code Review) 02 May '19

02 May '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32503 Change subject: soc/intel/icelake: Clear PMCON status bits ...................................................................... soc/intel/icelake: Clear PMCON status bits This patch ports CB:31902 changes from CNL to ICL. The prev_sleep_state value was showing 5 even after warm reboot, once the SUS_PWR_FLR bit is being set. This bit was not being cleared. Hence clearing the PMCON status bits. Change-Id: Ia07aa17b4491216a277c36edfe6ed2aa489287c6 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/icelake/finalize.c M src/soc/intel/icelake/include/soc/pm.h M src/soc/intel/icelake/pmutil.c 3 files changed, 19 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/32503/1 diff --git a/src/soc/intel/icelake/finalize.c b/src/soc/intel/icelake/finalize.c index c1e6dd0..e061cda 100644 --- a/src/soc/intel/icelake/finalize.c +++ b/src/soc/intel/icelake/finalize.c @@ -87,6 +87,8 @@ } pch_handle_sideband(config); + + pmc_clear_pmcon_sts(); } static void soc_finalize(void *unused) diff --git a/src/soc/intel/icelake/include/soc/pm.h b/src/soc/intel/icelake/include/soc/pm.h index 9caf49f..44888ec 100644 --- a/src/soc/intel/icelake/include/soc/pm.h +++ b/src/soc/intel/icelake/include/soc/pm.h @@ -168,5 +168,8 @@ /* Set the DISB after DRAM init */ void pmc_set_disb(void); +/* Clear PMCON status bits */ +void pmc_clear_pmcon_sts(void); + #endif /* !defined(__ACPI__) */ #endif diff --git a/src/soc/intel/icelake/pmutil.c b/src/soc/intel/icelake/pmutil.c index 96ff52d..e1b1665 100644 --- a/src/soc/intel/icelake/pmutil.c +++ b/src/soc/intel/icelake/pmutil.c @@ -141,6 +141,20 @@ write8(addr, disb_val); } +void pmc_clear_pmcon_sts(void) +{ + uint32_t reg_val; + uint8_t *addr; + addr = pmc_mmio_regs(); + + reg_val = read32(addr + GEN_PMCON_A); + /* Clear SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits + * while retaining MS4V write-1-to-clear bit */ + reg_val &= ~(MS4V); + + write32((addr + GEN_PMCON_A), reg_val); +} + /* * PMC controller gets hidden from PCI bus * during FSP-Silicon init call. Hence PWRMBASE -- To view, visit https://review.coreboot.org/c/coreboot/+/32503 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia07aa17b4491216a277c36edfe6ed2aa489287c6 Gerrit-Change-Number: 32503 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: x86emu: add console.h header to fix compilation
by Martin Kepplinger (Code Review) 02 May '19

02 May '19

Martin Kepplinger has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32499 Change subject: x86emu: add console.h header to fix compilation ...................................................................... x86emu: add console.h header to fix compilation Commit 351e3e5 ("src: Use include <console/console.h> when appropriate") has broken the build here, see below, so we include console.h again for x86emu. In file included from src/device/oprom/x86emu/x86emui.h:65, from src/device/oprom/x86emu/debug.c:40: src/device/oprom/x86emu/debug.c: In function 'x86emu_dump_regs': src/device/oprom/x86emu/debug.h:46:22: error: implicit declaration of function 'printk'; did you mean 'printf'? [-Werror=implicit-function-declaration] #define printf(x...) printk(BIOS_DEBUG, x) ^~~~~~ src/device/oprom/x86emu/debug.c:366:5: note: in expansion of macro 'printf' printf("\tAX=%04x ", M.x86.R_AX ); ^~~~~~ Fixes: 351e3e5 ("src: Use include <console/console.h> when appropriate") Change-Id: I75d0b7c08bfa6dcb07778bbb762223b62cfc3da7 Signed-off-by: Martin Kepplinger <martink(a)posteo.de> --- M src/device/oprom/include/x86emu/x86emu.h 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/32499/1 diff --git a/src/device/oprom/include/x86emu/x86emu.h b/src/device/oprom/include/x86emu/x86emu.h index 4ae82d9..fa23e55 100644 --- a/src/device/oprom/include/x86emu/x86emu.h +++ b/src/device/oprom/include/x86emu/x86emu.h @@ -42,6 +42,7 @@ #define __X86EMU_X86EMU_H #include <stddef.h> +#include <console/console.h> #if CONFIG(X86EMU_DEBUG) #define DEBUG #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/32499 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I75d0b7c08bfa6dcb07778bbb762223b62cfc3da7 Gerrit-Change-Number: 32499 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Kepplinger <martink(a)posteo.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/sarien: Add SMBIOS type 9 fields
by Lijian Zhao (Code Review) 01 May '19

01 May '19

Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32389 ) Change subject: mb/google/sarien: Add SMBIOS type 9 fields ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/#/c/32389/2/src/soc/intel/cannonlake/chip.h File src/soc/intel/cannonlake/chip.h: https://review.coreboot.org/#/c/32389/2/src/soc/intel/cannonlake/chip.h@24 PS2, Line 24: #include <smbios.h> > Actually I don't think that's needed any more. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/32389 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I47a697131b7aeeb64e0c4b4c0556842f1cb1b02e Gerrit-Change-Number: 32389 Gerrit-PatchSet: 3 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Comment-Date: Wed, 01 May 2019 22:34:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: HAOUAS Elyes <ehaouas(a)noos.fr> Comment-In-Reply-To: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/sarien: Add SMBIOS type 9 fields
by Lijian Zhao (Code Review) 01 May '19

01 May '19

Hello Patrick Rudolph, EricR Lai, Paul Menzel, Bora Guvendik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/32389 to look at the new patch set (#3). Change subject: mb/google/sarien: Add SMBIOS type 9 fields ...................................................................... mb/google/sarien: Add SMBIOS type 9 fields Fill SMBIOS type 9 fields for both sarien and arcada platform. BUG=b:129485789 TEST=Boot up into OS and check with dmidecode -t 9 to we do have entry. Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> Change-Id: I47a697131b7aeeb64e0c4b4c0556842f1cb1b02e --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb 2 files changed, 10 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/32389/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/32389 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I47a697131b7aeeb64e0c4b4c0556842f1cb1b02e Gerrit-Change-Number: 32389 Gerrit-PatchSet: 3 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: mb/google/sarien: Add SMBIOS type 9 fields
by Lijian Zhao (Code Review) 01 May '19

01 May '19

Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32389 ) Change subject: mb/google/sarien: Add SMBIOS type 9 fields ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/32389/2/src/soc/intel/cannonlake/chip.h File src/soc/intel/cannonlake/chip.h: https://review.coreboot.org/#/c/32389/2/src/soc/intel/cannonlake/chip.h@24 PS2, Line 24: #include <smbios.h> > Please why this is included ? Actually I don't think that's needed any more. -- To view, visit https://review.coreboot.org/c/coreboot/+/32389 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I47a697131b7aeeb64e0c4b4c0556842f1cb1b02e Gerrit-Change-Number: 32389 Gerrit-PatchSet: 2 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Comment-Date: Wed, 01 May 2019 22:33:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: comment

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Change in ...coreboot[master]: sdm845: Port I2C driver
by Julius Werner (Code Review) 01 May '19

01 May '19

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29104 ) Change subject: sdm845: Port I2C driver ...................................................................... Patch Set 32: (1 comment) https://review.coreboot.org/#/c/29104/31/src/soc/qualcomm/sdm845/qcom_qup_s… File src/soc/qualcomm/sdm845/qcom_qup_se.c: https://review.coreboot.org/#/c/29104/31/src/soc/qualcomm/sdm845/qcom_qup_s… PS31, Line 118: > Similar indentation we use in our HLOS driver and it looks good to us. […] The problem here is just that the second line is so far over to the right compared to the first line. How did you decide to do exactly 5 tabs? That just seems arbitrary... I thought maybe this used to line up with the previous line in an earlier version but then you shortened the name of the function and forgot to realign the second line. In general, there's no hard rule on this but the two most common versions are - Fill to 80 and indent all continuation lines 1 tab no matter what: int my_sample_func(int param1, int param2, int param3, int param4, int param5, int param6) - Fill to 80 and align continuation lines to opening parenthesis int my_sample_func(int param1, int param2, int param3, int param4, int param5, int param6) (Note that should be 2 tabs and 3 spaces in the second example.) -- To view, visit https://review.coreboot.org/c/coreboot/+/29104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifb76564d8a11427423dd14d8ba7c8c7d500ef346 Gerrit-Change-Number: 29104 Gerrit-PatchSet: 32 Gerrit-Owner: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: Akash Asthana <akashast(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: T Michael Turney <mturney(a)codeaurora.org> Gerrit-Reviewer: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 01 May 2019 20:15:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Akash Asthana <akashast(a)qualcomm.corp-partner.google.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/sarien: Disable S5 wake on LAN by default
by EricR Lai (Code Review) 01 May '19

01 May '19

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32502 Change subject: mb/google/sarien: Disable S5 wake on LAN by default ...................................................................... mb/google/sarien: Disable S5 wake on LAN by default Chromebook doesn't require support wake on LAN in S5. Disable it by default for power saving. BUG=b:131571666 TEST= check LAN indicator is off under S5 Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: Ia90c9d2f3ea9b3580e9a7bbfb47c917dd51e3c03 --- M src/mainboard/google/sarien/variants/sarien/devicetree.cb M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/fsp_params.c 3 files changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/32502/1 diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 96146ba..0cdd9d0 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -52,6 +52,9 @@ # Enable DDC for DDI port B register "DdiPortBDdc" = "1" + register "LanWakeFromDeepSx" = "0" + register "WolEnableOverride" = "0" + # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------+-------+ #| Domain/Setting | SA | IA | GTUS | GTS | diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 9bba226..ca44085 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -400,6 +400,8 @@ /* Unlock all GPIO Pads */ uint8_t PchUnlockGpioPads; + uint8_t LanWakeFromDeepSx; + uint8_t WolEnableOverride; }; typedef struct soc_intel_cannonlake_config config_t; diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 61d2520..cc01d10 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -212,6 +212,10 @@ params->DdiPortDDdc = config->DdiPortDDdc; params->DdiPortFDdc = config->DdiPortFDdc; + /* WOL */ + params->PchPmPcieWakeFromDeepSx = config->LanWakeFromDeepSx; + params->PchPmWolEnableOverride = config->WolEnableOverride; + /* S0ix */ params->PchPmSlpS0Enable = config->s0ix_enable; -- To view, visit https://review.coreboot.org/c/coreboot/+/32502 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia90c9d2f3ea9b3580e9a7bbfb47c917dd51e3c03 Gerrit-Change-Number: 32502 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: sdm845: Add QCLib to RomStage to perform IP init
by Julius Werner (Code Review) 01 May '19

01 May '19

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25208 ) Change subject: sdm845: Add QCLib to RomStage to perform IP init ...................................................................... Patch Set 77: Code-Review+2 (1 comment) https://review.coreboot.org/#/c/25208/76/src/soc/qualcomm/sdm845/qclib.c File src/soc/qualcomm/sdm845/qclib.c: https://review.coreboot.org/#/c/25208/76/src/soc/qualcomm/sdm845/qclib.c@43 PS76, Line 43: if (size < 0) > Ack […] Assigning the signed result to an unsigned variable would be -Wconversion, that's a huge hammer that we'll probably not be able to enable any time soon (because that happens all the time). But we might be able to catch the if (unsigned_var < 0) case with -Wtype-limits, I'll look into that if I find some time. -- To view, visit https://review.coreboot.org/c/coreboot/+/25208 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I073186674a1a593547d1ee1d15c7cd4fd8ad5bc1 Gerrit-Change-Number: 25208 Gerrit-PatchSet: 77 Gerrit-Owner: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: T Michael Turney <mturney(a)codeaurora.org> Gerrit-Reviewer: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Wed, 01 May 2019 20:04:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: T Michael Turney <mturney(a)codeaurora.org> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in ...coreboot[master]: smbios: Add memory type 9 system slot support
by Lijian Zhao (Code Review) 01 May '19

01 May '19

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32293 Change subject: smbios: Add memory type 9 system slot support ...................................................................... smbios: Add memory type 9 system slot support Add SMBIOS type 9 system slots into coreboot, the definiation is up to date with SMBIOS spec 3.2 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> Change-Id: Ibcfa377c260083203c1daf5562e103001f76b257 --- M src/arch/x86/smbios.c M src/include/smbios.h 2 files changed, 169 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/32293/1 diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 44ff578..10feb15 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -827,6 +827,32 @@ return len; } +int smbios_write_type9(unsigned long *current, int *handle, + const char *name, u8 type, u8 slot_char1, + u8 slot_char2, u8 bus, u8 dev_func) +{ + struct smbios_type9 *t = (struct smbios_type9 *)*current; + int len = sizeof(struct smbios_type9); + + memset(t, 0, sizeof(struct smbios_type9)); + t->type = SMBIOS_SYSTEM_SLOTS; + t->handle = *handle; + t->length = len - 2; + t->slot_designation = smbios_add_string(t->eos, name); + t->slot_type = type; + t->slot_data_bus_width = SlotDataBusWidthOther; + t->current_usage = SlotUsageAvailable; + t->slot_length = SlotLengthOther; + t->slot_characteristics_1 = slot_char1; + t->slot_characteristics_2 = slot_char2; + t->bus_number = bus; + t->device_function_number = dev_func; + + len = t->length + smbios_string_table_len(t->eos); + *current += len; + *handle += 1; + return len; +} static int smbios_write_type11(unsigned long *current, int *handle) { diff --git a/src/include/smbios.h b/src/include/smbios.h index 08e6b61..70d8179 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -25,6 +25,9 @@ int smbios_string_table_len(u8 *start); /* Used by mainboard to add an on-board device */ +int smbios_write_type9(unsigned long *current, int *handle, + const char *name, u8 type, u8 slot_char1, + u8 slot_char2, u8 bus, u8 dev_func); enum smbios_bmc_interface_type; int smbios_write_type38(unsigned long *current, int *handle, const enum smbios_bmc_interface_type interface_type, @@ -480,6 +483,146 @@ u8 eos[2]; } __packed; +/* System Slots - Slot Type */ +enum misc_slot_type { + SlotTypeOther = 0x01, + SlotTypeUnknown = 0x02, + SlotTypeIsa = 0x03, + SlotTypeMca = 0x04, + SlotTypeEisa = 0x05, + SlotTypePci = 0x06, + SlotTypePcmcia = 0x07, + SlotTypeVlVesa = 0x08, + SlotTypeProprietary = 0x09, + SlotTypeProcessorCardSlot = 0x0A, + SlotTypeProprietaryMemoryCardSlot = 0x0B, + SlotTypeIORiserCardSlot = 0x0C, + SlotTypeNuBus = 0x0D, + SlotTypePci66MhzCapable = 0x0E, + SlotTypeAgp = 0x0F, + SlotTypeApg2X = 0x10, + SlotTypeAgp4X = 0x11, + SlotTypePciX = 0x12, + SlotTypeAgp8X = 0x13, + SlotTypeM2Socket1_DP = 0x14, + SlotTypeM2Socket1_SD = 0x15, + SlotTypeM2Socket2 = 0x16, + SlotTypeM2Socket3 = 0x17, + SlotTypeMxmTypeI = 0x18, + SlotTypeMxmTypeII = 0x19, + SlotTypeMxmTypeIIIStandard = 0x1A, + SlotTypeMxmTypeIIIHe = 0x1B, + SlotTypeMxmTypeIV = 0x1C, + SlotTypeMxm30TypeA = 0x1D, + SlotTypeMxm30TypeB = 0x1E, + SlotTypePciExpressGen2Sff_8639 = 0x1F, + SlotTypePciExpressGen3Sff_8639 = 0x20, + SlotTypePciExpressMini52pinWithBSKO = 0x21, + SlotTypePciExpressMini52pinWithoutBSKO = 0x22, + SlotTypePciExpressMini76pin = 0x23, + SlotTypePC98C20 = 0xA0, + SlotTypePC98C24 = 0xA1, + SlotTypePC98E = 0xA2, + SlotTypePC98LocalBus = 0xA3, + SlotTypePC98Card = 0xA4, + SlotTypePciExpress = 0xA5, + SlotTypePciExpressX1 = 0xA6, + SlotTypePciExpressX2 = 0xA7, + SlotTypePciExpressX4 = 0xA8, + SlotTypePciExpressX8 = 0xA9, + SlotTypePciExpressX16 = 0xAA, + SlotTypePciExpressGen2 = 0xAB, + SlotTypePciExpressGen2X1 = 0xAC, + SlotTypePciExpressGen2X2 = 0xAD, + SlotTypePciExpressGen2X4 = 0xAE, + SlotTypePciExpressGen2X8 = 0xAF, + SlotTypePciExpressGen2X16 = 0xB0, + SlotTypePciExpressGen3 = 0xB1, + SlotTypePciExpressGen3X1 = 0xB2, + SlotTypePciExpressGen3X2 = 0xB3, + SlotTypePciExpressGen3X4 = 0xB4, + SlotTypePciExpressGen3X8 = 0xB5, + SlotTypePciExpressGen3X16 = 0xB6 +}; + +/* System Slots - Slot Data Bus Width. */ +enum slot_data_bus_bandwidth { + SlotDataBusWidthOther = 0x01, + SlotDataBusWidthUnknown = 0x02, + SlotDataBusWidth8Bit = 0x03, + SlotDataBusWidth16Bit = 0x04, + SlotDataBusWidth32Bit = 0x05, + SlotDataBusWidth64Bit = 0x06, + SlotDataBusWidth128Bit = 0x07, + SlotDataBusWidth1X = 0x08, + SlotDataBusWidth2X = 0x09, + SlotDataBusWidth4X = 0x0A, + SlotDataBusWidth8X = 0x0B, + SlotDataBusWidth12X = 0x0C, + SlotDataBusWidth16X = 0x0D, + SlotDataBusWidth32X = 0x0E +}; + +/* System Slots - Current Usage. */ +enum mist_slot_usage { + SlotUsageOther = 0x01, + SlotUsageUnknown = 0x02, + SlotUsageAvailable = 0x03, + SlotUsageInUse = 0x04, + SlotUsageUnavailable = 0x05 +}; + +/* System Slots - Slot Length.*/ +enum misc_slot_length { + SlotLengthOther = 0x01, + SlotLengthUnknown = 0x02, + SlotLengthShort = 0x03, + SlotLengthLong = 0x04 +}; + +/* System Slots - Slot Characteristics 1. */ +#define SMBIOS_SLOT_UNKNOWN (1 << 0) +#define SMBIOS_SLOT_5V (1 << 1) +#define SMBIOS_SLOT_3P3V (1 << 2) +#define SMBIOS_SLOT_SHARED (1 << 3) +#define SMBIOS_SLOT_PCCARD_16 (1 << 4) +#define SMBIOS_SLOT_PCCARD_CARDBUS (1 << 5) +#define SMBIOS_SLOT_PCCARD_ZOOM (1 << 6) +#define SMBIOS_SLOT_PCCARD_MODEM_RING (1 << 7) +/* System Slots - Slot Characteristics 2. */ +#define SMBIOS_SLOT_PME (1 << 0) +#define SMBIOS_SLOT_HOTPLUG (1 << 1) +#define SMBIOS_SLOT_SMBUS (1 << 2) +#define SMBIOS_SLOT_BIFURCATION (1 << 3) + +struct slot_peer_groups { + u16 peer_seg_num; + u8 peer_bus_num; + u8 peer_dev_fn_num; + u8 peer_data_bus_width; +} __packed; + +struct smbios_type9 { + u8 type; + u8 length; + u16 handle; + u8 slot_designation; + u8 slot_type; + u8 slot_data_bus_width; + u8 current_usage; + u8 slot_length; + u16 slot_id; + u8 slot_characteristics_1; + u8 slot_characteristics_2; + u16 segment_group_number; + u8 bus_number; + u8 device_function_number; + u8 data_bus_width; + u8 peer_group_count; + struct slot_peer_groups peer[1]; + u8 eos[2]; +} __packed; + struct smbios_type11 { u8 type; u8 length; -- To view, visit https://review.coreboot.org/c/coreboot/+/32293 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibcfa377c260083203c1daf5562e103001f76b257 Gerrit-Change-Number: 32293 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: google/cyan,intel/strago: increase default CBFS size
by Matt DeVillier (Code Review) 01 May '19

01 May '19

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32525 Change subject: google/cyan,intel/strago: increase default CBFS size ...................................................................... google/cyan,intel/strago: increase default CBFS size a 1M CBFS size is inadequate when adding the FSP binary to image due to default FSP location in CBFS, so bump to 2M to ensure autobuilds succeed. Change-Id: I0683bea43cc71fad32bc42bfbd72f3913256d53c Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/cyan/Kconfig M src/mainboard/intel/strago/Kconfig 2 files changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/32525/1 diff --git a/src/mainboard/google/cyan/Kconfig b/src/mainboard/google/cyan/Kconfig index 1d9b7b7..b3c6790 100644 --- a/src/mainboard/google/cyan/Kconfig +++ b/src/mainboard/google/cyan/Kconfig @@ -107,4 +107,8 @@ default "ULTIMA TEST A-A 6017" if BOARD_GOOGLE_ULTIMA default "WIZPIG TEST A-A 0597" if BOARD_GOOGLE_WIZPIG +config CBFS_SIZE + hex + default 0x200000 + endif # BOARD_GOOGLE_BASEBOARD_CYAN diff --git a/src/mainboard/intel/strago/Kconfig b/src/mainboard/intel/strago/Kconfig index 4aa7640..da04d78 100644 --- a/src/mainboard/intel/strago/Kconfig +++ b/src/mainboard/intel/strago/Kconfig @@ -58,4 +58,9 @@ string depends on CHROMEOS default "STRAGO TEST A-A 9657" + +config CBFS_SIZE + hex + default 0x200000 + endif # BOARD_INTEL_STRAGO -- To view, visit https://review.coreboot.org/c/coreboot/+/32525 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0683bea43cc71fad32bc42bfbd72f3913256d53c Gerrit-Change-Number: 32525 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit May 2019