coreboot-gerrit May 2019

coreboot-gerrit@coreboot.org

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1485 discussions

Change in ...coreboot[master]: sdm845: Port I2C driver
by Akash Asthana (Code Review) 01 May '19

01 May '19

Akash Asthana has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29104 ) Change subject: sdm845: Port I2C driver ...................................................................... Patch Set 31: (8 comments) I will share the final changes with Mike to upload here. Can you please answer the query on indentation. https://review.coreboot.org/#/c/29104/31/src/soc/qualcomm/sdm845/i2c.c File src/soc/qualcomm/sdm845/i2c.c: https://review.coreboot.org/#/c/29104/31/src/soc/qualcomm/sdm845/i2c.c@44 PS31, Line 44: struct qup_i2c_clk_fld *itr = qup_i2c_clk_map + idx; > When you rewrite this to use the generic enum (see other file), I'd write this stuff like this inste […] Done https://review.coreboot.org/#/c/29104/31/src/soc/qualcomm/sdm845/i2c.c@89 PS31, Line 89: (BITS_PER_WORD >> 4)); > What about rewriting this to log2(BITS_PER_WORD) - 3? You said "Done" to that, but it looks like you […] Sorry about it, I should've mentioned that changes are not yet shared here. https://review.coreboot.org/#/c/29104/31/src/soc/qualcomm/sdm845/i2c.c@130 PS31, Line 130: segment.buf, segment.buf > Note that if you combine the three size parameters into one like I'm suggesting in the other file, y […] Done https://review.coreboot.org/#/c/29104/31/src/soc/qualcomm/sdm845/include/so… File src/soc/qualcomm/sdm845/include/soc/i2c.h: https://review.coreboot.org/#/c/29104/31/src/soc/qualcomm/sdm845/include/so… PS31, Line 23: }; > Actually, looks like we have an existing enum for this in <device/i2c.h> (I2C_SPEED_FAST, etc. […] Done https://review.coreboot.org/#/c/29104/31/src/soc/qualcomm/sdm845/qcom_qup_s… File src/soc/qualcomm/sdm845/qcom_qup_se.c: https://review.coreboot.org/#/c/29104/31/src/soc/qualcomm/sdm845/qcom_qup_s… PS31, Line 101: u32 wait_till_irq_set(unsigned int bus) > I think all of these functions other than qup_isr_handle() could be static? […] Done, We want to export handle_error and wait_till_irq_set functions as well, I have renamed them as suggested. https://review.coreboot.org/#/c/29104/31/src/soc/qualcomm/sdm845/qcom_qup_s… PS31, Line 118: > Please fix indentation. Similar indentation we use in our HLOS driver and it looks good to us. Not sure whether any fixed rule exists here to break a line having more than 80 characters. How do you suggest to indent here? https://review.coreboot.org/#/c/29104/31/src/soc/qualcomm/sdm845/qcom_qup_s… PS31, Line 184: qup_isr_handle > "ISR handle" sounds a bit weird for that this function actually does (which is handle a full transfe […] Done https://review.coreboot.org/#/c/29104/31/src/soc/qualcomm/sdm845/qcom_qup_s… PS31, Line 185: unsigned int tx_rem_bytes, unsigned int rx_rem_bytes) > You shouldn't need to pass all of size, tx_rem_bytes and rx_rem_bytes. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/29104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifb76564d8a11427423dd14d8ba7c8c7d500ef346 Gerrit-Change-Number: 29104 Gerrit-PatchSet: 31 Gerrit-Owner: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: Akash Asthana <akashast(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: T Michael Turney <mturney(a)codeaurora.org> Gerrit-Reviewer: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 01 May 2019 12:37:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in ...coreboot[master]: sdm845: Add SPI QUP driver
by Akash Asthana (Code Review) 01 May '19

01 May '19

Akash Asthana has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27483 ) Change subject: sdm845: Add SPI QUP driver ...................................................................... Patch Set 51: (3 comments) Will share the changes with Mike to upload here. https://review.coreboot.org/#/c/27483/51/src/mainboard/google/cheza/bootblo… File src/mainboard/google/cheza/bootblock.c: https://review.coreboot.org/#/c/27483/51/src/mainboard/google/cheza/bootblo… PS51, Line 19: #include <soc/qcom_qup_se.h> > nit: please order alphabetically Done https://review.coreboot.org/#/c/27483/51/src/soc/qualcomm/sdm845/spi_qup.c File src/soc/qualcomm/sdm845/spi_qup.c: https://review.coreboot.org/#/c/27483/51/src/soc/qualcomm/sdm845/spi_qup.c@… PS51, Line 150: /n" > I think this is supposed to be a \n? Done https://review.coreboot.org/#/c/27483/51/src/soc/qualcomm/sdm845/spi_qup.c@… PS51, Line 153: } > You should actually return an error value here which you can then pass out of qup_spi_claim_bus(). Done -- To view, visit https://review.coreboot.org/c/coreboot/+/27483 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35061727d5ccc550eaeb06caef4524bc4cf25b54 Gerrit-Change-Number: 27483 Gerrit-PatchSet: 51 Gerrit-Owner: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mukesh Savaliya <msavaliy(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: T Michael Turney <mturney(a)codeaurora.org> Gerrit-Reviewer: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: Vin Kamath <vink(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Akash Asthana <akashast(a)qualcomm.corp-partner.google.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Wed, 01 May 2019 12:34:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in ...coreboot[master]: (drivers,soc/intel/braswell}: Add C_ENVIRONMENT_BOOTBLOCK support
by Frans Hendriks (Code Review) 01 May '19

01 May '19

Hello Patrick Rudolph, Huang Jin, Arthur Heymans, York Yang, Lee Leahy, build bot (Jenkins), Hannah Williams, Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29662 to look at the new patch set (#13). Change subject: (drivers,soc/intel/braswell}: Add C_ENVIRONMENT_BOOTBLOCK support ...................................................................... (drivers,soc/intel/braswell}: Add C_ENVIRONMENT_BOOTBLOCK support No C_ENVIRONMENT_BOOTBLOCK support for Braswell is available. Enable support and add required files for the Braswell Bootblock in C. The next changes are made support C_ENVIRONMENT_BOOTBLOCK: - Add post init console functions romstage_c_entry() . - Add car_stage_entry() function bootblock-c_entry() functions. - Specify config DCACHE_BSP_STACK_SIZE and C_ENV_BOOTBLOCK_SIZE. - Add bootblokc_c_entry(). Remove the unused cache_as_ram_main(). BUG=NA TEST=Booting Embedded Linux on Facebook FBG-1701 Change-Id: Iab48ad72f1514c93f20d70db5ef4fd8fa2383e8c Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/drivers/intel/fsp1_1/Makefile.inc M src/drivers/intel/fsp1_1/car.c M src/drivers/intel/fsp1_1/include/fsp/car.h M src/soc/intel/braswell/Kconfig M src/soc/intel/braswell/Makefile.inc M src/soc/intel/braswell/bootblock/bootblock.c R src/soc/intel/braswell/bootblock/cache_as_ram.S M src/soc/intel/braswell/romstage/Makefile.inc A src/soc/intel/braswell/romstage/car_stage_entry.S 9 files changed, 93 insertions(+), 171 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/29662/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/29662 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab48ad72f1514c93f20d70db5ef4fd8fa2383e8c Gerrit-Change-Number: 29662 Gerrit-PatchSet: 13 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: York Yang <yyang024(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: cpu/intel/car/p3: Update microcode in CAR setup
by HAOUAS Elyes (Code Review) 01 May '19

01 May '19

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30776 ) Change subject: cpu/intel/car/p3: Update microcode in CAR setup ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/30776 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f31f7f30d6ce970d3616c12dbb264b2cf070ed9 Gerrit-Change-Number: 30776 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 01 May 2019 11:20:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: (drivers,soc/intel/braswell}: Add C_ENVIRONMENT_BOOTBLOCK support
by Frans Hendriks (Code Review) 01 May '19

01 May '19

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Change in ...coreboot[master]: (drivers,soc/intel/braswell}: Add C_ENVIRONMENT_BOOTBLOCK support
by Frans Hendriks (Code Review) 01 May '19

01 May '19

Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29662 ) Change subject: (drivers,soc/intel/braswell}: Add C_ENVIRONMENT_BOOTBLOCK support ...................................................................... Patch Set 12: (2 comments) https://review.coreboot.org/#/c/29662/9/src/soc/intel/braswell/bootblock/bo… File src/soc/intel/braswell/bootblock/bootblock.c: https://review.coreboot.org/#/c/29662/9/src/soc/intel/braswell/bootblock/bo… PS9, Line 76: > See how it is done in src/cpu/intel/car/non-evict/cache_as_ram. […] I dont understand your comment. This file is not used in latest patch. file soc/intel/braswell/bootblock/cache_as_ram.S calls FSP TempRamInit API. The FSP API will handle microcode update. Do you want to handle microcode update at another place also? https://review.coreboot.org/#/c/29662/11/src/soc/intel/braswell/bootblock/c… File src/soc/intel/braswell/bootblock/cache_as_ram.S: https://review.coreboot.org/#/c/29662/11/src/soc/intel/braswell/bootblock/c… PS11, Line 12: either version 2 of the License, or : * (at your option) any later version. > Have you asked the previous copyright owners if they want to change the license? Have copied this notice from other file which I assumed is the standard. Will revert this change. -- To view, visit https://review.coreboot.org/c/coreboot/+/29662 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab48ad72f1514c93f20d70db5ef4fd8fa2383e8c Gerrit-Change-Number: 29662 Gerrit-PatchSet: 12 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: York Yang <yyang024(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 01 May 2019 09:18:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: sb/intel/bd82x6x/early_pch: Make use of RCBA and DMIBAR marcros
by HAOUAS Elyes (Code Review) 01 May '19

01 May '19

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32072 ) Change subject: sb/intel/bd82x6x/early_pch: Make use of RCBA and DMIBAR marcros ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/32072 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9be2240ea10b17c8cc289007dccadbb9e3f69ab Gerrit-Change-Number: 32072 Gerrit-PatchSet: 7 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 01 May 2019 07:36:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: (drivers,soc/intel/braswell}: Add C_ENVIRONMENT_BOOTBLOCK support
by Patrick Rudolph (Code Review) 01 May '19

01 May '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29662 ) Change subject: (drivers,soc/intel/braswell}: Add C_ENVIRONMENT_BOOTBLOCK support ...................................................................... Patch Set 12: (1 comment) https://review.coreboot.org/#/c/29662/12/src/drivers/intel/fsp1_1/car.c File src/drivers/intel/fsp1_1/car.c: https://review.coreboot.org/#/c/29662/12/src/drivers/intel/fsp1_1/car.c@a104 PS12, Line 104: car_soc_pre_console_init() car_mainboard_pre_console_init() are missing here -- To view, visit https://review.coreboot.org/c/coreboot/+/29662 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab48ad72f1514c93f20d70db5ef4fd8fa2383e8c Gerrit-Change-Number: 29662 Gerrit-PatchSet: 12 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: York Yang <yyang024(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 01 May 2019 06:43:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: sdm845: Add QCLib to RomStage to perform IP init
by Julius Werner (Code Review) 01 May '19

01 May '19

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25208 ) Change subject: sdm845: Add QCLib to RomStage to perform IP init ...................................................................... Patch Set 76: (5 comments) LGTM after fixing the size_t/ssize_t thing. https://review.coreboot.org/#/c/25208/76/src/mainboard/google/cheza/chromeo… File src/mainboard/google/cheza/chromeos.fmd: https://review.coreboot.org/#/c/25208/76/src/mainboard/google/cheza/chromeo… PS76, Line 27: ( nit: flags are normally written without space before the parenthesis (compare COREBOOT(CBFS) above). https://review.coreboot.org/#/c/25208/76/src/soc/qualcomm/sdm845/include/so… File src/soc/qualcomm/sdm845/include/soc/memlayout.ld: https://review.coreboot.org/#/c/25208/76/src/soc/qualcomm/sdm845/include/so… PS76, Line 31: 8192 nit: 8K https://review.coreboot.org/#/c/25208/69/src/soc/qualcomm/sdm845/include/so… File src/soc/qualcomm/sdm845/include/soc/qclib.h: https://review.coreboot.org/#/c/25208/69/src/soc/qualcomm/sdm845/include/so… PS69, Line 52: #define QCLIB_GA_ENABLE_UART_LOGGING 0x00000001 > OK, we will keep deprecated in list moving forward. […] Yeah, it doesn't really matter, it just makes it easier for me because I don't always get the new QcLib releases as soon as you do. (Which reminds me, I'm still on r38... any chance we could unblock the next one now?) https://review.coreboot.org/#/c/25208/76/src/soc/qualcomm/sdm845/qclib.c File src/soc/qualcomm/sdm845/qclib.c: https://review.coreboot.org/#/c/25208/76/src/soc/qualcomm/sdm845/qclib.c@43 PS76, Line 43: if (size < 0) This must be a different variable that's ssize_t. https://review.coreboot.org/#/c/25208/69/src/soc/qualcomm/sdm845/qclib_exec… File src/soc/qualcomm/sdm845/qclib_execute.c: https://review.coreboot.org/#/c/25208/69/src/soc/qualcomm/sdm845/qclib_exec… PS69, Line 1: /* > I think I addressed all of the earlier comments when I created the common/ patch. […] Yes, I think it's all good now, thanks. -- To view, visit https://review.coreboot.org/c/coreboot/+/25208 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I073186674a1a593547d1ee1d15c7cd4fd8ad5bc1 Gerrit-Change-Number: 25208 Gerrit-PatchSet: 76 Gerrit-Owner: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: T Michael Turney <mturney(a)codeaurora.org> Gerrit-Reviewer: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Wed, 01 May 2019 06:11:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: T Michael Turney <mturney(a)codeaurora.org> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in ...coreboot[master]: sdm845: Add USB support on cheza platform
by Julius Werner (Code Review) 01 May '19

01 May '19

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25213 ) Change subject: sdm845: Add USB support on cheza platform ...................................................................... Patch Set 70: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/25213 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I475a7757239acb8ef22a4d61afd59b304a7f0acc Gerrit-Change-Number: 25213 Gerrit-PatchSet: 70 Gerrit-Owner: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: Ciluveru chandana kishori <cchiluve(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: T Michael Turney <mturney(a)codeaurora.org> Gerrit-Reviewer: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Chandana Kishori Chiluveru <cchiluve(a)qualcomm.corp-partner.google.com> Gerrit-Comment-Date: Wed, 01 May 2019 05:42:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit May 2019