coreboot-gerrit May 2019

coreboot-gerrit@coreboot.org

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1485 discussions

Change in ...coreboot[master]: sdm845: Combine BB with QC-Sec for ROM boot
by mturney mturney (Code Review) 02 May '19

02 May '19

mturney mturney has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25207 ) Change subject: sdm845: Combine BB with QC-Sec for ROM boot ...................................................................... Patch Set 76: Julius, please confirm this is ready to go, now that binary blobs have been removed from this patch. -- To view, visit https://review.coreboot.org/c/coreboot/+/25207 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I222a56f1c9b74856a1e1ff8132bab5e041672c5d Gerrit-Change-Number: 25207 Gerrit-PatchSet: 76 Gerrit-Owner: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Thu, 02 May 2019 20:35:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/sarien: Add SMBIOS type 9 fields
by HAOUAS Elyes (Code Review) 02 May '19

02 May '19

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32389 ) Change subject: mb/google/sarien: Add SMBIOS type 9 fields ...................................................................... Patch Set 5: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/32389 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I47a697131b7aeeb64e0c4b4c0556842f1cb1b02e Gerrit-Change-Number: 32389 Gerrit-PatchSet: 5 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 02 May 2019 20:32:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/sarien: Add SMBIOS type 9 fields
by Lijian Zhao (Code Review) 02 May '19

02 May '19

Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32389 ) Change subject: mb/google/sarien: Add SMBIOS type 9 fields ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/#/c/32389/2/src/soc/intel/cannonlake/chip.h File src/soc/intel/cannonlake/chip.h: https://review.coreboot.org/#/c/32389/2/src/soc/intel/cannonlake/chip.h@24 PS2, Line 24: #include <smbios.h> > where please ? Compare to https://review.coreboot.org/c/coreboot/+/32309/ -- To view, visit https://review.coreboot.org/c/coreboot/+/32389 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I47a697131b7aeeb64e0c4b4c0556842f1cb1b02e Gerrit-Change-Number: 32389 Gerrit-PatchSet: 5 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Comment-Date: Thu, 02 May 2019 20:04:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: HAOUAS Elyes <ehaouas(a)noos.fr> Comment-In-Reply-To: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/sarien: Add SMBIOS type 9 fields
by HAOUAS Elyes (Code Review) 02 May '19

02 May '19

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32389 ) Change subject: mb/google/sarien: Add SMBIOS type 9 fields ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/32389/2/src/soc/intel/cannonlake/chip.h File src/soc/intel/cannonlake/chip.h: https://review.coreboot.org/#/c/32389/2/src/soc/intel/cannonlake/chip.h@24 PS2, Line 24: #include <smbios.h> > I see, because they are using the numbers directly to avoid get defines in smbios. […] where please ? -- To view, visit https://review.coreboot.org/c/coreboot/+/32389 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I47a697131b7aeeb64e0c4b4c0556842f1cb1b02e Gerrit-Change-Number: 32389 Gerrit-PatchSet: 2 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Comment-Date: Thu, 02 May 2019 19:47:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: HAOUAS Elyes <ehaouas(a)noos.fr> Comment-In-Reply-To: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/sarien: Add SMBIOS type 9 fields
by Lijian Zhao (Code Review) 02 May '19

02 May '19

Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32389 ) Change subject: mb/google/sarien: Add SMBIOS type 9 fields ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/#/c/32389/2/src/soc/intel/cannonlake/chip.h File src/soc/intel/cannonlake/chip.h: https://review.coreboot.org/#/c/32389/2/src/soc/intel/cannonlake/chip.h@24 PS2, Line 24: #include <smbios.h> > It looks that's still needed, how come the similar changes for lenovo can get it pass? I see, because they are using the numbers directly to avoid get defines in smbios.h, then the header file is still needed. -- To view, visit https://review.coreboot.org/c/coreboot/+/32389 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I47a697131b7aeeb64e0c4b4c0556842f1cb1b02e Gerrit-Change-Number: 32389 Gerrit-PatchSet: 5 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Comment-Date: Thu, 02 May 2019 17:49:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: HAOUAS Elyes <ehaouas(a)noos.fr> Comment-In-Reply-To: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/sarien: Add SMBIOS type 9 fields
by Lijian Zhao (Code Review) 02 May '19

02 May '19

Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32389 ) Change subject: mb/google/sarien: Add SMBIOS type 9 fields ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/#/c/32389/2/src/soc/intel/cannonlake/chip.h File src/soc/intel/cannonlake/chip.h: https://review.coreboot.org/#/c/32389/2/src/soc/intel/cannonlake/chip.h@24 PS2, Line 24: #include <smbios.h> > Done It looks that's still needed, how come the similar changes for lenovo can get it pass? -- To view, visit https://review.coreboot.org/c/coreboot/+/32389 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I47a697131b7aeeb64e0c4b4c0556842f1cb1b02e Gerrit-Change-Number: 32389 Gerrit-PatchSet: 5 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Comment-Date: Thu, 02 May 2019 17:37:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: HAOUAS Elyes <ehaouas(a)noos.fr> Comment-In-Reply-To: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/sarien: Add SMBIOS type 9 fields
by Lijian Zhao (Code Review) 02 May '19

02 May '19

Hello Patrick Rudolph, EricR Lai, Paul Menzel, Bora Guvendik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/32389 to look at the new patch set (#5). Change subject: mb/google/sarien: Add SMBIOS type 9 fields ...................................................................... mb/google/sarien: Add SMBIOS type 9 fields Fill SMBIOS type 9 fields for both sarien and arcada platform. BUG=b:129485789 TEST=Boot up into OS and check with dmidecode -t 9 to we do have entry. Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> Change-Id: I47a697131b7aeeb64e0c4b4c0556842f1cb1b02e --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb M src/soc/intel/cannonlake/chip.h 3 files changed, 13 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/32389/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/32389 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I47a697131b7aeeb64e0c4b4c0556842f1cb1b02e Gerrit-Change-Number: 32389 Gerrit-PatchSet: 5 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: TEMP: NOT FOR REVIEW: qcs405: Add bl31 stage and elf
by build bot (Jenkins) (Code Review) 02 May '19

02 May '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29981 ) Change subject: TEMP: NOT FOR REVIEW: qcs405: Add bl31 stage and elf ...................................................................... Patch Set 22: (1 comment) https://review.coreboot.org/#/c/29981/22/src/soc/qualcomm/qcs405/soc.c File src/soc/qualcomm/qcs405/soc.c: https://review.coreboot.org/#/c/29981/22/src/soc/qualcomm/qcs405/soc.c@26 PS22, Line 26: bootmem_add_range((uintptr_t)_dram_reserved, _dram_reserved_size, BM_MEM_BL31); line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/29981 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I967c0b78a3561574609bf8332a22838c85e43429 Gerrit-Change-Number: 29981 Gerrit-PatchSet: 22 Gerrit-Owner: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 02 May 2019 16:11:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: TEMP: NOT FOR REVIEW: qclib: Add qclib support
by Nitheesh Sekar (Code Review) 02 May '19

02 May '19

Hello Julius Werner, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29967 to look at the new patch set (#23). Change subject: TEMP: NOT FOR REVIEW: qclib: Add qclib support ...................................................................... TEMP: NOT FOR REVIEW: qclib: Add qclib support Add to load and execute qclib blob to configure pmic, clocks and ddr. This is the basic support without one-training and interface table to pass data between coreboot and qclib. That would be added later. Change-Id: I534af71163d034ea04420dda6a94ce31b08c8a07 Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> --- M src/mainboard/google/mistral/Makefile.inc M src/mainboard/google/mistral/romstage.c M src/soc/qualcomm/qcs405/Makefile.inc M src/soc/qualcomm/qcs405/include/soc/memlayout.ld M src/soc/qualcomm/qcs405/include/soc/mmu.h A src/soc/qualcomm/qcs405/include/soc/qclib.h M src/soc/qualcomm/qcs405/include/soc/symbols.h M src/soc/qualcomm/qcs405/mmu.c A src/soc/qualcomm/qcs405/qclib_execute.c 9 files changed, 154 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/29967/23 -- To view, visit https://review.coreboot.org/c/coreboot/+/29967 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I534af71163d034ea04420dda6a94ce31b08c8a07 Gerrit-Change-Number: 29967 Gerrit-PatchSet: 23 Gerrit-Owner: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Sricharan Ramabadhran <srichara(a)qualcomm.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: soc/apollolake: Add ramstage hook
by Felix Singer (Code Review) 02 May '19

02 May '19

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32543 ) Change subject: soc/apollolake: Add ramstage hook ...................................................................... Patch Set 2: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/32543 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9edc543943c5cbc696fc6c615cb77ef68294c980 Gerrit-Change-Number: 32543 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 02 May 2019 13:18:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit May 2019