coreboot-gerrit May 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: TEMP: NOT FOR REVIEW: qcs405: Add bl31 stage and elf
by build bot (Jenkins) (Code Review) 03 May '19

03 May '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29981 ) Change subject: TEMP: NOT FOR REVIEW: qcs405: Add bl31 stage and elf ...................................................................... Patch Set 23: (1 comment) https://review.coreboot.org/#/c/29981/23/src/soc/qualcomm/qcs405/soc.c File src/soc/qualcomm/qcs405/soc.c: https://review.coreboot.org/#/c/29981/23/src/soc/qualcomm/qcs405/soc.c@26 PS23, Line 26: bootmem_add_range((uintptr_t)_dram_reserved, _dram_reserved_size, BM_MEM_BL31); line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/29981 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I967c0b78a3561574609bf8332a22838c85e43429 Gerrit-Change-Number: 29981 Gerrit-PatchSet: 23 Gerrit-Owner: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 03 May 2019 15:00:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: nb/intel/haswell: correct a typo in Kconfig
by Joel Kitching (Code Review) 03 May '19

03 May '19

Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32518 Change subject: nb/intel/haswell: correct a typo in Kconfig ...................................................................... nb/intel/haswell: correct a typo in Kconfig Change-Id: I115e065ce11946b85571e7233203be68c1789d70 Signed-off-by: Joel Kitching <kitching(a)google.com> --- M src/northbridge/intel/haswell/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/32518/1 diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index 8c1e0b1..e1067c5 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -37,7 +37,7 @@ Haswell can either start verstage in a separate stage right after the bootblock has run or it can start it after romstage for compatibility reasons. - Haswell however uses a mrc.bin to initialse memory which + Haswell however uses a mrc.bin to initialize memory which needs to be located at a fixed offset. Therefore even with a separate verstage starting after the bootblock that same binary is used meaning a jump is made from RW to the RO region -- To view, visit https://review.coreboot.org/c/coreboot/+/32518 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I115e065ce11946b85571e7233203be68c1789d70 Gerrit-Change-Number: 32518 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/braswell/chip.c: Configure LPSS devices in correct mode
by Frans Hendriks (Code Review) 03 May '19

03 May '19

Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29284 ) Change subject: soc/intel/braswell/chip.c: Configure LPSS devices in correct mode ...................................................................... Patch Set 11: (1 comment) > Patch Set 11: > > (1 comment) https://review.coreboot.org/#/c/29284/11//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/29284/11//COMMIT_MSG@27 PS11, Line 27: devices/connections are available. > Shouldn't there at least be an OS driver that detects […] Linux is reporting 'i2c /dev entries driver' but I could not check if the controllers are working. I think we still talk along eachother. This fix is just a correction when devicetree.cb is incorrect. If you prefer to drop this change, no problem. (We can still use this fix for our projects/customers) -- To view, visit https://review.coreboot.org/c/coreboot/+/29284 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie271d8cb9f30f0c0ba538f1530cfb82f1306fea8 Gerrit-Change-Number: 29284 Gerrit-PatchSet: 11 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Fri, 03 May 2019 13:56:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/braswell/chip.c: Configure LPSS devices in correct mode
by Nico Huber (Code Review) 03 May '19

03 May '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29284 ) Change subject: soc/intel/braswell/chip.c: Configure LPSS devices in correct mode ...................................................................... Patch Set 11: (1 comment) https://review.coreboot.org/#/c/29284/11//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/29284/11//COMMIT_MSG@27 PS11, Line 27: devices/connections are available. Shouldn't there at least be an OS driver that detects the device? If we have no means to confirm if it's working (and expect it to break coreboot mechanisms), maybe just drop this change. -- To view, visit https://review.coreboot.org/c/coreboot/+/29284 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie271d8cb9f30f0c0ba538f1530cfb82f1306fea8 Gerrit-Change-Number: 29284 Gerrit-PatchSet: 11 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Fri, 03 May 2019 13:43:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/apollolake: Add ramstage hook
by Felix Singer (Code Review) 03 May '19

03 May '19

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32543 ) Change subject: soc/apollolake: Add ramstage hook ...................................................................... Patch Set 5: (1 comment) This change is ready for review. https://review.coreboot.org/#/c/32543/3/src/soc/intel/apollolake/include/so… File src/soc/intel/apollolake/include/soc/ramstage.h: https://review.coreboot.org/#/c/32543/3/src/soc/intel/apollolake/include/so… PS3, Line 6: * Copyright (C) 2019 9elements Cyber Security > 9elements Agency GmbH Done -- To view, visit https://review.coreboot.org/c/coreboot/+/32543 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9edc543943c5cbc696fc6c615cb77ef68294c980 Gerrit-Change-Number: 32543 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 03 May 2019 11:42:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/apollolake: Add ramstage hook
by Felix Singer (Code Review) 03 May '19

03 May '19

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32543 ) Change subject: soc/apollolake: Add ramstage hook ...................................................................... Patch Set 4: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/32543 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9edc543943c5cbc696fc6c615cb77ef68294c980 Gerrit-Change-Number: 32543 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 03 May 2019 11:39:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: sdm845: Add SPI QUP driver
by Akash Asthana (Code Review) 03 May '19

03 May '19

Akash Asthana has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27483 ) Change subject: sdm845: Add SPI QUP driver ...................................................................... Patch Set 51: Need clarification: We are using a common header file(qcom_qup_se.h) across I2C, SPI and UART drivers in CB. We need to have a similar common header in DC as well for I2C and SPI driver. What would be the ideal location to keep those common files (qcom_qup_se.h, qcom_qup_se.c) in DC. We are thinking to create a new folder "include" inside depthcharge/src/drivers/bus, to keep all the common files there. What do you say about it? -- To view, visit https://review.coreboot.org/c/coreboot/+/27483 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35061727d5ccc550eaeb06caef4524bc4cf25b54 Gerrit-Change-Number: 27483 Gerrit-PatchSet: 51 Gerrit-Owner: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mukesh Savaliya <msavaliy(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: Vin Kamath <vink(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Akash Asthana <akashast(a)qualcomm.corp-partner.google.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Fri, 03 May 2019 10:56:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: {drivers,soc/intel/braswell}: Add C_ENVIRONMENT_BOOTBLOCK support
by Patrick Rudolph (Code Review) 03 May '19

03 May '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29662 ) Change subject: {drivers,soc/intel/braswell}: Add C_ENVIRONMENT_BOOTBLOCK support ...................................................................... Patch Set 15: > Patch Set 15: > > The latest patches do not build. Jenskins report 'Cache as RAM area is too full' On Goolge Cyan and Intel Strago. > > In latest patch set I have increased DCACHE_RAM_SIZE to 0x6000, and was able to build local. > Is there there a way to retrieve the .config file Jenkins used for building? > > Any other hint/advice how to correct this build error? Intel Strago seems to suffer from a VERSTAGE problem. Jenkins builds the default config of every board as well as all configurations in configs/. For ChromeOS boards it builds with and without ChromeOS enabled. -- To view, visit https://review.coreboot.org/c/coreboot/+/29662 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab48ad72f1514c93f20d70db5ef4fd8fa2383e8c Gerrit-Change-Number: 29662 Gerrit-PatchSet: 15 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: York Yang <yyang024(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 03 May 2019 10:44:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: drivers/intel/fsp1_1: Configure UART after memory init
by Patrick Rudolph (Code Review) 03 May '19

03 May '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28464 ) Change subject: drivers/intel/fsp1_1: Configure UART after memory init ...................................................................... Patch Set 4: > Patch Set 4: > > > Patch Set 4: > > > > A "new" version of the FSP was released. Please test if it fixes your issue. > > The new FSP 1.1.8.0 still does not fix the issue. This patch set is still required. Thanks for testing. -- To view, visit https://review.coreboot.org/c/coreboot/+/28464 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb6c9e4153b3de58791b211c7f4241be3bceae9d Gerrit-Change-Number: 28464 Gerrit-PatchSet: 4 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Fri, 03 May 2019 10:39:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: drivers/intel/fsp1_1: Configure UART after memory init
by Frans Hendriks (Code Review) 03 May '19

03 May '19

Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28464 ) Change subject: drivers/intel/fsp1_1: Configure UART after memory init ...................................................................... Patch Set 4: > Patch Set 4: > > A "new" version of the FSP was released. Please test if it fixes your issue. The new FSP 1.1.8.0 still does not fix the issue. This patch set is still required. -- To view, visit https://review.coreboot.org/c/coreboot/+/28464 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb6c9e4153b3de58791b211c7f4241be3bceae9d Gerrit-Change-Number: 28464 Gerrit-PatchSet: 4 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Fri, 03 May 2019 10:37:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit May 2019