coreboot-gerrit May 2019

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Change in ...coreboot[master]: cbfstool: Add ifittool
by Patrick Rudolph (Code Review) 04 May '19

04 May '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31493 ) Change subject: cbfstool: Add ifittool ...................................................................... Patch Set 12: (16 comments) https://review.coreboot.org/#/c/31493/11/util/cbfstool/fit.c File util/cbfstool/fit.c: https://review.coreboot.org/#/c/31493/11/util/cbfstool/fit.c@a132 PS11, Line 132: > We can still assume that it contains at least the header. Done https://review.coreboot.org/#/c/31493/11/util/cbfstool/fit.c@45 PS11, Line 45: and must be set to 0 > Only until a platform starts to use them. It seems at least APL does. Then they violate the spec. https://review.coreboot.org/#/c/31493/11/util/cbfstool/fit.c@58 PS11, Line 58: * Bit 7 indicates whether component has valid checksum. > mention C_V? as it's referred to as that below Done https://review.coreboot.org/#/c/31493/11/util/cbfstool/fit.c@182 PS11, Line 182: but only mentioned on page 22 of > It is mentioned below "FIT Ordering Rules" in all specifications I know. Ack https://review.coreboot.org/#/c/31493/11/util/cbfstool/fit.c@188 PS11, Line 188: if (fit_table_entries(fit) <= 1) : return; > What difference does it make? None. Removed. https://review.coreboot.org/#/c/31493/11/util/cbfstool/fit.c@256 PS11, Line 256: cbfs_file_get_header(&buf, &header); > `buf.offset` (and `. […] Done https://review.coreboot.org/#/c/31493/11/util/cbfstool/fit.c@263 PS11, Line 263: ssize_t > why not `size_t`? Done https://review.coreboot.org/#/c/31493/11/util/cbfstool/fit.c@264 PS11, Line 264: total_entries > isn't this more like `max_entries`? Done https://review.coreboot.org/#/c/31493/11/util/cbfstool/fit.c@332 PS11, Line 332: zero or multiple > or one? […] Done https://review.coreboot.org/#/c/31493/11/util/cbfstool/fit.c@443 PS11, Line 443: entires > entries Done https://review.coreboot.org/#/c/31493/11/util/cbfstool/fit.c@443 PS11, Line 443: ERROR("Maximum of FIT entires reached.\n"); > free(mcus); Done https://review.coreboot.org/#/c/31493/11/util/cbfstool/fit.c@450 PS11, Line 450: mcus[i].offset), > NB. Looking through the code this still only works if the CBFS is memory […] Nobody cared until this point. https://review.coreboot.org/#/c/31493/11/util/cbfstool/fit.c@459 PS11, Line 459: > sort? no as fit_add_entry sorts already https://review.coreboot.org/#/c/31493/11/util/cbfstool/fit.c@480 PS11, Line 480: fit_pointer[1] != 0 > Any hint that it's a 64-bit pointer? otherwise it wouldn't be specified what […] @Aaron As you added the code, where do you got this from? https://review.coreboot.org/#/c/31493/11/util/cbfstool/fit.c@533 PS11, Line 533: break; > `break` is usually indented. Done https://review.coreboot.org/#/c/31493/11/util/cbfstool/fit.c@571 PS11, Line 571: lx > PRIx64 Done -- To view, visit https://review.coreboot.org/c/coreboot/+/31493 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0fe8cd70611d58823aca1147d5b830722ed72bd5 Gerrit-Change-Number: 31493 Gerrit-PatchSet: 12 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Amol N Sukerkar <amol.n.sukerkar(a)intel.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jens Drenhaus <jens.drenhaus(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kai Michaelis <kai.michaelis(a)9elements.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Roy Wen <rgzwen(a)arista.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Sat, 04 May 2019 07:05:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in ...coreboot[master]: cbfstool: Add ifittool
by build bot (Jenkins) (Code Review) 04 May '19

04 May '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31493 ) Change subject: cbfstool: Add ifittool ...................................................................... Patch Set 12: (2 comments) https://review.coreboot.org/#/c/31493/12/util/cbfstool/fit.h File util/cbfstool/fit.h: https://review.coreboot.org/#/c/31493/12/util/cbfstool/fit.h@77 PS12, Line 77: const char *microcode_blob_name, unsigned int empty_entries, line over 80 characters https://review.coreboot.org/#/c/31493/12/util/cbfstool/fit.c File util/cbfstool/fit.c: https://review.coreboot.org/#/c/31493/12/util/cbfstool/fit.c@750 PS12, Line 750: const char *microcode_blob_name, unsigned int empty_entries, line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/31493 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0fe8cd70611d58823aca1147d5b830722ed72bd5 Gerrit-Change-Number: 31493 Gerrit-PatchSet: 12 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Amol N Sukerkar <amol.n.sukerkar(a)intel.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jens Drenhaus <jens.drenhaus(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kai Michaelis <kai.michaelis(a)9elements.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Roy Wen <rgzwen(a)arista.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Sat, 04 May 2019 07:04:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: cbfstool: Add ifittool
by Patrick Rudolph (Code Review) 04 May '19

04 May '19

Hello Aaron Durbin, Julius Werner, Subrata Banik, Duncan Laurie, build bot (Jenkins), Kai Michaelis, Patrick Georgi, Furquan Shaikh, Amol N Sukerkar, Roy Wen, David Hendricks, Philipp Deppenwiese, Nico Huber, Martin Roth, Jens Drenhaus, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/31493 to look at the new patch set (#12). Change subject: cbfstool: Add ifittool ...................................................................... cbfstool: Add ifittool Add the IntelFirmwareInterfaceTable-tool to modify the FIT. As cbfstool is overloaded with arguments, introduce a new tool to only modify FIT, which brings it's own command line syntax. Provide clean interface to: * Clear FIT * Add entry to CBFS file * Add entry to REGION * Delete entries * Add support for types other than 1 * Add support to dump current table * Add support for top-swap * Sort entries by type Most code is reused from existing cbfstool and functionality of cbfstool is kept. It will be removed once the make system uses only ifittool. Based on "Intel Trusted Execution Technology (Intel TXT) LAB Handout" and https://github.com/slimbootloader/slimbootloader . Change-Id: I0fe8cd70611d58823aca1147d5b830722ed72bd5 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M util/cbfstool/Makefile M util/cbfstool/Makefile.inc M util/cbfstool/fit.c M util/cbfstool/fit.h A util/cbfstool/ifittool.c 5 files changed, 1,096 insertions(+), 142 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/31493/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/31493 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0fe8cd70611d58823aca1147d5b830722ed72bd5 Gerrit-Change-Number: 31493 Gerrit-PatchSet: 12 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Amol N Sukerkar <amol.n.sukerkar(a)intel.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jens Drenhaus <jens.drenhaus(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kai Michaelis <kai.michaelis(a)9elements.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Roy Wen <rgzwen(a)arista.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: cbfstool: Drop update-fit option
by Patrick Rudolph (Code Review) 04 May '19

04 May '19

Hello Patrick Rudolph, Aaron Durbin, Julius Werner, Subrata Banik, Duncan Laurie, build bot (Jenkins), Kai Michaelis, Patrick Georgi, Furquan Shaikh, Amol N Sukerkar, Roy Wen, David Hendricks, Philipp Deppenwiese, Martin Roth, Jens Drenhaus, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/31496 to look at the new patch set (#11). Change subject: cbfstool: Drop update-fit option ...................................................................... cbfstool: Drop update-fit option The ifittool is used instead. Drop old code. Change-Id: I70fec5fef9ffd1ba3049badb398783f31aefb02f Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/Kconfig M util/cbfstool/Makefile.inc M util/cbfstool/cbfstool.c M util/cbfstool/fit.c M util/cbfstool/fit.h 5 files changed, 1 insertion(+), 169 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/31496/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/31496 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70fec5fef9ffd1ba3049badb398783f31aefb02f Gerrit-Change-Number: 31496 Gerrit-PatchSet: 11 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Amol N Sukerkar <amol.n.sukerkar(a)intel.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jens Drenhaus <jens.drenhaus(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kai Michaelis <kai.michaelis(a)9elements.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Roy Wen <rgzwen(a)arista.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: soc/intel/common/block/cpu: Use core apic id to get cpu_index()
by Patrick Rudolph (Code Review) 04 May '19

04 May '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/26346 ) Change subject: soc/intel/common/block/cpu: Use core apic id to get cpu_index() ...................................................................... Patch Set 10: > Patch Set 10: > > (1 comment) > > > Why is it needed? As far as I understand FSP 2.1, that introduced > > MP_SERVICES_PPI, also introduced shared stack when selecting > > FSP_USES_CB_STACK. > > Simply select FSP_USES_CB_STACK when using MP_SERVICES_PPI should > > fix the issue. > > The reason is that, on FSP2.0 platform also we might need to enable MP PPI feature but same stack sharing concept might not applied on FSP 2.0 enabled platform, hence we are looking for some solution to bypass stack dependencies. Reading the commit message of https://review.coreboot.org/c/coreboot/+/30310 it sounds like MP PPI feature is only available on FSP2.1. Is it available on all FSP2.0 platforms as well? -- To view, visit https://review.coreboot.org/c/coreboot/+/26346 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I55023a3e0cf42f0496d45bc6af8ead447f402350 Gerrit-Change-Number: 26346 Gerrit-PatchSet: 10 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Sat, 04 May 2019 06:50:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/common/block/cpu: Use core apic id to get cpu_index()
by HAOUAS Elyes (Code Review) 04 May '19

04 May '19

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/26346 ) Change subject: soc/intel/common/block/cpu: Use core apic id to get cpu_index() ...................................................................... Patch Set 10: (1 comment) https://review.coreboot.org/#/c/26346/10/src/soc/intel/common/block/cpu/cpu… File src/soc/intel/common/block/cpu/cpulib.c: https://review.coreboot.org/#/c/26346/10/src/soc/intel/common/block/cpu/cpu… PS10, Line 26: #include <arch/cpu.h> duplicated ? -- To view, visit https://review.coreboot.org/c/coreboot/+/26346 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I55023a3e0cf42f0496d45bc6af8ead447f402350 Gerrit-Change-Number: 26346 Gerrit-PatchSet: 10 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Sat, 04 May 2019 05:40:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/common/block/cpu: Use core apic id to get cpu_index()
by Subrata Banik (Code Review) 04 May '19

04 May '19

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/26346 ) Change subject: soc/intel/common/block/cpu: Use core apic id to get cpu_index() ...................................................................... Patch Set 10: (1 comment) > Why is it needed? As far as I understand FSP 2.1, that introduced > MP_SERVICES_PPI, also introduced shared stack when selecting > FSP_USES_CB_STACK. > Simply select FSP_USES_CB_STACK when using MP_SERVICES_PPI should > fix the issue. The reason is that, on FSP2.0 platform also we might need to enable MP PPI feature but same stack sharing concept might not applied on FSP 2.0 enabled platform, hence we are looking for some solution to bypass stack dependencies. https://review.coreboot.org/#/c/26346/10/src/soc/intel/common/block/cpu/cpu… File src/soc/intel/common/block/cpu/cpulib.c: https://review.coreboot.org/#/c/26346/10/src/soc/intel/common/block/cpu/cpu… PS10, Line 327: unsigned long cpu_index(void) > will this function work for all x86 that exist? I believe it will. […] true, i believe this function qualify good to enable on all x86 platform -- To view, visit https://review.coreboot.org/c/coreboot/+/26346 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I55023a3e0cf42f0496d45bc6af8ead447f402350 Gerrit-Change-Number: 26346 Gerrit-PatchSet: 10 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Sat, 04 May 2019 02:57:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/braswell/southcluster.c: Correct typo in comment
by Frans Hendriks (Code Review) 04 May '19

04 May '19

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32453 Change subject: soc/intel/braswell/southcluster.c: Correct typo in comment ...................................................................... soc/intel/braswell/southcluster.c: Correct typo in comment BUG=N/A TEST=build Change-Id: I1b207e0b77bac8860ba7501378297c1f3604141c Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/soc/intel/braswell/southcluster.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/32453/1 diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c index 000790d..bf9f689 100644 --- a/src/soc/intel/braswell/southcluster.c +++ b/src/soc/intel/braswell/southcluster.c @@ -347,7 +347,7 @@ * Common code for the south cluster devices. */ -/* Set bit in function disble register to hide this device. */ +/* Set bit in function disable register to hide this device. */ static void sc_disable_devfn(struct device *dev) { void *func_dis = (void *)(PMC_BASE_ADDRESS + FUNC_DIS); -- To view, visit https://review.coreboot.org/c/coreboot/+/32453 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1b207e0b77bac8860ba7501378297c1f3604141c Gerrit-Change-Number: 32453 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mainboard/google/cyan/acpi: Method _CRS must be Serialized
by Frans Hendriks (Code Review) 04 May '19

04 May '19

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32331 Change subject: mainboard/google/cyan/acpi: Method _CRS must be Serialized ...................................................................... mainboard/google/cyan/acpi: Method _CRS must be Serialized IASL report warning 'Control Method should be made Serialized'. Change _CRS method to Serialized. BUG=N/A TEST=Build Google Banon and Google Cyan Change-Id: Iffa097a2100cfa91efa3b617311500b83f839bce Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/mainboard/google/cyan/acpi/codec_maxim.asl M src/mainboard/google/cyan/acpi/codec_realtek.asl 2 files changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/32331/1 diff --git a/src/mainboard/google/cyan/acpi/codec_maxim.asl b/src/mainboard/google/cyan/acpi/codec_maxim.asl index 81bec16..9319791 100644 --- a/src/mainboard/google/cyan/acpi/codec_maxim.asl +++ b/src/mainboard/google/cyan/acpi/codec_maxim.asl @@ -3,6 +3,7 @@ * * Copyright (C) 2012 Google Inc. * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -35,7 +36,7 @@ } }) - Method(_CRS, 0x0, NotSerialized) + Method(_CRS, 0x0, Serialized) { Name(SBUF,ResourceTemplate () { diff --git a/src/mainboard/google/cyan/acpi/codec_realtek.asl b/src/mainboard/google/cyan/acpi/codec_realtek.asl index 4a1d48d..6e4a638 100644 --- a/src/mainboard/google/cyan/acpi/codec_realtek.asl +++ b/src/mainboard/google/cyan/acpi/codec_realtek.asl @@ -3,6 +3,7 @@ * * Copyright (C) 2012 Google Inc. * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -26,7 +27,7 @@ Name (_DDN, AUDIO_CODEC_DDN) Name (_UID, 1) - Method(_CRS, 0x0, NotSerialized) + Method(_CRS, 0x0, Serialized) { Name(SBUF,ResourceTemplate () { -- To view, visit https://review.coreboot.org/c/coreboot/+/32331 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iffa097a2100cfa91efa3b617311500b83f839bce Gerrit-Change-Number: 32331 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: sdm845: Add QCLib to RomStage to perform IP init
by Julius Werner (Code Review) 03 May '19

03 May '19

Julius Werner has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/25208 ) Change subject: sdm845: Add QCLib to RomStage to perform IP init ...................................................................... sdm845: Add QCLib to RomStage to perform IP init CB acts as I/O handler for QCLib (e.g. DDR training data) This interface allows bi-directional data flow between CB and QCLib Tested and working interfaces: DDR Training data QCLib serial console output DDR Information (base & size) limits cfg data TEST=build & run Change-Id: I073186674a1a593547d1ee1d15c7cd4fd8ad5bc1 Signed-off-by: T Michael Turney <mturney(a)codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/25208 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M src/mainboard/google/cheza/chromeos.fmd M src/mainboard/google/cheza/romstage.c M src/soc/qualcomm/sdm845/Makefile.inc M src/soc/qualcomm/sdm845/include/soc/memlayout.ld M src/soc/qualcomm/sdm845/include/soc/mmu.h M src/soc/qualcomm/sdm845/include/soc/symbols.h M src/soc/qualcomm/sdm845/mmu.c A src/soc/qualcomm/sdm845/qclib.c M src/soc/qualcomm/sdm845/soc.c 9 files changed, 84 insertions(+), 22 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved diff --git a/src/mainboard/google/cheza/chromeos.fmd b/src/mainboard/google/cheza/chromeos.fmd index 71e8556..b0d2d99 100644 --- a/src/mainboard/google/cheza/chromeos.fmd +++ b/src/mainboard/google/cheza/chromeos.fmd @@ -24,16 +24,15 @@ RO_FRID 0x100 } RO_VPD(PRESERVE) 16K - # TODO(hungte): Remove RO_PRESERVE. - RO_PRESERVE(PRESERVE) { - RO_DDR_TRAINING 8K - RO_FSG - } + RO_DDR_TRAINING(PRESERVE) 8K + RO_LIMITS_CFG(PRESERVE) 4K + RO_FSG(PRESERVE) } RW_VPD(PRESERVE) 32K RW_NVRAM(PRESERVE) 16K - RW_DDR_TRAINING 8K + RW_DDR_TRAINING(PRESERVE) 8K + RW_LIMITS_CFG(PRESERVE) 4K RW_ELOG(PRESERVE) 4K RW_SHARED 4K { SHARED_DATA diff --git a/src/mainboard/google/cheza/romstage.c b/src/mainboard/google/cheza/romstage.c index 7b7da4c..de737b1 100644 --- a/src/mainboard/google/cheza/romstage.c +++ b/src/mainboard/google/cheza/romstage.c @@ -15,6 +15,7 @@ #include <arch/stages.h> #include <soc/usb.h> +#include <soc/qclib_common.h> static void prepare_usb(void) { @@ -28,4 +29,7 @@ void platform_romstage_main(void) { prepare_usb(); + + /* QCLib: DDR init & train */ + qclib_load_and_run(); } diff --git a/src/soc/qualcomm/sdm845/Makefile.inc b/src/soc/qualcomm/sdm845/Makefile.inc index d099bff..78b3568 100644 --- a/src/soc/qualcomm/sdm845/Makefile.inc +++ b/src/soc/qualcomm/sdm845/Makefile.inc @@ -25,6 +25,10 @@ romstage-y += clock.c romstage-$(CONFIG_SDM845_QSPI) += qspi.c romstage-y += usb.c +romstage-y += ../common/qclib.c +romstage-y += qclib.c +romstage-y += ../common/mmu.c +romstage-y += mmu.c ################################################################################ ramstage-y += soc.c @@ -39,6 +43,7 @@ ################################################################################ CPPFLAGS_common += -Isrc/soc/qualcomm/sdm845/include +CPPFLAGS_common += -Isrc/soc/qualcomm/common/include $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin @printf "Generating: $(subst $(obj)/,,$(@))\n" diff --git a/src/soc/qualcomm/sdm845/include/soc/memlayout.ld b/src/soc/qualcomm/sdm845/include/soc/memlayout.ld index 7063c69..b1b6333 100644 --- a/src/soc/qualcomm/sdm845/include/soc/memlayout.ld +++ b/src/soc/qualcomm/sdm845/include/soc/memlayout.ld @@ -28,11 +28,12 @@ { SSRAM_START(0x14680000) OVERLAP_VERSTAGE_ROMSTAGE(0x14680000, 100K) - DMA_COHERENT(0x14699000, 0x2000) + DMA_COHERENT(0x14699000, 8K) + REGION(qcsdi, 0x146AC000, 44K, 4K) SSRAM_END(0x146C0000) BSRAM_START(0x14800000) - REGION(fw_reserved2, 0x14800000, 0x16000, 4096) + REGION(fw_reserved2, 0x14800000, 0x16000, 0x1000) BOOTBLOCK(0x14816000, 40K) TTB(0x14820000, 56K) VBOOT2_WORK(0x1482E000, 12K) @@ -40,15 +41,19 @@ TIMESTAMP(0x14836000, 1K) PRERAM_CBMEM_CONSOLE(0x14836400, 32K) PRERAM_CBFS_CACHE(0x1483E400, 70K) - REGION(bsram_unused, 0x1484FC00, 0xA2400, 0x100) - REGION(qclib, 0x148F2000, 0x80000, 4096) - REGION(dcb, 0x14972000, 0x4000, 4096) - REGION(pmic, 0x14976000, 0xA000, 4096) + REGION(bsram_unused, 0x1484FC00, 0x9E300, 0x100) + REGION(ddr_information, 0x148EDF00, 256, 256) + REGION(limits_cfg, 0x148EE000, 4K, 4K) + REGION(qclib_serial_log, 0x148EF000, 4K, 4K) + REGION(ddr_training, 0x148F0000, 8K, 4K) + REGION(qclib, 0x148F2000, 512K, 4K) + REGION(dcb, 0x14972000, 16K, 4K) + REGION(pmic, 0x14976000, 40K, 4K) BSRAM_END(0x14980000) DRAM_START(0x80000000) /* Various hardware/software subsystems make use of this area */ - REGION(dram_reserved, 0x85000000, 0x1A800000, 4096) + REGION(dram_reserved, 0x85000000, 0x1A800000, 0x1000) POSTRAM_CBFS_CACHE(0x9F800000, 384K) - RAMSTAGE(0x9F860000, 128K) + RAMSTAGE(0x9F860000, 2M) } diff --git a/src/soc/qualcomm/sdm845/include/soc/mmu.h b/src/soc/qualcomm/sdm845/include/soc/mmu.h index 299700a..c9883bc 100644 --- a/src/soc/qualcomm/sdm845/include/soc/mmu.h +++ b/src/soc/qualcomm/sdm845/include/soc/mmu.h @@ -16,8 +16,6 @@ #ifndef _SOC_QUALCOMM_SDM845_MMU_H__ #define _SOC_QUALCOMM_SDM845_MMU_H__ -#define DRAMSIZE4GB 0x100000000 - void sdm845_mmu_init(void); #endif // _SOC_QUALCOMM_SDM845_MMU_H_ diff --git a/src/soc/qualcomm/sdm845/include/soc/symbols.h b/src/soc/qualcomm/sdm845/include/soc/symbols.h index 1c14c03..e7bf1b2 100644 --- a/src/soc/qualcomm/sdm845/include/soc/symbols.h +++ b/src/soc/qualcomm/sdm845/include/soc/symbols.h @@ -17,10 +17,12 @@ #define _SOC_QUALCOMM_SDM845_SYMBOLS_H_ #include <symbols.h> -#include <types.h> DECLARE_REGION(ssram) DECLARE_REGION(bsram) DECLARE_REGION(dram_reserved) +DECLARE_REGION(dcb); +DECLARE_REGION(pmic); +DECLARE_REGION(limits_cfg); #endif // _SOC_QUALCOMM_SDM845_SYMBOLS_H_ diff --git a/src/soc/qualcomm/sdm845/mmu.c b/src/soc/qualcomm/sdm845/mmu.c index ef6c058..ec5fa55 100644 --- a/src/soc/qualcomm/sdm845/mmu.c +++ b/src/soc/qualcomm/sdm845/mmu.c @@ -17,12 +17,9 @@ #include <arch/mmu.h> #include <arch/cache.h> #include <soc/mmu.h> +#include <soc/mmu_common.h> #include <soc/symbols.h> -#define CACHED_RAM (MA_MEM | MA_S | MA_RW) -#define UNCACHED_RAM (MA_MEM | MA_S | MA_RW | MA_MEM_NC) -#define DEV_MEM (MA_DEV | MA_S | MA_RW) - void sdm845_mmu_init(void) { mmu_init(); diff --git a/src/soc/qualcomm/sdm845/qclib.c b/src/soc/qualcomm/sdm845/qclib.c new file mode 100644 index 0000000..9c05452 --- /dev/null +++ b/src/soc/qualcomm/sdm845/qclib.c @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbfs.h> +#include <fmap.h> +#include <console/console.h> +#include <soc/symbols.h> +#include <soc/qclib_common.h> + +int qclib_soc_blob_load(void) +{ + size_t size; + ssize_t ssize; + + /* Attempt to load PMICCFG Blob */ + size = cbfs_boot_load_file(CONFIG_CBFS_PREFIX "/pmiccfg", + _pmic, REGION_SIZE(pmic), CBFS_TYPE_RAW); + if (!size) + return -1; + qclib_add_if_table_entry(QCLIB_TE_PMIC_SETTINGS, _pmic, size, 0); + + /* Attempt to load DCB Blob */ + size = cbfs_boot_load_file(CONFIG_CBFS_PREFIX "/dcb", + _dcb, REGION_SIZE(dcb), CBFS_TYPE_RAW); + if (!size) + return -1; + qclib_add_if_table_entry(QCLIB_TE_DCB_SETTINGS, _dcb, size, 0); + + /* Attempt to load Limits Config Blob */ + ssize = fmap_read_area(QCLIB_FR_LIMITS_CFG_DATA, _limits_cfg, + REGION_SIZE(limits_cfg)); + if (ssize < 0) + return -1; + qclib_add_if_table_entry(QCLIB_TE_LIMITS_CFG_DATA, + _limits_cfg, ssize, 0); + + return 0; +} diff --git a/src/soc/qualcomm/sdm845/soc.c b/src/soc/qualcomm/sdm845/soc.c index bc7235f..ef283c0 100644 --- a/src/soc/qualcomm/sdm845/soc.c +++ b/src/soc/qualcomm/sdm845/soc.c @@ -16,11 +16,13 @@ #include <symbols.h> #include <device/device.h> #include <soc/mmu.h> +#include <soc/mmu_common.h> #include <soc/symbols.h> static void soc_read_resources(struct device *dev) { - ram_resource(dev, 0, (uintptr_t)_dram / KiB, DRAMSIZE4GB / KiB); + ram_resource(dev, 0, (uintptr_t)ddr_region->offset / KiB, + ddr_region->size / KiB); reserved_ram_resource(dev, 1, (uintptr_t)_dram_reserved / KiB, REGION_SIZE(dram_reserved) / KiB); } -- To view, visit https://review.coreboot.org/c/coreboot/+/25208 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I073186674a1a593547d1ee1d15c7cd4fd8ad5bc1 Gerrit-Change-Number: 25208 Gerrit-PatchSet: 78 Gerrit-Owner: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: merged

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coreboot-gerrit May 2019