Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32509
Change subject: drivers/intel/fsp1_1/cache_as_ram.inc: Reduce max line length to 80.
......................................................................
drivers/intel/fsp1_1/cache_as_ram.inc: Reduce max line length to 80.
Cosmetic change to reduce line length to 80 max.
BUG=NA
TEST=Build Portwell PQ7-M107
Change-Id: Ib537592c0a6a3fffc85622e6b74ad5ec8041e7dc
Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com>
---
M src/drivers/intel/fsp1_1/cache_as_ram.inc
1 file changed, 7 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/32509/1
diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.inc b/src/drivers/intel/fsp1_1/cache_as_ram.inc
index 48fcb8f..01b5261 100644
--- a/src/drivers/intel/fsp1_1/cache_as_ram.inc
+++ b/src/drivers/intel/fsp1_1/cache_as_ram.inc
@@ -24,9 +24,8 @@
* performs the final stage of initialization.
*/
-
-#define LHLT_DELAY 0x50000 /* I/O delay between post codes on failure */
-
+/* I/O delay between post codes on failure */
+#define LHLT_DELAY 0x50000
/*
* Per FSP1.1 specs, following registers are preserved:
* EBX, EDI, ESI, EBP, MM0, MM1
@@ -165,8 +164,8 @@
* 0x01 - FV signature, "_FVH" not present
* 0x02 - FFS GUID not present
* 0x03 - FSP INFO Header not found
- * 0x04 - ImageBase does not equal CONFIG_FSP_LOC - Is the FSP rebased to
- * a different location, or does it need to be?
+ * 0x04 - ImageBase does not equal CONFIG_FSP_LOC - Is the FSP rebased
+ * to a different location, or does it need to be?
* 0x05 - FSP INFO Header signature "FSPH" not found
* 0x06 - FSP Image ID is not the expected ID.
*/
@@ -181,7 +180,8 @@
* 0x02 - FSP_INVALID_PARAMETER: Input parameters are invalid.
* 0x03 - FSP_UNSUPPORTED: The FSP calling conditions were not met.
* 0x07 - FSP_DEVICE_ERROR: Temp RAM initialization failed
- * 0x0E - FSP_NOT_FOUND: No valid microcode was found in the microcode region.
+ * 0x0E - FSP_NOT_FOUND: No valid microcode was found in the microcode
+ * region.
* 0x14 - FSP_ALREADY_STARTED: Temp RAM initialization has been invoked
*/
movb $0xBB, %ah
@@ -213,7 +213,7 @@
.long CONFIG_CPU_MICROCODE_CBFS_LOC /* Microcode Location */
.long CONFIG_CPU_MICROCODE_CBFS_LEN /* Microcode Length */
.long 0xFFFFFFFF - CONFIG_ROM_SIZE + 1 /* Firmware Location */
- .long CONFIG_ROM_SIZE /* Total Firmware Length */
+ .long CONFIG_ROM_SIZE /* Firmware Length */ * Length */
CAR_init_stack:
.long CAR_init_done
--
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Gerrit-Change-Id: Ib537592c0a6a3fffc85622e6b74ad5ec8041e7dc
Gerrit-Change-Number: 32509
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Hello Alexander Couzens, Evgeny Zinoviev, Arthur Heymans, Patrick Rudolph, Jonathan Neuschäfer, Paul Menzel, Philipp Deppenwiese, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/29204
to look at the new patch set (#4).
Change subject: ec/lenovo/h8: Add function to query sense state
......................................................................
ec/lenovo/h8: Add function to query sense state
* Add function to wait for sense registers to become valid.
* Add function to retrieve Fn-Key state.
Tested on Lenovo T500:
* It takes about 700msec for the registers to become valid.
Tested on Lenovo T520:
* It takes less than 150msec for the registers to become valid.
Change-Id: Ie27e2881a256c4efb3def11f05070c446db6e5fc
Signed-off-by: Patrick Rudolph <siro(a)das-labor.org>
---
M src/ec/lenovo/h8/Makefile.inc
M src/ec/lenovo/h8/h8.h
A src/ec/lenovo/h8/sense.c
3 files changed, 64 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/29204/4
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Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29204 )
Change subject: ec/lenovo/h8: Add function to query sense state
......................................................................
Patch Set 3:
(4 comments)
https://review.coreboot.org/#/c/29204/2//COMMIT_MSG
Commit Message:
https://review.coreboot.org/#/c/29204/2//COMMIT_MSG@9
PS2, Line 9: Wait for the EC to fully boot before jumping to payload.
: The probed registers reads as zero until the EC is ready.
: Add a new timestamp for debugging purposes.
> Please use bullet points when you want a list, a paragraph […]
Done
https://review.coreboot.org/#/c/29204/2/src/ec/lenovo/h8/h8.c
File src/ec/lenovo/h8/h8.c:
https://review.coreboot.org/#/c/29204/2/src/ec/lenovo/h8/h8.c@321
PS2, Line 321: h8_final
> Even an inb() sends something (a read request). Which triggers an […]
Added mdelay(1)
https://review.coreboot.org/#/c/29204/2/src/ec/lenovo/h8/h8.c@323
PS2, Line 323: int timeout = 3 * 1000;
> use a `stopwatch` instead?
Done
https://review.coreboot.org/#/c/29204/2/src/ec/lenovo/h8/h8.c@335
PS2, Line 335: printk(BIOS_ERR, "H8: Failed waiting for sense ready\n");
> Somehow ambiguous. maybe "Timed out ..." or "Not ready after ... […]
Removed
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29204 )
Change subject: ec/lenovo/h8: Add function to query sense state
......................................................................
Patch Set 3: Code-Review-1
Some comments are still not addressed.
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Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29204 )
Change subject: ec/lenovo/h8: Add function to query sense state
......................................................................
Patch Set 3: Code-Review+2
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Frans Hendriks has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/29661 )
Change subject: {drivers,mb,soc/intel/braswell}: Add support for Braswell FSP MR2
......................................................................
Abandoned
CB: 32381 contains similar fix, solving this issue.
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Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32542
Change subject: mb/siemens/mc_apl2: Limit SD-Card speed to DDR50
......................................................................
mb/siemens/mc_apl2: Limit SD-Card speed to DDR50
Due to PCB limitations the SD-Card interface is not able to operate
with the highest frequency reliably. The OS driver will switch to
the highest mode if a SD-Card is attached which supports this high
frequency mode. In order to work around this PCB limitation disable the
high frequency modes in the controller capabilities (SDR104 and HS400
mode) and leave SDR50 and DDR50 enabled.
Change-Id: Ia5fed5fb70b027de34170b49620927614a00fb7a
Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com>
---
M src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c
1 file changed, 22 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/32542/1
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c
index 0c2418a..1cbb689 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c
@@ -23,11 +23,17 @@
#include <timer.h>
#include <timestamp.h>
#include <baseboard/variants.h>
+#include <soc/pci_devs.h>
+
+#define SD_CAP_BYP 0x810
+#define SD_CAP_BYP_EN 0x5A
+#define SD_CAP_BYP_REG1 0x814
void variant_mainboard_final(void)
{
struct device *dev;
uint16_t cmd = 0;
+ void *base;
/* Set Master Enable for on-board PCI device. */
dev = dev_find_device(PCI_VENDOR_ID_SIEMENS, 0x403e, 0);
@@ -36,6 +42,22 @@
cmd |= PCI_COMMAND_MASTER;
pci_write_config16(dev, PCI_COMMAND, cmd);
}
+
+ /* Reduce SD-Card speed to DDR50 because of PCB constraints. */
+ dev = dev_find_slot(0, PCH_DEVFN_SDCARD);
+ if (dev) {
+ uint32_t reg;
+ base = (void *)(pci_read_config32(dev, PCI_BASE_ADDRESS_0) &
+ ~PCI_BASE_ADDRESS_MEM_ATTR_MASK);
+ if (!base)
+ return;
+
+ write32(base + SD_CAP_BYP, SD_CAP_BYP_EN);
+ reg = read32(base + SD_CAP_BYP_REG1);
+ /* Disable HS400 and SDR104, keep SDR50 and DDR50 modes. */
+ reg &= ~0x20005800;
+ write32(base + SD_CAP_BYP_REG1, reg);
+ }
}
static void wait_for_legacy_dev(void *unused)
--
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