Change in ...coreboot[master]: drivers/intel/fsp1_1/cache_as_ram.inc: Reduce max line length to 80.
Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32509
Change subject: drivers/intel/fsp1_1/cache_as_ram.inc: Reduce max line length to 80. ......................................................................
drivers/intel/fsp1_1/cache_as_ram.inc: Reduce max line length to 80.
Cosmetic change to reduce line length to 80 max.
BUG=NA TEST=Build Portwell PQ7-M107
Change-Id: Ib537592c0a6a3fffc85622e6b74ad5ec8041e7dc Signed-off-by: Frans Hendriks fhendriks@eltan.com --- M src/drivers/intel/fsp1_1/cache_as_ram.inc 1 file changed, 7 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/32509/1
diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.inc b/src/drivers/intel/fsp1_1/cache_as_ram.inc index 48fcb8f..01b5261 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.inc +++ b/src/drivers/intel/fsp1_1/cache_as_ram.inc @@ -24,9 +24,8 @@ * performs the final stage of initialization. */
- -#define LHLT_DELAY 0x50000 /* I/O delay between post codes on failure */ - +/* I/O delay between post codes on failure */ +#define LHLT_DELAY 0x50000 /* * Per FSP1.1 specs, following registers are preserved: * EBX, EDI, ESI, EBP, MM0, MM1 @@ -165,8 +164,8 @@ * 0x01 - FV signature, "_FVH" not present * 0x02 - FFS GUID not present * 0x03 - FSP INFO Header not found - * 0x04 - ImageBase does not equal CONFIG_FSP_LOC - Is the FSP rebased to - * a different location, or does it need to be? + * 0x04 - ImageBase does not equal CONFIG_FSP_LOC - Is the FSP rebased + * to a different location, or does it need to be? * 0x05 - FSP INFO Header signature "FSPH" not found * 0x06 - FSP Image ID is not the expected ID. */ @@ -181,7 +180,8 @@ * 0x02 - FSP_INVALID_PARAMETER: Input parameters are invalid. * 0x03 - FSP_UNSUPPORTED: The FSP calling conditions were not met. * 0x07 - FSP_DEVICE_ERROR: Temp RAM initialization failed - * 0x0E - FSP_NOT_FOUND: No valid microcode was found in the microcode region. + * 0x0E - FSP_NOT_FOUND: No valid microcode was found in the microcode + * region. * 0x14 - FSP_ALREADY_STARTED: Temp RAM initialization has been invoked */ movb $0xBB, %ah @@ -213,7 +213,7 @@ .long CONFIG_CPU_MICROCODE_CBFS_LOC /* Microcode Location */ .long CONFIG_CPU_MICROCODE_CBFS_LEN /* Microcode Length */ .long 0xFFFFFFFF - CONFIG_ROM_SIZE + 1 /* Firmware Location */ - .long CONFIG_ROM_SIZE /* Total Firmware Length */ + .long CONFIG_ROM_SIZE /* Firmware Length */ * Length */
CAR_init_stack: .long CAR_init_done
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32509 )
Change subject: drivers/intel/fsp1_1/cache_as_ram.inc: Reduce max line length to 80. ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/#/c/32509/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/32509/1//COMMIT_MSG@7 PS1, Line 7: drivers/intel/fsp1_1/cache_as_ram.inc: Reduce max line length to 80. Please remove the dot at the end.
https://review.coreboot.org/#/c/32509/1/src/drivers/intel/fsp1_1/cache_as_ra... File src/drivers/intel/fsp1_1/cache_as_ram.inc:
https://review.coreboot.org/#/c/32509/1/src/drivers/intel/fsp1_1/cache_as_ra... PS1, Line 216: .long CONFIG_ROM_SIZE /* Firmware Length */ * Length */ Use
/* Firmware Length Length */
Hello Patrick Rudolph, Huang Jin, Lee Leahy, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32509
to look at the new patch set (#2).
Change subject: drivers/intel/fsp1_1/cache_as_ram.inc: Reduce max line length to 80 ......................................................................
drivers/intel/fsp1_1/cache_as_ram.inc: Reduce max line length to 80
Cosmetic change to reduce line length to 80 max.
BUG=NA TEST=Build Portwell PQ7-M107
Change-Id: Ib537592c0a6a3fffc85622e6b74ad5ec8041e7dc Signed-off-by: Frans Hendriks fhendriks@eltan.com --- M src/drivers/intel/fsp1_1/cache_as_ram.inc 1 file changed, 7 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/32509/2
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32509 )
Change subject: drivers/intel/fsp1_1/cache_as_ram.inc: Reduce max line length to 80 ......................................................................
Patch Set 2: Code-Review+2
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32509 )
Change subject: drivers/intel/fsp1_1/cache_as_ram.inc: Reduce max line length to 80 ......................................................................
drivers/intel/fsp1_1/cache_as_ram.inc: Reduce max line length to 80
Cosmetic change to reduce line length to 80 max.
BUG=NA TEST=Build Portwell PQ7-M107
Change-Id: Ib537592c0a6a3fffc85622e6b74ad5ec8041e7dc Signed-off-by: Frans Hendriks fhendriks@eltan.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/32509 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Patrick Rudolph siro@das-labor.org --- M src/drivers/intel/fsp1_1/cache_as_ram.inc 1 file changed, 7 insertions(+), 7 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved
diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.inc b/src/drivers/intel/fsp1_1/cache_as_ram.inc index 48fcb8f..fa5c406 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.inc +++ b/src/drivers/intel/fsp1_1/cache_as_ram.inc @@ -24,9 +24,8 @@ * performs the final stage of initialization. */
- -#define LHLT_DELAY 0x50000 /* I/O delay between post codes on failure */ - +/* I/O delay between post codes on failure */ +#define LHLT_DELAY 0x50000 /* * Per FSP1.1 specs, following registers are preserved: * EBX, EDI, ESI, EBP, MM0, MM1 @@ -165,8 +164,8 @@ * 0x01 - FV signature, "_FVH" not present * 0x02 - FFS GUID not present * 0x03 - FSP INFO Header not found - * 0x04 - ImageBase does not equal CONFIG_FSP_LOC - Is the FSP rebased to - * a different location, or does it need to be? + * 0x04 - ImageBase does not equal CONFIG_FSP_LOC - Is the FSP rebased + * to a different location, or does it need to be? * 0x05 - FSP INFO Header signature "FSPH" not found * 0x06 - FSP Image ID is not the expected ID. */ @@ -181,7 +180,8 @@ * 0x02 - FSP_INVALID_PARAMETER: Input parameters are invalid. * 0x03 - FSP_UNSUPPORTED: The FSP calling conditions were not met. * 0x07 - FSP_DEVICE_ERROR: Temp RAM initialization failed - * 0x0E - FSP_NOT_FOUND: No valid microcode was found in the microcode region. + * 0x0E - FSP_NOT_FOUND: No valid microcode was found in the microcode + * region. * 0x14 - FSP_ALREADY_STARTED: Temp RAM initialization has been invoked */ movb $0xBB, %ah @@ -213,7 +213,7 @@ .long CONFIG_CPU_MICROCODE_CBFS_LOC /* Microcode Location */ .long CONFIG_CPU_MICROCODE_CBFS_LEN /* Microcode Length */ .long 0xFFFFFFFF - CONFIG_ROM_SIZE + 1 /* Firmware Location */ - .long CONFIG_ROM_SIZE /* Total Firmware Length */ + .long CONFIG_ROM_SIZE /* Firmware Length */
CAR_init_stack: .long CAR_init_done
-
Frans Hendriks (Code Review) -
Patrick Georgi (Code Review)
-
Patrick Rudolph (Code Review)
-
Paul Menzel (Code Review)