Frans Hendriks has uploaded this change for review.
drivers/intel/fsp1_1/cache_as_ram.inc: Reduce max line length to 80.
Cosmetic change to reduce line length to 80 max.
BUG=NA
TEST=Build Portwell PQ7-M107
Change-Id: Ib537592c0a6a3fffc85622e6b74ad5ec8041e7dc
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
---
M src/drivers/intel/fsp1_1/cache_as_ram.inc
1 file changed, 7 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/32509/1
diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.inc b/src/drivers/intel/fsp1_1/cache_as_ram.inc
index 48fcb8f..01b5261 100644
--- a/src/drivers/intel/fsp1_1/cache_as_ram.inc
+++ b/src/drivers/intel/fsp1_1/cache_as_ram.inc
@@ -24,9 +24,8 @@
* performs the final stage of initialization.
*/
-
-#define LHLT_DELAY 0x50000 /* I/O delay between post codes on failure */
-
+/* I/O delay between post codes on failure */
+#define LHLT_DELAY 0x50000
/*
* Per FSP1.1 specs, following registers are preserved:
* EBX, EDI, ESI, EBP, MM0, MM1
@@ -165,8 +164,8 @@
* 0x01 - FV signature, "_FVH" not present
* 0x02 - FFS GUID not present
* 0x03 - FSP INFO Header not found
- * 0x04 - ImageBase does not equal CONFIG_FSP_LOC - Is the FSP rebased to
- * a different location, or does it need to be?
+ * 0x04 - ImageBase does not equal CONFIG_FSP_LOC - Is the FSP rebased
+ * to a different location, or does it need to be?
* 0x05 - FSP INFO Header signature "FSPH" not found
* 0x06 - FSP Image ID is not the expected ID.
*/
@@ -181,7 +180,8 @@
* 0x02 - FSP_INVALID_PARAMETER: Input parameters are invalid.
* 0x03 - FSP_UNSUPPORTED: The FSP calling conditions were not met.
* 0x07 - FSP_DEVICE_ERROR: Temp RAM initialization failed
- * 0x0E - FSP_NOT_FOUND: No valid microcode was found in the microcode region.
+ * 0x0E - FSP_NOT_FOUND: No valid microcode was found in the microcode
+ * region.
* 0x14 - FSP_ALREADY_STARTED: Temp RAM initialization has been invoked
*/
movb $0xBB, %ah
@@ -213,7 +213,7 @@
.long CONFIG_CPU_MICROCODE_CBFS_LOC /* Microcode Location */
.long CONFIG_CPU_MICROCODE_CBFS_LEN /* Microcode Length */
.long 0xFFFFFFFF - CONFIG_ROM_SIZE + 1 /* Firmware Location */
- .long CONFIG_ROM_SIZE /* Total Firmware Length */
+ .long CONFIG_ROM_SIZE /* Firmware Length */ * Length */
CAR_init_stack:
.long CAR_init_done
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