coreboot-gerrit May 2019

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Change in ...coreboot[master]: util/inteltool: Add Sunrise Point LP (Skylake) IDs
by Felix Singer (Code Review) 06 May '19

06 May '19

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31506 Change subject: util/inteltool: Add Sunrise Point LP (Skylake) IDs ...................................................................... util/inteltool: Add Sunrise Point LP (Skylake) IDs Change-Id: Id46224fcc44b06c91cbcd6c74a55c95e1de65ec6 Signed-off-by: Felix Singer <migy(a)darmstadt.ccc.de> --- M util/inteltool/inteltool.c M util/inteltool/inteltool.h 2 files changed, 18 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/31506/1 diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 93a7ffe..bdcee02 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -224,11 +224,19 @@ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_LPC, "Bay Trail" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_PRE, "Sunrise Point Desktop Engineering Sample" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_PRE, + "Sunrise Point Mobile Engineering Sample" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_1, "Sunrise Point-LP U Base" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_2, + "Sunrise Point-LP U Base" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_1, "Sunrise Point-LP U Premium" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_2, + "Sunrise Point-LP U Premium" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_1, + "Sunrise Point-LP Y Premium" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_2, "Sunrise Point-LP Y Premium" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE, "Sunrise Point-LP U iHDCP 2.2 Base" }, diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index fb64811..9fbe9b5 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -144,10 +144,14 @@ #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_SATA 0xa102 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_P2SB 0xa120 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_PRE 0xa141 +#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_PRE 0x9d41 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SATA 0x9d03 -#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE 0x9d53 -#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM 0x9d58 -#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM 0x9d56 +#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_1 0x9d43 +#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_2 0x9d53 +#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_1 0x9d48 +#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_2 0x9d58 +#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_1 0x9d46 +#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_2 0x9d56 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE 0x9d50 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM 0x9d4e #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM 0x9d4b -- To view, visit https://review.coreboot.org/c/coreboot/+/31506 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id46224fcc44b06c91cbcd6c74a55c95e1de65ec6 Gerrit-Change-Number: 31506 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-MessageType: newchange

4 11

Change in ...coreboot[master]: Documentation: Add MSI MS-7707
by Bluemax (Code Review) 06 May '19

06 May '19

Bluemax has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32236 Change subject: Documentation: Add MSI MS-7707 ...................................................................... Documentation: Add MSI MS-7707 Change-Id: Iba38bda9becba9fcffb51afc4756023659f092ef Signed-off-by: Bluemax <1403092+BlueMax(a)users.noreply.github.com> --- A Documentation/mainboard/medion/ms_7707/board-ms-7707.jpg A Documentation/mainboard/medion/ms_7707/logs/cbmem.log A Documentation/mainboard/medion/ms_7707/logs/i2cdetect.txt A Documentation/mainboard/medion/ms_7707/logs/superiotool.log A Documentation/mainboard/medion/ms_7707/ms-7707.md 5 files changed, 1,084 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/32236/1 diff --git a/Documentation/mainboard/medion/ms_7707/board-ms-7707.jpg b/Documentation/mainboard/medion/ms_7707/board-ms-7707.jpg new file mode 100644 index 0000000..d747774 --- /dev/null +++ b/Documentation/mainboard/medion/ms_7707/board-ms-7707.jpg Binary files differ diff --git a/Documentation/mainboard/medion/ms_7707/logs/cbmem.log b/Documentation/mainboard/medion/ms_7707/logs/cbmem.log new file mode 100644 index 0000000..9921fe5 --- /dev/null +++ b/Documentation/mainboard/medion/ms_7707/logs/cbmem.log @@ -0,0 +1,751 @@ +*** Pre-CBMEM romstage console overflowed, log truncated! *** + : 24T +Selected tWR : 10T +Selected tFAW : 20T +Selected tRRD : 4T +Selected tRTP : 5T +Selected tWTR : 5T +Selected tRFC : 107T +Done dimm mapping +Update PCI-E configuration space: +PCI(0, 0, 0)[a0] = 0 +PCI(0, 0, 0)[a4] = 1 +PCI(0, 0, 0)[bc] = 8a800000 +PCI(0, 0, 0)[a8] = 75000000 +PCI(0, 0, 0)[ac] = 1 +PCI(0, 0, 0)[b8] = 80000000 +PCI(0, 0, 0)[b0] = 80800000 +PCI(0, 0, 0)[b4] = 80800000 +PCI(0, 0, 0)[7c] = 7f +PCI(0, 0, 0)[70] = ff800000 +PCI(0, 0, 0)[74] = 0 +PCI(0, 0, 0)[78] = ff800c00 +Done memory map +Done io registers +Done jedec reset +Done MRS commands +t123: 1912, 9120, 500 +ME: FW Partition Table : OK +ME: Bringup Loader Failure : NO +ME: Firmware Init Complete : NO +ME: Manufacturing Mode : NO +ME: Boot Options Present : NO +ME: Update In Progress : NO +ME: Current Working State : Normal +ME: Current Operation State : Bring up +ME: Current Operation Mode : Normal +ME: Error Code : No Error +ME: Progress Phase : BUP Phase +ME: Power Management Event : Clean Moff->Mx wake +ME: Progress Phase State : 0x4e +ME: FWS2: 0x104e0006 +ME: Bist in progress: 0x0 +ME: ICC Status : 0x3 +ME: Invoke MEBx : 0x0 +ME: CPU replaced : 0x0 +ME: MBP ready : 0x0 +ME: MFS failure : 0x0 +ME: Warm reset req : 0x0 +ME: CPU repl valid : 0x0 +ME: (Reserved) : 0x0 +ME: FW update req : 0x0 +ME: (Reserved) : 0x0 +ME: Current state : 0x4e +ME: Current PM event: 0x0 +ME: Progress code : 0x1 +Waited long enough, or CPU was not replaced, continue... +PASSED! Tell ME that DRAM is ready +ME: FWS2: 0x102c0006 +ME: Bist in progress: 0x0 +ME: ICC Status : 0x3 +ME: Invoke MEBx : 0x0 +ME: CPU replaced : 0x0 +ME: MBP ready : 0x0 +ME: MFS failure : 0x0 +ME: Warm reset req : 0x0 +ME: CPU repl valid : 0x0 +ME: (Reserved) : 0x0 +ME: FW update req : 0x0 +ME: (Reserved) : 0x0 +ME: Current state : 0x2c +ME: Current PM event: 0x0 +ME: Progress code : 0x1 +ME: Requested BIOS Action: Continue to boot +ME: FW Partition Table : OK +ME: Bringup Loader Failure : NO +ME: Firmware Init Complete : NO +ME: Manufacturing Mode : NO +ME: Boot Options Present : NO +ME: Update In Progress : NO +ME: Current Working State : Normal +ME: Current Operation State : Bring up +ME: Current Operation Mode : Normal +ME: Error Code : No Error +ME: Progress Phase : BUP Phase +ME: Power Management Event : Clean Moff->Mx wake +ME: Progress Phase State : 0x2c +memcfg DDR3 ref clock 133 MHz +memcfg DDR3 clock 1330 MHz +memcfg channel assignment: A: 0, B 1, C 2 +memcfg channel[0] config (00600008): + ECC inactive + enhanced interleave mode on + rank interleave on + DIMMA 2048 MB width x8 single rank, selected + DIMMB 0 MB width x8 single rank +memcfg channel[1] config (00600008): + ECC inactive + enhanced interleave mode on + rank interleave on + DIMMA 2048 MB width x8 single rank, selected + DIMMB 0 MB width x8 single rank +CBMEM: +IMD: root @ 7ffff000 254 entries. +IMD: root @ 7fffec00 62 entries. +External stage cache: +IMD: root @ 803ff000 254 entries. +IMD: root @ 803fec00 62 entries. +CBMEM entry for DIMM info: 0x7fffea40 +MTRR Range: Start=ffc00000 End=0 (Size 400000) +MTRR Range: Start=0 End=1000000 (Size 1000000) +MTRR Range: Start=7f800000 End=80000000 (Size 800000) +MTRR Range: Start=80000000 End=80800000 (Size 800000) +CBFS: 'Master Header Locator' located CBFS at [210200:400000) +CBFS: Locating 'fallback/postcar' +CBFS: Found @ offset 2ef00 size 3c28 +Decompressing stage fallback/postcar @ 0x7ffcefc0 (32016 bytes) +Loading module at 7ffcf000 with entry 7ffcf000. filesize: 0x3a10 memsize: 0x7cd0 +Processing 111 relocs. Offset value of 0x7dfcf000 + + +coreboot-4.9-1212-g3eebb16c05-dirty Wed Apr 3 16:57:19 UTC 2019 postcar starting (log level: 7)... +CBFS: 'Master Header Locator' located CBFS at [210200:400000) +CBFS: Locating 'fallback/ramstage' +CBFS: Found @ offset 19c00 size 14d90 +Decompressing stage fallback/ramstage @ 0x7ff8bfc0 (270072 bytes) +Loading module at 7ff8c000 with entry 7ff8c000. filesize: 0x2c590 memsize: 0x41eb8 +Processing 3092 relocs. Offset value of 0x7f18c000 + + +coreboot-4.9-1212-g3eebb16c05-dirty Wed Apr 3 16:57:19 UTC 2019 ramstage starting (log level: 7)... +Normal boot. +BS: BS_PRE_DEVICE times (us): entry 0 run 0 exit 0 +BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 0 exit 0 +Enumerating buses... +CPU_CLUSTER: 0 enabled +DOMAIN: 0000 enabled +PCI: pci_scan_bus for bus 00 +PCI: 00:00.0 [8086/0100] enabled +PCI: 00:01.0 [8086/0101] enabled +PCI: 00:16.0 [8086/1c3a] enabled +PCI: 00:16.1: Disabling device +PCI: 00:16.1 [8086/1c3b] disabled No operations +PCI: 00:16.2: Disabling device +PCI: 00:16.2 [8086/1c3c] disabled No operations +PCI: 00:16.3: Disabling device +PCI: 00:16.3 [8086/1c3d] disabled No operations +PCI: 00:19.0 [8086/1503] enabled +PCI: 00:1a.0 [8086/1c2d] enabled +PCI: 00:1b.0 [8086/1c20] enabled +PCH: PCIe Root Port coalescing is enabled +PCI: 00:1c.0 [8086/1c10] enabled +PCI: 00:1c.1: Disabling device +PCI: 00:1c.2: Disabling device +PCI: 00:1c.3: Disabling device +PCI: 00:1c.4: Disabling device +PCI: 00:1c.4: check set enabled +PCI: 00:1c.4 [8086/1c18] disabled +PCI: 00:1c.5: Disabling device +PCI: 00:1c.5 [8086/1c1a] disabled +PCH: Remap PCIe function 6 to 1 +PCI: 00:1c.6 [8086/1c1c] enabled +PCI: 00:1c.7: Disabling device +PCH: PCIe map 1c.1 -> 1c.6 +PCH: PCIe map 1c.6 -> 1c.1 +PCI: 00:1d.0 [8086/1c26] enabled +PCI: 00:1e.0: Disabling device +PCI: 00:1e.0 [8086/244e] disabled No operations +PCI: 00:1f.0 [8086/1c46] enabled +PCI: 00:1f.2 [8086/1c00] enabled +PCI: 00:1f.3 [8086/1c22] enabled +PCI: 00:1f.5: Disabling device +PCI: 00:1f.5 [8086/1c08] disabled No operations +PCI: 00:1f.6: Disabling device +PCI: 00:1f.6 [8086/1c24] disabled No operations +PCI: Leftover static devices: +PCI: 00:02.0 +PCI: 00:1c.6 +PCI: 00:1c.2 +PCI: 00:1c.3 +PCI: 00:1c.7 +PCI: Check your devicetree.cb. +PCI: pci_scan_bus for bus 01 +PCI: 01:00.0 [10de/0614] enabled +Enabling Common Clock Configuration +ASPM: Enabled L0s and L1 +Failed to enable LTR for dev = PCI: 01:00.0 +scan_bus: scanning of bus PCI: 00:01.0 took 127 usecs +PCI: pci_scan_bus for bus 02 +scan_bus: scanning of bus PCI: 00:1c.0 took 41 usecs +PCI: pci_scan_bus for bus 03 +PCI: 03:00.0 [1033/0194] enabled +Enabling Common Clock Configuration +ASPM: Enabled L0s and L1 +scan_bus: scanning of bus PCI: 00:1c.1 took 219 usecs +PNP: 004e.1 disabled +PNP: 004e.4 enabled +PNP: 004e.5 enabled +PNP: 004e.6 enabled +PNP: 004e.7 enabled +PNP: 004e.8 disabled +PNP: 004e.a enabled +scan_bus: scanning of bus PCI: 00:1f.0 took 111 usecs +scan_bus: scanning of bus PCI: 00:1f.3 took 1 usecs +scan_bus: scanning of bus DOMAIN: 0000 took 735 usecs +scan_bus: scanning of bus Root Device took 738 usecs +done +FMAP: Found "FLASH" version 1.1 at 210000. +FMAP: base = ffc00000 size = 400000 #areas = 4 +FMAP: area RW_MRC_CACHE found @ 200000 (65536 bytes) +MRC: Checking cached data update for 'RW_MRC_CACHE'. +Manufacturer: ef +SF: Detected W25Q32_V with sector size 0x1000, total 0x400000 +MRC: no data in 'RW_MRC_CACHE' +MRC: cache data 'RW_MRC_CACHE' needs update. +BS: BS_DEV_ENUMERATE times (us): entry 0 run 755 exit 7946 +found VGA at PCI: 01:00.0 +Setting up VGA for PCI: 01:00.0 +Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:01.0 +Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 +Setting PCI_BRIDGE_CTL_VGA for bridge Root Device +Allocating resources... +Reading resources... +Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000. +Done reading resources. +skipping PNP: 004e.6@c1 fixed resource, size=0! +skipping PNP: 004e.6@c5 fixed resource, size=0! +skipping PNP: 004e.6@ce fixed resource, size=0! +skipping PNP: 004e.6@cf fixed resource, size=0! +skipping PNP: 004e.6@d0 fixed resource, size=0! +skipping PNP: 004e.6@d1 fixed resource, size=0! +skipping PNP: 004e.6@d3 fixed resource, size=0! +skipping PNP: 004e.6@e1 fixed resource, size=0! +skipping PNP: 004e.6@f1 fixed resource, size=0! +skipping PNP: 004e.7@f6 fixed resource, size=0! +skipping PNP: 004e.7@30 fixed resource, size=0! +skipping PNP: 004e.7@f0 fixed resource, size=0! +skipping PNP: 004e.a@30 fixed resource, size=0! +skipping PNP: 004e.a@e0 fixed resource, size=0! +skipping PNP: 004e.a@f4 fixed resource, size=0! +skipping PNP: 004e.a@f8 fixed resource, size=0! +skipping PNP: 004e.a@f9 fixed resource, size=0! +skipping PNP: 004e.a@fa fixed resource, size=0! +Setting resources... +TOUUD 0x175000000 TOLUD 0x8a800000 TOM 0x100000000 +MEBASE 0xff800000 +IGD decoded, subtracting 160M UMA and 0M GTT +TSEG base 0x80000000 size 8M +Available memory below 4GB: 2048M +Available memory above 4GB: 1872M +PCI: 00:01.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 01 io +PCI: 00:01.0 24 <- [0x00d0000000 - 0x00dfffffff] size 0x10000000 gran 0x14 bus 01 prefmem +PCI: 00:01.0 20 <- [0x00e0000000 - 0x00e30fffff] size 0x03100000 gran 0x14 bus 01 mem +PCI: 01:00.0 10 <- [0x00e2000000 - 0x00e2ffffff] size 0x01000000 gran 0x18 mem +PCI: 01:00.0 14 <- [0x00d0000000 - 0x00dfffffff] size 0x10000000 gran 0x1c prefmem64 +PCI: 01:00.0 1c <- [0x00e0000000 - 0x00e1ffffff] size 0x02000000 gran 0x19 mem64 +PCI: 01:00.0 24 <- [0x0000001000 - 0x000000107f] size 0x00000080 gran 0x07 io +PCI: 01:00.0 30 <- [0x00e3000000 - 0x00e301ffff] size 0x00020000 gran 0x11 romem +PCI: 00:16.0 10 <- [0x00e3229000 - 0x00e322900f] size 0x00000010 gran 0x04 mem64 +PCI: 00:19.0 10 <- [0x00e3200000 - 0x00e321ffff] size 0x00020000 gran 0x11 mem +PCI: 00:19.0 14 <- [0x00e3224000 - 0x00e3224fff] size 0x00001000 gran 0x0c mem +PCI: 00:19.0 18 <- [0x0000002000 - 0x000000201f] size 0x00000020 gran 0x05 io +PCI: 00:1a.0 10 <- [0x00e3226000 - 0x00e32263ff] size 0x00000400 gran 0x0a mem +PCI: 00:1b.0 10 <- [0x00e3220000 - 0x00e3223fff] size 0x00004000 gran 0x0e mem64 +PCI: 00:1c.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io +PCI: 00:1c.0 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 02 prefmem +PCI: 00:1c.0 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 02 mem +PCI: 00:1c.1 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 03 io +PCI: 00:1c.1 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 03 prefmem +PCI: 00:1c.1 20 <- [0x00e3100000 - 0x00e31fffff] size 0x00100000 gran 0x14 bus 03 mem +PCI: 03:00.0 10 <- [0x00e3100000 - 0x00e3101fff] size 0x00002000 gran 0x0d mem64 +PCI: 00:1d.0 10 <- [0x00e3227000 - 0x00e32273ff] size 0x00000400 gran 0x0a mem +PNP: 004e.4 60 <- [0x0000000295 - 0x000000029c] size 0x00000008 gran 0x03 io +PNP: 004e.4 70 <- [0x0000000000 - 0x0000000000] size 0x00000001 gran 0x00 irq +PNP: 004e.5 60 <- [0x0000000060 - 0x0000000060] size 0x00000001 gran 0x00 io +PNP: 004e.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq +PNP: 004e.5 72 <- [0x000000000c - 0x000000000c] size 0x00000001 gran 0x00 irq +PNP: 004e.6 70 <- [0x0000000000 - 0x0000000000] size 0x00000001 gran 0x00 irq +PNP: 004e.6 c1 <- [0x000000003f - 0x000000003e] size 0x00000000 gran 0x00 irq +PNP: 004e.6 c5 <- [0x000000001f - 0x000000001e] size 0x00000000 gran 0x00 irq +PNP: 004e.6 ce <- [0x00000000e0 - 0x00000000df] size 0x00000000 gran 0x00 irq +PNP: 004e.6 cf <- [0x0000000040 - 0x000000003f] size 0x00000000 gran 0x00 irq +PNP: 004e.6 d0 <- [0x0000000020 - 0x000000001f] size 0x00000000 gran 0x00 irq +PNP: 004e.6 d1 <- [0x0000000020 - 0x000000001f] size 0x00000000 gran 0x00 irq +PNP: 004e.6 d3 <- [0x0000000020 - 0x000000001f] size 0x00000000 gran 0x00 irq +PNP: 004e.6 e1 <- [0x000000001f - 0x000000001e] size 0x00000000 gran 0x00 irq +PNP: 004e.6 f1 <- [0x00000000ff - 0x00000000fe] size 0x00000000 gran 0x00 irq +PNP: 004e.7 60 <- [0x0000000000 - 0x0000000007] size 0x00000008 gran 0x03 io +PNP: 004e.7 f6 <- [0x0000000a00 - 0x00000009ff] size 0x00000000 gran 0x00 io +PNP: 004e.7 30 <- [0x0000000000 - 0xffffffffffffffff] size 0x00000000 gran 0x00 irq +PNP: 004e.7 f0 <- [0x0000000003 - 0x0000000002] size 0x00000000 gran 0x00 irq +PNP: 004e.a 30 <- [0x0000000001 - 0x0000000000] size 0x00000000 gran 0x00 irq +PNP: 004e.a e0 <- [0x0000000010 - 0x000000000f] size 0x00000000 gran 0x00 irq +PNP: 004e.a f4 <- [0x0000000004 - 0x0000000003] size 0x00000000 gran 0x00 irq +PNP: 004e.a f8 <- [0x0000000000 - 0xffffffffffffffff] size 0x00000000 gran 0x00 irq +PNP: 004e.a f9 <- [0x0000000009 - 0x0000000008] size 0x00000000 gran 0x00 irq +PNP: 004e.a fa <- [0x0000000000 - 0xffffffffffffffff] size 0x00000000 gran 0x00 irq +PCI: 00:1f.2 10 <- [0x0000002040 - 0x0000002047] size 0x00000008 gran 0x03 io +PCI: 00:1f.2 14 <- [0x0000002050 - 0x0000002053] size 0x00000004 gran 0x02 io +PCI: 00:1f.2 18 <- [0x0000002048 - 0x000000204f] size 0x00000008 gran 0x03 io +PCI: 00:1f.2 1c <- [0x0000002054 - 0x0000002057] size 0x00000004 gran 0x02 io +PCI: 00:1f.2 20 <- [0x0000002020 - 0x000000203f] size 0x00000020 gran 0x05 io +PCI: 00:1f.2 24 <- [0x00e3225000 - 0x00e32257ff] size 0x00000800 gran 0x0b mem +PCI: 00:1f.3 10 <- [0x00e3228000 - 0x00e32280ff] size 0x00000100 gran 0x08 mem64 +Done setting resources. +Done allocating resources. +BS: BS_DEV_RESOURCES times (us): entry 0 run 1040 exit 0 +Enabling resources... +PCI: 00:00.0 subsystem <- 1462/7707 +PCI: 00:00.0 cmd <- 06 +PCI: 00:01.0 bridge ctrl <- 000b +PCI: 00:01.0 subsystem <- 1462/7707 +PCI: 00:01.0 cmd <- 07 +PCI: 00:16.0 subsystem <- 1462/7707 +PCI: 00:16.0 cmd <- 02 +PCI: 00:19.0 subsystem <- 1462/7707 +PCI: 00:19.0 cmd <- 103 +PCI: 00:1a.0 subsystem <- 1462/7707 +PCI: 00:1a.0 cmd <- 102 +PCI: 00:1b.0 subsystem <- 1462/7707 +PCI: 00:1b.0 cmd <- 102 +PCI: 00:1c.0 bridge ctrl <- 0003 +PCI: 00:1c.0 subsystem <- 1462/7707 +PCI: 00:1c.0 cmd <- 100 +PCI: 00:1c.1 bridge ctrl <- 0003 +PCI: 00:1c.1 subsystem <- 1462/7707 +PCI: 00:1c.1 cmd <- 106 +PCI: 00:1d.0 subsystem <- 1462/7707 +PCI: 00:1d.0 cmd <- 102 +pch_decode_init +PCI: 00:1f.0 subsystem <- 1462/7707 +PCI: 00:1f.0 cmd <- 107 +PCI: 00:1f.2 subsystem <- 1462/7707 +PCI: 00:1f.2 cmd <- 03 +PCI: 00:1f.3 subsystem <- 1462/7707 +PCI: 00:1f.3 cmd <- 103 +PCI: 01:00.0 cmd <- 03 +PCI: 03:00.0 cmd <- 02 +done. +BS: BS_DEV_ENABLE times (us): entry 0 run 162 exit 0 +Initializing devices... +Root Device init ... +Root Device init finished in 0 usecs +CPU_CLUSTER: 0 init ... +MTRR: Physical address space: +0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 +0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 +0x00000000000c0000 - 0x0000000080000000 size 0x7ff40000 type 6 +0x0000000080000000 - 0x00000000d0000000 size 0x50000000 type 0 +0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1 +0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0 +0x0000000100000000 - 0x0000000175000000 size 0x75000000 type 6 +MTRR: Fixed MSR 0x250 0x0606060606060606 +MTRR: Fixed MSR 0x258 0x0606060606060606 +MTRR: Fixed MSR 0x259 0x0000000000000000 +MTRR: Fixed MSR 0x268 0x0606060606060606 +MTRR: Fixed MSR 0x269 0x0606060606060606 +MTRR: Fixed MSR 0x26a 0x0606060606060606 +MTRR: Fixed MSR 0x26b 0x0606060606060606 +MTRR: Fixed MSR 0x26c 0x0606060606060606 +MTRR: Fixed MSR 0x26d 0x0606060606060606 +MTRR: Fixed MSR 0x26e 0x0606060606060606 +MTRR: Fixed MSR 0x26f 0x0606060606060606 +CPU physical address size: 36 bits +MTRR: default type WB/UC MTRR counts: 4/3. +MTRR: UC selected as default type. +MTRR: 0 base 0x0000000000000000 mask 0x0000000f80000000 type 6 +MTRR: 1 base 0x00000000d0000000 mask 0x0000000ff0000000 type 1 +MTRR: 2 base 0x0000000100000000 mask 0x0000000f80000000 type 6 + +MTRR check +Fixed MTRRs : Enabled +Variable MTRRs: Enabled + +CPU has 4 cores, 4 threads enabled. +Setting up SMI for CPU +Will perform SMM setup. +CBFS: 'Master Header Locator' located CBFS at [210200:400000) +CBFS: Locating 'cpu_microcode_blob.bin' +CBFS: Found @ offset 13380 size 6800 +microcode: sig=0x206a7 pf=0x2 revision=0x2e +CPU: Intel(R) Core(TM) i5-2300 CPU @ 2.80GHz. +Loading module at 00030000 with entry 00030000. filesize: 0x170 memsize: 0x170 +Processing 16 relocs. Offset value of 0x00030000 +Attempting to start 3 APs +Waiting for 10ms after sending INIT. +Waiting for 1st SIPI to complete...done. +Waiting for 2nd SIPI to complete...done. +AP: slot 1 apic_id 2. +AP: slot 2 apic_id 4. +AP: slot 3 apic_id 6. +Loading module at 00038000 with entry 00038000. filesize: 0x1a8 memsize: 0x1a8 +Processing 13 relocs. Offset value of 0x00038000 +SMM Module: stub loaded at 00038000. Will call 7ffa3c4d(00000000) +Installing SMM handler to 0x80000000 +Loading module at 80010000 with entry 80010112. filesize: 0x1048 memsize: 0x5068 +Processing 40 relocs. Offset value of 0x80010000 +Loading module at 80008000 with entry 80008000. filesize: 0x1a8 memsize: 0x1a8 +Processing 13 relocs. Offset value of 0x80008000 +SMM Module: placing jmp sequence at 80007c00 rel16 0x03fd +SMM Module: placing jmp sequence at 80007800 rel16 0x07fd +SMM Module: placing jmp sequence at 80007400 rel16 0x0bfd +SMM Module: stub loaded at 80008000. Will call 80010112(00000000) +Initializing Southbridge SMI... + +New SMBASE 0x80000000 +In relocation handler: cpu 0 +New SMBASE=0x80000000 IEDBASE=0x80400000 +Writing SMRR. base = 0x80000006, mask=0xff800800 +Relocation complete. +New SMBASE 0x7ffffc00 +In relocation handler: cpu 1 +New SMBASE=0x7ffffc00 IEDBASE=0x80400000 +Writing SMRR. base = 0x80000006, mask=0xff800800 +Relocation complete. +New SMBASE 0x7ffff400 +In relocation handler: cpu 3 +New SMBASE=0x7ffff400 IEDBASE=0x80400000 +Writing SMRR. base = 0x80000006, mask=0xff800800 +Relocation complete. +New SMBASE 0x7ffff800 +In relocation handler: cpu 2 +New SMBASE=0x7ffff800 IEDBASE=0x80400000 +microcode: Update skipped, already up-to-date +Writing SMRR. base = 0x80000006, mask=0xff800800 +Relocation complete. +microcode: Update skipped, already up-to-date +microcode: updated to revision 0x2e date=2018-04-10 +microcode: updated to revision 0x2e date=2018-04-10 +Initializing CPU #0 +CPU: vendor Intel device 206a7 +CPU: family 06, model 2a, stepping 07 +Enabling cache +CPU: Intel(R) Core(TM) i5-2300 CPU @ 2.80GHz. +CPU: platform id 1 +CPU: cpuid(1) 0x206a7 +CPU: AES supported +CPU: TXT NOT supported +CPU: VT supported +Setting up local APIC... apic_id: 0x00 done. +VMX status: enabled +IA32_FEATURE_CONTROL status: locked +model_x06ax: energy policy set to 6 +model_x06ax: frequency set to 2800 +Turbo is available but hidden +Turbo has been enabled +CPU #0 initialized +Initializing CPU #3 +Initializing CPU #2 +Initializing CPU #1 +CPU: vendor Intel device 206a7 +CPU: family 06, model 2a, stepping 07 +CPU: vendor Intel device 206a7 +CPU: family 06, model 2a, stepping 07 +Enabling cache +Enabling cache +CPU: vendor Intel device 206a7 +CPU: family 06, model 2a, stepping 07 +Enabling cache +CPU: Intel(R) Core(TM) i5-2300 CPU @ 2.80GHz. +CPU: Intel(R) Core(TM) i5-2300 CPU @ 2.80GHz. +CPU: platform id 1 +CPU: platform id 1 +CPU: Intel(R) Core(TM) i5-2300 CPU @ 2.80GHz. +CPU: cpuid(1) 0x206a7 +CPU: platform id 1 +CPU: AES supported +CPU: TXT NOT supported +CPU: VT supported +CPU: cpuid(1) 0x206a7 +CPU: cpuid(1) 0x206a7 +Setting up local APIC...CPU: AES supported +CPU: TXT NOT supported +CPU: VT supported + apic_id: 0x04 done. +CPU: AES supported +CPU: TXT NOT supported +CPU: VT supported +Setting up local APIC...Setting up local APIC...VMX status: enabled + apic_id: 0x02 done. +IA32_FEATURE_CONTROL status: locked +VMX status: enabled + apic_id: 0x06 done. +IA32_FEATURE_CONTROL status: locked +VMX status: enabled +IA32_FEATURE_CONTROL status: locked +model_x06ax: energy policy set to 6 +model_x06ax: energy policy set to 6 +model_x06ax: frequency set to 2800 +model_x06ax: energy policy set to 6 +model_x06ax: frequency set to 2800 +CPU #2 initialized +CPU #1 initialized +model_x06ax: frequency set to 2800 +CPU #3 initialized +bsp_do_flight_plan done after 16 msecs. +Initializing southbridge SMI... +SMI_STS: +GPE0_STS: GPIO14 GPIO11 GPIO10 GPIO9 GPIO7 GPIO6 GPIO1 +ALT_GP_SMI_STS: GPI14 GPI13 GPI11 GPI10 GPI9 GPI7 GPI6 GPI5 GPI4 GPI3 GPI2 GPI1 +TCO_STS: +Locking SMM. +CPU_CLUSTER: 0 init finished in 29496 usecs +PCI: 00:00.0 init ... +Disabling PEG12. +Disabling PEG11. +Disabling IGD. +Disabling Device 4. +Disabling PEG60. +Disabling Device 7. +Set BIOS_RESET_CPL +CPU TDP: 95 Watts +PCI: 00:00.0 init finished in 1010 usecs +PCI: 00:01.0 init ... +PCI: 00:01.0 init finished in 1 usecs +PCI: 00:16.0 init ... +ME: FW Partition Table : OK +ME: Bringup Loader Failure : NO +ME: Firmware Init Complete : NO +ME: Manufacturing Mode : NO +ME: Boot Options Present : NO +ME: Update In Progress : NO +ME: Current Working State : Normal +ME: Current Operation State : M0 with UMA +ME: Current Operation Mode : Normal +ME: Error Code : No Error +ME: Progress Phase : uKernel Phase +ME: Power Management Event : Clean Moff->Mx wake +ME: Progress Phase State : Unknown 0x02 +ME: BIOS path: Normal +ME: Extend SHA-256: 286a9a97f425b427f5c26060982dffbd791397de171c1f63d77a81466114685d +ME: Firmware Version 7.0.1197.4 (code) 7.0.1197.4 (recovery) +ME Capability: Full Network manageability : disabled +ME Capability: Regular Network manageability : disabled +ME Capability: Manageability : disabled +ME Capability: Small business technology : disabled +ME Capability: Level III manageability : disabled +ME Capability: IntelR Anti-Theft (AT) : disabled +ME Capability: IntelR Capability Licensing Service (CLS) : enabled +ME Capability: IntelR Power Sharing Technology (MPC) : enabled +ME Capability: ICC Over Clocking : enabled +ME Capability: Protected Audio Video Path (PAVP) : disabled +ME Capability: IPV6 : disabled +ME Capability: KVM Remote Control (KVM) : disabled +ME Capability: Outbreak Containment Heuristic (OCH) : disabled +ME Capability: Virtual LAN (VLAN) : disabled +ME Capability: TLS : disabled +ME Capability: Wireless LAN (WLAN) : disabled +PCI: 00:16.0 init finished in 176416 usecs +PCI: 00:19.0 init ... +PCI: 00:19.0 init finished in 0 usecs +PCI: 00:1a.0 init ... +EHCI: Setting up controller.. done. +PCI: 00:1a.0 init finished in 12 usecs +PCI: 00:1b.0 init ... +Azalia: base = e3220000 +Azalia: codec_mask = 09 +Azalia: Initializing codec #3 + codec not valid. +Azalia: Initializing codec #0 + codec not ready. +PCI: 00:1b.0 init finished in 6438 usecs +PCI: 00:1c.0 init ... +Initializing PCH PCIe bridge. +PCI: 00:1c.0 init finished in 9 usecs +PCI: 00:1c.1 init ... +Initializing PCH PCIe bridge. +PCI: 00:1c.1 init finished in 8 usecs +PCI: 00:1d.0 init ... +EHCI: Setting up controller.. done. +PCI: 00:1d.0 init finished in 12 usecs +PCI: 00:1f.0 init ... +pch: lpc_init +PCH: detected P67, device id: 0x1c46, rev id 0x5 +IOAPIC: Initializing IOAPIC at 0xfec00000 +IOAPIC: Bootstrap Processor Local APIC = 0x00 +IOAPIC: ID = 0x02 +Set power on after power failure. +NMI sources disabled. +CougarPoint PM init +RTC: failed = 0x0 +RTC Init +Disabling ACPI via APMC: +done. +pch_spi_init +PCI: 00:1f.0 init finished in 236 usecs +PCI: 00:1f.2 init ... +SATA: Initializing... +SATA: Controller in AHCI mode. +ABAR: e3225000 +PCI: 00:1f.2 init finished in 72 usecs +PCI: 00:1f.3 init ... +PCI: 00:1f.3 init finished in 7 usecs +PCI: 01:00.0 init ... +CBFS: 'Master Header Locator' located CBFS at [210200:400000) +CBFS: Locating 'pci10de,0614.rom' +CBFS: 'pci10de,0614.rom' not found. +Option ROM address for PCI: 01:00.0 = e3000000 +Copying VGA ROM Image from e3000000 to 0xc0000, 0xf200 bytes +Calling Option ROM... +Unsupported software interrupt #0x15 eax 0x5f14 +... Option ROM returned. +VBE: Getting information about VESA mode 4115 +VBE: resolution: 800x600@32 +VBE: framebuffer: e1000000 +VBE: Setting VESA mode 4115 +VGA Option ROM was run +PCI: 01:00.0 init finished in 4530635 usecs +PCI: 03:00.0 init ... +PCI: 03:00.0 init finished in 0 usecs +PNP: 004e.4 init ... +PNP: 004e.4 init finished in 69 usecs +PNP: 004e.5 init ... +PNP: 004e.5 init finished in 1 usecs +PNP: 004e.6 init ... +PNP: 004e.6 init finished in 1 usecs +PNP: 004e.7 init ... +PNP: 004e.7 init finished in 1 usecs +PNP: 004e.a init ... +PNP: 004e.a init finished in 1 usecs +Devices initialized +BS: BS_DEV_INIT times (us): entry 6 run 4744434 exit 0 +Finalize devices... +PCI: 00:1f.0 final +Devices finalized +BS: BS_POST_DEVICE times (us): entry 0 run 13170 exit 0 +BS: BS_OS_RESUME_CHECK times (us): entry 0 run 0 exit 0 +CBFS: 'Master Header Locator' located CBFS at [210200:400000) +CBFS: Locating 'fallback/dsdt.aml' +CBFS: Found @ offset 32b80 size 2526 +CBFS: 'Master Header Locator' located CBFS at [210200:400000) +CBFS: Locating 'fallback/slic' +CBFS: 'fallback/slic' not found. +ACPI: Writing ACPI tables at 7ff4f000. +ACPI: * FACS +ACPI: * DSDT +ACPI: * FADT +ACPI: added table 1/32, length now 40 +ACPI: * SSDT +Generating ACPI PIRQ entries +Found 1 CPU(s) with 4 core(s) each. +PSS: 2801MHz power 95000 control 0x1f00 status 0x1f00 +PSS: 2800MHz power 95000 control 0x1c00 status 0x1c00 +PSS: 2600MHz power 86132 control 0x1a00 status 0x1a00 +PSS: 2400MHz power 77669 control 0x1800 status 0x1800 +PSS: 2200MHz power 69503 control 0x1600 status 0x1600 +PSS: 2000MHz power 61793 control 0x1400 status 0x1400 +PSS: 1800MHz power 54220 control 0x1200 status 0x1200 +PSS: 1600MHz power 47084 control 0x1000 status 0x1000 +PSS: 2801MHz power 95000 control 0x1f00 status 0x1f00 +PSS: 2800MHz power 95000 control 0x1c00 status 0x1c00 +PSS: 2600MHz power 86132 control 0x1a00 status 0x1a00 +PSS: 2400MHz power 77669 control 0x1800 status 0x1800 +PSS: 2200MHz power 69503 control 0x1600 status 0x1600 +PSS: 2000MHz power 61793 control 0x1400 status 0x1400 +PSS: 1800MHz power 54220 control 0x1200 status 0x1200 +PSS: 1600MHz power 47084 control 0x1000 status 0x1000 +PSS: 2801MHz power 95000 control 0x1f00 status 0x1f00 +PSS: 2800MHz power 95000 control 0x1c00 status 0x1c00 +PSS: 2600MHz power 86132 control 0x1a00 status 0x1a00 +PSS: 2400MHz power 77669 control 0x1800 status 0x1800 +PSS: 2200MHz power 69503 control 0x1600 status 0x1600 +PSS: 2000MHz power 61793 control 0x1400 status 0x1400 +PSS: 1800MHz power 54220 control 0x1200 status 0x1200 +PSS: 1600MHz power 47084 control 0x1000 status 0x1000 +PSS: 2801MHz power 95000 control 0x1f00 status 0x1f00 +PSS: 2800MHz power 95000 control 0x1c00 status 0x1c00 +PSS: 2600MHz power 86132 control 0x1a00 status 0x1a00 +PSS: 2400MHz power 77669 control 0x1800 status 0x1800 +PSS: 2200MHz power 69503 control 0x1600 status 0x1600 +PSS: 2000MHz power 61793 control 0x1400 status 0x1400 +PSS: 1800MHz power 54220 control 0x1200 status 0x1200 +PSS: 1600MHz power 47084 control 0x1000 status 0x1000 +CBFS: 'Master Header Locator' located CBFS at [210200:400000) +CBFS: Locating 'pci10de,0614.rom' +CBFS: 'pci10de,0614.rom' not found. +Option ROM address for PCI: 01:00.0 = e3000001 +Incorrect expansion ROM header signature 78aa +PCI: 01:00.0: Missing PCI Option ROM +ACPI: added table 2/32, length now 44 +ACPI: * MCFG +ACPI: added table 3/32, length now 48 +ACPI: * MADT +ACPI: added table 4/32, length now 52 +current = 7ff53080 +ACPI: * HPET +ACPI: added table 5/32, length now 56 +CBFS: 'Master Header Locator' located CBFS at [210200:400000) +CBFS: Locating 'pci10de,0614.rom' +CBFS: 'pci10de,0614.rom' not found. +Option ROM address for PCI: 01:00.0 = e3000001 +Incorrect expansion ROM header signature 78aa +ACPI: done. +ACPI tables: 16576 bytes. +smbios_write_tables: 7ff4d000 +Create SMBIOS type 17 +SMBIOS tables: 558 bytes. +Writing table forward entry at 0x00000500 +Wrote coreboot table at: 00000500, 0x10 bytes, checksum 4fe7 +Writing coreboot table at 0x7ff73000 + 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES + 1. 0000000000001000-000000000009ffff: RAM + 2. 00000000000a0000-00000000000fffff: RESERVED + 3. 0000000000100000-000000001fffffff: RAM + 4. 0000000020000000-00000000201fffff: RESERVED + 5. 0000000020200000-000000003fffffff: RAM + 6. 0000000040000000-00000000401fffff: RESERVED + 7. 0000000040200000-000000007ff4cfff: RAM + 8. 000000007ff4d000-000000007ff8bfff: CONFIGURATION TABLES + 9. 000000007ff8c000-000000007ffcdfff: RAMSTAGE +10. 000000007ffce000-000000007fffffff: CONFIGURATION TABLES +11. 0000000080000000-000000008a7fffff: RESERVED +12. 00000000f0000000-00000000f3ffffff: RESERVED +13. 0000000100000000-0000000174ffffff: RAM +CBFS: 'Master Header Locator' located CBFS at [210200:400000) +Wrote coreboot table at: 7ff73000, 0x38c bytes, checksum 1f06 +coreboot table: 932 bytes. +IMD ROOT 0. 7ffff000 00001000 +IMD SMALL 1. 7fffe000 00001000 +CONSOLE 2. 7ffde000 00020000 +TIME STAMP 3. 7ffdd000 00000910 +MRC DATA 4. 7ffdc000 000005d4 +ROMSTG STCK 5. 7ffd7000 00005000 +AFTER CAR 6. 7ffce000 00009000 +RAMSTAGE 7. 7ff8b000 00043000 +SMM BACKUP 8. 7ff7b000 00010000 +COREBOOT 9. 7ff73000 00008000 +ACPI 10. 7ff4f000 00024000 +ACPI GNVS 11. 7ff4e000 00001000 +SMBIOS 12. 7ff4d000 00000800 +IMD small region: + IMD ROOT 0. 7fffec00 00000400 + MEM INFO 1. 7fffea40 000001a9 + ROMSTAGE 2. 7fffea20 00000004 + COREBOOTFWD 3. 7fffe9e0 00000028 +BS: BS_WRITE_TABLES times (us): entry 0 run 3842 exit 0 +CBFS: 'Master Header Locator' located CBFS at [210200:400000) +CBFS: Locating 'fallback/payload' +CBFS: Found @ offset 35100 size af0b1 +Checking segment from ROM address 0xffe45338 +Checking segment from ROM address 0xffe45354 +Loading segment from ROM address 0xffe45338 + code (compression=1) + New segment dstaddr 0x00800000 memsize 0x410000 srcaddr 0xffe45370 filesize 0xaf079 +Loading Segment: addr: 0x00800000 memsz: 0x0000000000410000 filesz: 0x00000000000af079 +using LZMA +Loading segment from ROM address 0xffe45354 + Entry Point 0x008008f0 +BS: BS_PAYLOAD_LOAD times (us): entry 0 run 269229 exit 0 +PCH: watchdog disabled +Jumping to boot code at 008008f0(7ff73000) + diff --git a/Documentation/mainboard/medion/ms_7707/logs/i2cdetect.txt b/Documentation/mainboard/medion/ms_7707/logs/i2cdetect.txt new file mode 100644 index 0000000..2bb51dd --- /dev/null +++ b/Documentation/mainboard/medion/ms_7707/logs/i2cdetect.txt @@ -0,0 +1,9 @@ + 0 1 2 3 4 5 6 7 8 9 a b c d e f +00: -- -- -- -- -- 08 -- -- -- -- -- -- -- +10: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- +20: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- +30: 30 -- 32 -- -- -- -- -- -- -- -- -- -- -- -- -- +40: -- -- -- -- 44 -- -- -- -- -- -- -- -- -- -- -- +50: 50 -- 52 -- -- -- -- -- -- -- -- -- -- -- -- -- +60: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- +70: -- -- -- -- -- -- -- -- diff --git a/Documentation/mainboard/medion/ms_7707/logs/superiotool.log b/Documentation/mainboard/medion/ms_7707/logs/superiotool.log new file mode 100644 index 0000000..0540f1f --- /dev/null +++ b/Documentation/mainboard/medion/ms_7707/logs/superiotool.log @@ -0,0 +1,290 @@ +superiotool r4.9-1191-geb789f0b79 +Found Fintek F71808A (vid=0x3419, id=0x0110) at 0x4e +Register dump: +idx val def +0x02: 0x00 (0x00) +0x07: 0x0a (0x00) +0x20: 0x10 (0x10) +0x21: 0x01 (0x01) +0x23: 0x19 (0x19) +0x24: 0x34 (0x34) +0x25: 0x00 (0x00) +0x26: 0x00 (0x00) +0x27: 0x10 (MM) +0x28: 0x00 (0x00) +0x29: 0xc0 (0xc0) +0x2a: 0x20 (0x21) +0x2b: 0x4f (0x2f) +0x2c: 0x90 (0x5c) +0x2d: 0x2f (0x27) + +LDN 0x01 (COM1) +idx val def +0x30: 0x00 (0x01) +0x60: 0x03 (0x03) +0x61: 0xf8 (0xf8) +0x70: 0x04 (0x04) +0xf0: 0x00 (0x00) + +LDN 0x04 (Hardware monitor) +idx val def +0x30: 0x01 (0x01) +0x60: 0x02 (0x02) +0x61: 0x95 (0x95) +0x70: 0x00 (0x00) + +LDN 0x05 (Keyboard) +idx val def +0x30: 0x01 (0x01) +0x60: 0x00 (0x00) +0x61: 0x60 (0x60) +0x70: 0x01 (0x01) +0x72: 0x0c (0x0c) +0xfe: 0x01 (0x01) +0xff: 0x29 (0x29) + +LDN 0x06 (GPIO) +idx val def +0x70: 0x00 (0x00) +0xc0: 0x00 (0x00) +0xc1: 0x3f (0x3f) +0xc2: 0x13 (NA) +0xc3: 0x00 (0x00) +0xc4: 0x00 (0x00) +0xc5: 0x1f (0x00) +0xc6: 0x03 (0x00) +0xcb: 0x00 (0x00) +0xcc: 0x00 (0x00) +0xcd: 0x00 (0x00) +0xce: 0xe0 (0xe0) +0xcf: 0x40 (0x40) +0xd0: 0x20 (0x00) +0xd1: 0x20 (0x00) +0xd2: 0xdb (NA) +0xd3: 0x20 (0x00) +0xd4: 0x00 (0x00) +0xd5: 0x00 (0x00) +0xd6: 0x18 (0x00) +0xd7: 0x00 (0x00) +0xd8: 0x00 (0x00) +0xe0: 0x00 (0x00) +0xe1: 0x1f (0x1f) +0xe2: 0x17 (NA) +0xe3: 0x00 (0x00) +0xf0: 0x00 (0x00) +0xf1: 0xff (0xff) +0xf2: 0xe7 (NA) +0xf3: 0x00 (0x00) + +LDN 0x07 (WDT) +idx val def +0x30: 0x00 (0x00) +0x60: 0x00 (0x00) +0x61: 0x00 (0x00) +0xf0: 0x03 (0x03) +0xf2: 0xff (NA) +0xf3: 0xff (NA) +0xf4: 0xff (NA) +0xf5: 0x00 (0x00) +0xf6: 0x0a (0x0a) +0xf7: 0x00 (0x00) + +LDN 0x08 (CIR) +idx val def +0x30: 0x00 (0x00) +0x60: 0x00 (0x00) +0x61: 0x00 (0x00) +0x70: 0x00 (0x00) +0xf0: 0x00 (NA) +0xf1: 0x00 (NA) +0xf8: 0x00 (0x00) +0xf9: 0x00 (0x00) +0xfa: 0x80 (0x80) +0xfb: 0x3b (0x3b) +0xfc: 0x00 (0x00) +0xfd: 0x00 (0x00) +0xfe: 0x00 (0x00) + +LDN 0x0a (PME, ACPI, and EUP Power Saving) +idx val def +0x30: 0x01 (0x00) +0xe0: 0x10 (0x10) +0xe1: 0xcc (0xcc) +0xe2: 0x0c (0x0c) +0xe3: 0x13 (0x13) +0xe4: 0x09 (0x09) +0xe5: 0xc7 (0xc7) +0xe6: 0x09 (0x09) +0xe7: 0x63 (0x63) +0xe8: 0x00 (0x00) +0xe9: 0x0f (0x0f) +0xec: 0x00 (0x00) +0xed: 0xc0 (0x00) +0xee: 0x00 (0x00) +0xf0: 0x00 (0x00) +0xf1: 0x20 (NA) +0xf2: 0x00 (0x00) +0xf3: 0x02 (NA) +0xf4: 0x04 (0x06) +0xf5: 0x3c (0x3c) +0xf6: 0x1f (0x1f) +0xf7: 0x00 (0x00) +0xf8: 0x00 (0x00) +0xf9: 0x09 (0x00) +0xfa: 0x00 (0x00) +0xfd: 0xff (NA) + +Hardware monitor (0x0295) +Register dump: +idx val def +0x01: 0x03 (0x03) +0x02: 0x00 (0x00) +0x03: 0x01 (0x01) +0x08: 0x4c (0x4c) +0x0a: 0x00 (0x00) +0x0b: 0x00 (0x00) +0x0c: 0x55 (0x55) +0x0d: 0x00 (0x00) +0x0f: 0x20 (0x20) +0x20: 0xca (NA) +0x21: 0x81 (NA) +0x22: 0xff (NA) +0x23: 0xff (NA) +0x24: 0xff (RR) +0x25: 0xff (RR) +0x26: 0xff (RR) +0x27: 0xc9 (NA) +0x28: 0xda (NA) +0x29: 0xff (RR) +0x2a: 0xff (RR) +0x2b: 0xff (RR) +0x2c: 0xff (RR) +0x2d: 0x80 (NA) +0x2e: 0x8a (NA) +0x2f: 0x7f (NA) +0x40: 0x44 (0x44) +0x41: 0x00 (0x00) +0x42: 0x00 (NA) +0x43: 0x00 (0x00) +0x44: 0x00 (0x00) +0x45: 0x00 (0x00) +0x46: 0x00 (0x00) +0x47: 0x00 (0x00) +0x48: 0x00 (0x00) +0x49: 0x00 (0x00) +0x4a: 0x00 (0x00) +0x4b: 0x00 (0x00) +0x4c: 0x00 (0x00) +0x4d: 0x00 (0x00) +0x4e: 0x00 (0x00) +0x4f: 0x00 (0x00) +0x60: 0x00 (0x00) +0x61: 0x00 (0x00) +0x62: 0x00 (0x00) +0x63: 0x00 (0x00) +0x64: 0x00 (0x00) +0x66: 0x02 (0x02) +0x6b: 0x06 (0x06) +0x6c: 0x40 (0x40) +0x6d: 0x04 (0x04) +0x6f: 0x00 (0x00) +0x7f: 0x00 (0x00) +0x70: 0xff (RR) +0x71: 0xff (RR) +0x72: 0x19 (NA) +0x73: 0xff (RR) +0x74: 0x22 (NA) +0x75: 0xff (RR) +0x76: 0xff (RR) +0x77: 0xff (RR) +0x78: 0xff (NA) +0x79: 0xff (NA) +0x7a: 0x00 (NA) +0x7b: 0x00 (NA) +0x7c: 0x00 (NA) +0x7d: 0x00 (RR) +0x7e: 0x00 (RR) +0x80: 0xff (RR) +0x81: 0xff (RR) +0x82: 0x64 (NA) +0x83: 0x55 (NA) +0x84: 0x64 (NA) +0x85: 0x55 (NA) +0x86: 0xff (RR) +0x87: 0xff (RR) +0x88: 0xff (RR) +0x89: 0xff (RR) +0x8a: 0xff (RR) +0x8b: 0xff (RR) +0x8c: 0xff (RR) +0x8d: 0xff (RR) +0x90: 0x00 (0x00) +0x91: 0x06 (NA) +0x92: 0x06 (NA) +0x93: 0x00 (0x00) +0x94: 0x2a (0x2e) +0x95: 0xff (0xff) +0x96: 0x05 (0x05) +0x98: 0x44 (0x44) +0x9b: 0x05 (0x05) +0x9c: 0x55 (0x55) +0x9e: 0x66 (0x66) +0x9f: 0x00 (0x00) +0xa0: 0x05 (0x03) +0xa1: 0x7d (0xff) +0xa2: 0x00 (0x00) +0xa3: 0x80 (0x83) +0xa4: 0x03 (0x03) +0xa5: 0xff (0xff) +0xa6: 0x3c (0x3c) +0xa7: 0x32 (0x32) +0xa8: 0x28 (0x28) +0xa9: 0x1e (0x1e) +0xaa: 0xff (0xff) +0xab: 0xd9 (0xd9) +0xac: 0xb2 (0xb2) +0xad: 0x99 (0x99) +0xae: 0x80 (0x80) +0xaf: 0x1d (0x1d) +0xb0: 0x0f (0x0c) +0xb1: 0xff (0x25) +0xb2: 0x00 (0x00) +0xb3: 0x8a (0x80) +0xb4: 0x03 (0x03) +0xb5: 0xff (0xff) +0xb6: 0x3c (0x3c) +0xb7: 0x32 (0x32) +0xb8: 0x28 (0x28) +0xb9: 0x1e (0x1e) +0xba: 0xff (0xff) +0xbb: 0xd9 (0xd9) +0xbc: 0xb2 (0xb2) +0xbd: 0x99 (0x99) +0xbe: 0x80 (0x80) +0xbf: 0x1e (0x1e) +0xc0: 0x0f (0x0f) +0xc1: 0xff (0xff) +0xc2: 0xff (RR) +0xc3: 0x7f (0x7f) +0xc4: 0xff (RR) +0xc5: 0xff (RR) +0xc6: 0xff (RR) +0xc7: 0xff (RR) +0xc8: 0xff (RR) +0xc9: 0xff (RR) +0xca: 0xff (RR) +0xcb: 0xff (RR) +0xcc: 0xff (RR) +0xcd: 0xff (RR) +0xce: 0xff (RR) +0xcf: 0x00 (0x00) +0xe0: 0x00 (NA) +0xe1: 0x00 (NA) +0xe2: 0x00 (NA) +0xe3: 0x00 (NA) +0xe4: 0x00 (NA) +0xec: 0x00 (0x00) +0xed: 0x01 (0x01) +0xee: 0x01 (0x01) +0xef: 0x00 (0x00) + diff --git a/Documentation/mainboard/medion/ms_7707/ms-7707.md b/Documentation/mainboard/medion/ms_7707/ms-7707.md new file mode 100644 index 0000000..3b79dca --- /dev/null +++ b/Documentation/mainboard/medion/ms_7707/ms-7707.md @@ -0,0 +1,34 @@ +# MSI MS-7707 V1.1 + +## Specifications + +MSI MS-7707 V1.1 (Medion OEM Akoya P4385D MSN10014555) +SandyBridge Intel P67 (BD82x6x) +Winbond 25Q32BV (4MB) +Fintek F71808A +Intel 82579V Gigabit +NEC uPD720200 USB 3.0 Host Controller +IME 7.0.4.1197 + +## Working +- Tested on Arch Linux 5.0.5 +- PCIe gfx adapter +- PS/2 Keyboard +- USB3.0 +- coreboot 4.9 (TianoCore) +- S0/S5 states +- H/W FAN control (proper HWM function not checked though) + +## Known issues + +- S0/S5 states work properly as long as the board gets powered. After power cut the system is dead. Needs battery removal and CMOSCLR to revive. SuperIO is supposed to be in an unknown state as current coreboot SuperIO initialization isn't able to set all registers (see cbmem.log - skipping PNP: 004e.a@e0 fixed resource, size=0!). + +## Resources + +- [BIOS ROM] +- [Fintek F71808A datasheet] +- [Winbond 25Q32BV datasheet] + +[BIOS ROM]: https://www.medion.com/de/servicebackend/_lightbox/treiber_details.php?did=… +[Winbond 25Q32BV datasheet]: https://www.winbond.com/resource-files/w25q32bv_revi_100413_wo_automotive.p… +[Fintek F71808A datasheet]: https://www.alldatasheet.com/datasheet-pdf/pdf/459069/FINTEK/F71808A.html -- To view, visit https://review.coreboot.org/c/coreboot/+/32236 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iba38bda9becba9fcffb51afc4756023659f092ef Gerrit-Change-Number: 32236 Gerrit-PatchSet: 1 Gerrit-Owner: Bluemax Gerrit-MessageType: newchange

4 14

Change in ...coreboot[master]: arch/x86: Remove unused file
by Patrick Rudolph (Code Review) 06 May '19

06 May '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32584 Change subject: arch/x86: Remove unused file ...................................................................... arch/x86: Remove unused file The file is no longer used by any code. Remove it. Change-Id: I73f06cac11201dc37218d352ab995cf4f012c36a Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- D src/arch/x86/stages.c 1 file changed, 0 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/32584/1 diff --git a/src/arch/x86/stages.c b/src/arch/x86/stages.c deleted file mode 100644 index b4d0723..0000000 --- a/src/arch/x86/stages.c +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -static void skip_romstage(void) -{ - asm volatile ( - "jmp __main\n" - ); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/32584 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I73f06cac11201dc37218d352ab995cf4f012c36a Gerrit-Change-Number: 32584 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

3 2

Change in ...coreboot[master]: Fix fsp post-init validation
by Matthew Garrett (Code Review) 06 May '19

06 May '19

Matthew Garrett has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32530 Change subject: Fix fsp post-init validation ...................................................................... Fix fsp post-init validation Part of this checks whether tolum_base and cbmem_top are the same - however, cbmem_top hasn't been initialised at the point where this call occurs. Change the ordering to fix that. Signed-off-by: Matthew Garrett <mjg59(a)google.com> Change-Id: Ib89e0513bdc35c3751a9d4c2a2789a2836046789 --- M src/drivers/intel/fsp2_0/memory_init.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/32530/1 diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 985ee3a..e021f52 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -310,8 +310,6 @@ post_code(POST_FSP_MEMORY_EXIT); timestamp_add_now(TS_FSP_MEMORY_INIT_END); - fsp_debug_after_memory_init(status); - /* Handle any errors returned by FspMemoryInit */ fsp_handle_reset(status); if (status != FSP_SUCCESS) { @@ -320,6 +318,8 @@ } do_fsp_post_memory_init(s3wake, fsp_version); + + fsp_debug_after_memory_init(status); } /* Load the binary into the memory specified by the info header. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32530 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib89e0513bdc35c3751a9d4c2a2789a2836046789 Gerrit-Change-Number: 32530 Gerrit-PatchSet: 1 Gerrit-Owner: Matthew Garrett <mjg59(a)google.com> Gerrit-MessageType: newchange

6 13

Change in ...coreboot[master]: soc/intel/apollolake: Reset GPI IS & IE registers at ramstage
by Karthik Ramasubramanian (Code Review) 06 May '19

06 May '19

Hello Karthikeyan Ramasubramanian, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/32534 to review the following change. Change subject: soc/intel/apollolake: Reset GPI IS & IE registers at ramstage ...................................................................... soc/intel/apollolake: Reset GPI IS & IE registers at ramstage Reset GPI Interrupt status and enable registers from ramstage instead of bootblock so that it applies to devices in field. BUG=b:130593883 BRANCH=octopus TEST=Ensure that the Interrupt status & enable registers are reset during the boot up when the system is brought out of G3, S5 & S3. Ensure that the system boots fine to ChromeOS. Change-Id: Ib11b580ceb23bd1fe789f549b667a8ced2d859a1 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/soc/intel/apollolake/bootblock/bootblock.c M src/soc/intel/apollolake/chip.c 2 files changed, 6 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/32534/1 diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index c791378..ac6903a 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -122,12 +122,3 @@ paging_enable_for_car("pdpt", "pt"); } } - -void bootblock_soc_init(void) -{ - /* - * Clear the GPI interrupt enable & status registers to avoid any - * interrupt storm during the kernel bootup. - */ - gpi_clear_int_cfg(); -} diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index c3de4ee..83af26e 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -399,6 +399,12 @@ /* Restore GPIO IRQ polarities back to previous settings. */ itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); + /* + * Clear the GPI interrupt status and enable registers. These + * registers do not get reset to default state when booting from S5. + */ + gpi_clear_int_cfg(); + /* override 'enabled' setting in device tree if needed */ pcie_override_devicetree_after_silicon_init(); -- To view, visit https://review.coreboot.org/c/coreboot/+/32534 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib11b580ceb23bd1fe789f549b667a8ced2d859a1 Gerrit-Change-Number: 32534 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-MessageType: newchange

3 5

Change in ...coreboot[master]: soc/intel/cannonlake/acpi: Add board level s0ix call back
by EricR Lai (Code Review) 06 May '19

06 May '19

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32539 Change subject: soc/intel/cannonlake/acpi: Add board level s0ix call back ...................................................................... soc/intel/cannonlake/acpi: Add board level s0ix call back Add board level s0ix call back. Since some driver doesn't care _ON/_OFF method. Add a control method for s0ix usage. BUG=b:129177593 TEST=NA Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I404f388b19355ae89b36d1fb07f9fb4f97eb3b2d --- M src/soc/intel/cannonlake/acpi/lpit.asl 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/32539/1 diff --git a/src/soc/intel/cannonlake/acpi/lpit.asl b/src/soc/intel/cannonlake/acpi/lpit.asl index 8515806..828efd0 100644 --- a/src/soc/intel/cannonlake/acpi/lpit.asl +++ b/src/soc/intel/cannonlake/acpi/lpit.asl @@ -14,6 +14,8 @@ * GNU General Public License for more details. */ +External(\_SB.MS0X, MethodObj) + scope(\_SB) { Device(LPID) { @@ -62,12 +64,20 @@ */ If(Arg2 == 5) { \_SB.PCI0.LPCB.EC0.S0IX(1) + /* provide board level s0ix hook */ + If (CondRefOf (\_SB.MS0X)) { + \_SB.MS0X(1) + } } /* * Function 6. */ If(Arg2 == 6) { \_SB.PCI0.LPCB.EC0.S0IX(0) + /* provide board level s0ix hook */ + If (CondRefOf (\_SB.MS0X)) { + \_SB.MS0X(1) + } } } Return(Buffer(One) {0x00}) -- To view, visit https://review.coreboot.org/c/coreboot/+/32539 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I404f388b19355ae89b36d1fb07f9fb4f97eb3b2d Gerrit-Change-Number: 32539 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

5 9

Change in ...coreboot[master]: soc/apollolake: Add ramstage hook
by Patrick Georgi (Code Review) 06 May '19

06 May '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32543 ) Change subject: soc/apollolake: Add ramstage hook ...................................................................... soc/apollolake: Add ramstage hook A hook for romstage is already existing but not for ramstage. It's very useful for debugging as it allows to run code for testing purposes by the mainboard. Also, it allows to run configuration code or configure FSP options, which don't have a devicetree option. Change-Id: I9edc543943c5cbc696fc6c615cb77ef68294c980 Signed-off-by: Felix Singer <felix.singer(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32543 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/soc/intel/apollolake/chip.c A src/soc/intel/apollolake/include/soc/ramstage.h 2 files changed, 35 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index c3de4ee..279551f 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -50,6 +50,7 @@ #include <soc/systemagent.h> #include <spi-generic.h> #include <timer.h> +#include <soc/ramstage.h> #include "chip.h" @@ -762,6 +763,8 @@ /* Set VTD feature according to devicetree */ silconfig->VtdEnable = cfg->enable_vtd; + + mainboard_silicon_init_params(silconfig); } struct chip_operations soc_intel_apollolake_ops = { @@ -879,4 +882,10 @@ fast_spi_init(); } +__weak +void mainboard_silicon_init_params(FSP_S_CONFIG *silconfig) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +} + BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, spi_flash_init_cb, NULL); diff --git a/src/soc/intel/apollolake/include/soc/ramstage.h b/src/soc/intel/apollolake/include/soc/ramstage.h new file mode 100644 index 0000000..287f2ff --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/ramstage.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * Copyright (C) 2019 9elements Agency GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_APOLLOLAKE_RAMSTAGE_H_ +#define _SOC_APOLLOLAKE_RAMSTAGE_H_ + +#include <fsp/api.h> + +void mainboard_silicon_init_params(FSP_S_CONFIG *silconfig); + +#endif /* _SOC_APOLLOLAKE_RAMSTAGE_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32543 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9edc543943c5cbc696fc6c615cb77ef68294c980 Gerrit-Change-Number: 32543 Gerrit-PatchSet: 6 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in ...coreboot[master]: soc/amd/stoneyridge: Correct bugs in lpc.c
by Marshall Dawson (Code Review) 06 May '19

06 May '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32551 Change subject: soc/amd/stoneyridge: Correct bugs in lpc.c ...................................................................... soc/amd/stoneyridge: Correct bugs in lpc.c Remove the bridge enable step of accessing D14F0x64. This method for enabling the bridge appears to be last present in the SB700 device. Beginning in the SB800 (and all FCH, SoC devices), the enable is in PMxEC[0]. Since the bridge is enabled in bootblock to allow port 80h, there is no need to maintain it in ramstage. Correct the device used for misc. configuration of the LPC bridge. The #defined value removed is 14.0 but the settings are in 14.3. TEST=Boot Grunt, check console and dmesg for errors and warnings BUG=b:131862871 Change-Id: I078be974dc3c78c94cb7c0832518f21bac029ff2 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/lpc.c 1 file changed, 13 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/32551/1 diff --git a/src/soc/amd/stoneyridge/lpc.c b/src/soc/amd/stoneyridge/lpc.c index 9a8c8ef..a838146 100644 --- a/src/soc/amd/stoneyridge/lpc.c +++ b/src/soc/amd/stoneyridge/lpc.c @@ -35,31 +35,22 @@ static void lpc_init(struct device *dev) { u8 byte; - u32 dword; - - /* - * Enable the LPC Controller - * SMBus register 0x64 is not defined in public datasheet. - */ - dword = pci_read_config32(SOC_SMBUS_DEV, 0x64); - dword |= 1 << 20; - pci_write_config32(SOC_SMBUS_DEV, 0x64, dword); /* Initialize isa dma */ isa_dma_init(); /* Enable DMA transaction on the LPC bus */ - byte = pci_read_config8(SOC_SMBUS_DEV, LPC_PCI_CONTROL); + byte = pci_read_config8(dev, LPC_PCI_CONTROL); byte |= LEGACY_DMA_EN; - pci_write_config8(SOC_SMBUS_DEV, LPC_PCI_CONTROL, byte); + pci_write_config8(dev, LPC_PCI_CONTROL, byte); /* Disable the timeout mechanism on LPC */ - byte = pci_read_config8(SOC_SMBUS_DEV, LPC_IO_OR_MEM_DECODE_ENABLE); + byte = pci_read_config8(dev, LPC_IO_OR_MEM_DECODE_ENABLE); byte &= ~LPC_SYNC_TIMEOUT_COUNT_ENABLE; - pci_write_config8(SOC_SMBUS_DEV, LPC_IO_OR_MEM_DECODE_ENABLE, byte); + pci_write_config8(dev, LPC_IO_OR_MEM_DECODE_ENABLE, byte); /* Disable LPC MSI Capability */ - byte = pci_read_config8(SOC_SMBUS_DEV, LPC_MISC_CONTROL_BITS); + byte = pci_read_config8(dev, LPC_MISC_CONTROL_BITS); /* BIT 1 is not defined in public datasheet. */ byte &= ~(1 << 1); @@ -69,15 +60,15 @@ * interrupt and visit LPC. */ byte &= ~LPC_NOHOG; - pci_write_config8(SOC_SMBUS_DEV, LPC_MISC_CONTROL_BITS, byte); + pci_write_config8(dev, LPC_MISC_CONTROL_BITS, byte); /* * Enable hand-instance of the pulse generator and SPI * controller prefetch of flash. */ - byte = pci_read_config8(SOC_SMBUS_DEV, LPC_HOST_CONTROL); + byte = pci_read_config8(dev, LPC_HOST_CONTROL); byte |= PREFETCH_EN_SPI_FROM_HOST | T_START_ENH; - pci_write_config8(SOC_SMBUS_DEV, LPC_HOST_CONTROL, byte); + pci_write_config8(dev, LPC_HOST_CONTROL, byte); cmos_check_update_date(); @@ -161,9 +152,8 @@ pci_dev_set_resources(dev); } -static void set_child_resource(struct device *child, - u32 *reg, - u32 *reg_x) +static void set_child_resource(struct device *dev, struct device *child, + u32 *reg, u32 *reg_x) { struct resource *res; u32 base, end; @@ -272,7 +262,7 @@ wideio_index = sb_set_wideio_range(base, res->size); if (wideio_index != WIDEIO_RANGE_ERROR) { /* preserve wide IO related bits. */ - *reg_x = pci_read_config32(SOC_LPC_DEV, + *reg_x = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE); printk(BIOS_DEBUG, @@ -308,11 +298,8 @@ for (child = link->children; child; child = child->sibling) { if (child->enabled - && (child->path.type == DEVICE_PATH_PNP)) { - set_child_resource(child, - &reg, - &reg_x); - } + && (child->path.type == DEVICE_PATH_PNP)) + set_child_resource(dev, child, &reg, &reg_x); } } pci_write_config32(dev, LPC_IO_PORT_DECODE_ENABLE, reg); -- To view, visit https://review.coreboot.org/c/coreboot/+/32551 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I078be974dc3c78c94cb7c0832518f21bac029ff2 Gerrit-Change-Number: 32551 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/amd/stoneyridge: Move acpi_fill_mcfg to northbridge
by Marshall Dawson (Code Review) 06 May '19

06 May '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32550 Change subject: soc/amd/stoneyridge: Move acpi_fill_mcfg to northbridge ...................................................................... soc/amd/stoneyridge: Move acpi_fill_mcfg to northbridge Relocate the function to the more appropriate file. Change-Id: I92a3e8d0461ae228f6c01567db159e2458de5f6b Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/lpc.c M src/soc/amd/stoneyridge/northbridge.c 2 files changed, 12 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/32550/1 diff --git a/src/soc/amd/stoneyridge/lpc.c b/src/soc/amd/stoneyridge/lpc.c index 87da9f1..9a8c8ef 100644 --- a/src/soc/amd/stoneyridge/lpc.c +++ b/src/soc/amd/stoneyridge/lpc.c @@ -25,7 +25,6 @@ #include <pc80/mc146818rtc.h> #include <pc80/isa-dma.h> #include <arch/ioapic.h> -#include <arch/acpi.h> #include <pc80/i8254.h> #include <pc80/i8259.h> #include <soc/acpi.h> @@ -326,18 +325,6 @@ lpc_enable_childrens_resources(dev); } -unsigned long acpi_fill_mcfg(unsigned long current) -{ - - current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, - CONFIG_MMCONF_BASE_ADDRESS, - 0, - 0, - CONFIG_MMCONF_BUS_NUMBER); - - return current; -} - static struct pci_operations lops_pci = { .set_subsystem = pci_dev_set_subsystem, }; diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 42963c0..5985832 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -176,6 +176,18 @@ setup_ioapic((u8 *)IO_APIC2_ADDR, CONFIG_MAX_CPUS+1); } +unsigned long acpi_fill_mcfg(unsigned long current) +{ + + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, + CONFIG_MMCONF_BASE_ADDRESS, + 0, + 0, + CONFIG_MMCONF_BUS_NUMBER); + + return current; +} + static unsigned long acpi_fill_hest(acpi_hest_t *hest) { void *addr, *current; -- To view, visit https://review.coreboot.org/c/coreboot/+/32550 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I92a3e8d0461ae228f6c01567db159e2458de5f6b Gerrit-Change-Number: 32550 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: WIP: fixup
by Julius Werner (Code Review) 06 May '19

06 May '19

Julius Werner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32537 Change subject: WIP: fixup ...................................................................... WIP: fixup DO NOT REVIEW (yet) Change-Id: Iacd37eb1fad388d9db7267ceccb03e6dcf1ad0d2 Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M src/drivers/pc80/rtc/mc146818rtc.c M src/lib/Makefile.inc M src/soc/rockchip/common/spi.c 3 files changed, 7 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/32537/1 diff --git a/src/drivers/pc80/rtc/mc146818rtc.c b/src/drivers/pc80/rtc/mc146818rtc.c index 99079b9..6e37cd2 100644 --- a/src/drivers/pc80/rtc/mc146818rtc.c +++ b/src/drivers/pc80/rtc/mc146818rtc.c @@ -39,6 +39,9 @@ #define LB_CKS_LOC 0 #endif +/* Don't warn for checking >= LB_CKS_RANGE_START even though it may be 0. */ +#pragma GCC diagnostic ignored "-Wtype-limits" + #include <smp/spinlock.h> #if (defined(__PRE_RAM__) && \ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 1350152..7cf0a62 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -322,9 +322,9 @@ endif # CONFIG_RAMSTAGE_LIBHWBASE +ifeq ($(CONFIG_GENERIC_SPD_BIN),y) romstage-y += spd_bin.c -ifeq ($(CONFIG_GENERIC_SPD_BIN),y) LIB_SPD_BIN = $(obj)/spd.bin LIB_SPD_DEPS = $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) diff --git a/src/soc/rockchip/common/spi.c b/src/soc/rockchip/common/spi.c index 98016c0..e929419 100644 --- a/src/soc/rockchip/common/spi.c +++ b/src/soc/rockchip/common/spi.c @@ -96,7 +96,7 @@ void rockchip_spi_init(unsigned int bus, unsigned int speed_hz) { - assert(bus >= 0 && bus < ARRAY_SIZE(rockchip_spi_slaves)); + assert(bus < ARRAY_SIZE(rockchip_spi_slaves)); struct rockchip_spi *regs = rockchip_spi_slaves[bus].regs; unsigned int ctrlr0 = 0; @@ -134,13 +134,13 @@ void rockchip_spi_set_sample_delay(unsigned int bus, unsigned int delay_ns) { - assert(bus >= 0 && bus < ARRAY_SIZE(rockchip_spi_slaves)); + assert(bus < ARRAY_SIZE(rockchip_spi_slaves)); struct rockchip_spi *regs = rockchip_spi_slaves[bus].regs; unsigned int rsd; /* Rxd Sample Delay */ rsd = DIV_ROUND_CLOSEST(delay_ns * (SPI_SRCCLK_HZ >> 8), 1*GHz >> 8); - assert(rsd >= 0 && rsd <= 3); + assert(rsd <= 3); clrsetbits_le32(&regs->ctrlr0, SPI_RXDSD_MASK << SPI_RXDSD_OFFSET, rsd << SPI_RXDSD_OFFSET); } -- To view, visit https://review.coreboot.org/c/coreboot/+/32537 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iacd37eb1fad388d9db7267ceccb03e6dcf1ad0d2 Gerrit-Change-Number: 32537 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

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