coreboot-gerrit May 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: mb/lenovo/r500: Add mainboard
by Angel Pons (Code Review) 06 May '19

06 May '19

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28644 ) Change subject: mb/lenovo/r500: Add mainboard ...................................................................... Patch Set 9: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/28644 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e129b2e916acdf2b8534fa9d8d2cfc8f64f5815 Gerrit-Change-Number: 28644 Gerrit-PatchSet: 9 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 06 May 2019 20:36:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...libgfxinit[master]: gma config: Make Config.CPU and Config.CPU_Var variable
by Patrick Georgi (Code Review) 06 May '19

06 May '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/libgfxinit/+/27068 ) Change subject: gma config: Make Config.CPU and Config.CPU_Var variable ...................................................................... Patch Set 7: Code-Review+2 (1 comment) https://review.coreboot.org/#/c/27068/7/common/Makefile.inc File common/Makefile.inc: https://review.coreboot.org/#/c/27068/7/common/Makefile.inc@64 PS7, Line 64: _GEN_CONST_TARGET := <cpufunc> # set to `constant` to generate constants. that's positively crazy :-) -- To view, visit https://review.coreboot.org/c/libgfxinit/+/27068 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: If409b5afbd975f3a42e28ff191a092f89ece5ae2 Gerrit-Change-Number: 27068 Gerrit-PatchSet: 7 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Adrian-Ken Rueegsegger <ken(a)codelabs.ch> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Reto Buerki <reet(a)codelabs.ch> Gerrit-Comment-Date: Mon, 06 May 2019 19:56:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...libhwbase[master]: direct pci, debug: Fix minor style issues
by Patrick Georgi (Code Review) 06 May '19

06 May '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/libhwbase/+/26840 ) Change subject: direct pci, debug: Fix minor style issues ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/libhwbase/+/26840 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libhwbase Gerrit-Branch: master Gerrit-Change-Id: I8adbf75babc233dff79e5c8921d1f24692a939ab Gerrit-Change-Number: 26840 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 06 May 2019 19:53:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...libhwbase[master]: Makefile: Revise support for generated sources
by Patrick Georgi (Code Review) 06 May '19

06 May '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/libhwbase/+/27139 ) Change subject: Makefile: Revise support for generated sources ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/libhwbase/+/27139 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libhwbase Gerrit-Branch: master Gerrit-Change-Id: I5479c436f39088ae9d0ebddf9a97446be0f191f3 Gerrit-Change-Number: 27139 Gerrit-PatchSet: 3 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Adrian-Ken Rueegsegger <ken(a)codelabs.ch> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Reto Buerki <reet(a)codelabs.ch> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Mon, 06 May 2019 19:53:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...libhwbase[master]: Makefile: Add bincompare target
by Stefan Reinauer (Code Review) 06 May '19

06 May '19

Stefan Reinauer has posted comments on this change. ( https://review.coreboot.org/c/libhwbase/+/27144 ) Change subject: Makefile: Add bincompare target ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/libhwbase/+/27144 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libhwbase Gerrit-Branch: master Gerrit-Change-Id: I7d2dfc7a2e34851fe01a9d72e0d90db00a284eaf Gerrit-Change-Number: 27144 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-CC: Alex Thiessen <alex.thiessen.de+coreboot(a)gmail.com> Gerrit-Comment-Date: Mon, 06 May 2019 18:34:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...libhwbase[master]: Makefile: Revise support for generated sources
by Stefan Reinauer (Code Review) 06 May '19

06 May '19

Stefan Reinauer has posted comments on this change. ( https://review.coreboot.org/c/libhwbase/+/27139 ) Change subject: Makefile: Revise support for generated sources ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/libhwbase/+/27139 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libhwbase Gerrit-Branch: master Gerrit-Change-Id: I5479c436f39088ae9d0ebddf9a97446be0f191f3 Gerrit-Change-Number: 27139 Gerrit-PatchSet: 3 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Adrian-Ken Rueegsegger <ken(a)codelabs.ch> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Reto Buerki <reet(a)codelabs.ch> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Mon, 06 May 2019 18:33:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/bsw: Move memory init values into `romstage.h`
by Nico Huber (Code Review) 06 May '19

06 May '19

Hello Patrick Rudolph, Frans Hendriks, Matt DeVillier, build bot (Jenkins), Michał Żygowski, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/32592 to look at the new patch set (#3). Change subject: soc/intel/bsw: Move memory init values into `romstage.h` ...................................................................... soc/intel/bsw: Move memory init values into `romstage.h` `chip.h` is usually used as devicetree interface. Change-Id: Ied30927d68927b86758a84ccf3f5fbd8cce632f1 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/mainboard/google/cyan/romstage.c M src/mainboard/intel/strago/romstage.c M src/soc/intel/braswell/chip.h M src/soc/intel/braswell/include/soc/romstage.h 4 files changed, 4 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/32592/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/32592 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied30927d68927b86758a84ccf3f5fbd8cce632f1 Gerrit-Change-Number: 32592 Gerrit-PatchSet: 3 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: mb/google/sarien: Turn off camera power when s0ix
by EricR Lai (Code Review) 06 May '19

06 May '19

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32519 Change subject: mb/google/sarien: Turn off camera power when s0ix ...................................................................... mb/google/sarien: Turn off camera power when s0ix Turn off camera power when s0ix for power saving. ACPI _ON/_OFF is not taken by UVC driver, so invoke s0ix method from LPIT. BUG=b:129177593 TEST= measure camera power comsumption is 0mV under s0ix Change-Id: I5a9b7ec1e95cc9931d8d5f2dc1254805c9d0ffed Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> --- M src/mainboard/google/sarien/dsdt.asl A src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl A src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl M src/soc/intel/cannonlake/acpi/lpit.asl 4 files changed, 62 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/32519/1 diff --git a/src/mainboard/google/sarien/dsdt.asl b/src/mainboard/google/sarien/dsdt.asl index e5b0cca..58e0704 100644 --- a/src/mainboard/google/sarien/dsdt.asl +++ b/src/mainboard/google/sarien/dsdt.asl @@ -40,6 +40,8 @@ #include <soc/intel/cannonlake/acpi/northbridge.asl> #include <soc/intel/cannonlake/acpi/southbridge.asl> } + /* Per board variant mainboard hooks. */ + #include <variant/acpi/mainboard.asl> } #if CONFIG(CHROMEOS) diff --git a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000..7c22710 --- /dev/null +++ b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define CAM_EN GPP_B11 + +/* Method called from LPIT prior to enter s0ix state */ +Method (MS0X, 1) { + If (Arg0) { + Printf ("OS Enter S0ix") + /* Turn on camera power */ + \_SB.PCI0.STXS (GPP_B11) + } Else { + Printf ("OS Exit S0ix") + /* Turn off camera power */ + \_SB.PCI0.CTXS (GPP_B11) + } +} diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000..7c22710 --- /dev/null +++ b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define CAM_EN GPP_B11 + +/* Method called from LPIT prior to enter s0ix state */ +Method (MS0X, 1) { + If (Arg0) { + Printf ("OS Enter S0ix") + /* Turn on camera power */ + \_SB.PCI0.STXS (GPP_B11) + } Else { + Printf ("OS Exit S0ix") + /* Turn off camera power */ + \_SB.PCI0.CTXS (GPP_B11) + } +} diff --git a/src/soc/intel/cannonlake/acpi/lpit.asl b/src/soc/intel/cannonlake/acpi/lpit.asl index 8515806..00115a5 100644 --- a/src/soc/intel/cannonlake/acpi/lpit.asl +++ b/src/soc/intel/cannonlake/acpi/lpit.asl @@ -62,12 +62,14 @@ */ If(Arg2 == 5) { \_SB.PCI0.LPCB.EC0.S0IX(1) + \_SB.MS0X(1) } /* * Function 6. */ If(Arg2 == 6) { \_SB.PCI0.LPCB.EC0.S0IX(0) + \_SB.MS0X(0) } } Return(Buffer(One) {0x00}) -- To view, visit https://review.coreboot.org/c/coreboot/+/32519 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a9b7ec1e95cc9931d8d5f2dc1254805c9d0ffed Gerrit-Change-Number: 32519 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: WIP: Power resource stub
by Tim Wawrzynczak (Code Review) 06 May '19

06 May '19

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32188 Change subject: WIP: Power resource stub ...................................................................... WIP: Power resource stub Change-Id: I253a11e24a086792e151c3e47335586d43c3fce0 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/device/device_util.c A src/drivers/generic/power_resource/Kconfig A src/drivers/generic/power_resource/Makefile.inc A src/drivers/generic/power_resource/chip.h A src/drivers/generic/power_resource/power_resource.c M src/drivers/i2c/generic/chip.h M src/drivers/i2c/generic/generic.c M src/include/device/device.h M src/include/device/path.h M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M util/sconfig/main.c M util/sconfig/sconfig.h M util/sconfig/sconfig.l M util/sconfig/sconfig.y 14 files changed, 256 insertions(+), 54 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/32188/1 diff --git a/src/device/device_util.c b/src/device/device_util.c index 5c4f911..f6474ef 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -232,6 +232,8 @@ snprintf(buffer, sizeof(buffer), "MMIO: %08x", dev->path.mmio.addr); break; + case DEVICE_PATH_POWER_RES: + snprintf(buffer, sizeof(buffer), "POWER_RES"); default: printk(BIOS_ERR, "Unknown device path type: %d\n", dev->path.type); diff --git a/src/drivers/generic/power_resource/Kconfig b/src/drivers/generic/power_resource/Kconfig new file mode 100644 index 0000000..f0d4769 --- /dev/null +++ b/src/drivers/generic/power_resource/Kconfig @@ -0,0 +1,3 @@ +config DRIVERS_GENERIC_POWER_RESOURCE + bool + depends on HAVE_ACPI_TABLES diff --git a/src/drivers/generic/power_resource/Makefile.inc b/src/drivers/generic/power_resource/Makefile.inc new file mode 100644 index 0000000..e076252 --- /dev/null +++ b/src/drivers/generic/power_resource/Makefile.inc @@ -0,0 +1 @@ +ramstage-y += power_resource.c diff --git a/src/drivers/generic/power_resource/chip.h b/src/drivers/generic/power_resource/chip.h new file mode 100644 index 0000000..49ce49f --- /dev/null +++ b/src/drivers/generic/power_resource/chip.h @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __GENERIC_POWER_RESOURCE_CHIP_H__ +#define __GENERIC_POWER_RESOURCE_CHIP_H__ + +#include <arch/acpi_device.h> + +struct drivers_generic_power_resource_config { + /* GPIO used to take device out of reset or to put it into reset. */ + struct acpi_gpio reset_gpio; + /* Delay to be inserted after device is taken out of reset. */ + unsigned int reset_delay_ms; + /* Delay to be inserted after device is put into reset. */ + unsigned int reset_off_delay_ms; + /* GPIO used to enable device. */ + struct acpi_gpio enable_gpio; + /* Delay to be inserted after device is enabled. */ + unsigned int enable_delay_ms; + /* Delay to be inserted after device is disabled. */ + unsigned int enable_off_delay_ms; + /* GPIO used to stop operation of device. */ + struct acpi_gpio stop_gpio; + /* Delay to be inserted after disabling stop. */ + unsigned int stop_delay_ms; + /* Delay to be inserted after enabling stop. */ + unsigned int stop_off_delay_ms; +}; + +#if CONFIG(HAVE_ACPI_TABLES) + +/* + * + */ +void power_resource_generic_fill_ssdt(struct device *dev); + +#endif /* #if CONFIG(HAVE_ACPI_TABLES) */ + +#endif /* __GENERIC_POWER_RESOURCE_CHIP_H__ */ diff --git a/src/drivers/generic/power_resource/power_resource.c b/src/drivers/generic/power_resource/power_resource.c new file mode 100644 index 0000000..13f922e --- /dev/null +++ b/src/drivers/generic/power_resource/power_resource.c @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <device/path.h> +#include <console/console.h> +#include "chip.h" + +static struct device_operations power_resource_dev_ops = { + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, + .scan_bus = &scan_generic_bus, + .acpi_fill_ssdt_generator = &power_resource_generic_fill_ssdt +}; + +static void power_resource_dev_enable(struct device *dev) +{ + printk(BIOS_WARNING, "@@ in power_resource_dev_enable\n"); + dev->ops = &power_resource_dev_ops; +} + +struct chip_operations drivers_generic_power_resource_ops = { + CHIP_NAME("Power resource") + .enable_dev = power_resource_dev_enable +}; + +#if CONFIG(HAVE_ACPI_TABLES) + +static void fill_ssdt(struct device *dev, + struct drivers_generic_power_resource_config *config) +{ + const struct acpi_power_res_params power_res_params = { + &config->reset_gpio, + config->reset_delay_ms, + config->reset_off_delay_ms, + &config->enable_gpio, + config->enable_delay_ms, + config->enable_off_delay_ms, + &config->stop_gpio, + config->stop_delay_ms, + config->stop_off_delay_ms + }; + + acpi_device_add_power_res(&power_res_params); +} + +void power_resource_generic_fill_ssdt(struct device *dev) +{ + printk(BIOS_WARNING, "@@ in power_resource fill ssdt\n"); + fill_ssdt(dev, dev->chip_info); +} + +#endif /* CONFIG(HAVE_ACPI_TABLES) */ diff --git a/src/drivers/i2c/generic/chip.h b/src/drivers/i2c/generic/chip.h index 9e2abb9..ec83365 100644 --- a/src/drivers/i2c/generic/chip.h +++ b/src/drivers/i2c/generic/chip.h @@ -50,28 +50,6 @@ /* Disable reset and enable GPIO export in _CRS */ bool disable_gpio_export_in_crs; - /* Does the device have a power resource? */ - bool has_power_resource; - - /* GPIO used to take device out of reset or to put it into reset. */ - struct acpi_gpio reset_gpio; - /* Delay to be inserted after device is taken out of reset. */ - unsigned int reset_delay_ms; - /* Delay to be inserted after device is put into reset. */ - unsigned int reset_off_delay_ms; - /* GPIO used to enable device. */ - struct acpi_gpio enable_gpio; - /* Delay to be inserted after device is enabled. */ - unsigned int enable_delay_ms; - /* Delay to be inserted after device is disabled. */ - unsigned int enable_off_delay_ms; - /* GPIO used to stop operation of device. */ - struct acpi_gpio stop_gpio; - /* Delay to be inserted after disabling stop. */ - unsigned int stop_delay_ms; - /* Delay to be inserted after enabling stop. */ - unsigned int stop_off_delay_ms; - /* Generic properties for exporting device-specific data to the OS */ struct acpi_dp property_list[MAX_GENERIC_PROPERTY_LIST]; int property_count; diff --git a/src/drivers/i2c/generic/generic.c b/src/drivers/i2c/generic/generic.c index 598f211..161086e 100644 --- a/src/drivers/i2c/generic/generic.c +++ b/src/drivers/i2c/generic/generic.c @@ -23,19 +23,24 @@ #include <stdint.h> #include <string.h> #include "chip.h" +#include <drivers/generic/power_resource/chip.h> #if CONFIG(HAVE_ACPI_TABLES) -static bool i2c_generic_add_gpios_to_crs(struct drivers_i2c_generic_config *cfg) +static bool i2c_generic_add_gpios_to_crs(struct drivers_generic_power_resource_config *pr_config, + struct drivers_i2c_generic_config *cfg) { /* * Return false if: * 1. Request to explicitly disable export of GPIOs in CRS, or * 2. Both reset and enable GPIOs are not provided. */ + if (!pr_config) + return false; + if (cfg->disable_gpio_export_in_crs || - ((cfg->reset_gpio.pin_count == 0) && - (cfg->enable_gpio.pin_count == 0))) + ((pr_config->reset_gpio.pin_count == 0) && + (pr_config->enable_gpio.pin_count == 0))) return false; return true; @@ -70,6 +75,10 @@ int curr_index = 0; int reset_gpio_index = -1, enable_gpio_index = -1, irq_gpio_index = -1; const char *path = acpi_device_path(dev); + struct device *pr_dev; + struct drivers_generic_power_resource_config *pr_config; + struct acpi_gpio *reset_gpio; + struct acpi_gpio *enable_gpio; if (!dev->enabled || !scope) return; @@ -79,6 +88,20 @@ return; } + /* Check for an associated power resource device */ + if (dev->link_list && dev->link_list->children && + dev->link_list->children->path.type == DEVICE_PATH_POWER_RES) { + pr_dev = dev->link_list->children; + pr_config = pr_dev->chip_info; + reset_gpio = &pr_config->reset_gpio; + enable_gpio = &pr_config->enable_gpio; + } else { + pr_dev = NULL; + pr_config = NULL; + reset_gpio = NULL; + enable_gpio = NULL; + } + /* Device */ acpigen_write_scope(scope); acpigen_write_device(acpi_device_name(dev)); @@ -101,10 +124,10 @@ else acpi_device_write_interrupt(&config->irq); - if (i2c_generic_add_gpios_to_crs(config) == true) { - reset_gpio_index = i2c_generic_write_gpio(&config->reset_gpio, + if (pr_config && i2c_generic_add_gpios_to_crs(pr_config, config) == true) { + reset_gpio_index = i2c_generic_write_gpio(reset_gpio, &curr_index); - enable_gpio_index = i2c_generic_write_gpio(&config->enable_gpio, + enable_gpio_index = i2c_generic_write_gpio(enable_gpio, &curr_index); } acpigen_write_resourcetemplate_footer(); @@ -120,8 +143,15 @@ (reset_gpio_index != -1) || (enable_gpio_index != -1) || (irq_gpio_index != -1)) { dsd = acpi_dp_new_table("_DSD"); + + /* + TODO: tdw + remove this + */ if (config->probed) acpi_dp_add_integer(dsd, "linux,probed", 1); + /* end remove */ + if (irq_gpio_index != -1) acpi_dp_add_gpio(dsd, "irq-gpios", path, irq_gpio_index, 0, @@ -130,11 +160,11 @@ if (reset_gpio_index != -1) acpi_dp_add_gpio(dsd, "reset-gpios", path, reset_gpio_index, 0, - config->reset_gpio.polarity); + reset_gpio->polarity); if (enable_gpio_index != -1) acpi_dp_add_gpio(dsd, "enable-gpios", path, enable_gpio_index, 0, - config->enable_gpio.polarity); + enable_gpio->polarity); /* Add generic property list */ acpi_dp_add_property_list(dsd, config->property_list, config->property_count); @@ -142,20 +172,8 @@ } /* Power Resource */ - if (config->has_power_resource) { - const struct acpi_power_res_params power_res_params = { - &config->reset_gpio, - config->reset_delay_ms, - config->reset_off_delay_ms, - &config->enable_gpio, - config->enable_delay_ms, - config->enable_off_delay_ms, - &config->stop_gpio, - config->stop_delay_ms, - config->stop_off_delay_ms - }; - acpi_device_add_power_res(&power_res_params); - } + if (pr_dev) + power_resource_generic_fill_ssdt(pr_dev); /* Callback if any. */ if (callback) diff --git a/src/include/device/device.h b/src/include/device/device.h index 39a4d56..6a24365 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -126,6 +126,7 @@ unsigned int on_mainboard : 1; unsigned int disable_pcie_aspm : 1; unsigned int hidden : 1; /* set if we should hide from UI */ + unsigned int probed : 1; /* set if device's presence should be probed */ struct pci_irq_info pci_irq_info[4]; u8 command; diff --git a/src/include/device/path.h b/src/include/device/path.h index 6736bed..46180d7 100644 --- a/src/include/device/path.h +++ b/src/include/device/path.h @@ -19,6 +19,7 @@ DEVICE_PATH_SPI, DEVICE_PATH_USB, DEVICE_PATH_MMIO, + DEVICE_PATH_POWER_RES /* * When adding path types to this table, please also update the @@ -42,6 +43,7 @@ "DEVICE_PATH_SPI", \ "DEVICE_PATH_USB", \ "DEVICE_PATH_MMIO", \ + "DEVICE_PATH_POWER_RES", \ } struct domain_path { diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 2f1120a..2562cfb 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -185,11 +185,75 @@ register "wake" = "GPE0_PME_B0" device pci 14.3 on end # CNVi wifi end - device pci 14.5 on end # SDCard - device pci 15.0 on end # I2C #0 - device pci 15.1 on end # I2C #1 - device pci 15.2 on end # I2C #2 - device pci 15.3 on end # I2C #3 + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D21_IRQ)" + register "wake" = "GPE0_DW0_21" + device i2c 15 on end + end + end # I2C #0 + device pci 15.1 on + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + device i2c 49 on #probed + chip drivers/generic/power_resource + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "reset_delay_ms" = "100" + register "reset_off_delay_ms" = "5" + register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)" + register "stop_off_delay_ms" = "5" + device power_resource 0 on end + end + end + end + end # I2C #1 + device pci 15.2 on + chip drivers/generic/gpio_keys + register "name" = ""PENH"" + register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_HIGH(GPP_A8)" + register "key.dev_name" = ""EJCT"" + register "key.linux_code" = "SW_PEN_INSERTED" + register "key.linux_input_type" = "EV_SW" + register "key.label" = ""pen_eject"" + device generic 0 on end + end + end # I2C #2 + device pci 15.3 on + chip drivers/i2c/sx9310 + register "desc" = ""SAR Proximity Sensor"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A0_IRQ)" + register "speed" = "I2C_SPEED_FAST" + register "uid" = "1" + register "reg_prox_ctrl0" = "0x10" + register "reg_prox_ctrl1" = "0x00" + register "reg_prox_ctrl2" = "0x84" + register "reg_prox_ctrl3" = "0x0e" + register "reg_prox_ctrl4" = "0x07" + register "reg_prox_ctrl5" = "0xc6" + register "reg_prox_ctrl6" = "0x20" + register "reg_prox_ctrl7" = "0x0d" + register "reg_prox_ctrl8" = "0x8d" + register "reg_prox_ctrl9" = "0x43" + register "reg_prox_ctrl10" = "0x1f" + register "reg_prox_ctrl11" = "0x00" + register "reg_prox_ctrl12" = "0x00" + register "reg_prox_ctrl13" = "0x00" + register "reg_prox_ctrl14" = "0x00" + register "reg_prox_ctrl15" = "0x00" + register "reg_prox_ctrl16" = "0x00" + register "reg_prox_ctrl17" = "0x00" + register "reg_prox_ctrl18" = "0x00" + register "reg_prox_ctrl19" = "0x00" + register "reg_sar_ctrl0" = "0x50" + register "reg_sar_ctrl1" = "0x8a" + register "reg_sar_ctrl2" = "0x3c" + device i2c 28 on end + end + end # I2C #3 device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 4ac935e..c66e66e 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -511,8 +511,17 @@ sprintf(name, "_dev%d", new_d->id); new_d->name = name; - new_d->enabled = status & 0x01; - new_d->hidden = (status >> 1) & 0x01; + /* probed? */ + if (status == 2) { + new_d->probed = 1; + new_d->enabled = 0; + new_d->hidden = 0; + } else { + new_d->enabled = status & 0x01; + new_d->hidden = (status >> 1) & 0x01; + new_d->probed = 0; + } + new_d->chip_instance = chip_instance; chip_instance->ref_count++; @@ -566,6 +575,9 @@ case MMIO: new_d->path = ".type=DEVICE_PATH_MMIO,{.mmio={ .addr = 0x%x }}"; break; + + case POWER_RESOURCE: + new_d->path = ".type=DEVICE_PATH_POWER_RES,"; } return new_d; @@ -789,6 +801,7 @@ fprintf(fil, "},\n"); fprintf(fil, "\t.enabled = %d,\n", ptr->enabled); fprintf(fil, "\t.hidden = %d,\n", ptr->hidden); + fprintf(fil, "\t.probed = %d,\n", ptr->probed); fprintf(fil, "\t.on_mainboard = 1,\n"); if (ptr->subsystem_vendor > 0) fprintf(fil, "\t.subsystem_vendor = 0x%04x,\n", diff --git a/util/sconfig/sconfig.h b/util/sconfig/sconfig.h index 389d697..5aae51ad 100644 --- a/util/sconfig/sconfig.h +++ b/util/sconfig/sconfig.h @@ -102,9 +102,10 @@ /* Monotonically increasing ID for the device. */ int id; - /* Indicates device status (enabled / hidden or not). */ + /* Indicates device status (enabled / hidden / probed or not). */ int enabled; int hidden; + int probed; /* Subsystem IDs for the device. */ int subsystem_vendor; diff --git a/util/sconfig/sconfig.l b/util/sconfig/sconfig.l index b21cca5..32ecd57 100755 --- a/util/sconfig/sconfig.l +++ b/util/sconfig/sconfig.l @@ -29,11 +29,13 @@ register {return(REGISTER);} on {yylval.number=1; return(BOOL);} off {yylval.number=0; return(BOOL);} +probed {yylval.number=2; return(PROBED);} hidden {yylval.number=3; return(HIDDEN);} pci {yylval.number=PCI; return(BUS);} ioapic {yylval.number=IOAPIC; return(BUS);} pnp {yylval.number=PNP; return(BUS);} i2c {yylval.number=I2C; return(BUS);} +power_resource {yylval.number=POWER_RESOURCE; return(BUS);} lapic {yylval.number=APIC; return(BUS);} cpu_cluster {yylval.number=CPU_CLUSTER; return(BUS);} cpu {yylval.number=CPU; return(BUS);} diff --git a/util/sconfig/sconfig.y b/util/sconfig/sconfig.y index 3a6e9ab..ce0f111 100755 --- a/util/sconfig/sconfig.y +++ b/util/sconfig/sconfig.y @@ -31,7 +31,7 @@ int number; } -%token CHIP DEVICE REGISTER BOOL HIDDEN BUS RESOURCE END EQUALS HEX STRING PCI PNP I2C APIC CPU_CLUSTER CPU DOMAIN IRQ DRQ IO NUMBER SUBSYSTEMID INHERIT IOAPIC_IRQ IOAPIC PCIINT GENERIC SPI USB MMIO +%token CHIP DEVICE REGISTER BOOL HIDDEN PROBED BUS RESOURCE END EQUALS HEX STRING PCI PNP I2C APIC CPU_CLUSTER CPU DOMAIN IRQ DRQ IO NUMBER SUBSYSTEMID INHERIT IOAPIC_IRQ IOAPIC PCIINT GENERIC SPI USB MMIO POWER_RESOURCE %% devtree: { cur_parent = root_parent; } chip; @@ -56,7 +56,7 @@ cur_parent = $<dev>5->parent; }; -status: BOOL | HIDDEN; +status: BOOL | HIDDEN | PROBED; resource: RESOURCE NUMBER /* == resnum */ EQUALS NUMBER /* == resval */ { add_resource(cur_parent, $<number>1, strtol($<string>2, NULL, 0), strtol($<string>4, NULL, 0)); } ; -- To view, visit https://review.coreboot.org/c/coreboot/+/32188 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I253a11e24a086792e151c3e47335586d43c3fce0 Gerrit-Change-Number: 32188 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

4 13

Change in ...libgfxinit[master]: gma broxton power/clocks: Turn pre-condition into code
by Nico Huber (Code Review) 06 May '19

06 May '19

Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/c/libgfxinit/+/27054 ) Change subject: gma broxton power/clocks: Turn pre-condition into code ...................................................................... gma broxton power/clocks: Turn pre-condition into code In case `Config.Default_CDClk_Freq` is not constant, we have to filter it. Change-Id: I3ccafdc91a6e11fdc565e154f1394598a4572449 Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/c/libgfxinit/+/27054 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M common/broxton/hw-gfx-gma-power_and_clocks.adb 1 file changed, 8 insertions(+), 5 deletions(-) Approvals: Nico Huber: Verified Arthur Heymans: Looks good to me, approved diff --git a/common/broxton/hw-gfx-gma-power_and_clocks.adb b/common/broxton/hw-gfx-gma-power_and_clocks.adb index 8aa9a21..f6576d9 100644 --- a/common/broxton/hw-gfx-gma-power_and_clocks.adb +++ b/common/broxton/hw-gfx-gma-power_and_clocks.adb @@ -216,12 +216,15 @@ CDClk_Ref : constant := 19_200_000; - procedure Set_CDClk (Freq : Frequency_Type) - with - Pre => - Freq = CDClk_Ref or Freq = 144_000_000 or Freq = 288_000_000 or - Freq = 384_000_000 or Freq = 576_000_000 or Freq = 624_000_000 + procedure Set_CDClk (Freq_In : Frequency_Type) is + Freq : constant Frequency_Type := + (if Freq_In = CDClk_Ref then CDClk_Ref + elsif Freq_In <= 144_000_000 then 144_000_000 + elsif Freq_In <= 288_000_000 then 288_000_000 + elsif Freq_In <= 384_000_000 then 384_000_000 + elsif Freq_In <= 576_000_000 then 576_000_000 + else 624_000_000); VCO : constant Int64 := CDClk_Ref * (if Freq = CDClk_Ref then -- To view, visit https://review.coreboot.org/c/libgfxinit/+/27054 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I3ccafdc91a6e11fdc565e154f1394598a4572449 Gerrit-Change-Number: 27054 Gerrit-PatchSet: 8 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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coreboot-gerrit May 2019