coreboot-gerrit May 2019

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Change in ...coreboot[master]: mb/intel/saddlebrook: Refactor to get rid of `pei_data`
by Patrick Rudolph (Code Review) 06 May '19

06 May '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32591 ) Change subject: mb/intel/saddlebrook: Refactor to get rid of `pei_data` ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/32591 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I399dd89f85ccea43fdf90bd895e71324f4b409cc Gerrit-Change-Number: 32591 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 06 May 2019 15:41:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: src/arch/x86: Use core apic id to get cpu_index()
by Subrata Banik (Code Review) 06 May '19

06 May '19

Hello Patrick Rudolph, Aaron Durbin, ron minnich, Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/26346 to look at the new patch set (#12). Change subject: src/arch/x86: Use core apic id to get cpu_index() ...................................................................... src/arch/x86: Use core apic id to get cpu_index() This cpu_index() implementation assumes that cpu_index() function might always getting called from coreboot context (ESP stack pointer will always refer to coreboot). This might not true incase of proposed PI spec MP_SERVICES_PPI implementation, where FSP context (stack pointer refers to fsp) will request to get cpu_index(), natural alignment logic will use ESP and retrieve struct cpu_info *ci from (stack_top - 8 byte). This is not the place where cpu_index is actually stored by ramstage c_start.S Hence this patch tries to remove those dependencies while retriving cpu_index(), rather it uses cpuid to fetch lapic id and matches with cpu_mp structure to get correct cpu_index() BRANCH=none BUG=b:79562868 TEST=Ensures functions can be run on APs without any failure and cpu_index() also provides correct index number. Change-Id: I55023a3e0cf42f0496d45bc6af8ead447f402350 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/arch/x86/cpu.c M src/arch/x86/include/arch/cpu.h 2 files changed, 20 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/26346/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/26346 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I55023a3e0cf42f0496d45bc6af8ead447f402350 Gerrit-Change-Number: 26346 Gerrit-PatchSet: 12 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: ec/lenovo/h8: Add function to query sense state
by Patrick Rudolph (Code Review) 06 May '19

06 May '19

Patrick Rudolph has uploaded a new patch set (#5) to the change originally created by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/29204 ) Change subject: ec/lenovo/h8: Add function to query sense state ...................................................................... ec/lenovo/h8: Add function to query sense state * Add function to wait for sense registers to become valid. * Add function to retrieve Fn-Key state. Tested on Lenovo T500: * It takes about 700msec for the registers to become valid. Tested on Lenovo T520: * It takes less than 150msec for the registers to become valid. Change-Id: Ie27e2881a256c4efb3def11f05070c446db6e5fc Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/ec/lenovo/h8/Makefile.inc M src/ec/lenovo/h8/h8.h A src/ec/lenovo/h8/sense.c 3 files changed, 66 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/29204/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/29204 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie27e2881a256c4efb3def11f05070c446db6e5fc Gerrit-Change-Number: 29204 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: src/arch/x86: Use core apic id to get cpu_index()
by Subrata Banik (Code Review) 06 May '19

06 May '19

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/26346 ) Change subject: src/arch/x86: Use core apic id to get cpu_index() ...................................................................... Patch Set 10: (1 comment) https://review.coreboot.org/#/c/26346/10/src/soc/intel/common/block/cpu/cpu… File src/soc/intel/common/block/cpu/cpulib.c: https://review.coreboot.org/#/c/26346/10/src/soc/intel/common/block/cpu/cpu… PS10, Line 26: #include <arch/cpu.h> > duplicated ? removed this file now -- To view, visit https://review.coreboot.org/c/coreboot/+/26346 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I55023a3e0cf42f0496d45bc6af8ead447f402350 Gerrit-Change-Number: 26346 Gerrit-PatchSet: 10 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Mon, 06 May 2019 14:28:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: comment

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Change in ...coreboot[master]: src/arch/x86: Use core apic id to get cpu_index()
by Subrata Banik (Code Review) 06 May '19

06 May '19

Hello Patrick Rudolph, Aaron Durbin, ron minnich, Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/26346 to look at the new patch set (#11). Change subject: src/arch/x86: Use core apic id to get cpu_index() ...................................................................... src/arch/x86: Use core apic id to get cpu_index() This cpu_index() implementation assumes that cpu_index() function might always getting called from coreboot context (ESP stack pointer will always refer to coreboot). This might not true incase of proposed PI spec MP_SERVICES_PPI implementation, where FSP context (stack pointer refers to fsp) will request to get cpu_index(), natural alignment logic will use ESP and retrieve struct cpu_info *ci from (stack_top - 8 byte). This is not the place where cpu_index is actually stored by ramstage c_start.S Hence this patch tries to remove those dependencies while retriving cpu_index(), rather it uses cpuid to fetch lapic id and matches with cpu_mp structure to get correct cpu_index() BRANCH=none BUG=b:79562868 TEST=Ensures functions can be run on APs without any failure and cpu_index() also provides correct index number. Change-Id: I55023a3e0cf42f0496d45bc6af8ead447f402350 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/arch/x86/cpu.c M src/arch/x86/include/arch/cpu.h 2 files changed, 14 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/26346/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/26346 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I55023a3e0cf42f0496d45bc6af8ead447f402350 Gerrit-Change-Number: 26346 Gerrit-PatchSet: 11 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: vboot: remove use of GoogleBinaryBlockHeader
by Joel Kitching (Code Review) 06 May '19

06 May '19

Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32455 Change subject: vboot: remove use of GoogleBinaryBlockHeader ...................................................................... vboot: remove use of GoogleBinaryBlockHeader Remove use of deprecated GoogleBinaryBlockHeader struct, and replace with vb2_gbb_header. BUG=b:124141368, chromium:954774 TEST=make clean && make test-abuild BRANCH=none Change-Id: Iee3bd877cb1791a689efdeabda324f43f7d0c6f2 Signed-off-by: Joel Kitching <kitching(a)google.com> --- M src/security/vboot/gbb.c M src/security/vboot/gbb.h M src/security/vboot/vboot_common.c 3 files changed, 11 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/32455/1 diff --git a/src/security/vboot/gbb.c b/src/security/vboot/gbb.c index 8f57c79..5293033 100644 --- a/src/security/vboot/gbb.c +++ b/src/security/vboot/gbb.c @@ -13,17 +13,19 @@ * GNU General Public License for more details. */ +#define NEED_VB20_INTERNALS /* Peeking into vb2_gbb_header */ + #include <commonlib/region.h> #include <console/console.h> #include <fmap.h> -#include <gbb_header.h> #include <security/vboot/gbb.h> #include <string.h> +#include <vb2_api.h> #define GBB_FMAP_REGION_NAME "GBB" /* Copy of GBB header read from boot media. */ -static GoogleBinaryBlockHeader gbb_header; +static struct vb2_gbb_header gbb_header; /* * Read "GBB" region from SPI flash to obtain GBB header and validate @@ -45,13 +47,14 @@ return 1; if (rdev_readat(&gbb_rdev, &gbb_header, 0, - sizeof(GoogleBinaryBlockHeader)) != - sizeof(GoogleBinaryBlockHeader)) { + sizeof(struct vb2_gbb_header)) != + sizeof(struct vb2_gbb_header)) { printk(BIOS_ERR, "%s: Failure to read GBB header!\n", __func__); return 1; } - if (memcmp(gbb_header.signature, GBB_SIGNATURE, GBB_SIGNATURE_SIZE)) { + if (memcmp(gbb_header.signature, VB2_GBB_SIGNATURE, + VB2_GBB_SIGNATURE_SIZE)) { printk(BIOS_ERR, "%s: Signature check failed!\n", __func__); return 1; } diff --git a/src/security/vboot/gbb.h b/src/security/vboot/gbb.h index 550548d..389242a 100644 --- a/src/security/vboot/gbb.h +++ b/src/security/vboot/gbb.h @@ -18,7 +18,7 @@ #include <stdint.h> -/* In order to use GBB_FLAG_* macros from vboot, include gbb_header.h. */ +/* In order to use VB2_GBB_FLAG_* macros from vboot, include vb2_api.h. */ /* * Read flags field from GBB header. diff --git a/src/security/vboot/vboot_common.c b/src/security/vboot/vboot_common.c index 5e95c62..b434f8d 100644 --- a/src/security/vboot/vboot_common.c +++ b/src/security/vboot/vboot_common.c @@ -18,12 +18,12 @@ #include <cbmem.h> #include <console/cbmem_console.h> #include <fmap.h> -#include <gbb_header.h> #include <reset.h> #include <stddef.h> #include <security/vboot/gbb.h> #include <security/vboot/vboot_common.h> #include <security/vboot/vbnv.h> +#include <vb2_api.h> int vboot_named_region_device(const char *name, struct region_device *rdev) { @@ -42,7 +42,7 @@ if (!vboot_developer_mode_enabled()) return 0; /* Enable if GBB flag is set */ - if (gbb_is_flag_set(GBB_FLAG_ENABLE_UDC)) + if (gbb_is_flag_set(VB2_GBB_FLAG_ENABLE_UDC)) return 1; /* Enable if VBNV flag is set */ if (vbnv_udc_enable_flag()) -- To view, visit https://review.coreboot.org/c/coreboot/+/32455 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iee3bd877cb1791a689efdeabda324f43f7d0c6f2 Gerrit-Change-Number: 32455 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: ec/lenovo/h8: Add function to query sense state
by Patrick Rudolph (Code Review) 06 May '19

06 May '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29204 ) Change subject: ec/lenovo/h8: Add function to query sense state ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/#/c/29204/2/src/ec/lenovo/h8/sense.c File src/ec/lenovo/h8/sense.c: https://review.coreboot.org/#/c/29204/2/src/ec/lenovo/h8/sense.c@25 PS2, Line 25: * Unlikely that all register will be zero after booting has : * finished. > Patrick, I still wonder what this sentence refers to, […] the EC. You are correct, if we see the first bit there's no guarantee that the other bits are valid, as we don't have a insight into the EC firmware. My tests however showed no toggling bits once it doesn't read as zero any more. I'll update the comment that this is based on observation. -- To view, visit https://review.coreboot.org/c/coreboot/+/29204 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie27e2881a256c4efb3def11f05070c446db6e5fc Gerrit-Change-Number: 29204 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 06 May 2019 12:09:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Alexander Couzens <lynxis(a)fe80.eu> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in ...coreboot[master]: ec/lenovo/h8: Add function to query sense state
by Nico Huber (Code Review) 06 May '19

06 May '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29204 ) Change subject: ec/lenovo/h8: Add function to query sense state ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/#/c/29204/2/src/ec/lenovo/h8/sense.c File src/ec/lenovo/h8/sense.c: https://review.coreboot.org/#/c/29204/2/src/ec/lenovo/h8/sense.c@25 PS2, Line 25: * Unlikely that all register will be zero after booting has : * finished. > So far I understood, the EC reboots when powering the laptop on. Patrick, I still wonder what this sentence refers to, coreboot boot process? the EC's? If it's the EC, the statement may be true, but it doesn't work the other way. i.e. doesn't imply that the EC finished populating these registers, when we see the first bit set. -- To view, visit https://review.coreboot.org/c/coreboot/+/29204 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie27e2881a256c4efb3def11f05070c446db6e5fc Gerrit-Change-Number: 29204 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 06 May 2019 12:02:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Alexander Couzens <lynxis(a)fe80.eu> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in ...coreboot[master]: Update vboot submodule to upstream master
by Martin Roth (Code Review) 06 May '19

06 May '19

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32344 Change subject: Update vboot submodule to upstream master ...................................................................... Update vboot submodule to upstream master Updating from commit id 304aa429: 2019-03-12 10:38:56 -0700 - (futility: updater: Unit test for preserving sections using FMAP flags) to commit id dccea9ae: 2019-04-15 02:06:22 -0700 - (vboot: add magic and version to vb2_shared_data) This brings in 37 new commits. Change-Id: Ia91fadf4f50d9b7ce14143aaa0a1e2e1c5cbef07 Signed-off-by: Martin Roth <martinroth(a)google.com> --- M 3rdparty/vboot 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/32344/1 diff --git a/3rdparty/vboot b/3rdparty/vboot index 304aa42..dccea9a 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit 304aa429c1a04cda3ab2ce37b9e31af84405bfca +Subproject commit dccea9ae88059c8cb7dff76d2682835184fc8338 -- To view, visit https://review.coreboot.org/c/coreboot/+/32344 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia91fadf4f50d9b7ce14143aaa0a1e2e1c5cbef07 Gerrit-Change-Number: 32344 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src: Remove unused include <halt.h>
by HAOUAS Elyes (Code Review) 06 May '19

06 May '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32611 Change subject: src: Remove unused include <halt.h> ...................................................................... src: Remove unused include <halt.h> Change-Id: I2f142cc80692e60eb0f81f57339a247f6ef4a524 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/apple/macbook21/romstage.c M src/mainboard/asus/p5gc-mx/romstage.c M src/mainboard/asus/p5qpl-am/romstage.c M src/mainboard/getac/p470/romstage.c M src/mainboard/ibase/mb899/romstage.c M src/mainboard/intel/dcp847ske/early_southbridge.c M src/mainboard/kontron/986lcd-m/romstage.c M src/mainboard/lenovo/t60/romstage.c M src/mainboard/lenovo/z61t/romstage.c M src/mainboard/roda/rk886ex/romstage.c M src/northbridge/intel/haswell/raminit.c M src/northbridge/intel/i945/early_init.c M src/northbridge/intel/i945/raminit.c M src/northbridge/intel/pineview/romstage.c M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/raminit_mrc.c 16 files changed, 0 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/32611/1 diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c index c056ac8f..468cffb 100644 --- a/src/mainboard/apple/macbook21/romstage.c +++ b/src/mainboard/apple/macbook21/romstage.c @@ -26,7 +26,6 @@ #include <cpu/x86/lapic.h> #include <console/console.h> #include <cpu/x86/bist.h> -#include <halt.h> #include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/raminit.h> #include <southbridge/intel/i82801gx/i82801gx.h> diff --git a/src/mainboard/asus/p5gc-mx/romstage.c b/src/mainboard/asus/p5gc-mx/romstage.c index beb276c..08379f7 100644 --- a/src/mainboard/asus/p5gc-mx/romstage.c +++ b/src/mainboard/asus/p5gc-mx/romstage.c @@ -29,7 +29,6 @@ #include <console/console.h> #include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> -#include <halt.h> #include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/raminit.h> #include <southbridge/intel/i82801gx/i82801gx.h> diff --git a/src/mainboard/asus/p5qpl-am/romstage.c b/src/mainboard/asus/p5qpl-am/romstage.c index 4174981..bd6bfc6 100644 --- a/src/mainboard/asus/p5qpl-am/romstage.c +++ b/src/mainboard/asus/p5qpl-am/romstage.c @@ -24,7 +24,6 @@ #include <cpu/intel/speedstep.h> #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> -#include <halt.h> #include <northbridge/intel/x4x/iomap.h> #include <northbridge/intel/x4x/x4x.h> #include <southbridge/intel/common/gpio.h> diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index d643b12..aaa3422 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -25,7 +25,6 @@ #include <console/console.h> #include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> -#include <halt.h> #include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/raminit.h> #include <southbridge/intel/i82801gx/i82801gx.h> diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index 7e3b7db..9cb1144 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -16,7 +16,6 @@ // __PRE_RAM__ means: use "unsigned" for device, not a struct. #include <stdint.h> -#include <halt.h> #include <arch/io.h> #include <cf9_reset.h> #include <device/pnp_ops.h> diff --git a/src/mainboard/intel/dcp847ske/early_southbridge.c b/src/mainboard/intel/dcp847ske/early_southbridge.c index 46f9a94..778525f 100644 --- a/src/mainboard/intel/dcp847ske/early_southbridge.c +++ b/src/mainboard/intel/dcp847ske/early_southbridge.c @@ -17,7 +17,6 @@ */ #include <stdint.h> -#include <halt.h> #include <arch/io.h> #include <cf9_reset.h> #include <device/pci_ops.h> diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index 3d01eb1..b85bd68 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -16,7 +16,6 @@ /* __PRE_RAM__ means: use "unsigned" for device, not a struct. */ #include <stdint.h> -#include <halt.h> #include <arch/io.h> #include <cf9_reset.h> #include <console/console.h> diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index ea207e8..0c7c0cf 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -28,7 +28,6 @@ #include <console/console.h> #include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> -#include <halt.h> #include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/raminit.h> #include <southbridge/intel/i82801gx/i82801gx.h> diff --git a/src/mainboard/lenovo/z61t/romstage.c b/src/mainboard/lenovo/z61t/romstage.c index 0d68fac..47a52db 100644 --- a/src/mainboard/lenovo/z61t/romstage.c +++ b/src/mainboard/lenovo/z61t/romstage.c @@ -29,7 +29,6 @@ #include <console/console.h> #include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> -#include <halt.h> #include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/raminit.h> #include <southbridge/intel/i82801gx/i82801gx.h> diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index e85da1f..2bdad27 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -27,7 +27,6 @@ #include <console/console.h> #include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> -#include <halt.h> #include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/raminit.h> #include <southbridge/intel/i82801gx/i82801gx.h> diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index fddada4..96dc94e 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -20,7 +20,6 @@ #include <arch/cbfs.h> #include <cbfs.h> #include <cf9_reset.h> -#include <halt.h> #include <ip_checksum.h> #include <memory_info.h> #include <mrc_cache.h> diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index a9de844..274296d 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -21,7 +21,6 @@ #include <device/pci_ops.h> #include <device/pci_def.h> #include <cbmem.h> -#include <halt.h> #include <romstage_handoff.h> #include "i945.h" #include <pc80/mc146818rtc.h> diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 1e8cf65..0cf03ae 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -26,7 +26,6 @@ #include <pc80/mc146818rtc.h> #include <spd.h> #include <string.h> -#include <halt.h> #include "raminit.h" #include "i945.h" #include "chip.h" diff --git a/src/northbridge/intel/pineview/romstage.c b/src/northbridge/intel/pineview/romstage.c index bdb685b..a3e6c39 100644 --- a/src/northbridge/intel/pineview/romstage.c +++ b/src/northbridge/intel/pineview/romstage.c @@ -23,7 +23,6 @@ #include <device/pci_ops.h> #include <cbmem.h> #include <cf9_reset.h> -#include <halt.h> #include <romstage_handoff.h> #include <southbridge/intel/i82801gx/i82801gx.h> #include <southbridge/intel/common/gpio.h> diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index cea3f2c..e60c378 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -25,7 +25,6 @@ #include <device/mmio.h> #include <device/pci_ops.h> #include <cbmem.h> -#include <halt.h> #include <timestamp.h> #include <mrc_cache.h> #include <southbridge/intel/bd82x6x/me.h> diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index a68ae49..ea3590f 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -28,7 +28,6 @@ #include <device/pci_def.h> #include <lib.h> #include <mrc_cache.h> -#include <halt.h> #include <timestamp.h> #include "raminit.h" #include "pei_data.h" -- To view, visit https://review.coreboot.org/c/coreboot/+/32611 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f142cc80692e60eb0f81f57339a247f6ef4a524 Gerrit-Change-Number: 32611 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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coreboot-gerrit May 2019